74HC74D-Q100 [NEXPERIA]
Dual D-type flip-flop with set and reset; positive edge-trigger;
| 型号： | 74HC74D-Q100 |
| 厂家： | 
Nexperia |
| 描述： | Dual D-type flip-flop with set and reset; positive edge-trigger 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总19页 (文件大小：798K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC74-Q100; 74HCT74-Q100
Dual D-type flip-flop with set and reset; positive edge-trigger
Rev. 3 — 4 December 2015
Product data sheet
1. General description
The 74HC74-Q100; 74HCT74-Q100 are dual positive edge triggered D-type flip-flop with
individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary
nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time
requirements on the LOW-to-HIGH clock transition, will be stored in the flip-flop and
appear at the nQ output. The Schmitt-trigger action in the clock input, makes the circuit
highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This
enables the use of current limiting resistors to interface inputs to voltages in excess of
VCC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Input levels:
For 74HC74-Q100: CMOS level
For 74HCT74-Q100: TTL level
Symmetrical output impedance
Low power dissipation
High noise immunity
Balanced propagation delays
Specified in compliance with JEDEC standard no. 7A
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
74HC74-Q100; 74HCT74-Q100
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74HC74D-Q100
40 C to +125 C
40 C to +125 C
40 C to +125 C
SO14
plastic small outline package; 14 leads; body
width 3.9 mm
SOT108-1
74HCT74D-Q100
74HC74PW-Q100
74HCT74PW-Q100
74HC74BQ-Q100
74HCT74BQ-Q100
TSSOP14
DHVQFN14
plastic thin shrink small outline package;
14 leads; body width 4.4 mm
SOT402-1
SOT762-1
plastic dual in-line compatible thermal
enhanced very thin quad flat package; no
leads; 14 terminals; body 2.5 3 0.85 mm
4. Functional diagram
ꢁ6'
ꢀ
6'
ꢁ'
ꢁ4
ꢃ
ꢆ
4
4
'
ꢄ
ꢇ
ꢁ&3
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))
ꢁ4
5'
ꢀ
ꢀ
ꢁꢂ
6
ꢄ
ꢇ
ꢁ5'
ꢃ6'
ꢆ
ꢃ
ꢁ
ꢁ
&ꢁ
ꢁ'
ꢁ6' ꢃ6'
ꢁꢂ
6'
ꢁ4
ꢃ4
ꢄ
ꢅ
ꢃ
ꢁꢃ
ꢆ
ꢁ'
ꢃ'
5
'
4
4
6'
ꢃ4
ꢃ4
ꢃ'
ꢁ&3
ꢅ
ꢈ
ꢁꢃ
ꢁꢁ
'
4
4
&3
ꢁꢂ
ꢁꢁ
ꢁꢃ
ꢁꢆ
ꢁꢁ ꢃ&3
6
))
ꢃ&3
ꢅ
ꢈ
ꢁ4
ꢃ4
ꢇ
ꢈ
&3
&ꢁ
))
5'
ꢁ5' ꢃ5'
ꢁꢆ
ꢁ'
5
5'
ꢃ5'
ꢁ
PQDꢀꢄꢅ
ꢁꢆ
PQDꢀꢁꢂ
PQDꢀꢁꢃ
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Functional diagram
74HC_HCT74_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 4 December 2015
2 of 19
74HC74-Q100; 74HCT74-Q100
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
4
&
&
&
&
&
&
&
4
&
'
5'
6'
&3
PQDꢀꢄꢁ
&
&
Fig 4. Logic diagram for one flip-flop
5. Pinning information
5.1 Pinning
ꢀꢁ+&ꢀꢁꢂ4ꢃꢄꢄ
ꢀꢁ+&7ꢀꢁꢂ4ꢃꢄꢄ
WHUPLQDOꢊꢁ
LQGH[ꢊDUHD
ꢀꢁ+&ꢀꢁꢂ4ꢃꢄꢄ
ꢀꢁ+&7ꢀꢁꢂ4ꢃꢄꢄ
ꢃ
ꢆ
ꢀ
ꢄ
ꢇ
ꢁꢆ
ꢁꢃ
ꢁꢁ
ꢁꢂ
ꢅ
ꢁ'
ꢁ&3
ꢁ6'
ꢁ4
ꢃ5'
ꢃ'
ꢁ
ꢃ
ꢆ
ꢀ
ꢄ
ꢇ
ꢉ
ꢁꢀ
ꢁꢆ
ꢁꢃ
ꢁꢁ
ꢁꢂ
ꢅ
ꢁ5'
ꢁ'
9
&&
ꢃ5'
ꢃ'
ꢃ&3
ꢃ6'
ꢃ4
ꢁ&3
ꢁ6'
ꢁ4
ꢋꢁꢌ
*1'
ꢃ&3
ꢃ6'
ꢃ4
ꢁ4
ꢁ4
DDDꢆꢅꢅꢀꢇꢃꢉ
*1'
ꢈ
ꢃ4
7UDQVSDUHQWꢊWRSꢊYLHZ
DDDꢆꢅꢅꢀꢇꢃꢈ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5. Pin configuration for SO14 and TSSOP14
Fig 6. Pin configuration for DHVQFN14
74HC_HCT74_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 4 December 2015
3 of 19
74HC74-Q100; 74HCT74-Q100
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
5.2 Pin description
Table 2.
Symbol
1RD
1D
Pin description
Pin
1
Description
asynchronous reset-direct input (active LOW)
data input
2
1CP
1SD
1Q
3
clock input (LOW-to-HIGH, edge-triggered)
asynchronous set-direct input (active LOW)
output
4
5
1Q
6
complement output
GND
2Q
7
ground (0 V)
8
complement output
2Q
9
output
2SD
2CP
2D
10
11
12
13
14
asynchronous set-direct input (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
data input
2RD
VCC
asynchronous reset-direct input (active LOW)
supply voltage
6. Functional description
Table 3.
Function table[1]
Input
nSD
L
Output
nRD
H
nCP
X
nD
X
nQ
H
nQ
L
H
L
X
X
L
H
L
L
X
X
H
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
Table 4.
Input
nSD
H
Function table[1]
Output
nRD
H
nCP
nD
L
nQn+1
nQn+1
L
H
L
H
H
H
H
[1] H = HIGH voltage level; L = LOW voltage level; = LOW-to-HIGH transition; Qn+1 = state after the next LOW-to-HIGH CP transition;
X = don’t care.
74HC_HCT74_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 4 December 2015
4 of 19
74HC74-Q100; 74HCT74-Q100
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
7. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max Unit
supply voltage
0.5
+7
V
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
-
20
20
25
mA
mA
mA
IOK
-
IO
-
ICC
supply current
-
100
65
-
+100 mA
mA
+150 C
IGND
Tstg
Ptot
ground current
-
storage temperature
total power dissipation
[1]
[1]
DIP14 package
750
500
mW
SO14, TSSOP14 and DHVQFN14
packages
-
mW
[1] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.
For SO14 packages: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C.
8. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions
74HC74-Q100
74HCT74-Q100
Unit
Min
Typ
Max
Min
Typ
Max
VCC
VI
supply voltage
2.0
5.0
6.0
VCC
VCC
+125
625
139
83
4.5
5.0
5.5
VCC
VCC
V
V
V
input voltage
0
-
0
-
VO
output voltage
0
-
+25
-
0
-
+25
-
Tamb
t/V
ambient temperature
input transition rise and fall rate VCC = 2.0 V
VCC = 4.5 V
40
40
+125 C
-
-
-
-
-
-
-
ns/V
1.67
-
1.67
-
139 ns/V
VCC = 6.0 V
-
ns/V
9. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = 40 C to +85 C
Tamb = 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
74HC74-Q100
VIH
HIGH-level
input voltage
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1.5
3.15
4.2
1.2
2.4
3.2
-
-
-
1.5
3.15
4.2
-
-
-
V
V
V
74HC_HCT74_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 4 December 2015
5 of 19
74HC74-Q100; 74HCT74-Q100
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Tamb = 40 C to +85 C
Tamb = 40 C to +125 C Unit
Min
Typ[1]
Max
0.5
Min
Max
0.5
VIL
LOW-level
input voltage
VCC = 2.0 V
-
-
-
0.8
-
-
-
V
V
V
VCC = 4.5 V
2.1
1.35
1.8
1.35
1.8
VCC = 6.0 V
2.8
VOH
HIGH-level
VI = VIH or VIL
output voltage
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
VI = VIH or VIL
3.84
5.34
4.32
5.81
-
-
3.7
5.2
-
-
V
V
VOL
LOW-level
output voltage
IO = 4.0 mA; VCC = 4.5 V
IO = 5.2 mA; VCC = 6.0 V
-
-
-
0.15
0.16
-
0.33
0.33
1.0
-
-
-
0.4
0.4
V
V
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
1.0
A
ICC
CI
supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
-
40
-
-
-
80
-
A
input
3.5
pF
capacitance
74HCT74-Q100
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
2.0
-
1.6
1.2
-
2.0
-
-
V
V
VIL
LOW-level
0.8
0.8
input voltage
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 4 mA
3.84
4.32
-
3.7
-
V
VOL
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 4.0 mA
-
-
0.15
-
0.33
-
-
0.4
V
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
1.0
1.0
A
ICC
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
40
-
80
A
additional
VI = VCC 2.1 V;
supply current other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V;
IO = 0 A
per input pin; nD, nRD
inputs
-
-
-
70
80
315
360
-
-
-
-
343
392
-
A
A
pF
per input pin; nSD, nCP
input
CI
input
3.5
capacitance
[1] All typical values are measured at Tamb = 25 C.
74HC_HCT74_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 4 December 2015
6 of 19
74HC74-Q100; 74HCT74-Q100
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
10. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9.
Symbol Parameter Conditions
74HC74-Q100
Tamb = 40 C to +85 C
Tamb = 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
[2]
[2]
[2]
[3]
tpd
propagation nCP to nQ, nQ; see
delay
Figure 7
VCC = 2.0 V
-
-
-
-
47
17
14
14
220
44
-
-
-
-
-
265
53
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
37
45
nSD to nQ, nQ; see
Figure 8
VCC = 2.0 V
-
-
-
-
50
18
15
14
250
50
-
-
-
-
-
300
60
-
ns
ns
ns
ns
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
43
51
nRD to nQ, nQ; see
Figure 8
VCC = 2.0 V
VCC = 4.5 V
-
-
-
-
52
19
16
15
250
50
-
-
-
-
-
300
60
-
ns
ns
ns
ns
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
43
51
tt
transition
time
nQ, nQ; see Figure 7
VCC = 2.0 V
-
-
-
19
7
95
19
16
-
-
-
110
22
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
6
19
tW
pulse width nCP HIGH or LOW;
see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
100
20
19
7
-
-
-
120
24
-
-
-
ns
ns
ns
17
6
20
nSD, nRD LOW;
see Figure 8
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
100
20
19
7
-
-
-
120
24
-
-
-
ns
ns
ns
17
6
20
trec
recovery
time
nSD, nRD; see Figure 8
VCC = 2.0 V
40
8
3
1
1
-
-
-
45
9
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
7
8
74HC_HCT74_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 4 December 2015
7 of 19
74HC74-Q100; 74HCT74-Q100
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9.
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
tsu
set-up time nD to nCP; see Figure 7
VCC = 2.0 V
VCC = 4.5 V
75
15
13
6
2
2
-
-
-
90
18
15
-
-
-
ns
ns
ns
VCC = 6.0 V
th
hold time
nD to nCP; see Figure 7
VCC = 2.0 V
3
3
3
6
2
2
-
-
-
3
3
3
-
-
-
ns
ns
ns
VCC = 4.5 V
VCC = 6.0 V
fmax
maximum
frequency
nCP; see Figure 7
VCC = 2.0 V
4.8
24
-
23
69
76
82
24
-
-
-
-
-
4.0
20
-
-
-
-
-
-
MHz
MHz
MHz
MHz
pF
VCC = 4.5 V
VCC = 5 V; CL = 15 pF
VCC = 6.0 V
28
-
24
-
[4]
[2]
CPD
power
dissipation
capacitance
CL = 50 pF; f = 1 MHz;
VI = GND to VCC
74HCT74-Q100
tpd
propagation nCP to nQ, nQ; see
delay
Figure 7
VCC = 4.5 V
-
-
18
15
44
-
-
-
53
-
ns
ns
VCC = 5 V; CL = 15 pF
[2]
[2]
[3]
nSD to nQ, nQ; see
Figure 8
VCC = 4.5 V
-
-
23
18
50
-
-
-
60
-
ns
ns
VCC = 5 V; CL = 15 pF
nRD to nQ, nQ; see
Figure 8
VCC = 4.5 V
-
-
24
18
50
-
-
-
60
-
ns
ns
VCC = 5 V; CL = 15 pF
nQ, nQ; see Figure 7
VCC = 4.5 V
tt
transition
time
-
7
9
19
-
-
22
-
ns
ns
tW
pulse width nCP HIGH or LOW;
see Figure 7
VCC = 4.5 V
23
27
nSD, nRD LOW;
see Figure 8
VCC = 4.5 V
20
8
9
1
5
-
-
-
24
9
-
-
-
ns
ns
ns
trec
recovery
time
nSD, nRD; see Figure 8
VCC = 4.5 V
tsu
set-up time nD to nCP; see Figure 7
VCC = 4.5 V
15
18
74HC_HCT74_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 4 December 2015
8 of 19
74HC74-Q100; 74HCT74-Q100
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 9.
Symbol Parameter Conditions Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Min
Typ[1]
Max
Min
Max
th
hold time
nD to nCP; see Figure 7
VCC = 4.5 V
3
3
-
3
-
ns
fmax
maximum
frequency
nCP; see Figure 7
VCC = 4.5 V
22
-
54
59
29
-
-
-
18
-
-
-
-
MHz
MHz
pF
VCC = 5 V; CL = 15 pF
[4]
CPD
power
CL = 50 pF; f = 1 MHz;
-
-
dissipation
capacitance
VI = GND to VCC 1.5 V
[1] All typical values are measured at Tamb = 25 C.
[2] tpd is the same as tPLH and tPHL
[3] tt is the same as tTHL and tTLH
.
.
[4]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
74HC_HCT74_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 4 December 2015
9 of 19
74HC74-Q100; 74HCT74-Q100
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
11. Waveforms
9
,
Q'ꢊLQSXW
9
0
*1'
W
W
K
K
W
VX
W
VX
ꢁꢍI
PD[
9
,
Q&3ꢊLQSXW
9
0
*1'
W
:
W
W
3/+
3+/
9
9
2+
9
Q4ꢊRXWSXW
Q4ꢊRXWSXW
0
9
2/
W
W
3+/
3/+
2+
ꢅꢂꢊꢎ
W
ꢅꢂꢊꢎ
9
ꢁꢂꢊꢎ
0
ꢁꢂꢊꢎ
9
2/
W
7/+
7+/
DDDꢆꢅꢅꢀꢅꢅꢇ
Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Propagation delay input (CP) to output (Qn), output transition time, clock input (CP) pulse width and the
maximum frequency (CP)
74HC_HCT74_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 4 December 2015
10 of 19
74HC74-Q100; 74HCT74-Q100
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
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Measurement points are given in Table 9.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. The set (nSD) and reset (nRD) input to output (nQ,nQ) propagation delays, set and reset pulse widths and
the nSD, nRD to nCP recovery time
Table 9.
Type
Measurement points
Input
VM
Output
VM
74HC74-Q100
74HCT74-Q100
0.5VCC
1.3 V
0.5VCC
1.3 V
74HC_HCT74_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 4 December 2015
11 of 19
74HC74-Q100; 74HCT74-Q100
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
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Test data is given in Table 10.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 9. Test circuit for measuring switching times
Table 10. Test data
Type
Input
VI
Load
Test
tr, tf
6 ns
6 ns
CL
RL
74HC74-Q100
74HCT74-Q100
VCC
3 V
15 pF, 50 pF
15 pF, 50 pF
1 k
1 k
tPLH, tPHL
tPLH, tPHL
74HC_HCT74_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 4 December 2015
12 of 19
74HC74-Q100; 74HCT74-Q100
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
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74HC_HCT74_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 4 December 2015
13 of 19
74HC74-Q100; 74HCT74-Q100
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
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Fig 11. Package outline SOT402-1 (TSSOP14)
74HC_HCT74_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 4 December 2015
14 of 19
74HC74-Q100; 74HCT74-Q100
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
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74HC_HCT74_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 4 December 2015
15 of 19
74HC74-Q100; 74HCT74-Q100
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
13. Abbreviations
Table 11. Abbreviations
Acronym
CMOS
ESD
Description
Complementary Metal Oxide Semiconductor
ElectroStatic Discharge
Human Body Model
HBM
MIL
Military
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 12. Revision history
Document ID
Release date Data sheet status
20151204 Product data sheet
Change notice
Supersedes
74HC_HCT74_Q100 v.3
Modifications:
-
74HC_HCT74_Q100 v.2
• Type number 74HC74N-Q100 (SOT27-1) removed.
74HC_HCT74_Q100 v.2
Modifications:
20130906
• 74HC74N-Q100 (DIP14) added.
20120807 Product data sheet
Product data sheet
-
74HC_HCT74_Q100 v.1
-
74HC_HCT74_Q100 v.1
-
74HC_HCT74_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 4 December 2015
16 of 19
74HC74-Q100; 74HCT74-Q100
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nexperia.com.
Suitability for use in automotive applications — This Nexperia
product has been qualified for use in automotive
15.2 Definitions
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of a Nexperia product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. Nexperia and its suppliers accept no liability for
inclusion and/or use of Nexperia products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. Nexperia does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. Nexperia makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using Nexperia products, and Nexperia
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
Nexperia and its customer, unless Nexperia and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the Nexperia product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the Nexperia
product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Nexperia does not accept any liability related to any default,
15.3 Disclaimers
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using Nexperia
products in order to avoid a default of the applications and
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, Nexperia does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. Nexperia takes no
responsibility for the content in this document if provided by an information
source outside of Nexperia.
the products or of the application or use by customer’s third party
customer(s). Nexperia does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
In no event shall Nexperia be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, Nexperia’s aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of Nexperia.
Terms and conditions of commercial sale — Nexperia
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nexperia.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. Nexperia hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of Nexperia products by customer.
Right to make changes — Nexperia reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT74_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 4 December 2015
17 of 19
74HC74-Q100; 74HCT74-Q100
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
No offer to sell or license — Nothing in this document may be interpreted or
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15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
74HC_HCT74_Q100
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 3 — 4 December 2015
18 of 19
74HC74-Q100; 74HCT74-Q100
Nexperia
Dual D-type flip-flop with set and reset; positive edge-trigger
17. Contents
1
2
3
4
General description. . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
© Nexperia B.V. 2017. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release: 04 December 2015
相关型号：
74HC74D/G,118
74HC(T)74 - Dual D-type flip-flop with set and reset; positive-edge trigger SOIC 14-Pin
NXP
74HC74D/T3
IC HC/UH SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, 3.90 MM, PLASTIC, MS-012, SOT-108-1, SOP-14, FF/Latch
NXP
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