74HC74DR2G [ONSEMI]
Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS; 双D触发器具有置位和复位高性能硅栅CMOS
| 型号： | 74HC74DR2G |
| 厂家： | 
ONSEMI |
| 描述： | Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS |
| 文件： | 总8页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74HC74
Dual D Flip−Flop with Set
and Reset
High−Performance Silicon−Gate CMOS
The 74HC74 is identical in pinout to the LS74. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they
are compatible with LSTTL outputs.
This device consists of two D flip−flops with individual Set, Reset,
and Clock inputs. Information at a D−input is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flip−flop. The Set
and Reset inputs are asynchronous.
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MARKING
DIAGRAMS
14
SOIC−14
D SUFFIX
CASE 751A
HC74G
AWLYWW
14
14
Features
1
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
1
14
• Low Input Current: 1.0 mA
HC
74
TSSOP−14
DT SUFFIX
CASE 948G
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the JEDEC Standard No. 7A Requirements
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: 128 FETs or 32 Equivalent Gates
• Pb−Free Packages are Available
ALYW G
1
G
1
HC74
A
L, WL
Y
= Device Code
= Assembly Location
= Wafer Lot
= Year
W, WW = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
©
Semiconductor Components Industries, LLC, 2007
1
Publication Order Number:
February, 2007 − Rev. 0
74HC74/D
74HC74
PIN ASSIGNMENT
LOGIC DIAGRAM
1
RESET 1
DATA 1
1
2
14
13 RESET 2
12
V
RESET 1
CC
5
6
2
3
DATA 1
Q1
Q1
3
4
CLOCK 1
SET 1
DATA 2
CLOCK 1
11 CLOCK 2
10 SET 2
4
Q1
Q1
5
6
7
SET 1
9
8
Q2
Q2
13
RESET 2
GND
9
8
12
11
DATA 2
Q2
Q2
FUNCTION TABLE
CLOCK 2
Inputs
Outputs
10
Set Reset Clock Data
Q
Q
SET 2
PIN 14 = V
CC
PIN 7 = GND
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
H
L
X
X
X
H
L
H*
H
L
L
H
H*
L
H
L
H
No Change
No Change
No Change
*Both outputs will remain high as long as Set and Reset are low, but the output
states are unpredictable if Set and Reset go high simultaneously.
MAXIMUM RATINGS
Symbol
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
– 0.5 to + 7.0
CC
V
in
– 0.5 to V + 0.5
V
CC
V
out
– 0.5 to V + 0.5
V
CC
I
±20
±25
±50
mA
mA
mA
mW
in
I
DC Output Current, per Pin
out
CC
cuit. For proper operation, V and
in
I
DC Supply Current, V and GND Pins
CC
V
out
should be constrained to the
P
Power Dissipation in Still Air,
SOIC Package†
TSSOP Package†
500
450
range GND v (V or V ) v V
.
D
in
out
CC
Unused inputs must always be
tied to an appropriate logic voltage
T
stg
Storage Temperature
– 65 to + 150
_C
_C
level (e.g., either GND or V ).
CC
T
Lead Temperature, 1 mm from Case for 10 Seconds
(SOIC or TSSOP Package)
L
Unused outputs must be left open.
260
300
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
CC
V , V
in out
V
V
CC
T
A
– 55
+ 125
_C
ns
t , t
Input Rise and Fall Time
(Figures 1, 2, 3)
V
V
V
V
= 2.0 V
= 3.0 V
= 4.5 V
= 6.0 V
0
0
0
0
1000
600
500
400
r
f
CC
CC
CC
CC
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2
74HC74
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
25_C
(V)
v 85_C v 125_C
Symbol
Parameter
Test Conditions
Unit
V
2.0
3.0
4.5
6.0
1.5
2.1
V
Minimum High−Level Input
V
= 0.1 V or V – 0.1 V
1.5
2.1
1.5
2.1
IH
out
CC
Voltage
|I | v 20 mA
out
3.15
4.2
3.15
4.2
3.15
4.2
V
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
V
V
Maximum Low−Level Input
Voltage
V
= 0.1 V or V – 0.1 V
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
IL
out
CC
|I | v 20 mA
out
V
Minimum High−Level Output
Voltage
V
in
= V or V
IL
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
OH
IH
|I | v 20 mA
out
V
= V or V
|I | v 2.4 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
in
IH
IL
out
|I | v 4.0 mA
out
|I | v 5.2 mA
out
V
V
Maximum Low−Level Output
V
in
= V or V
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
OL
IH
IL
Voltage
|I | v 20 mA
out
V
= V or V
|I | v 2.4 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
in
IH
IL
out
|I | v 4.0 mA
out
|I | v 5.2 mA
out
I
Maximum Input Leakage Current
V
V
= V or GND
6.0
6.0
±0.1
±1.0
±1.0
mA
mA
in
in
CC
I
Maximum Quiescent Supply
Current (per Package)
2.0
20
80
= V or GND
CC
in
CC
I
= 0 mA
out
NOTE:Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
(DL129/D).
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
25_C
(V)
v 85_C v 125_C
Symbol
Parameter
Unit
f
MHz
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
3.0
4.5
6.0
6.0
15
30
35
4.8
10
24
28
4.0
8.0
20
max
24
ns
ns
ns
pF
t
t
t
,
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
2.0
3.0
4.5
6.0
100
75
20
125
90
25
150
120
30
PLH
t
PHL
17
21
26
,
Maximum Propagation Delay, Set or Reset to Q or Q
(Figures 2 and 4)
2.0
3.0
4.5
6.0
105
80
21
130
95
26
160
130
32
PLH
t
PHL
18
22
27
,
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
TLH
t
THL
19
C
in
Maximum Input Capacitance
—
10
10
10
NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V = 5.0 V
CC
32
C
PD
Power Dissipation Capacitance (Per Flip−Flop)*
pF
2
* Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
. For load considerations, see Chapter 2 of the
D
PD CC
CC CC
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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3
74HC74
TIMING REQUIREMENTS (Input t = t = 6.0 ns)
r
f
Guaranteed Limit
– 55 to
V
CC
25_C
80
35
16
14
(V)
v 85_C v 125_C
Symbol
Parameter
Unit
t
ns
Minimum Setup Time, Data to Clock
(Figure 3)
2.0
3.0
4.5
6.0
100
45
120
55
su
20
24
17
20
t
3.0
3.0
3.0
3.0
ns
ns
ns
ns
ns
Minimum Hold Time, Clock to Data
(Figure 3)
2.0
3.0
4.5
6.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
h
t
Minimum Recovery Time, Set or Reset Inactive to Clock
(Figure 2)
2.0
3.0
4.5
6.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
rec
t
Minimum Pulse Width, Clock
(Figure 1)
2.0
3.0
4.5
6.0
60
25
12
10
75
30
15
13
90
40
18
15
w
t
Minimum Pulse Width, Set or Reset
(Figure 2)
2.0
3.0
4.5
6.0
60
25
12
10
75
30
15
13
90
40
18
15
w
t , t
r
Maximum Input Rise and Fall Times
(Figures 1, 2, 3)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
f
ORDERING INFORMATION
Device
†
Package
Shipping
74HC74D
SOIC−14
55 Units / Rail
74HC74DG
SOIC−14
(Pb−Free)
74HC74DR2
SOIC−14
74HC74DR2G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
74HC74DTR2
TSSOP−14*
TSSOP−14*
74HC74DTR2G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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4
74HC74
SWITCHING WAVEFORMS
t
w
t
f
t
r
V
CC
V
50%
CC
SET OR
90%
50%
10%
CLOCK
GND
RESET
GND
t
PHL
t
w
50%
Q OR Q
1/f
max
t
t
PLH
PHL
t
PLH
90%
50%
10%
50%
Q or Q
Q OR Q
CLOCK
t
rec
t
t
THL
TLH
V
CC
50%
GND
Figure 1.
Figure 2.
TEST POINT
OUTPUT
VALID
V
CC
50%
DATA
DEVICE
UNDER
TEST
GND
t
su
t
h
C *
L
V
CC
50%
CLOCK
GND
*Includes all probe and jig capacitance
Figure 3.
Figure 4.
4, 10
SET
2, 12
5, 9
DATA
Q
3, 11
CLOCK
6, 8
Q
1, 13
RESET
Figure 5. EXPANDED LOGIC DIAGRAM
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5
74HC74
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−A−
14
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−B−
P 7 PL
M
M
B
0.25 (0.010)
7
1
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
F
R X 45
_
C
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
SEATING
PLANE
J
M
K
1.27 BSC
D 14 PL
0.19
0.10
0
M
S
S
0.25 (0.010)
T
B
A
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
74HC74
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
14X K REF
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
M
S
S
V
0.10 (0.004)
T
U
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
DETAIL E
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T
U
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
K1
A
B
C
D
F
G
H
J
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
J1
K
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0
8
0
8
_
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
74HC74
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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74HC74/D
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