UPD784031YGC-8BT-A [NEC]
Microcontroller, 16-Bit, 32MHz, CMOS, PQFP80, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP-80;型号: | UPD784031YGC-8BT-A |
厂家: | NEC |
描述: | Microcontroller, 16-Bit, 32MHz, CMOS, PQFP80, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP-80 微控制器和处理器 外围集成电路 时钟 |
文件: | 总88页 (文件大小:457K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD784031Y
16-/8-BIT SINGLE-CHIP MICROCONTROLLERS
The µPD784031Y is based on the µPD784031 with an I2C bus control function appended, and is ideal for
applications in audio-visual systems.
The µPD784031Y is a ROM-less version of µPD784035Y and 784036Y.
The functions are explained in detail in the following User’s Manual. Be sure to read this manual when
designing your system.
µPD784038, 784038Y Subseries User’s Manual - Hardware : U11316E
78K/IV Series User’s Manual - Instruction
: U10905E
FEATURES
78K/IV Series
Timer/counter
Pin-compatible with µPD78234 Subseries,
µPD784026 Subseries, and µPD784038
Subseries
16-bit Timer/counter x 3 units
16-bit Timer x 1 unit
Standby function
Minimum instruction execution time: 125 ns
(@ 32-MHz operation)
HALT/STOP/IDLE mode
Clock division function
I/O ports: 46
Watchdog timer: 1 channel
A/D converter: 8-bit resolution x 8 channels
D/A converter: 8-bit resolution x 2 channels
Supply voltage: VDD = 2.7 to 5.5 V
Serial interface: 3 channels
UART/IOE (3-wire serial I/O): 2 channels
CSI (3-wire serial I/O, 2-wire serial I/O, I2C bus):
1 channel
PWM output: 2 outputs
APPLICATION FIELDS
Cellular phones, cordless phones, audio-visual systems, etc.
ORDERING INFORMATION
Part Number
Package
80-pin plastic QFP (14 x 14 mm, thickness 2.7 mm)
Internal ROM (Bytes) Internal RAM (Bytes)
µPD784031YGC-3B9
None
None
None
2048
2048
2048
µPD784031YGC-8BT 80-pin plastic QFP (14 x 14 mm, thickness 1.4 mm)
µPD784031YGK-BE9 80-pin plastic TQFP (fine pitch) (12 x 12 mm)
The information in this document is subject to change without notice.
The mark shows major revised points.
Document No. U11504EJ1V0DS00 (1st edition)
Date Published July 1997 N
Printed in Japan
1996
©
µPD784031Y
78K/IV SERIES PRODUCT DEVELOPMENT
: Under mass production
: Under development
2
2
I C bus supported
Multimaster I C bus supported
µPD784225Y
µPD784038Y
µPD784038
Standard models
µPD784225
Enhanced internal memory capacity,
pin compatible with the µPD784026
80 pins,
added ROM correction
µPD784026
Enhanced A/D,
16-bit timer,
and power
2
2
Multimaster I C bus supported
Multimaster I C bus supported
µPD784216Y
µPD784216
µPD784218Y
µPD784218
management
100 pins,
enhanced I/O and
internal memory capacity
Enhanced internal memory capacity,
added ROM correction
µPD784054
µPD784046
ASSP models
Equipped with 10-bit A/D
µPD784908
TM
Equipped with IEBus
controller
2
µPD78F4943
For CD-ROM,
Multimaster I C bus supported
µPD784928Y
56-Kbyte flash memory
µPD784928
Enhanced function of the µPD784915
µPD784915
Equipped with analog circuit for
software servo control VCR,
enhanced timer
2
µPD784031Y
FUNCTIONS
Item
Function
Number of basic instructions
(mnemonics)
113
General-purpose register
8 bits x 16 registers x 8 banks, or 16 bits x 8 registers x 8 banks (memory mapping)
125 ns/250 ns/500 ns/1000 ns (at 32 MHz)
Minimum instruction execution
time
Internal memory
ROM
RAM
None
2048 bytes
Memory space
I/O port
1 Mbytes with program and data spaces combined
Total
Input
I/O
46
8
34
4
Output
Pins with pull- 32
up resistor
Pins with
ancillary
LEDs direct
drive output
8
Note
function
Transistor
direct drive
8
Real-time output port
Timer/counter
4 bits x 2, or 8 bits x 1
Timer/counter 0: Timer register x 1
Capture register x 1
Compare register x 2
(16 bits)
Pulse output
• Toggle output
• PWM/PPG output
• One-shot pulse output
Timer/counter 1: Timer register x 1
Capture register x 1
Pulse output
• Real-time output (4 bits x 2)
(8/16 bits)
Capture/compare register x 1
Compare register x 1
Timer/counter 2: Timer register x 1
Capture register x 1
Pulse output
• Toggle output
• PWM/PPG output
(8/16 bits)
Capture/compare register x 1
Compare register x 1
Timer 3:
Timer register x 1
(8/16 bits)
Compare register x 1
PWM output
12-bit resolution x 2 channels
UART/IOE (3-wire serial I/O)
Serial interface
: 2 channels (on-chip baud rate generator)
2
CSI (3-wire serial I/O, 2-wire serial I/O, I C bus) : 1 channel
8-bit resolution x 8 channels
8-bit resolution x 2 channels
1 channel
A/D converter
D/A converter
Watchdog timer
Standby
HALT/STOP/IDLE mode
Interrupt
Hardware source 24 (internal: 17, external: 7 (variable sampling clock input: 1))
Software source
Non-maskable
Maskable
BRK instruction, BRKCS instruction, operand error
Internal: 1, external: 1
Internal: 16, external: 6
• 4 programmable priority levels
• 3 processing styles: vectored interrupt/macro service/context switching
Supply voltage
Package
VDD = 2.7 to 5.5 V
80-pin plastic QFP (14 x 14 mm, thickness 2.7 mm)
80-pin plastic QFP (14 x 14 mm, thickness 1.4 mm)
80-pin plastic TQFP (fine pitch) (12 x 12 mm)
Note The pins with ancillary function are included in the I/O pins.
3
µPD784031Y
CONTENTS
1. DIFFERENCES AMONG MODELS IN µPD784038Y SUBSERIES.................................................. 6
2. MAJOR DIFFERENCES FROM µPD784026 SUBSERIES AND µPD78234 SUBSERIES.............. 7
3. PIN CONFIGURATION (Top View)................................................................................................... 8
4. BLOCK DIAGRAM ............................................................................................................................ 10
5. PIN FUNCTION ............................................................................................................................... 11
5.1 Port Pins ................................................................................................................................................ 11
5.2 Non-port Pins ........................................................................................................................................ 12
5.3 Types of Pin I/O Circuits and Connections for Unused Pins............................................................ 14
6. CPU ARCHITECTURE .................................................................................................................... 17
6.1 Memory Space....................................................................................................................................... 17
6.2 CPU Registers ....................................................................................................................................... 19
6.2.1 General-purpose registers .......................................................................................................... 19
6.2.2 Control registers.......................................................................................................................... 20
6.2.3 Special function registers (SFRs) ............................................................................................... 21
7. PERIPHERAL HARDWARE FUNCTIONS ..................................................................................... 26
7.1 Ports ....................................................................................................................................................... 26
7.2 Clock Generation Circuit ...................................................................................................................... 27
7.3 Real-time Output Port ........................................................................................................................... 29
7.4 Timer/Counter........................................................................................................................................ 30
7.5 PWM Output (PWM0, PWM1)................................................................................................................ 32
7.6 A/D Converter ........................................................................................................................................ 33
7.7 D/A Converter ........................................................................................................................................ 34
7.8 Serial Interface ...................................................................................................................................... 35
7.8.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) ...................................................... 36
7.8.2 Clocked serial interface (CSI) ..................................................................................................... 38
7.9 Edge Detection Function ...................................................................................................................... 39
7.10 Watchdog Timer .................................................................................................................................... 40
8. INTERRUPT FUNCTION ................................................................................................................. 41
8.1 Interrupt Sources .................................................................................................................................. 41
8.2 Vectored Interrupt ................................................................................................................................. 43
8.3 Context Switching................................................................................................................................. 44
8.4 Macro Service........................................................................................................................................ 44
8.5 Application Example of Macro Service ............................................................................................... 45
4
µPD784031Y
9. LOCAL BUS INTERFACE .............................................................................................................. 47
9.1 Memory Expansion ............................................................................................................................... 47
9.2 Memory Space....................................................................................................................................... 48
9.3 Programmable Wait .............................................................................................................................. 49
9.4 Pseudo Static RAM Refresh Function................................................................................................. 49
9.5 Bus Hold Function ................................................................................................................................ 49
10. STANDBY FUNCTION .................................................................................................................... 50
11. RESET FUNCTION ......................................................................................................................... 51
12. INSTRUCTION SET ........................................................................................................................ 52
13. ELECTRICAL SPECIFICATIONS ................................................................................................... 57
14. PACKAGE DRAWINGS .................................................................................................................. 77
15. RECOMMENDED SOLDERING CONDITIONS .............................................................................. 80
APPENDIX A. DEVELOPMENT TOOLS ............................................................................................... 82
APPENDIX B. RELATED DOCUMENTS ............................................................................................... 84
5
µPD784031Y
1. DIFFERENCES AMONG MODELS IN µPD784038Y SUBSERIES
The only difference among the µPD784031Y, 784035Y, 784036Y, 784037Y, and 784038Y lies in the internal memory
capacity.
The µPD78P4038Y is provided with a 128-Kbyte one-time PROM or EPROM instead of the mask ROM of the
µPD784035Y, 784036Y, 784037Y, and 784038Y. These differences are summarized in Table 1-1.
Table 1-1. Differences among Models in µPD784038Y Subseries
Part Number
Item
µPD784031Y
µPD784035Y µPD784036Y
µPD784037Y
µPD784038Y µPD78P4038Y
Internal ROM
None
48 Kbytes
64 Kbytes
96 Kbytes
128 Kbytes
128 Kbytes
(mask ROM)
(mask ROM)
(mask ROM)
(mask ROM)
(one-time PROM
or EPROM)
Internal RAM
Package
2048 bytes
3584 bytes
4352 bytes
80-pin plastic QFP (14 x 14 mm, thickness 2.7 mm)
80-pin plastic QFP (14 x 14 mm, thickness 1.4 mm)
80-pin plastic TQFP (fine pitch) (12 x 12 mm)
80-pin ceramic
WQFN
(14 x 14 mm)
6
µPD784031Y
2. MAJOR DIFFERENCES FROM µPD784026 SUBSERIES AND µPD78234 SUBSERIES
Series Name
µPD784038Y Subseries
µPD784038 Subseries
µPD784026 Subseries
µPD78234 Subseries
Item
Number of basic instructions
(mnemonics)
113
65
Minimum instruction execution time
125 ns
160 ns
333 ns
(@ 32-MHz operation)
(@ 25-MHz operation)
(@ 12-MHz operation)
Memory space (program/data)
Timer/counter
1 Mbytes combined
64 Kbytes/1 Mbytes
16-bit timer/counter x 1
8-/16-bit timer/counter x 2
8-/16-bit timer x 1
16-bit timer/counter x 1
8-bit timer/counter x 2
8-bit timer x 1
Clock output function
Watchdog timer
Serial interface
Provided
Provided
None
None
UART/IOE (3-wire serial
I/O) x 2 channels
UART/IOE (3-wire serial
I/O) x 2 channels
UART x 1 channel
CSI (3-wire serial I/O, SBI)
x 1 channel
CSI (3-wire serial I/O,
CSI (3-wire serial I/O, SBI)
x 1 channel
2
2-wire serial I/O, I C
Note
bus
) x 1 channel
Interrupt
Context
Provided
None
switching
Priority
4 levels
2 levels
Standby function
Operating clock
Pin function
HALT/STOP/IDLE mode
HALT/STOP mode
Fixed to fXX/2
Selectable from fXX/2, fXX/4, fXX/8, and fXX/16
None
MODE pin
TEST pin
Specifies ROM-less mode
(always high level with
µPD78233 and 78237)
Device test pin
None
Usually, low level
Package
80-pin plastic QFP
80-pin plastic QFP
80-pin plastic QFP
(14 x 14 mm, thickness 2.7 mm)
(14 x 14 mm, thickness 2.7 mm)
(14 x 14 mm, thickness 2.7 mm)
80-pin plastic QFP
80-pin plastic TQFP
(fine pitch) (12 x 12 mm):
µPD784021 only
94-pin plastic QFP
(20 x 20 mm)
(14 x 14 mm, thickness 1.4 mm)
80-pin plastic TQFP
84-pin plastic QFJ
(1150 x 1150 mil)
(fine pitch) (12 x 12 mm)
80-pin ceramic WQFN
(14 x 14 mm):
80-pin ceramic WQFN
(14 x 14 mm):
94-pin ceramic WQFN
(20 x 20 mm):
µPD78P4026 only
µPD78P4038Y and
78P4038 only
µPD78P238 only
Note µPD784038Y Subseries only
7
µPD784031Y
3. PIN CONFIGURATION (Top View)
• 80-pin plastic QFP (14 x 14 mm, thickness 2.7 mm)
µPD784031YGC-3B9
• 80-pin plastic QFP (14 x 14 mm, thickness 1.4 mm)
µPD784031YGC-8BT
• 80-pin plastic TQFP (fine pitch) (12 x 12 mm)
µPD784031YGK-BE9
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
P32/SCK0/SCL
P33/SO0/SDA
P34/TO0
1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P74/ANI4
2
P73/ANI3
P72/ANI2
P71/ANI1
P70/ANI0
3
P35/TO1
4
P36/TO2
5
P37/TO3
6
VDD0
RESET
7
P17
V
DD1
X2
X1
8
P16
9
P15
10
11
12
13
14
15
16
17
18
19
20
P14/TxD2/SO2
P13/TxD2/SI2
P12/ASCK2/SCK2
P11/PWM1
P10/PWM0
VSS1
P00
P01
P02
Note
P03
TEST
P04
VSS0
P05
P06
ASTB
AD0
AD1
AD2
P07
P67/REFRQ/HLDAK
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Note Directly connect the TEST pin to VSS0.
8
µPD784031Y
A8 to A19
AD0 to AD7
ANI0 to ANI7
ANO0, ANO1
ASCK, ASCK2
ASTB
: Address Bus
P70 to P77
PWM0, PWM1
RD
: Port7
: Address/Data Bus
: Analog Input
: Pulse Width Modulation Output
: Read Strobe
: Refresh Request
: Reset
: Analog Output
REFRQ
: Asynchronous Serial Clock
: Address Strobe
RESET
RxD, RxD2
SCK0 to SCK2
SCL
: Receive Data
: Serial Clock
: Serial Clock
: Serial Data
: Serial Input
: Serial Output
: Test
AVDD
: Analog Power Supply
AVREF1 to AVREF3 : Reference Voltage
AVSS
: Analog Ground
: Clock Input
SDA
CI
SI0 to SI2
SO0 to SO2
TEST
HLDAK
HLDRQ
: Hold Acknowledge
: Hold Request
INTP0 to INTP5 : Interrupt from Peripherals
TO0 to TO3
TxD, TxD2
VDD0, VDD1
VSS0, VSS1
WAIT
: Timer Output
: Transmit Data
: Power Supply
: Ground
NMI
: Non-maskable Interrupt
P00 to P07
P10 to P17
P20 to P27
P30 to P37
: Port0
: Port1
: Port2
: Port3
: Wait
WR
: Write Strobe
: Crystal
P60 to P63, P66, P67 : Port6
X1, X2
9
µPD784031Y
4. BLOCK DIAGRAM
RxD/SI1
UART/IOE2
PROGRAMMABLE
INTERRUPT
CONTROLLER
NMI
TxD/SO1
BAUD-RATE
GENERATOR
INTP0 to INTP5
ASCK/SCK1
RxD2/SI2
TxD2/SO2
UART/IOE1
INTP3
TO0
TO1
TIMER/COUNTER0
(16 BITS)
BAUD-RATE
GENERATOR
ASCK2/SCK2
TIMER/COUNTER1
(16 BITS)
SCK0/SCL
SO0/SDA
SI0
CLOCKED
SERIAL
INTERFACE
INTP0
INTP1
INTP2/CI
TO2
TIMER/COUNTER2
(16 BITS)
ASTB
78K/IV
CPU CORE
AD0 to AD7
TO3
A8 to A15
A16 to A19
RD
WR
BUS I/F
TIMER3
(16 BITS)
WAIT/HLDRQ
REFRQ/HLDAK
P00 to P03
P04 to P07
REAL-TIME
OUTPUT PORT
PORT0
PORT1
PORT2
PORT3
P00 to P07
P10 to P17
P20 to P27
P30 to P37
PWM0
PWM1
PWM
RAM
ANO0
ANO1
AVREF2
AVREF3
D/A
CONVERTER
P60 to P63
P66 to P67
P70 to P77
PORT6
PORT7
ANI0 to ANI7
AVDD
A/D
CONVERTER
AVREF1
AVSS
RESET
TEST
X1
WATCHDOG
TIMER
SYSTEM
CONTROL
INTP5
X2
V
DD0,
V
DD1
VSS0,
V
SS1
10
µPD784031Y
5. PIN FUNCTION
5.1 Port Pins
Pin Name
I/O
I/O
Alternate Function
–
Function
Port 0 (P0):
P00 to P07
• 8-bit I/O port
• Can be used as real-time output port (4 bits x 2).
• Can be set in input or output mode bitwise.
• Pins set in input mode can be connected to internal pull-up
resistors by software.
• Can drive transistor.
Port 1 (P1):
P10
I/O
PWM0
• 8-bit I/O port
P11
PWM1
• Can be set in input or output mode bitwise.
• Pins set in input mode can be connected to internal pull-up
resistors by software.
P12
ASCK2/SCK2
RxD2/SI2
TxD2/SO2
–
P13
• Can drive LEDs.
P14
P15 to P17
P20
Port 2 (P2):
Input
NMI
• 8-bit input port
P21
INTP0
• P20cannotbeusedasgeneral-purposeportpin(non-maskable
interrupt). However, its input level can be checked by interrupt
routine.
P22
INTP1
P23
INTP2/CI
INTP3
• P22 through P27 can be connected to internal pull-up resistors
by software in 6-bit units.
P24
P25
INTP4/ASCK/SCK1
INTP5
• P25/INTP4/ASCK/SCK1 pin can operate as SCK1 output pin if
so specified by CSIM1.
P26
P27
SI0
Port 3 (P3):
P30
I/O
RxD/S1
• 8-bit I/O port
P31
TxD/SO1
SCK0/SCL
SO0/SDA
TO0 to TO3
A16 to A19
WAIT/HLDRQ
REFRQ/HLDAK
• Can be set in input or output mode bitwise.
• Pins set in input mode can be connected to internal pull-up
resistors by software.
P32
P33
P34 to P37
P60 to P63
P66
Port 6 (P6):
I/O
I/O
• P60 through P63 is dedicated ports for output.
• P66 and P67 can be set in input or output mode bitwise.
• Pins set in input mode can be connected to internal pull-up
resistors by software.
P67
P70 to P77
AN10 to AN17
Port 7 (P7):
• 8-bit I/O port
• Can be set in input or output mode bitwise.
11
µPD784031Y
5.2 Non-port Pins
Pin Name
TO0 to TO3
CI
I/O
Alternate Function
P34 to P37
P23/INTP2
P30/SI1
Function
Output
Input
Timer output
Count clock input to timer/counter 2
Serial data input (UART0)
RxD
Input
RxD2
TxD
P13/SI2
Serial data input (UART2)
Output
Input
P31/SO1
Serial data output (UART0)
Serial data output (UART2)
Baud rate clock input (UART0)
Baud rate clock input (UART2)
TxD2
ASCK
ASCK2
SDA
P14/SO2
P25/INTP4/SCK1
P12/SCK2
P33/SO0
2
I/O
Serial data input/output (2-wire serial I/O, I C bus)
SI0
Input
P27
Serial data input (3-wire serial I/O0)
SI1
P30/RxD
Serial data input (3-wire serial I/O1)
SI2
P13/RxD2
P33/SDA
P31/TxD
Serial data input (3-wire serial I/O2)
SO0
Output
I/O
Serial data output (3-wire serial I/O0)
Serial data output (3-wire serial I/O1)
Serial data output (3-wire serial I/O2)
Serial clock input/output (3-wire serial I/O0)
Serial clock input/output (3-wire serial I/O1)
Serial clock input/output (3-wire serial I/O2)
SO1
SO2
P14/TxD2
P32/SCL
SCK0
SCK1
SCK2
SCL
P25/INTP4/ASCK
P12/ASCK2
P32/SCK0
P20
2
Serial clock input/output (2-wire serial I/O, I C bus)
NMI
Input
External interrupt requests
–
INTP0
P21
• Count clock input to timer/counter 1
• Capture trigger signal of CR11 or CR12
INTP1
INTP2
INTP3
P22
• Count clock input to timer/counter 2
• Capture trigger signal of CR22
P23/CI
P24
• Count clock input to timer/counter 2
• Capture trigger signal of CR21
• Count clock input to timer/counter 0
• Capture trigger signal of CR02
INTP4
P25/ASCK/SCK1
–
Conversion start trigger input to A/D converter
Time-division address/data bus (for external memory connection)
Higher address bus (for external memory connection)
Higher address when address is extended (for external memory connection)
Read strobe to external memory
INTP5
P26
AD0 to AD7
A8 to A15
A16 to A19
RD
I/O
–
Output
Output
Output
Output
Input
–
P60 to P63
–
WR
–
Write strobe to external memory
WAIT
P66/HLDRQ
P67/HLDAK
Wait insertion
REFRQ
Output
Refresh pulse output to external pseudo static memory
HLDRQ
HLDAK
ASTB
Input
P66/WAIT
P67/REFRQ
–
Bus hold request input
Output
Output
Bus hold acknowledge output
Latch timing output of time-division address (A0 through A7)
(when accessing external memory)
12
µPD784031Y
Pin Name
RESET
I/O
Input
Input
–
Alternate Function
Function
–
–
Chip reset
X1
Crystal connection for system clock oscillation
(Clock can also be input to X1.)
Analog voltage input to A/D converter
Analog voltage output from D/A converter
Reference voltage to A/D converter
Reference voltage to D/A converter
A/D converter power supply
A/D converter GND
X2
ANI0 to ANI7
ANO0, ANO1
AVREF1
Input
Output
–
P70 to P77
–
–
AVREF2, AVREF3
AVDD
AVSS
VDD0Note 1
Power supply of port
VDD1Note 1
VSS0Note 2
VSS1Note 2
Power supply except for port
GND of port
GND except for port
TEST
Directly connect to VSS0 (IC test pin).
Notes 1. Provide the same potential to VDD0 and VDD1.
2. Provide the same potential to VSS0 and VSS1.
13
µPD784031Y
5.3 Types of Pin I/O Circuits and Connections for Unused Pins
Table 5-1 shows types of pin I/O circuits and the connections for unused pins.
For the input/output circuit of each type, refer to Figure 5-1.
Table 5-1. Types of Pin I/O Circuits and Connections for Unused Pins (1/2)
Pin Name
P00 to P07
I/O Circuit Type
5-H
I/O
Recommended Connection for Unused Pins
Input: Connect to VDD0.
I/O
P10/PWM0
P11/PWM1
Output: Open
P12/ASCK2/SCK2
P13/RxD2/SI2
P14/TxD2/SO2
P15 to P17
8-C
5-H
P20/NMI
2
Input
Connect to VDD0 or VSS0.
Connect to VDD0.
P21/INTP0
P22/INTP1
2-C
P23/INTP2/CI
P24/INTP3
P25/INTP4/ASCK/SCK1 8-C
I/O
Input: Connect to VDD0.
Output: Open
P26/INTP5
2-C
5-H
10-B
5-H
Input
Connect to VDD0.
P27/SI0
P30/RxD/SI1
P31/TxD/SO1
P32/SCK0/SCL
P33/SO0/SDA
P34/TO0 to P37/TO3
AD0 to AD7
I/O
Input: Connect to VDD0.
Output: Open
Note
A8 to A15
Output
Open
P60/A16 to P63/A19
RD
WR
P66/WAIT/HLDRQ
P67/REFRQ/HLDAK
P70/ANI0 to P77/ANI7
I/O
Input: Connect to VDD0.
Output: Open
20-A
Input: Connect to VDD0 or VSS0.
Output: Open
ANO0, ANO1
ASTB
12
Output
Open
4-B
Note I/O circuit type of these pins is 5-H. However these pins perform only as output by an internal circuit.
14
µPD784031Y
Table 5-1. Types of Pin I/O Circuits and Connections for Unused Pins (2/2)
Pin Name
RESET
I/O Circuit Type
I/O
Recommended Connection for Unused Pins
2
Input
–
TEST
1-A
Directly connect to VSS0.
Connect to VSS0.
AVREF1 to AVREF3
AVSS
–
AVDD
Connect to VDD0.
Caution Connect an I/O pin whose input/output mode is unstable to VDD0 via a resistor of several 10 kΩ
(especially if the voltage on the reset input pin rises higher than the low-level input level on power
application or when the mode is switched between input and output by software).
Remark Because the circuit type numbers shown in the above table are commonly used with all the models in the 78K
Series, these numbers of some models are not serial (because some circuits are not provided to some models).
15
µPD784031Y
Figure 5-1. Types of Pin I/O Circuits
Type 1-A
Type 2-C
VDD0
V
DD0
P
IN
pullup
enable
P
N
V
SS0
Type 2
IN
IN
Schmitt trigger input with hysteresis characteristics
Type 5-H
Schmitt trigger input with hysteresis characteristics
V
DD0
Type 4-B
pullup
enable
VDD0
P
V
DD0
data
P
data
P
OUT
IN/OUT
output
disable
N
output
disable
N
V
SS0
VSS0
input
enable
Push-pull output that can go into a high-impedance
state (with both P-ch and N-ch off)
Type 8-C
Type 12
VDD0
pullup
enable
P
V
DD0
P
data
Analog output voltage
OUT
P
N
IN/OUT
output
disable
N
V
SS0
Type 20-A
data
Type 10-B
V
DD0
V
DD0
P
N
pullup
enable
P
IN/OUT
V
DD0
output
disable
data
P
N
V
SS0
IN/OUT
P
N
Comparator
+
–
open drain
AVSS
output disable
AVREF (threshold voltage)
V
SS0
input
enable
16
µPD784031Y
6. CPU ARCHITECTURE
6.1 Memory Space
Amemoryspaceof1Mbytescanbeaccessed. Mappingoftheinternaldataarea(specialfunctionregistersandinternal
RAM) can be specified the LOCATION instruction. The LOCATION instruction must be always executed after reset
cancellation, and must not be used more than once.
(1) When LOCATION 0 instruction is executed
The internal data area is mapped in 0F700H to 0FFFFH.
(2) When LOCATION 0FH instruction is executed
The internal data area is mapped in FF700H to FFFFFH.
17
Figure 6-1. Memory Map of µPD784031Y
On execution of
On execution of
LOCATION 0 instruction
LOCATION 0FH instruction
F F F F FH
F F F F FH
F F FDFH
Special function registers (SFR)
F F FD0H
F F F 0 0H
(256 bytes)
F FEF FH
0 FEF FH
F FEF FH
General-purpose
registers (128 bytes)
Internal RAM
(2 Kbytes)
External memory
(960 Kbytes)
F F 7 0 0H
F F 6 F FH
0 FE 8 0H
0 FE 7 FH
F FE 8 0H
F FE 7 FH
F FE 31H
F FE 0 6H
0 FE 3 1H
0 FE 0 6H
1 0 0 0 0H
0 F F F FH
0 F FDFH
0 F FD0H
0 F F 0 0H
0 FEF FH
0 FD0 0H
0 FCF FH
Macro service control word
area (44 bytes)
Special function registers (SFR)
(256 bytes)
Data area (512 bytes)
0 FD0 0H
0 FCF FH
F FD0 0H
F FCF FH
External memory
(1046272 bytes)
Internal RAM
(2 Kbytes)
Program/data area
(1536 bytes)
0 F 7 0 0H
F F 7 0 0H
0 F 7 0 0H
0 F 6 F FH
Note
External memory
(63232 bytes)
0 1 0 0 0H
0 0 F F FH
0 0 F F FH
CALLF entry area
(2 Kbytes)
0 0 8 0 0H
0 0 7 F FH
0 0 8 0 0H
0 0 7 F FH
1 0 0 0 0H
0 F F F FH
Note
0 0 0 8 0H
0 0 0 7 FH
0 0 0 8 0H
0 0 0 7 FH
CALLT table area
(64 bytes)
0 0 0 4 0H
0 0 0 3 FH
Vector table area
(64 bytes)
µ
0 0 0 0 0H
0 0 0 0 0H
0 0 0 0 0H
Note Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.
µPD784031Y
6.2 CPU Registers
6.2.1 General-purpose registers
Sixteen 8-bit general-purpose registers are available. Two 8-bit registers can be also used in pairs as a 16-bit register.
Of the 16-bit registers, four can be used in combination with an 8-bit register for address expansion as 24-bit address
specification registers.
Eight banks of these registers are available which can be selected by using software or the context switching function.
The general-purpose registers except V, U, T, and W registers for address expansion are mapped to the internal RAM.
Figure 6-2. General-purpose Register Format
A (R1)
B (R3)
R5
X (R0)
C (R2)
R4
AX (RP0)
BC (RP1)
RP2
R7
R6
RP3
V
U
T
R9
R8
VP (RP4)
UP (RP5)
DE (RP6)
HL (RP7)
VVP (RG4)
UUP (RG5)
R11
R10
D (R13)
E (R12)
L (R14)
TDE (RG6)
H (R15)
W
8 banks
WHL (RG7)
Parentheses ( ) indicate an absolute name.
Caution Registers R4, R5, R6, R7, RP2, and RP3 can be used as X, A, C, B, AX, and BC registers, respectively,
by setting the RSS bit of the PSW to 1. However, use this function only for recycling the program of
the 78K/III Series.
19
µPD784031Y
6.2.2 Control registers
(1) Program counter (PC)
The program counter is a 20-bit register whose contents are automatically updated when the program is executed.
Figure 6-3. Program Counter (PC) Format
19
0
PC
(2) Program status word (PSW)
This register holds the statuses of the CPU. Its contents are automatically updated when the program is executed.
Figure 6-4. Program Status Word (PSW) Format
15
14
13
12
11
–
10
–
9
–
8
–
PSWH
PSWL
UF
RBS2
RBS1
RBS0
PSW
7
6
Z
5
4
3
2
1
0
0
S
RSSNote
AC
IE
P/V
CY
Note This flag is provided to maintain compatibility with the 78K/III Series. Be sure to clear this flag to 0, except when
the software for the 78K/III Series is used.
(3) Stack pointer (SP)
This is a 24-bit pointer that holds the first address of the stack.
Be sure to write 0 to the higher 4 bits of this pointer.
Figure 6-5. Stack Pointer (SP) Format
23
20
0
SP
0
0
0
0
20
µPD784031Y
6.2.3 Special function registers (SFRs)
The special function registers, such as the mode registers and control registers of the internal peripheral hardware, are
registers to which special functions are allocated. These registers are mapped to a 256-byte space of addresses 0FF00H
through 0FFFFHNote
.
Note On execution of the LOCATION 0 instruction. FFF00H through FFFFFH on execution of the LOCATION 0FH
instruction.
Caution Do not access an address in this area to which no SFR is allocated. If such an address is accessed by
mistake, the µPD784031Y may be in the deadlock status. This deadlock status can be cleared only by
inputting the reset signal.
Table 6-1 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows:
•
•
Symbol................................ Symbol indicating an SFR. This symbol is reserved for NEC’s assembler (RA78K4).
It can be used as an sfr variable by the #pragma sfr command with the C compiler
(CC78K4).
R/W..................................... Indicates whether the SFR is read-only, write-only, or read/write.
R/W : Read/write
R
: Read-only
: Write-only
W
•
Bit units for manipulation .... Bit units in which the value of the SFR can be manipulated.
SFRs that can be manipulated in 16-bit units can be described as the operand
sfrp of an instruction. To specify the address of this SFR, describe an even
address.
SFRs that can be manipulated in 1-bit units can be described as the operand of a
bit manipulation instruction.
•
After reset ........................... Indicates the status of the register when the RESET signal has been input.
21
µPD784031Y
Table 6-1. Special Function Registers (SFRs) (1/4)
Note
Address
Special Function Register (SFR) Name
Symbol
R/W
R/W
Bit Units for Manipulation
After Reset
Undefined
1 bit
√
√
√
√
√
√
√
√
–
–
–
–
–
–
–
–
–
–
–
–
√
√
√
√
√
√
–
√
–
–
8 bits
√
16 bits
0FF00H
0FF01H
0FF02H
0FF03H
0FF06H
0FF07H
0FF0EH
0FF0FH
0FF10H
0FF12H
0FF14H
0FF15H
0FF16H
0FF17H
0FF18H
0FF19H
0FF1AH
0FF1BH
0FF1CH
0FF1DH
0FF20H
0FF21H
0FF23H
0FF26H
0FF27H
0FF2EH
0FF30H
0FF31H
0FF32H
0FF33H
Port 0
P0
–
–
–
–
–
–
–
–
√
√
√
Port 1
Port 2
Port 3
Port 6
Port 7
P1
√
P2
R
√
P3
R/W
√
P6
√
00H
P7
√
Undefined
Port 0 buffer register L
P0L
√
Port 0 buffer register H
P0H
√
Compare register (timer/counter 0)
Capture/compare register (timer/counter 0)
Compare register L (timer/counter 1)
Compare register H (timer/counter 1)
Capture/compare register L (timer/counter 1)
Capture/compare register H (timer/counter 1)
Compare register L (timer/counter 2)
Compare register H (timer/counter 2)
Capture/compare register L (timer/counter 2)
Capture/compare register H (timer/counter 2)
Compare register L (timer 3)
CR00
CR01
CR10 CR10W
–
–
–
√
–
√
CR11 CR11W
–
√
√
√
√
–
√
CR20 CR20W
–
–
√
CR21 CR21W
–
–
√
CR30 CR30W
–
Compare register H (timer 3)
–
√
Port 0 mode register
PM0
–
–
–
–
–
–
–
–
–
–
FFH
Port 1 mode register
PM1
√
Port 3 mode register
PM3
√
Port 6 mode register
PM6
√
Port 7 mode register
PM7
√
Real-time output port control register
Capture/compare control register 0
Timer output control register
RTPC
CRC0
TOC
√
00H
10H
00H
√
√
Capture/compare control register 1
Capture/compare control register 2
CRC1
CRC2
√
√
10H
Note When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, “F0000H” is
added to this value.
22
µPD784031Y
Table 6-1. Special Function Registers (SFRs) (2/4)
AddressNote 1
Special Function Register (SFR) Name
Symbol
R/W
R
Bit Units for Manipulation
After Reset
0000H
1 bit
–
–
–
–
–
√
√
√
–
–
–
–
–
–
–
–
–
√
–
√
–
–
√
√
–
√
–
–
–
√
√
–
8 bits
–
√
–
√
–
√
√
√
–
–
√
–
√
–
√
–
√
√
√
√
√
√
√
√
√
√
√
–
–
√
√
√
√
√
16 bits
0FF36H
0FF38H
0FF39H
0FF3AH
0FF3BH
0FF41H
0FF43H
0FF4EH
0FF50H
0FF51H
0FF52H
0FF53H
0FF54H
0FF55H
0FF56H
0FF57H
0FF5CH
0FF5DH
0FF5EH
0FF5FH
0FF60H
0FF61H
0FF62H
0FF68H
0FF6AH
0FF70H
0FF71H
0FF72H
0FF74H
0FF7DH
0FF80H
0FF81H
0FF82H
0FF83H
Capture register (timer/counter 0)
Capture register L (timer/counter 1)
Capture register H (timer/counter 1)
Capture register L (timer/counter 2)
Capture register H (timer/counter 2)
Port 1 mode control register
CR02
√
√
CR12 CR12W
–
CR22 CR22W
–
√
PMC1
PMC3
PUO
R/W
R
–
–
–
√
00H
Port 3 mode control register
Pull-up resistor option register
Timer register 0
TM0
0000H
Timer register 1
Timer register 2
Timer register 3
TM1 TM1W
–
√
√
√
TM2 TM2W
–
TM3 TM3W
–
Prescaler mode register 0
Timer control register 0
PRM0
TMC0
PRM1
TMC1
DACS0
DACS1
DAM
R/W
–
–
–
–
–
–
–
–
–
–
–
√
√
–
–
–
–
–
11H
00H
11H
00H
Prescaler mode register 1
Timer control register 1
D/A conversion value setting register 0
D/A conversion value setting register 1
D/A converter mode register
A/D converter mode register
A/D conversion result register
PWM control register
03H
ADM
00H
ADCR
PWMC
PWPR
PWM0
PWM1
OSPC
IICC
R
Undefined
05H
R/W
PWM prescaler register
00H
PWM modulo register 0
Undefined
PWM modulo register 1
One-shot pulse output control register
00H
2
I C bus control register
Prescaler mode register for serial clock
Clocked serial interface mode register
Slave address register
SPRM
CSIM
04H
00H
01H
√
Note 3
SVA
R/WNote 2
√
Notes 1. When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, “F0000H”
is added to this value.
2. Bit 0 is read-only.
3. Only bit 0 can be manipulated in bit units.
23
µPD784031Y
Table 6-1. Special Function Registers (SFRs) (3/4)
AddressNote 1
Special Function Register (SFR) Name
Symbol
R/W
R/W
Bit Units for Manipulation
After Reset
00H
1 bit
√
√
–
√
√
√
√
–
–
–
–
–
–
–
–
√
√
–
√
√
√
√
√
–
–
√
√
√
–
–
8 bits
√
16 bits
0FF84H
0FF85H
0FF86H
0FF88H
0FF89H
0FF8AH
0FF8BH
0FF8CH
Clocked serial interface mode register 1
Clocked serial interface mode register 2
Serial shift register
CSIM1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
√
CSIM2
SIO
√
√
Asynchronous serial interface mode register
Asynchronous serial interface mode register 2
Asynchronous serial interface status register
Asynchronous serial interface status register 2
Serial receive buffer: UART0
ASIM
ASIM2
ASIS
√
√
R
√
ASIS2
RXB
√
√
Undefined
Serial transmit shift register: UART0
Serial shift register: IOE1
TXS
W
R/W
R
√
SIO1
√
0FF8DH
Serial receive buffer: UART2
RXB2
TXS2
SIO2
√
Serial transmit shift register: UART2
Serial shift register: IOE2
W
√
R/W
√
0FF90H
0FF91H
0FFA0H
0FFA1H
0FFA4H
0FFA8H
0FFAAH
0FFACH
0FFADH
0FFAEH
0FFC0H
0FFC2H
0FFC4H
0FFC5H
0FFC6H
0FFC7H
0FFC8H
Baud rate generator control register
Baud rate generator control register 2
External interrupt mode register 0
External interrupt mode register 1
Sampling clock select register
In-service priority register
BRGC
BRGC2
INTM0
INTM1
SCS0
ISPR
√
00H
√
√
√
√
R
√
Interrupt mode control register
Interrupt mask register 0L
IMC
R/W
√
80H
MK0L MK0
MK0H
MK1L
STBC
WDM
MM
√
FFFFH
Interrupt mask register 0H
√
Interrupt mask register 1L
√
–
–
–
–
–
–
–
√
FFH
30H
00H
20H
00H
Note 2
Standby control register
√
Note 2
Watchdog timer mode register
Memory expansion mode register
Hold mode register
√
√
√
√
√
–
HLDM
CLOM
PWC1
PWC2
Clock output mode register
Programmable wait control register 1
Programmable wait control register 2
AAH
AAAAH
Notes 1. When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, “F0000H”
is added to this value.
2. Data can be written by using only dedicated instructions such as MOV STBC, #byte and MOV WDM, #byte,
and cannot be written with any other instructions.
24
µPD784031Y
Table 6-1. Special Function Registers (SFRs) (4/4)
Note
Address
Special Function Register (SFR) Name
Symbol
R/W
R/W
Bit Units for Manipulation
After Reset
00H
1 bit
8 bits
16 bits
0FFCCH
0FFCDH
0FFCFH
Refresh mode register
RFM
√
√
–
√
√
√
–
–
–
Refresh area specification register
RFA
Oscillation stabilization time specification
register
OSTS
0FFD0H to External SFR area
0FFDFH
–
√
√
–
–
0FFE0H
0FFE1H
0FFE2H
0FFE3H
0FFE4H
0FFE5H
0FFE6H
0FFE7H
0FFE8H
0FFE9H
0FFEAH
0FFEBH
0FFECH
0FFEDH
0FFEEH
0FFEFH
Interrupt control register (INTP0)
PIC0
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
43H
Interrupt control register (INTP1)
Interrupt control register (INTP2)
Interrupt control register (INTP3)
Interrupt control register (INTC00)
Interrupt control register (INTC01)
Interrupt control register (INTC10)
Interrupt control register (INTC11)
Interrupt control register (INTC20)
Interrupt control register (INTC21)
Interrupt control register (INTC30)
Interrupt control register (INTP4)
Interrupt control register (INTP5)
Interrupt control register (INTAD)
Interrupt control register (INTSER)
Interrupt control register (INTSR)
Interrupt control register (INTCSI1)
Interrupt control register (INTST)
Interrupt control register (INTCSI)
Interrupt control register (INTSER2)
Interrupt control register (INTSR2)
Interrupt control register (INTCSI2)
Interrupt control register (INTST2)
Interrupt control register (INTSPC)
PIC1
PIC2
PIC3
CIC00
CIC01
CIC10
CIC11
CIC20
CIC21
CIC30
PIC4
PIC5
ADIC
SERIC
SRIC
CSIIC1
STIC
0FFF0H
0FFF1H
0FFF2H
0FFF3H
CSIIC
SERIC2
SRIC2
CSIIC2
STIC2
SPCIC
0FFF4H
0FFF5H
Note When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, “F0000H” is
added to this value.
25
µPD784031Y
7. PERIPHERAL HARDWARE FUNCTIONS
7.1 Ports
The ports shown in Figure 7-1 are provided to make various control operations possible. Table 7-1 shows the function
of each port. Ports 0 through 6 can be connected to internal pull-up resistors by software when inputting.
Figure 7-1. Port Configuration
P00
Port 0
P07
P10
Port 1
P17
P20 to P27
P30
8
Port 2
Port 3
P37
P60
Port 6
Port 7
P63
P66
P67
P70
P77
26
µPD784031Y
Table 7-1. Port Functions
Port Name
Port 0
Pin Name
Function
Specification of Pull-up Resistor
Connection by Software
P00 to P07
• Can be set in input or output mode in 1-bit units. All port pins in input mode
• Can operate as 4-bit real-time output port
(P00 through P03 and P04 through P07).
• Can drive transistor.
Port 1
P10 to P17
• Can be set in input or output mode in 1-bit units. All port pins in input mode
• Can drive LEDs.
Port 2
Port 3
Port 6
P20 to P27
P30 to P37
P60 to P63
P66, P67
• Input port
In 6-bit units (P22 through P27)
• Can be set in input or output mode in 1-bit units. All port pins in input mode
• Output only
All port pins in input mode
• Can be set in input or output mode in 1-bit units.
• Can be set in input or output mode in 1-bit units.
Port 7
P70 to P77
–
7.2 Clock Generation Circuit
Anon-chipclockgenerationcircuitnecessaryforoperationisprovided. Thisclockgenerationcircuithasadividercircuit.
If high-speed operation is not necessary, the internal operating frequency can be lowered by the divider circuit to reduce
the current consumption.
Figure 7-2. Block Diagram of Clock Generation Circuit
X1
f
XX
Oscillation
circuit
1/2
1/2
1/2
1/2
X2
f
CLK
CPU
Peripheral circuit
f
XX/2
UART/IOE
INTP0 noise reduction circuit
Oscillation stabilization timer
Remark fXX : oscillation frequency or external clock input
fCLK: internal operating frequency
27
µPD784031Y
Figure 7-3. Example of Using Oscillation Circuit
(1) Crystal/ceramic oscillation
PD784031Y
µ
V
SS1
X1
X2
(2) External clock
• EXTC bit of OSTS = 1
• EXTC bit of OSTS = 0
PD784031Y
PD784031Y
µ
µ
X1
X1
X2
Open
X2
µ
PD74HC04, etc.
Caution When using the clock oscillation circuit, wire the dotted portion in the above figure as follows to avoid
adverse influences of wiring capacitance.
•
•
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with other signal lines.
Do not route the wiring in the vicinity of lines through which a high alternating current flows.
Always keep the potential at the ground point of the capacitor in the oscillation circuit the same
as VSS1. Do not ground to a ground pattern through which a high current flows.
Do not extract signals from the oscillation circuit.
•
28
µPD784031Y
7.3 Real-time Output Port
The real-time output port outputs data stored in a buffer in synchronization with the coincidence interrupt generated by
timer/counter 1 or with an external interrupt. As a result, pulses without jitter can be output.
The real-time output port is therefore ideal for applications where arbitrary patterns must be output at specific intervals
(such as open loop control of a stepping motor).
The real-time output port mainly consists of port 0 and port 0 buffer registers (P0H and P0L) as shown in Figure 7-4.
Figure 7-4. Block Diagram of Real-time Output Port
Internal bus
8
4
4
Buffer register
Real-time output port
control register (RTPC)
8
P0H
4
P0L
4
INTP0 (from external source)
INTC10 (from timer/counter 1)
INTC11 (from timer/counter 1)
Output trigger
control circuit
Output latch (P0)
P07
P00
29
µPD784031Y
7.4 Timer/Counter
Three units of timers/counters and one unit of timer are provided.
Because a total of seven interrupt requests are supported, these timers/counters and timer can be used as seven units
of timers/counters.
Table 7-2. Operations of Timers/Counters
Name
Timer/Counter 0
Timer/Counter 1
Timer/Counter 2
Timer 3
Item
Count width
8 bits
–
√
√
√
√
16 bits
√
√
√
Interval timer
External event counter
One-shot timer
Timer output
Toggle output
PWM/PPG output
2ch
2ch
2ch
1ch
–
Operation
mode
√
√
√
–
–
√
–
Function
2ch
–
2ch
–
√
–
√
–
√
–
√
–
Note
One-shot pulse output
Real-time output
√
–
–
–
–
1 input
2
√
1 input
2
–
2 inputs
2
–
Pulse width measurement
Number of interrupt requests
–
1
Note Theone-shotpulseoutputfunctionmakesapulseoutputlevelactivebysoftwareandinactivebyhardware(interrupt
request signal).
This function is different in nature from the one-shot timer function of timer/counter 2.
30
µPD784031Y
Figure 7-5. Block Diagram of Timers/Counters
Timer/counter 0
Clear control
Software trigger
Timer register 0
fXX/8
Prescaler
OVF
(TM0)
Match
Match
Compare register
(CR00)
TO0
TO1
Compare register
(CR01)
Capture register
(CR02)
Edge detection
INTP3
INTC00
INTC01
INTP3
Timer/counter 1
Clear control
Timer register 1
(TM1/TM1W)
fXX/8
Prescaler
OVF
Event input
Match
Match
Compare register
(CR10/CR10W)
INTC10
To real-time output port
INTC11
Capture/Compare register
(CR11/CR11W)
Edge detection
INTP0
INTP0
Capture register
(CR12/CR12W)
Timer/counter 2
Clear control
Timer register 2
(TM2/TM2W)
Prescaler
OVF
TO2
TO3
fXX/8
Match
Match
Compare register
(CR20/CR20W)
Edge detection
INTP2/CI
Capture/Compare register
(CR21/CR21W)
INTP2
Capture register
(CR22/CR22W)
Edge detection
INTP1
INTC20
INTC21
INTP1
Timer 3
Clear
Timer register 3
(TM3/TM3W)
fXX/8
Prescaler
CSI
Match
Compare register
(CR30/CR30W)
INTC30
Remark OVF: overflow flag
31
µPD784031Y
7.5 PWM Output (PWM0, PWM1)
Two channels of PWM (pulse width modulation) output circuits with a resolution of 12 bits and a repeat frequency of
62.5 kHz (fCLK = 16 MHz) are provided. Both these PWM output channels can select a high or low level as the active level.
These outputs are ideal for controlling the speed of a DC motor.
Figure 7-6. Block Diagram of PWM Output Unit
Internal bus
16
8
PWM control
PWM modulo register
15
8 7
4 3
0
PWMn
register (PWMC)
8
4
Reload
control
Output
control
Pulse control circuit
4-bit counter
8-bit down counter
1/256
Prescaler
f
CLK
PWMn (output pin)
Remark n = 0 or 1
32
µPD784031Y
7.6 A/D Converter
An analog-to-digital (A/D) converter with eight multiplexed inputs (ANI0 through ANI7) is provided.
This A/D converter is of successive approximation type. The result of conversion is retained by an 8-bit A/D conversion
result register (ADCR). Therefore, high-speed, high-accuracy conversion can be performed (conversion time: approx. 7.5
µs at fCLK = 16 MHz).
A/D conversion can be started in either of the following two modes:
• Hardware start: Conversion is started by trigger input (INTP5).
• Software start: Conversion is started by setting a bit of the A/D converter mode register (ADM).
After started, the A/D converter operates in the following modes:
• Scan mode: Two or more analog inputs are sequentially selected, and data to be converted are obtained from all the
input pins.
• Select mode: Only one analog input pin is used to continuously obtain converted values.
These operation modes and whether starting or stopping the A/D converter are specified by the ADM.
When the result of conversion is transferred to the ADCR, interrupt request INTAD is generated. By using this request
and macro service, the converted values can be successively transferred to the memory.
Figure 7-7. Block Diagram of A/D Converter
ANI0
Series resistor string
Sample & hold circuit
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
AVREF1
R/2
R
Voltage comparator
Successive approximation
register (SAR)
Edge
detection
circuit
Conversion trigger
INTAD
INTP5
Control
Circuit
R/2
AVSS
Trigger enable
8
A/D converter mode
register (ADM)
A/D conversion result
register (ADCR)
8
8
Internal bus
33
µPD784031Y
7.7 D/A Converter
Two circuits of digital-to-analog (D/A) converters are provided. These D/A converters are of voltage output type and
have a resolution of 8 bits.
The conversion method is of R-2R resistor ladder type. By writing a value to be output to an 8-bit D/A conversion value
setting register (DACSn: n = 0 or 1), an analog value is output to the ANOn (n = 0 or 1) pin. The output voltage range is
determined by the voltage applied across the AVREF2 and AVREF3 pins.
Because the output impedance is high, no current can be extracted from the output. If the impedance of the load is low,
insert a buffer amplifier between the load and output pin.
TheANOnpingoesintoahigh-impedancestatewhiletheRESETsignalislow. Afterreleasingreset, DACSniscleared
to 0.
Figure 7-8. Block Diagram of D/A Converter
ANOn
2R
AVREF2
R
2R
Selector
R
2R
AVREF3
R
2R
DACSn
DACEn
Internal bus
Remark n = 0 or 1
34
µPD784031Y
7.8 Serial Interface
Three independent serial interface channels are provided.
Asynchronous serial interface (UART)/3-wire serial I/O (IOE) x 2
Clocked serial interface (CSI) x 1
• 3-wire serial I/O (IOE)
• 2-wire serial I/O (IOE)
• I2C bus interface (I2C)
Therefore, communication with an external system and local communication within the system can be simultaneously
executed (refer to Figure 7-9).
Figure 7-9. Example of Serial Interface
(a) UART + I2C
µ
PD784031Y (master)
V
DD
VDD
µ
PD6272 (EEPROMTM
)
µPD4711A
2
[I C]
[UART]
SDA
SCL
SDA
RxD
RS-232-C
driver/receiver
SCL
TxD
Port
µ
PD78062Y (slave)
µPD4711A
SDA
SCL
LCD
[UART]
RxD2
TxD2
RS-232-C
driver/receiver
Port
(b) UART + 3-wire serial I/O + 2-wire serial I/O
µ
PD784031Y (master)
µ
PD75108 (slave)
[3-wire serial I/O]
µPD4711A
SO1
SI
[UART]
SI1
SO
SCK
Port
INT
RxD
SCK1
RS-232-C
driver/receiver
TxD
Note
INTPm
Port
Port
VDD
VDD
µ
PD78014 (slave)
SDA
SCL
SB0
SCK0
Port
Note
INTPn
Port
INT
[2-wire serial I/O]
Note Handshake line
35
µPD784031Y
7.8.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE)
Two channels of serial interfaces that can select an asynchronous serial interface mode and 3-wire serial I/O mode are
provided.
(1) Asynchronous serial interface mode
In this mode, data of 1 byte following the start bit is transferred or received.
Because an on-chip baud rate generator is provided, a wide range of baud rates can be set.
Moreover, the clock input to the ASCK pin can be divided to define a baud rate.
When the baud rate generator is used, a baud rate conforming to the MIDI standard (31.25 kbps) can be also
obtained.
Figure 7-10. Block Diagram in Asynchronous Serial Interface Mode
Internal bus
Receive buffer RXB, RXB2
Receive shift
register
Transmit shift
register
R
X
D, R
X
D2
D2
TXS, TXS2
T D, T
X
X
INTSR,
INTSR2
Transmit control
parity append
Receive control
parity check
INTST, INTST2
INTSER,
INTSER2
Baud rate generator
1/2m
1/2m
f
XX/2
n + 1
1/2
ASCK, ASCK2
Remark fXX: oscillation frequency or external clock input
n = 0 through 11
m = 16 through 30
36
µPD784031Y
(2) 3-wire serial I/O mode
In this mode, the master device starts transfer by making the serial clock active and transfers 1-byte data in
synchronization with this clock.
This mode is used to communicate with a device having the conventional clocked serial interface. Basically,
communication is established by using three lines: one serial clock (SCK) and two serial data (SI and SO) lines.
Generally, to check the communication status, a handshake line is necessary.
Figure 7-11. Block Diagram in 3-wire Serial I/O Mode
Internal bus
Direction control circuit
SIO1, SIO2
Shift register
Output latch
SI1, SI2
SO1, SO2
Interrupt signal
generation circuit
INTCSI1,
INTCSI2
SCK1, SCK2
Serial clock counter
n + 1
1/m
1/2
fXX/2
Serial clock
control circuit
Remark fXX: oscillation frequency or external clock input
n = 0 through 11
m = 1 or 16 through 30
37
µPD784031Y
7.8.2 Clocked serial interface (CSI)
In this mode, the master device starts transfer by making the serial clock active and communicates 1-byte data in
synchronization with this clock.
Figure 7-12. Block Diagram of Clocked Serial Interface
Internal bus
Direction
Slave address
control
register
register
Match signal
Set
Reset
SI0
Selector
Shift register
Output latch
SO0/SDA
Acknowledge
detection
control
N-ch open drain output
(in 2-wire or I C bus mode)
Start condition
detection circuit
2
Acknowledge
detection circuit
Wake-up
control circuit
Stop condition
detection circuit
INTSPC
Interrupt signal
generation
circuit
Serial clock
counter
SCK0/SCL
INTCSI
Timer 3 output
Serial clock
control circuit
Selector
fXX/16
N-ch open drain output
2
(in 2-wire or I C bus mode)
CLS0
CLS1
Selector
Prescaler
fXX/2
Remark fXX: oscillation frequency or external clock input
38
µPD784031Y
(1) 3-wire serial I/O mode
This mode is to communicate with devices having the conventional clocked serial interface.
Basically, communication is established in this mode with three lines: one serial clock (SCK0) and two serial data
(SI0 and SO0) lines.
Generally, a handshake line is necessary to check the communication status.
(2) 2-wire serial I/O mode
This mode is to transfer 8-bit data by using two lines: serial clock (SCL) and serial data bus (SDA).
Generally, a handshake line is necessary to check the communication status.
(3) I2C (Inter IC) bus mode
This mode is to communicate with devices conforming to the I2C bus format.
This mode is to transfer 8-bit data with two or more devices by using two lines: serial clock (SCL) and serial data
bus (SDA).
During transfer, a “start condition”, “data”, and “stop condition” can be output onto the serial data bus. During
reception, these data can be automatically detected by hardware.
7.9 Edge Detection Function
The interrupt input pins (NMI and INTP0 through INTP5) are used not only to input interrupt requests but also to input
triggersignalstotheinternalhardwareunits. Becausethesepinsoperateatanedgeoftheinputsignal,theyhaveafunction
to detect an edge. Moreover, a noise reduction circuit is also provided to prevent erroneous detection due to noise.
Pin Name
Detectable Edge
Noise Reduction
By analog delay
NMI
Either of rising or falling edge
INTP0 to INTP3
INTP4, INTP5
Either or both of rising and falling edges
By clock samplingNote
By analog delay
Note INTP0 can select a sampling clock.
39
µPD784031Y
7.10 Watchdog Timer
A watchdog timer is provided to detect a hang up of the CPU. This watchdog timer generates a non-maskable interrupt
unless it is cleared by software within a specified interval time. Once enabled to operate, the watchdog timer cannot be
stoppedbysoftware. WhethertheinterruptbythewatchdogtimerortheinterruptinputfromtheNMIpintakesprecedence
can be specified.
Figure 7-13. Block Diagram of Watchdog Timer
Timer
f
CLK
21
20
19
17
fCLK/2
fCLK/2
fCLK/2
fCLK/2
INTWDT
Clear signal
40
µPD784031Y
8. INTERRUPT FUNCTION
As the servicing in response to an interrupt request, the three types shown in Table 8-1 can be selected by program.
Table 8-1. Servicing of Interrupt Request
Servicing Mode
Vector interrupt
Entity of Servicing
Software
Servicing
Contents of PC and PSW
Branches and executes servicing routine
(servicing is arbitrary).
Saves to and restores
from stack.
Context switching
Macro service
Automatically switches register bank,
branches and executes servicing routine
(servicing is arbitrary).
Saves to or restores from
fixed area in register bank.
Firmware
Executes data transfer between memory
and I/O (servicing is fixed).
Retained
8.1 Interrupt Sources
Table 8-2 shows the interrupt sources available. As shown, interrupts are generated by 24 types of sources, execution
of the BRK instruction or BRKCS instruction, or an operand error.
The priority of interrupt servicing can be set to four levels, so that nesting can be controlled during interrupt servicing
and that which of the two or more interrupts that simultaneously occur should be serviced first. When the macro service
function is used, however, nesting always proceeds.
Thedefaultpriorityisthepriority(fixed)oftheservicethatisperformediftwoormoreinterruptrequests,havingthesame
request, simultaneously generate (refer to Table 8-2).
41
µPD784031Y
Table 8-2. Interrupt Sources
Type
Default
Priority
–
Source
Trigger
Internal/
External
–
Macro Service
–
Name
Software
BRK instruction Instruction execution
BRKCS instruction
Operand error
If result of exclusive OR between byte of operand and
byte is not FFH when MOV STBC, #byte, MOV WDM,
#byte, or LOCATION instruction is executed
Non-maskable
Maskable
–
NMI
Detection of pin input edge
Overflow of watchdog timer
External
Internal
External
–
WDT
0 (highest) INTP0
Detection of pin input edge
√
(TM1/TM1W capture trigger, TM1/TM1W event counter input)
1
2
3
INTP1
INTP2
INTP3
Detection of pin input edge
(TM2/TM2W capture trigger, TM2/TM2W event counter input)
Detection of pin input edge
(TM2/TM2W capture trigger, TM2/TM2W event counter input)
Detection of pin input edge
(TM0 capture trigger, TM0 event counter input)
4
5
6
INTC00
INTC01
INTC10
Generation of TM0-CR00 match signal
Generation of TM0-CR01 match signal
Internal
√
Generation of TM1-CR10 match signal
(in 8-bit operation mode)
Generation of TM1W-CR10W match signal
(in 16-bit operation mode)
7
INTC11
INTC20
INTC21
INTC30
Generation of TM1-CR11 match signal
(in 8-bit operation mode)
Generation of TM1W-CR11W match signal
(in 16-bit operation mode)
8
Generation of TM2-CR20 match signal
(in 8-bit operation mode)
Generation of TM2W-CR20W match signal
(in 16-bit operation mode)
9
Generation of TM2-CR21 match signal
(in 8-bit operation mode)
Generation of TM2W-CR21W match signal
(in 16-bit operation mode)
10
Generation of TM3-CR30 match signal
(in 8-bit operation mode)
Generation of TM3W-CR30W match signal
(in 16-bit operation mode)
11
12
13
14
15
INTP4
Detection of pin input edge
External
Internal
√
INTP5
Detection of pin input edge
INTAD
End of A/D conversion (transfer of ADCR)
Occurrence of ASI0 reception error
End of ASI0 reception or CSI1 transfer
√
–
√
INTSER
INTSR
INTCSI1
INTST
16
17
18
19
End of ASI0 transfer
INTCSI
INTSER2
INTSR2
INTCSI2
INTST2
End of CSI1 transfer
Occurrence of ASI2 reception error
End of ASI2 reception or CSI2 transfer
–
√
20
End of ASI2 transfer
2
21 (lowest) INTSPC
I C bus stop condition interrupt
Remark ASI: asynchronous serial interface
CSI: clocked serial interface
42
µPD784031Y
8.2 Vectored Interrupt
Execution branches to a servicing routing by using the memory contents of a vector table address corresponding to
the interrupt source as the address of the branch destination.
So that the CPU performs interrupt servicing, the following operations are performed:
• On branching : Saves the status of the CPU (contents of PC and PSW) to stack
• On returning : Restores the status of the CPU (contents of PC and PSW) from stack
To return to the main routine from an interrupt service routine, the RETI instruction is used.
The branch destination address is in a range of 0 to FFFFH.
Table 8-3. Vector Table Address
Interrupt Source
BRK instruction
Operand error
NMI
Vector Table Address
003EH
003CH
0002H
0004H
0006H
0008H
000AH
000CH
000EH
0010H
0012H
0014H
0016H
0018H
001AH
001CH
001EH
0020H
0022H
0024H
WDT
INTP0
INTP1
INTP2
INTP3
INTC00
INTC01
INTC10
INTC11
INTC20
INTC21
INTC30
INTP4
INTP5
INTAD
INTSER
INTSR
INTCSI1
INTST
0026H
0028H
002AH
002CH
INTCSI
INTSER2
INTSR2
INTCSI2
INTST2
INTSPC
002EH
0030H
43
µPD784031Y
8.3 Context Switching
When an interrupt request is generated or when the BRKCS instruction is executed, a predetermined register bank is
selected by hardware. Context switching is a function that branches execution to a vector address stored in advance in
the register bank, and to stack the current contents of the program counter (PC) and program status word (PSW) to the
register bank.
The branch address is in a range of 0 to FFFFH.
Figure 8-1. Context Switching Operation when Interrupt Request is Generated
Register bank n
0000B
<7> Transfer
(0 to 7)
Register bank n (n = 0 to 7)
PC19 to 16
PC15 to 0
A
B
X
C
<6> Exchange
<5> Save
R5
R7
R4
R6
<2> Save
(bits 8 through 11
of temporary register)
VP
UP
V
U
<3> Switching of register bank
Temporary register
(RBS0 to RBS2 ← n)
D
H
E
L
T
<4> RSS ← 0
IE ← 0
W
<1> Save
PSW
8.4 Macro Service
Thisfunctionistotransferdatabetweenmemoryandaspecialfunctionregister(SFR)withoutinterventionbytheCPU.
A macro service controller accesses the memory and SFR in the same transfer cycle and directly transfers data without
loading it.
Because this function does not save or restore the status of the CPU, or load data, data can be transferred at high
speeds.
Figure 8-2. Macro Service
Read
Write
Write
Read
Macro service
controller
CPU
Memory
SFR
Internal bus
44
µPD784031Y
8.5 Application Example of Macro Service
(1) Transfer of serial interface
Transfer data storage buffer (memory)
Data n
Data n – 1
Data 2
Data 1
Internal bus
TxD
TXS (SFR)
Transfer shift register
Transfer control
INTST
Each time macro service request INTST is generated, the next transfer data is transferred from memory to TXS. When
datan(lastbyte)hasbeentransferredtoTXS(whenthetransferdatastoragebufferhasbecomeempty),vectoredinterrupt
request INTST is generated.
(2) Reception of serial interface
Receive data storage buffer (memory)
Data n
Data n – 1
Data 2
Data 1
Internal bus
Receive buffer
RXB (SFR)
RxD
Receive shift register
Reception control
INTSR
Each time macro service request INTSR is generated, the receive data is transferred from RXB to memory. When data
n (last byte) has been transferred to memory (when the receive data storage buffer has become full), vectored interrupt
request INTSR is generated.
45
µPD784031Y
(3) Real-time output port
INTC10 and INTC11 serve as the output triggers of the real-time output port. The macro services for these can
set the following output pattern and intervals simultaneously. Therefore, INTC10 and INTC11 can control two
stepping motors independently of each other. They can also be used for PWM output or to control DC motors.
Output pattern profile (memory)
Pn
Output timing profile (memory)
Tn
Pn – 1
Tn – 1
P2
P1
T2
T1
Internal bus
Internal bus
Match
(SFR)
(SFR)
P0L
CR10
TM1
INTC10
Output latch
P00 to P03
EachtimemacroservicerequestINTC10isgenerated,thepatternandtimingaretransferredtothebufferregister(P0L)
and compare register (CR10), respectively. When the contents of the timer register 1 (TM1) coincide with those of CR10,
INTC10isgeneratedagain,andthecontentsofP0Laretransferredtotheoutputlatch. WhenTn(lastbyte)hastransferred
to CR10, vectored interrupt request INTC10 is generated.
The same applies to INTC11.
46
µPD784031Y
9. LOCAL BUS INTERFACE
The local bus interface can connect an external memory or I/O (memory mapped I/O) and support a memory space
of 1 Mbytes (refer to Figure 9-1).
Figure 9-1. Example of Local Bus Interface
µ
PD784031Y
A16 to A19
RD
WR
Character
generator
PD24C1000
PROM
PD27C1001A
Pseudo SRAM
µ
µ
REFRQ
AD0 to AD7
Data bus
ASTB
Latch
Address bus
A8 to A15
Gate array
I/O expansion
Centronics I/F, etc.
9.1 Memory Expansion
The memory capacity can be expanded in seven steps, from 256 bytes to 1 Mbytes, by connecting an external program
memory and data memory.
47
µPD784031Y
9.2 Memory Space
The 1-Mbyte memory space is divided into eight spaces of logical addresses. Each space can be controlled by using
the programmable wait function and pseudo static RAM refresh function.
Figure 9-2. Memory Space
F F F F FH
512 Kbytes
8 0 0 0 0 H
7 F F F FH
256 Kbytes
4 0 0 0 0 H
3 F F F FH
128 Kbytes
2 0 0 0 0 H
1 F F F FH
64 Kbytes
1 0 0 0 0 H
0 F F F FH
16 Kbytes
0 C 0 0 0 H
0 B F F FH
16 Kbytes
0 8 0 0 0 H
0 7 F F FH
16 Kbytes
0 4 0 0 0 H
0 3 F F FH
16 Kbytes
0 0 0 0 0 H
48
µPD784031Y
9.3 Programmable Wait
The memory space can be divided into eight spaces and wait states can be independently inserted in each of these
spaces while the RD and WR signals are active. Even when a memory with a different access time is connected, therefore,
the efficiency of the entire system does not drop.
In addition, an address wait function that extends the active period of the ASTB signal is also provided so as to have
a sufficient address decode time (this function can be set to the entire space).
9.4 Pseudo Static RAM Refresh Function
The following refresh operations can be performed:
• Pulse refresh
: A bus cycle that outputs a refresh pulse to the REFRQ pin at a fixed cycle is inserted. The
memory spaces is divided into eight spaces, and a refresh pulse can be output from the
REFRQ pin while a specified memory space is accessed. Therefore, the normal memory
access is not kept to wait by the refresh cycle.
• Power-down self-refresh : The low level is output to the REFRQ pin in the standby mode to retain the contents of the
pseudo static RAM.
9.5 Bus Hold Function
A bus hold function is provided to facilitate connection of a DMA controller. When a bus hold request signal (HLDRQ)
is received from an external bus master, the address bus, address/data bus, and ASTB, RD, and WR pins go into a high-
impedance state when the current bus cycle has been completed. This makes the bus hold acknowledge (HLDAK) signal
active, and releases the bus to the external bus master.
Note that, while the bus hold function is used, the external wait function and pseudo static RAM refresh function cannot
be used.
49
µPD784031Y
10. STANDBY FUNCTION
This function is to reduce the power dissipation of the chip, and can be used in the following modes:
• HALT mode : Stops supply of the operating clock to the CPU. This mode is used in combination with the normal
operation mode for intermittent operation to reduce the average power dissipation.
• IDLE mode : Stops the entire system with the oscillation circuit continuing operation. The power dissipation in this
mode is close to that in the STOP mode. However, the time required to restore the normal program
operation from this mode is almost the same as that from the HALT mode.
• STOP mode : Stopstheoscillatorandtherebytostopalltheinternaloperationsofthechip. Consequently, thepower
dissipation is minimized with only leakage current flowing.
These modes are programmable.
The macro service can be started from the HALT mode.
Figure 10-1. Transition of Standby Status
Macro service request
End of one processing
End of macro service
Program
operation
Macro
service
Waits for
oscillation
stabilization
NMI, INTP4, INTP5 input
STOP
(standby)
IDLE
(standby)
HALT
(standby)
Interrupt request of
masked interrupt
Notes 1. When INTP4 and INTP5 are not masked
2. Only interrupt requests that are not masked
Remark Only the externally input NMI is valid. The watchdog timer cannot be used to release the standby mode (STOP/
IDLE mode).
50
µPD784031Y
11. RESET FUNCTION
When the low level is input to the RESET pin, the internal hardware is initialized (reset status).
When the RESET pin goes high, the following data are set to the program counter (PC).
• Lower 8 bits of PC : contents of address 0000H
• Middle 8 bits of PC : contents of address 0001H
• Higher 4 bits of PC : 0
Program execution is started from a branch destination address which is the contents of the PC. Therefore, the system
can be reset and started from any address.
Set the contents of each register by program as necessary.
TheRESETinputcircuithasanoisereductioncircuittopreventmalfunctioningduetonoise. Thisnoisereductioncircuit
is a sampling circuit by analog delay.
Figure 11-1. Accepting Reset Signal
Executes instruction at
reset start address
Delay
Delay
Delay
Initialize PC
RESET
(input)
Internal reset signal
Reset starts
Reset ends
Assert the RESET signal active until the oscillation stabilization time (approx. 40 ms) elapses to execute a power-ON
reset operation.
Figure 11-2. Power-ON Reset Operation
Executes instruction at
reset start address
Oscillation stabilization time
Delay
Initialize PC
VDD
RESET
(input)
Internal reset signal
Reset ends
51
µPD784031Y
12. INSTRUCTION SET
(1) 8-bit instructions (The instructions in parentheses are combinations realized by describing A as r)
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC,SHR,SHL,ROR4,DBNZ,PUSH,POP,MOVM,XCHM,CMPME,CMPMNE,CMPMNC,CMPMC,MOVBK,
XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHIKL, CHKLA
Table 12-1. Instruction List by 8-bit Addressing
Second Operand
#byte
A
r
saddr
saddr'
sfr
!addr16
!!addr24
mem
r3
[WHL+]
[WHL–]
n
NoneNote 2
r'
[saddrp]
[%saddrg]
PSWL
PSWH
First Operand
A
Note 6
(MOV)
(MOV)
MOV
XCH
(MOV)
(XCH)
MOV
(MOV)
(XCH)
MOV
XCH
MOV
(MOV)
(XCH)
ADDNote 1 (XCH)
(XCH)
Note 6
Note 1
Note 1
Note 1,6
Note 1
Note 1
Note 1
Note 1
(ADD)
(ADD)
(ADD)
(ADD)
ADD
ADD
(ADD)
r
MOV
(MOV)
MOV
XCH
MOV
XCH
MOV
XCH
MOV
XCH
RORNote 3 MULU
ADDNote 1 (XCH)
DIVUW
INC
Note 1
(ADD)
ADDNote 1 ADDNote 1 ADDNote 1
DEC
Note 6
Note 1
saddr
sfr
MOV
(MOV)
MOV
MOV
XCH
INC
DEC
ADDNote 1 (ADD)
ADDNote 1
ADDNote 1
DBNZ
MOV
MOV
MOV
PUSH
POP
Note 1
Note 1
ADDNote 1 (ADD)
ADD
CHKL
CHKLA
!addr16
!!addr24
MOV
(MOV)
MOV
ADDNote 1
mem
MOV
[saddrp]
[%saddrg]
ADDNote 1
mem3
ROR4
ROL4
r3
MOV
MOV
MOV
PSWL
PSWH
B, C
DBNZ
STBC, WDM
Note 5
[TDE+]
[TDE–]
(MOV)
MOVBK
(ADD)Note 1
Note 4
MOVM
Notes 1. The operands of ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as that of ADD.
2. Either the second operand is not used, or the second operand is not an operand address.
3. The operands of ROL, RORC, ROLC, SHR, and SHL are the same as that of ROR.
4. The operands of XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as that of MOVM.
5. The operands of XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as that of MOVBK.
6. The code length of some instructions having saddr2 as saddr in this combination is short.
52
µPD784031Y
(2) 16-bit instructions (The instructions in parentheses are combinations realized by describing AX as rp)
MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP,
ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW
Table 12-2. Instruction List by 16-bit Addressing
Second Operand
#word
AX
rp
saddrp
saddrp'
sfrp
!addr16
mem
[WHL+]
byte
n
NoneNote 2
rp'
!!addr24 [saddrp]
[%saddrg]
First Operand
AX
(MOVW) (MOVW) (MOVW) (MOVW)Note 3 MOVW
(MOVW)
XCHW
MOVW
XCHW
(MOVW)
(XCHW)
ADDWNote 1 (XCHW) (XCHW) (XCHW)Note 3 (XCHW)
Note 1
(ADD)Note 1 (ADDW)
(ADDW)Note 1,3 (ADDW)Note 1
rp
MOVW
(MOVW)
MOVW
XCHW
MOVW
XCHW
MOVW
XCHW
MOVW
SHRW MULWNote 4
ADDWNote 1 (XCHW)
SHLW
INCW
Note 1
Note 1
Note 1
(ADDW)
ADDWNote 1 ADDW
ADDW
DECW
saddrp
sfrp
MOVW (MOVW)Note 3 MOVW
ADDWNote 1 (ADDW)Note 1 ADDWNote 1 XCHW
MOVW
INCW
DECW
Note 1
ADDW
MOVW
MOVW
MOVW
PUSH
POP
Note 1
Note 1
Note 1
ADDW
(ADDW)
ADDW
!addr16
!!addr24
MOVW
(MOVW)
MOVW
MOVW
MOVTBLW
mem
[saddrp]
[%saddrg]
PSW
PUSH
POP
SP
ADDWG
SUBWG
post
PUSH
POP
PUSHU
POPU
[TDE+]
byte
(MOVW)
SACW
MACW
MACSW
Notes 1. The operands of SUBW and CMPW are the same as that of ADDW.
2. Either the second operand is not used, or the second operand is not an operand address.
3. The code length of some instructions having saddrp2 as saddrp in this combination is short.
4. The operands of MULUW and DIVUX are the same as that of MULW.
53
µPD784031Y
(3) 24-bit instructions (The instructions in parentheses are combinations realized by describing WHL as rg)
MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP
Table 12-3. Instruction List by 24-bit Addressing
Second Operand #imm24
First Operand
WHL
rg
saddrg
!!addr24
mem1
[%saddrg]
SP
NoneNote
rg'
WHL
(MOVG) (MOVG) (MOVG) (MOVG) (MOVG)
MOVG
MOVG
MOVG
(ADDG)
(SUBG)
(ADDG)
(SUBG)
(ADDG)
(SUBG)
ADDG
SUBG
rg
MOVG
ADDG
SUBG
(MOVG)
(ADDG)
(SUBG)
MOVG
ADDG
SUBG
MOVG
MOVG
INCG
DECG
PUSH
POP
saddrg
!!addr24
mem1
(MOVG)
(MOVG)
MOVG
MOVG
MOVG
MOVG
MOVG
[%saddrg]
SP
MOVG
INCG
DECG
Note Either the second operand is not used, or the second operand is not an operand address.
54
µPD784031Y
(4) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET
Table 12-4. Bit Manipulation Instructions
Second Operand
CY
saddr.bit sfr.bit
A.bit X.bit
/saddr.bit /sfr. bit
/A.bit /X.bit
NoneNote
PSWL.bit PSWH.bit
mem2.bit
/PSWL.bit /PSWH.bit
/mem2.bit
First Operand
CY
!addr16.bit !!addr24.bit
/!addr16.bit /!!addr24.bit
MOV1
AND1
OR1
AND1
OR1
NOT1
SET1
CLR1
XOR1
saddr.bit
sfr.bit
MOV1
NOT1
SET1
CLR1
BF
A.bit
X.bit
PSWL.bit
PSWH.bit
mem2.bit
!addr16.bit
!!addr24.bit
BT
BTCLR
BFSET
Note Either the second operand is not used, or the second operand is not an
operand address.
55
µPD784031Y
(5) Call and return/branch instructions
CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL,
BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ
Table 12-5. Call and Return/Branch Instructions
Operand of Instruction
Address
$addr20 $!addr20 !addr16 !!addr20
rp
rg
[rp]
[rg]
!addr11 [addr5]
RBn
None
Basic instruction
BCNote CALL
CALL
BR
CALL
BR
CALL
BR
CALL
BR
CALL
BR
CALL
BR
CALLF CALLF BRKCS BRK
BR
BR
RET
RETCS
RETCSB
RETI
RETB
Compound instruction
BF
BT
BTCLR
BFSET
DBNZ
Note The operands of BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH,
and BH are the same as BC.
(6) Other instructions
ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS
56
µPD784031Y
13. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
VDD
Test Conditions
Ratings
Unit
V
–0.5 to +7.0
AVSS to VDD + 0.5
–0.5 to +0.5
–0.5 to VDD + 0.5
–0.5 to VDD + 0.5
15
AVDD
AVSS
VI
V
V
Input voltage
V
Output voltage
VO
V
Output current low-level
IOL
1 pin
mA
mA
mA
mA
V
Total of output pins
1 pin
100
Output current high-level
IOH
–10
Total of output pins
–100
Reference input voltage
to A/D converter
AVREF1
–0.5 to VDD + 0.3
Reference input voltage
to D/A converter
AVREF2
AVREF3
TA
–0.5 to VDD + 0.3
–0.5 to VDD + 0.3
–40 to +85
V
V
Operating ambient
temperature
°C
Storage temperature
Tstg
–65 to +150
°C
Caution The product quality may be damaged even if a value of only one of the above parameters exceeds the
absolute maximum rating or any value exceeds the absolute maximum rating for an instant. That is,
the absolute maximum rating is a rating value which may cause a product to be damaged physically.
The absolute maximum rating values must therefore be observed in using the product.
57
µPD784031Y
Operating Condition
• Operating ambient temperature (TA) : –40 to +85°C
• Rise, fall time (tr, tf) (unspecified pins) : 0 to 200 µs
• Supply voltage and clock cycle time : refer to Figure 13-1
Figure 13-1. Supply Voltage and Clock Cycle Time
10000
4000
1000
Guaranteed
Operation
Range
125
100
62.5
10
0
1
2
3
4
5
6
7
Supply Voltage [V]
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Input capacitance
Output capacitance
I/O capacitance
Symbol
CI
Test Conditions
f = 1 MHz
MIN.
TYP.
MAX.
10
Unit
pF
Unmeasured pins returned to
0 V.
CO
10
pF
CIO
10
pF
58
µPD784031Y
Oscillator Characteristics (TA = –40 to +85°C, VDD = +4.5 to 5.5 V, VSS = 0 V)
Resonator
Recommended Circuit
Parameter
MIN.
4
MAX.
32
Unit
Ceramic resonator or
crystal resonator
Oscillation frequency (fXX)
MHz
V
SS1 X1
X2
C1
C2
External clock
X1 input frequency (fX)
4
0
32
10
MHz
ns
X1
X2
X1 input rise, fall time (tXR, tXF)
X1 input high-/low-level width
10
125
ns
HCMOS
inverter
(tWXH, tWXL)
Caution When using the clock oscillator, wiring in the area enclosed with the dotted line should be carried out
as follows to avoid an adverse effect from wiring capacitance.
• Wiring should be as short as possible.
• Wiring should not cross other signal lines.
• Wiring should not be placed close to a varying high current.
• The potential of the oscillator capacitor ground should be the same as VSS1. Do not ground it to
the ground pattern in which a high current flows.
• Do not fetch a signal from the oscillator.
59
µPD784031Y
Oscillator Characteristics (TA = –40 to +85°C, VDD = +2.7 to 5.5 V, VSS = 0 V)
Resonator
Recommended Circuit
Parameter
MIN.
4
MAX.
16
Unit
Ceramic resonator or
crystal resonator
Oscillation frequency (fXX)
MHz
V
SS1 X1
X2
C1
C2
External clock
X1 input frequency (fX)
4
0
16
10
MHz
ns
X1
X2
X1 input rise, fall time (tXR, tXF)
X1 input high-/low-level width
10
125
ns
HCMOS
inverter
(tWXH, tWXL)
Caution When using the clock oscillator, wiring in the area enclosed with the dotted line should be carried out
as follows to avoid an adverse effect from wiring capacitance.
• Wiring should be as short as possible.
• Wiring should not cross other signal lines.
• Wiring should not be placed close to a varying high current.
• The potential of the oscillator capacitor ground should be the same as VSS1. Do not ground it to
the ground pattern in which a high current flows.
• Do not fetch a signal from the oscillator.
60
µPD784031Y
DC Characteristics (TA = –40 to +85°C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V) (1/2)
Parameter
Symbol
Test Conditions
MIN.
–0.3
TYP.
MAX.
Unit
V
Input voltage low-level
VIL1
Except for pins shown in
0.3VDD
Notes 1, 2, 3, 4, 6
VIL2
VIL3
Pins shown in Notes 1, 2, 3, 4, 6
–0.3
–0.3
0.2VDD
+0.8
V
V
VDD = +5.0 V ± 10 %
Pins shown in Notes 2, 3, 4
Input voltage high-level
Output voltage low-level
VIH1
VIH2
VIH3
Except for pins shown in Notes 1, 6
Pins shown in Notes 1, 6
0.7VDD
0.8VDD
2.2
VDD + 0.3
VDD + 0.3
VDD + 0.3
V
V
V
VDD = +5.0 V ± 10 %
Pins shown in Notes 2, 3, 4
VOL1
IOL = 2 mA
0.4
0.4
0.6
1.0
V
V
V
V
Except for pins shown in Note 6
VOL2
IOL = 3 mA
Pins shown in Note 6
IOL = 6 mA
Pins shown in Note 6
VOL3
VDD = +5.0 V ± 10 %
IOL = 8 mA
Pins shown in Notes 2, 5
Output voltage high-level
VOH1
VOH2
IOH = –2 mA
VDD – 1.0
VDD – 1.4
V
V
VDD = +5.0 V ± 10 %
IOH = –5 mA
Pins shown in Note 4
X1 input current low-level
X1 input current high-level
IIL
EXTC = 0
–30
+30
µA
µA
0 V ≤ VI ≤ VIL2
IIH
EXTC = 0
VIH2 ≤ VI ≤ VDD
Notes 1. X1, X2, RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3,
P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, TEST
2. AD0 to AD7, A8 to A15
3. P60/A16 to P63/A19, RD, WR, P66/WAIT/HLDRQ, P67/REFRQ/HLDAK
4. P00 to P07
5. P10 to P17
6. P32/SCK0/SCL, P33/SO0/SDA
61
µPD784031Y
DC Characteristics (TA = –40 to +85°C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V) (2/2)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Input leakage current
ILI
0 V ≤ VI ≤ VDD
±10
µA
Except for X1 pin when EXTC = 0
Output leakage current
VDD supply current
ILO
0 V ≤ VO ≤ VDD
±10
µA
IDD1
Operating
mode
fXX = 32 MHz
25
12
13
8
45
mA
VDD = +5.0 V ± 10 %
fXX = 16 MHz
25
26
12
12
8
mA
mA
mA
mA
mA
kΩ
VDD = +2.7 to 3.3 V
IDD2
IDD3
RL
HALT mode
fXX = 32 MHz
VDD = +5.0 V ± 10 %
fXX = 16 MHz
VDD = +2.7 to 3.3 V
IDLE mode
(EXTC = 0)
fXX = 32 MHz
VDD = +5.0 V ± 10 %
fXX = 16 MHz
VDD = +2.7 to 3.3 V
Pull-up resistor
VI = 0 V
15
80
62
µPD784031Y
AC Characteristics (TA = –40 to +85°C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V)
(1) Read/write operation (1/2)
Parameter
Symbol
Test Conditions
VDD = +5.0 V ± 10 %
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup time
tSAST
(0.5 + a) T – 15
(0.5 + a) T – 31
(0.5 + a) T – 17
(0.5 + a) T – 40
0.5T – 24
ASTB high-level width
tWSTH
tHSTLA
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
Address hold time (from ASTB↓)
0.5T – 34
Address hold time (from RD↑)
Address → RD↓ delay time
tHRA
tDAR
0.5T – 14
VDD = +5.0 V ± 10 %
(1 + a) T – 9
(1 + a) T – 15
Address float time (from RD↓)
Address → data input time
tFRA
0
tDAID
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
(2.5 + a + n) T – 37
(2.5 + a + n) T – 52
(2 + n) T – 40
(2 + n) T – 60
(1.5 + n) T – 50
(1.5 + n) T – 70
ASTB↓ → data input time
RD↓ → data input time
tDSTID
tDRID
ASTB↓ → RD↓ delay time
Data hold time (from RD↑)
RD↑ → address active time
tDSTR
tHRID
tDRA
0.5T – 9
0
After program
read
VDD = +5.0 V ± 10 %
0.5T – 8
0.5T – 12
1.5T – 8
After data
read
VDD = +5.0 V ± 10 %
1.5T – 12
0.5T – 17
(1.5 + n) T – 30
(1.5 + n) T – 40
0.5T – 14
(1 + a) T – 5
(1 + a) T – 15
RD↑ → ASTB↑ delay time
tDRST
tWRL
RD low-level width
VDD = +5.0 V ± 10 %
Address hold time (from WR↑)
Address → WR↓ delay time
tHWA
tDAW
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
ASTB↓ → data output delay time
tDSTOD
0.5T + 19
0.5T + 35
0.5T – 11
WR↓ → data output delay time
ASTB↓ → WR↓ output delay time
tDWOD
tDSTW
0.5T – 9
Remark T : TCYK (system clock cycle time)
a : 1 in address wait, 0 in the other conditions
n : the number of wait (n ≥ 0)
63
µPD784031Y
(1) Read/write operation (2/2)
Parameter
Symbol
Test Conditions
VDD = +5.0 V ± 10 %
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
Data setup time (to WR↑)
tSODW
tHWOD
(1.5 + n) T – 30
(1.5 + n) T – 40
0.5T – 5
Note
Data hold time (from WR↑)
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
0.5T – 25
WR↑ → ASTB↑ delay time
tDWST
tWWL
0.5T – 12
WR low-level width
(1.5 + n) T – 30
(1.5 + n) T – 40
Note The data hold time includes the time to hold VOH1 and VOL1 in the load condition of CL = 50 pF, RL = 4.7 kΩ.
Remark T : TCYK (system clock cycle time)
n : the number of wait (n ≥ 0)
(2) Bus hold timing
Parameter
Symbol
tFHQC
Test Conditions
MIN.
MAX.
(6 + a + n) T + 50
(7 + a + n) T + 30
(7 + a + n) T + 40
1T + 30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
HLDRQ↑ → float delay time
HLDRQ↑ → HLDAK↑
tDHQHHAH
VDD = +5.0 V ± 10 %
delay time
Float → HLDAK↑ delay time
tDCFHA
HLDRQ↓ → HLDAK↓
tDHQLHAL
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
2T + 40
delay time
2T + 60
HLDAK↓ → active delay time
tDHAC
1T – 20
1T – 30
Remark T : TCYK (system clock cycle time)
a : 1 in address wait, 0 in the other conditions
n : the number of wait (n ≥ 0)
64
µPD784031Y
(3) External wait timing
Parameter
Symbol
Test Conditions
VDD = +5.0 V ± 10 %
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address → WAIT↓ input time
tDAWT
(2 + a) T – 40
(2 + a) T – 60
1.5T – 40
ASTB↓ → WAIT↓ input time
ASTB↓ → WAIT hold time
ASTB↓ → WAIT↑ delay time
RD↓ → WAIT↓ input time
RD↓ → WAIT↓ hold time
RD↓ → WAIT↑ delay time
WAIT↑ → data input time
tDSTWT
tHSTWTH
tDSTWTH
tDRWTL
tHRWT
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
1.5T – 60
(0.5 + n) T + 5
(0.5 + n) T + 10
(1.5 + n) T – 40
(1.5 + n) T – 60
T – 50
T – 70
nT + 5
nT + 10
tDRWTH
tDWTID
(1 + n) T – 40
(1 + n) T – 60
0.5T – 5
0.5T – 10
WAIT↑ → WR↑ delay time
WAIT↑ → RD↑ delay time
WR↓ → WAIT↓ input time
tDWTW
tDWTR
0.5T
0.5T
tDWWTL
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
T – 50
T – 75
WR↓ → WAIT hold time
tHWWT
nT + 5
nT + 10
WR↓ → WAIT↑ delay time
tDWWTH
(1 + n) T – 40
(1 + n) T – 70
Remark T : TCYK (system clock cycle time)
a : 1 in address wait, 0 in the other conditions
n : the number of wait (n ≥ 0)
(4) Refresh timing
Parameter
Symbol
tRC
Test Conditions
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Random read/write cycle time
REFRQ low-level pulse width
3T
tWRFQL
VDD = +5.0 V ± 10 %
1.5T – 25
1.5T – 30
0.5T – 9
1.5T – 9
1.5T – 9
0.5T – 15
1.5T – 25
1.5T – 30
ASTB↓ → REFRQ delay time
RD↑ → REFRQ delay time
WR↑ → REFRQ delay time
REFRQ↑ → ASTB delay time
REFRQ high-level pulse width
tDSTRFQ
tDRRFQ
tDWRFQ
tDRFQST
tWRFQH
VDD = +5.0 V ± 10 %
Remark T: TCYK (system clock cycle time)
65
µPD784031Y
Serial Operation (TA = –40 to +85°C, VDD = +2.7 to 5.5 V, AVSS = VSS = 0 V)
(1) CSI
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
ns
Serial clock cycle time (SCK0)
tCYSK0
Input
External clock
10/fXX + 380
when SCK0, SO0 are CMOS
input/output
Output
Input
T
µs
Serial clock low-level width
(SCK0)
tWSKL0
External clock
5/fXX + 150
ns
when SCK0, SO0 are CMOS
input/output
Output
Input
0.5T – 40
µs
Serial clock high-level width
(SCK0)
tWSKH0
External clock
5/fXX + 150
ns
when SCK0, SO0 are CMOS
input/output
Output
0.5T – 40
µs
ns
ns
ns
SI0 setup time (to SCK0↑)
SI0 hold time (from SCK0↑)
tSSSK0
tHSSK0
tDSBSK1
40
5/fXX + 40
0
SO0 output delay time
CMOS push-pull output
(3-wire serial I/O mode)
5/fXX + 150
5/fXX + 400
(from SCK0↓)
tDSBSK2
Open drain output
0
ns
(2-wire serial I/O mode), RL = 1 kΩ
Remarks 1. The values shown in the table above are those in the condition of CL = 100 pF.
2. T : serial clock cycle set by the software. The minimum value is 16/fXX.
3. fXX : oscillation frequency
(2) I2C
2
2
Parameter
Symbol
Standard Mode I C Bus
fXX = 4 to 32 MHz
High-speed Mode I C Bus
fXX = 8 to 32 MHz
Unit
MIN.
0
MAX.
100
MIN.
0
MAX.
400
SCL clock frequency
fSCL
kHz
Low status hold time of SCL
clock
tLOW
4.7
1.3
µs
High status hold time of SCL
clock
tHIGH
4.0
0.6
µs
Data hold time
tHD ; DAT
300
250
300
900
ns
ns
ns
ns
pF
Data setup time
tSU ; DAT
100
SDA, SCL signal rise time
SDA, SCL signal fall time
Load capacitance of each bus line
tR
tF
1000
300
20 + 0.1Cb
20 + 0.1Cb
300
300
400
Cb
400
66
µPD784031Y
(3) IOE1, IOE2
Parameter
Serial clock cycle time
(SCK1, SCK2)
Symbol
Test Conditions
MIN.
250
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCYSK1
Input
VDD = +5.0 V ± 10 %
500
Output Internal 16 frequency division
Input VDD = +5.0 V ± 10 %
T
Serial clock low-level width
(SCK1, SCK2)
tWSKL1
tWSKH1
85
210
Output Internal 16 frequency division
Input VDD = +5.0 V ± 10 %
0.5T – 40
85
Serial clock high-level width
(SCK1, SCK2)
210
Output Internal 16 frequency division
0.5T – 40
40
SI1, SI2 setup time
tSSSK1
tHSSK1
tDSOSK
tHSOSK
(to SCK1, SCK2↑)
SI1, SI2 hold time
40
ns
ns
ns
(from SCK1, SCK2↑)
SO1, SO2 output delay time
0
50
(from SCK1, SCK2↓)
SO1, SO2 output hold time
When transferring data
0.5tCYSK1 – 40
(from SCK1, SCK2↑)
Remarks 1. The values shown in the table above are those in the condition of CL = 100 pF.
2. T: serial clock cycle set by the software. The minimum value is 16/fXX.
(4) UART, UART2
Parameter
Symbol
Test Conditions
VDD = +5.0 V ± 10 %
MIN.
125
250
52.5
85
MAX.
Unit
ns
ns
ns
ns
ns
ns
ASCK clock input cycle time
tCYASK
ASCK clock low-level width
ASCK clock high-level width
tWASKL
tWASKH
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
52.5
85
67
µPD784031Y
Other Operations
Parameter
Symbol
tWNIL
Test Conditions
MIN.
MAX.
Unit
µs
µs
ns
ns
ns
ns
µs
µs
µs
µs
NMI low-level width
10
NMI high-level width
tWNIH
10
3tCYSMP + 10
3tCYSMP + 10
3tCYCPU + 10
3tCYCPU + 10
10
INTP0 low-level width
tWIT0L
tWIT0H
tWIT1L
tWIT1H
tWIT2L
tWIT2H
tWRSL
tWRSH
INTP0 high-level width
INTP1 to INTP3, CI low-level width
INTP1 to INTP3, CI high-level width
INTP4, INTP5 low-level width
INTP4, INTP5 high-level width
RESET low-level width
RESET high-level width
10
10
10
Remark tCYSMP : sampling clock set by the software
tCYCPU : CPU operation clock set by the software
A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = AVREF1 = +2.7 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Test Conditions
MIN.
8
TYP.
MAX.
Unit
bit
Resolution
Total error
Note
Note
1.0
0.8
%
Linearity error
%
Quantization error
Conversion time
±1/2
LSB
tCYK
tCYK
tCYK
tCYK
V
tCONV
tSAMP
FR = 1
FR = 0
FR = 1
FR = 0
120
180
24
Sampling time
36
Analog input voltage
Analog input impedance
AVREF1 current
VIAN
RAN
–0.3
AVREF1 + 0.3
1000
0.5
MΩ
mA
mA
µA
AIREF1
AIDD1
AIDD2
1.5
5.0
20
AVDD supply current
fXX = 32 MHz, CS = 1
STOP mode, CS = 0
2.0
1.0
Note Quantization error is not included. This is expressed in proportion to the full-scale value.
Remark tCYK: system clock cycle time
68
µPD784031Y
D/A Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Test Conditions
MIN.
8
TYP.
MAX.
0.6
Unit
bit
Resolution
Total error
Load
VDD = AVDD = AVREF2
%
condition
4 MΩ, 30 pF
= +2.7 to 5.5 V
AVREF3 = 0 V
V
DD = AVDD = +2.7 to 5.5 V
0.8
0.8
1.0
10
%
%
%
AVREF2 = 0.75VDD
AVREF3 = 0.25VDD
Load
VDD = AVDD = AVREF2
= +2.7 to 5.5 V
AVREF3 = 0 V
condition
2 MΩ, 30 pF
V
DD = AVDD = +2.7 to 5.5 V
AVREF2 = 0.75VDD
AVREF3 = 0.25VDD
Settling time
Load condition 2 MΩ, 30 pF
µs
kΩ
V
Output resistance
Analog reference voltage
RO
DACS0, 1 = 55 H
10
8
AVREF2
AVREF3
RAIREF
AIREF2
AIREF3
0.75VDD
VDD
0
4
0.25VDD
V
AVREF2, AVREF3 resistance value
Reference supply input current
DACS0, 1 = 55 H
kΩ
mA
mA
0
5
0
–5
69
µPD784031Y
Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Data retention voltage
Data retention current
Symbol
VDDDR
IDDDR
Test Conditions
STOP mode
MIN.
2.5
TYP.
MAX.
5.5
50
Unit
V
VDDDR = +2.7 to 5.5 V
VDDDR = +2.5 V
10
2
µA
µA
µs
10
VDD rise time
VDD fall time
tRVD
tFVD
tHVD
200
200
0
µs
VDD hold time
ms
(from setting STOP mode)
STOP release signal input time
Oscillation stabilization wait time
tDREL
tWAIT
0
ms
ms
ms
Crystal resonator
Ceramic resonator
30
5
0
Note
Input voltage low-level
Input voltage high-level
VIL
Specified pins
0.1VDDDR
VDDDR
V
V
VIH
0.9VDDDR
Note RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5,
P27/SI0, P32/SCK0/SCL, and P33/SO0/SDA pins
AC Timing Test Point
V
DD – 1 V
0.8VDD or 2.2 V
0.8 V
0.8VDD or 2.2 V
0.8 V
Test Points
0.45 V
70
µPD784031Y
Timing Waveform
(1) Read operation
tWSTH
ASTB
tSAST
t
DRST
tDSTID
t
HSTLA
A8 to A19
t
DAID
tHRA
AD0 to AD7
t
DSTR
t
FRA
tHRID
tDAR
tDRID
tDRA
RD
tWRL
(2) Write operation
tWSTH
ASTB
t
SAST
t
DWST
t
DSTOD
t
HSTLA
A8 to A19
t
HWA
AD0 to AD7
t
DSTW
t
HWOD
t
DAW
t
DWOD
t
SODW
WR
t
WWL
71
µPD784031Y
Hold Timing
ADTB, A8 to A19,
AD0 to AD7, RD, WR
HLDRQ
tFHQC tDCFHA
tDHAC
tDHQHHAH
tDHQLHAL
HLDAK
External WAIT Signal Input Timing
(1) Read operation
ASTB
t
DSTWTH
t
HSTWTH
t
DSTWT
A8 to A19
AD0 to AD7
RD
t
DAWT
tDWTID
t
DRWTL
t
DWTR
WAIT
t
HRWT
DRWTH
t
(2) Write operation
ASTB
t
DSTWTH
t
HSTWTH
t
DSTWT
A8 to A19
AD0 to AD7
WR
t
DAWT
t
DWWTL
t
DWTW
WAIT
t
HWWT
DWWTH
t
72
µPD784031Y
Refresh Timing Waveform
(1) Random read/write cycle
t
RC
ASTB
WR
t
RC
t
RC
tRC
t
RC
RD
(2) When refresh memory access is simultaneous with read, write
ASTB
RD, WR
tDSTRFQ
t
DRFQST
t
WRFQH
REFRQ
t
WRFQL
(3) Refresh after read
ASTB
t
DRFQST
RD
t
DRRFQ
REFRQ
t
WRFQL
(4) Refresh after write
ASTB
t
DRFQST
WR
tDWRFQ
REFRQ
t
WRFQL
73
µPD784031Y
Serial Operation
(1) CSI
t
WSKL0
t
WSKH0
SCK
tSSSK0
t
HSSK0
tCYSK0
SI
Input Data
t
HSBSK1
tDSBSK1
SO
Output Data
(2) I2C
tR
tF
t
HIGH
t
LOW
SCL
SDA
tHD ; DAT
tSU ; DAT
(3) IOE1, IOE2
t
WSKL1
t
WSKH1
SCK
SI
t
SSSK1
t
HSSK1
tCYSK1
Input Data
tHSOSK
tDSOSK
SO
Output Data
(4) UART, UART2
tWASKH
tWASKL
ASCK,
ASCK2
tCYASK
74
µPD784031Y
Interrupt Input Timing
tWNIH
tWNIL
NMI
tWIT0H
tWIT1H
t
WIT2H
tWIT0L
tWIT1L
t
WIT2L
INTP0
CI,
INTP1 to INTP3
INTP4, INTP5
Reset Input Timing
tWRSH
t
WRSL
RESET
75
µPD784031Y
External Clock Timing
t
WXH
t
WXL
X1
t
XR
t
XF
t
CYX
Data Retention Characteristics
STOP Mode Setting
VDD
V
DDDR
tDREL
t
WAIT
tHVD
tFVD
tRVD
RESET
NMI
(release by falling edge)
NMI
(release by rising edge)
76
µPD784031Y
14. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14×14)
A
B
60
61
41
40
detail of lead end
S
C D
R
Q
21
20
80
1
F
P
J
G
M
H
I
K
M
N
L
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
A
B
17.2±0.4
14.0±0.2
0.677±0.016
+0.009
0.551
–0.008
+0.009
0.551
C
14.0±0.2
–0.008
D
F
17.2±0.4
0.825
0.677±0.016
0.032
G
0.825
0.032
+0.004
0.012
H
0.30±0.10
–0.005
I
0.13
0.005
J
K
0.65 (T.P.)
1.6±0.2
0.026 (T.P.)
0.063±0.008
+0.009
0.031
L
0.8±0.2
–0.008
+0.004
0.006
+0.10
0.15
M
–0.003
–0.05
N
P
Q
R
S
0.10
0.004
2.7
0.106
0.1±0.1
5°±5°
3.0 MAX.
0.004±0.004
5°±5°
0.119 MAX.
S80GC-65-3B9-4
Remark Dimensions and materials of ES products are the same as those of mass-produced products.
77
µPD784031Y
80 PIN PLASTIC QFP (14×14)
A
B
60
61
41
40
detail of lead end
S
C
D
R
Q
80
1
21
20
F
J
M
G
P
H
I
K
L
M
N
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
A
B
17.20±0.20
14.00±0.20
0.677±0.008
+0.009
0.551
–0.008
+0.009
0.551
C
D
14.00±0.20
17.20±0.20
–0.008
0.677±0.008
F
0.825
0.825
0.032
0.032
G
+0.002
0.013
H
0.32±0.06
–0.003
I
0.13
0.005
J
K
0.65 (T.P.)
1.60±0.20
0.026 (T.P.)
0.063±0.008
+0.009
0.031
L
0.80±0.20
–0.008
+0.03
0.17
+0.001
0.007
M
–0.07
–0.003
N
P
Q
0.10
0.004
1.40±0.10
0.125±0.075
0.055±0.004
0.005±0.003
+7°
3°
+7°
3°
R
S
–3°
–3°
1.70 MAX.
0.067 MAX.
P80GC-65-8BT
Remark Dimensions and materials of ES products are the same as those of mass-produced products.
78
µPD784031Y
80-PIN PLASTIC TQFP (FINE PITCH) (12 × 12 mm)
A
B
60
61
41
40
detail of lead end
80
1
21
20
G
M
I
J
H
K
N
L
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.
+0.009
A
B
C
D
14.0±0.2
12.0±0.2
12.0±0.2
14.0±0.2
0.551
0.472
0.472
0.551
–0.008
+0.009
–0.008
+0.009
–0.008
+0.009
–0.008
F
1.25
1.25
0.049
0.049
G
+0.05
0.22
H
0.009±0.002
–0.04
I
0.10
0.004
J
0.5 (T.P.)
0.020 (T.P.)
+0.009
0.039
K
L
1.0±0.2
0.5±0.2
–0.008
+0.008
0.020
–0.009
+0.055
M
0.145
0.006±0.002
–0.045
N
P
Q
R
S
0.10
1.05
0.004
0.041
0.05±0.05
5°±5°
0.002±0.002
5°±5°
1.27 MAX.
0.050 MAX.
P80GK-50-BE9-4
Remark Dimensions and materials of ES products are the same as those of mass-produced products.
79
µPD784031Y
15. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the conditions recommended in the table below.
Fordetailsofrecommendedsolderingconditions,refertotheinformationdocumentSemiconductorDeviceMounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC sales representative.
Table 15-1. Surface Mounting Type Soldering Conditions (1/2)
(1) µPD784031YGC-3B9: 80-pin plastic QFP (14 × 14 mm, thickness 2.7 mm)
Soldering Method
Infrared reflow
Soldering Conditions
Symbol
Package peak temperature: 235°C, Duration: 30 sec. max. (at 210°C or above),
IR35-00-3
Number of times: 3 times max.
VPS
Package peak temperature: 215°C, Duration: 40 sec. max. (at 200°C or above),
VP15-00-3
WS60-00-1
—
Number of times: 3 times max.
Wave soldering
Partial heating
Solder bath temperature: 260°C max., Duration: 10 sec. max., Number of times: Once,
Preliminary heat temperature: 120°C max. (Package surface temperature)
Pin temperature: 300°C max. Duration: 3 sec. max. (per device side)
Caution Use of more than one soldering method should be avoided (except in the case of partial heating).
(2) µPD784031YGC-8BT: 80-pin plastic QFP (14 × 14 mm, thickness 1.4 mm)
Soldering Method
Infrared reflow
Soldering Conditions
Symbol
Package peak temperature: 235°C, Duration: 30 sec. max. (at 210°C or above),
IR35-00-2
Number of times: Twice max.
VPS
Package peak temperature: 215°C, Duration: 40 sec. max. (at 200°C or above),
VP15-00-2
WS60-00-1
—
Number of times: Twice max.
Wave soldering
Partial heating
Solder bath temperature: 260°C max., Duration: 10 sec. max., Number of times: Once,
Preliminary heat temperature: 120°C max. (Package surface temperature)
Pin temperature: 300°C max. Duration: 3 sec. max. (per device side)
Caution Use of more than one soldering method should be avoided (except in the case of partial heating).
80
µPD784031Y
Table 15-1. Surface Mounting Type Soldering Conditions (2/2)
(3) µPD784031YGK-BE9: 80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Soldering Method
Infrared reflow
Soldering Conditions
Symbol
Package peak temperature: 235°C, Duration: 30 sec. max. (at 210°C or above),
IR35-107-2
Note
Number of times: Twice max., Time limit: 7 days
required at 125°C)
(thereafter 10 hours prebaking
<precaution>
Do not bake devices by packing them in non-heat resistant trays or packing materials
such as magazine cases and tapes. Use heat-resistant trays.
VPS
Package peak temperature: 215°C, Duration: 40 sec. (at 200°C or above),
VP15-107-2
Note
Number of times: Twice max., Time limit: 7 days
required at 125°C)
(thereafter 10 hours prebaking
<precaution>
Do not bake devices by packing them in non-heat resistant trays or packing materials
such as magazine cases and tapes. Use heat-resistant trays.
Partial heating
Pin temperature: 300°C max. Duration: 3 sec. max. (per device side)
—
Note For the storage period after dry-pack decapsulation, storage conditions are max. 25°C, 65 % RH.
Caution Use of more than one soldering method should be avoided (except in the case of partial heating).
81
µPD784031Y
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for supporting development of a system using the µPD784031Y.
Language Processor Software
RA78K4Note 1
CC78K4Note 1
CC78K4-LNote 1
Assembler package common to 78K/IV Series
C compiler package common to 78K/IV Series
C compiler library source file common to 78K/IV Series
PROM Writing Tool
PG-1500
PROM programmer
PA-78P4026GC
PA-78P4038GK
PA-78P4026KK
Programmer adapter connected to PG-1500
PG-1500 controllerNote 2
PG-1500 control program
Debugging Tool
IE-784000-R
In-circuit emulator common to 78K/IV Subseries
Break board common to 78K/IV Series
IE-784000-R-BK
IE-784038-R-EM1
IE-784000-R-EM
Emulation board for evaluation of µPD784038Y Subseries
IE-70000-98-IF-B
IE-70000-98N-IF
InterfaceadapterwhenPC-9800Series(exceptnotebooktype)isusedashostmachine
Interface adapter and cable when notebook type PC-9800 Series is used as host
machine
IE-70000-PC-IF-B
IE-78000-R-SV3
EP-78230GC-R
Interface adapter when IBM PC/ATTM is used as host machine
Interface adapter and cable when EWS is used as host machine
Emulation probe for 80-pin plastic QFP (GC-3B9 and GC-8BT types) common to
µPD784038Y Subseries
EP-78054GK-R
EV-9200GC-80
TGK-080SDW
Emulation probe for 80-pin plastic TQFP (fine pitch) (GK-BE9 type) common to
µPD784038Y Subseries
Socket mounted on board of target system created for 80-pin plastic QFP (GC-3B9 and
GC-8BT types)
Adapter mounted on board of target system created for 80-pin plastic TQFP (fine pitch)
(GK-BE9 type)
EV-9900
Jig used to remove µPD78P4038YKK-T from EV-9200GC-80
System simulator common to 78K/IV Series
Integrated debugger for IE-784000-R
SM78K4Note 3
ID78K4Note 3
DF784038Note 4
Device file for µPD784038Y Subseries
Real-time OS
RX78K/IVNote 4
MX78K4Note 2
Real-time OS for 78K/IV Series
OS for 78K/IV Series
82
µPD784031Y
Notes 1. • PC-9800 Series (MS-DOSTM) based
• IBM PC/AT and compatible machine (PC DOSTM, WindowsTM, MS-DOS, IBM DOSTM) based
• HP9000 Series 700TM (HP-UXTM) based
• SPARCstationTM (SunOSTM) based
• NEWSTM (NEWS-OSTM) based
2. • PC-9800 Series (MS-DOS) based
• IBM PC/AT and compatible machine (PC DOS, Windows, MS-DOS, IBM DOS) based
3. • PC-9800 Series (MS-DOS + Windows) based
• IBM PC/AT and compatible machine (PC DOS, Windows, MS-DOS, IBM DOS) based
• HP9000 Series 700 (HP-UX) based
• SPARCstation (SunOS) based
4. • PC-9800 Series (MS-DOS) based
• IBM PC/AT and compatible machine (PC DOS, Windows, MS-DOS, IBM DOS) based
• HP9000 Series 700 (HP-UX) based
• SPARCstation (SunOS) based
Remarks 1. RA78K4, CC78K4, SM78K4, and ID78K4 are used in combination with DF784038.
2. TGK-080SDW is manufactured by TOKYO ELETECH Corporation. Consult your local NEC sales
representative when purchasing it.
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µPD784031Y
APPENDIX B. RELATED DOCUMENTS
Documents Related to Device
Document Name
Document No.
English
Japanese
U11504J
U10741J
U10742J
U11316J
U11091J
U10905J
U10594J
U10595J
U10095J
µPD784031Y Data Sheet
This manual
µPD784035Y, 784036Y, 784037Y, 784038Y Data Sheet
µPD78P4038Y Data Sheet
U10741E
U10742E
µPD784038, 784038Y Subseries User’s Manual - Hardware
µPD784038Y Subseries Special Function Register Table
78K/IV Series User’s Manual - Instruction
78K/IV Series Instruction Table
U11316E
–
U10905E
–
–
–
78K/IV Series Instruction Set
78K/IV Series Application Note - Software Basics
Documents Related to Development Tools (User’s Manuals)
Document Name
Document No.
English
U11334E
–
Japanese
U11334J
U11162J
EEU-817
EEU-960
EEU-961
U12322J
U11940J
EEU-704
EEU-5008
EEU-5004
U11383J
EEU-985
EEU-932
U10093J
U10092J
U10440J
U11960J
RA78K4 Assembler Package
Operation
Language
RA78K Series Structured Assembler Preprocessor
CC78K4 Series
EEU-1402
–
Operation
Language
–
CC78K Series Library Source File
PG-1500 PROM Programmer
–
EEU-1335
EEU-1291
U10540E
EEU-1534
U11383E
EEU-1515
EEU-1468
U10093E
U10092E
U10440E
To be released soon
PG-1500 Controller - PC-9800 Series (MS-DOS) Based
PG-1500 Controller - IBM PC Series (PC DOS) Based
IE-784000-R
IE-784038-R-EM1
EP-78230
EP-78054GK-R
SM78K4 System Simulator - Windows Based
SM78K Series External Part User Open Interface Specifications
ID78K4 Integrated Debugger - Windows Based
Reference
Reference
ID78K4 Integrated Debugger - HP9000 Series 700 (HP-UX) Based Reference
Caution The above related documents are subject to change without prior notice. Be sure to use the latest
version when starting design.
84
µPD784031Y
Documents Related to Embedded Software (User’s Manual)
Document Name
Document No.
English
U10603E
U10604E
–
Japanese
U10603J
U10604J
U10364J
U11779J
78K/IV Series Real-time OS
Basics
Installation
Debugger
Basics
78K/IV Series OS MX78K4
–
Other Documents
Document Name
Document No.
English
Japanese
IC Package Manual
C10943X
Semiconductor Device Mounting Technology Manual
Quality Grades on NEC Semiconductor Devices
Reliability Quality Control on NEC Semiconductor Device
Electric Static Discharge (ESD) Test
C10535E
C11531E
C10983E
–
C10535J
C11531J
C10983J
MEM-539
C11893J
U11416J
Semiconductor Devices Quality Assurance Guide
Microcomputer Product Series Guide
MEI-1202
–
Caution The above related documents are subject to change without prior notice. Be sure to use the latest
version when starting design.
85
µPD784031Y
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it once, when it has occurred. Environmental control must be
adequate. When it is dry, humidifier should be used. It is recommended to avoid
using insulators that easily build static electricity. Semiconductor devices
must be stored and transported in an anti-static container, static shielding bag
or conductive material. All test and measurement tools including work bench
and floor should be grounded. The operator should be grounded using wrist
strap. Semiconductor devices must not be touched with bare hands. Similar
precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level
may be generated due to noise, etc., hence causing malfunction. CMOS device
behave differently than Bipolar or NMOS devices. Input levels of CMOS devices
must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have
a possibility of being an output pin. All handling related to the unused pins must
be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee out-
pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after
power-on for devices having reset function.
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µPD784031Y
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Developmentenvironmentspecifications(forexample, specificationsforthird-partytoolsandcomponents,
host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from
country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 800-366-9782
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 800-729-9288
Fax: 2886-9022/9044
Fax: 040-2444580
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 0211-65 03 490
Tel: 02-528-0303
Fax: 01-30-67 58 99
Fax: 02-528-4411
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 253-8311
Fax: 01908-670-290
Tel: 01-504-2787
Fax: 250-3583
Fax: 01-504-2860
NEC Electronics Italiana s.r.1.
Milano, Italy
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
NEC Electronics (Germany) GmbH
Scandinavia Office
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Taeby, Sweden
Fax: 02-719-5951
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
J96. 8
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µPD784031Y
Caution Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use
these components in an I2C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips.
EEPROM and IEBus are trademarks of NEC Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United
States and/or other countries.
IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
The related documents indicated in this publication may include preliminary versions. However, preliminary versions
are not marked as such.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use of
such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property
arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in
its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
“Standard”, “Special”, and “Specific”. The Specific quality grade applies only to devices developed based on a
customer designated “quality assurance program” for a specific application. The recommended applications of a
device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment and
industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for
life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support
systems or medical equipment for life support, etc.
The quality grade of NEC devices is “Standard” unless otherwise specified in NEC’s Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they
should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
相关型号:
UPD784035GC-XXX-8BT-A
Microcontroller, 16-Bit, MROM, 32MHz, CMOS, PQFP80, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP-80
NEC
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