UPD78368AGF_技术文档

µPD78363A, 78365A, 78366A, 78368A

78K/III Series Product Development

PD78372 subseries

µ

PD78366A subseries

µ

(for control application

in automotive appliance)

Reinforced timer,

A/D added

µ

PD78363A

µ

PD78361A

PD78362A

PD78P364A

PD78365A

µ

PD78366A

Pulse output function

for inverter control,

expanded ROM, RAM

µ

PD78368A

PD78P368A

(for inverter)

µ

PD78356 subseries

(for camera, HDD)

A/D, D/A relative instruction

added, expanded ROM, RAM

µ

PD78352A subseries

(for HDD)

High-performance CPU,

sum-of-products instruction added

Reinforced timer and

A/D, expanded ROM

and RAM

µ

PD78334 subseries

(for control application in OA and FA fields)

Pulse output function

for inverter control

µ

PD78328 subseries

(for inverter)

µ

PD78322 subseries

High-speed, multi-function,

reinforced interrupt,

10-bit A/D

(for control application in OA and FA fields)

PD78312A subseries

µ

(for control application in OA and FA fields)

2

µPD78363A, 78365A, 78366A, 78368A

PIN CONFIGURATION (TOP VIEW)

•

80-pin plastic QFP (14 × 20 mm)

µPD78363AGF-×××-3B9, 78365AGF-3B9, 78366AGF-×××-3B9, 78368AGF-×××-3B9

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

VSS

P00/RTP0

P01/RTP1

P02/RTP2

P03/RTP3

P04/PWM0

P52/A10

P51/A9

64

63

62

61

60

59

58

57

56

55

1

2

3

P50/A8

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P43/AD3

P42/AD2

P41/AD1

P40/AD0

V^SS

4

5

6

P05/TCUD/PWM1

7

8

P06/TIUD/TO40

9

P07/TCLRUD

10

11

12

13

14

15

16

17

18

19

20

WDTO

IC

54

53

52

V^DD

V^SS

V^DD

51

50

49

48

47

46

45

AVDD

X1

X2

AVREF

MODE1

P77/ANI7

P76/ANI6

P75/ANI5

P74/ANI4

P73/ANI3

P72/ANI2

P71/ANI1

P70/ANI0

AV^SS

RESET

P30/T^XD0

P31/R^XD0

P32/SO/SB0

P33/SI/SB1

P34/SCK

P35/T^XD1

P36/R^XD1

44

43

42

41

21

22

23

24

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Caution Connect the IC pin directly to VSS.

Remark ××× indicates a ROM code suffix

3

µPD78363A, 78365A, 78366A, 78368A

P00-P07

P10-P17

P20-P25

P30-P36

P40-P47

P50-P57

P70-P77

P80-P85

P90-P93

RTP0-RTP3

NMI

: Port0

: Port1

: Port2

: Port3

: Port4

: Port5

: Port7

: Port8

: Port9

: Real-time Port

: Nonmaskable Interrupt

: Interrupt From Peripherals

INTP0-INTP4

TO00-TO05, TO04 : Timer Output

TI

: Timer Input

TIUD

: Timer Input Up Down Counter

: Timer Control Up Down Counter

: Timer Clear Up Down Counter

: Analog Input

TCUD

TCLRUD

ANI0-ANI7

T^XD0, TXD1

RXD0, RXD1

SI

: Transmit Data

: Receive Data

: Serial Input

SO

: Serial Output

SB0, SB1

SCK

: Serial Bus

: Serial Clock

PWM0, PWM1

WDTO

MODE0, MODE1

AD0-AD7

A8-A15

ASTB

: Pulse Width Modulation Output

: Watchdog Timer Ouput

: Mode

: Address/Data Bus

: Address Bus

: Address Strobe

: Read Strobe

RD

WR

: Write Strobe

RESET

X1, X2

AV^DD

: Reset

: Crystal

: Analog VDD

AVSS

: Analog VSS

AVREF

: Analog Reference Voltage

: Power Supply

VDD

V^SS

: Ground

IC

: Internally Connected

4

µPD78363A, 78365A, 78366A, 78368A

FUNCTIONAL OUTLINE

Product name

Item

µPD78368A

µPD78363A

µPD78365A

µPD78366A

Minimum instruction

execution time

125 ns (internal clock: 16 MHz, external clock: 8 MHz)

Internal memory

ROM

RAM

24K bytes

768 bytes

None

32K bytes

48K bytes

2K bytes

Memory space

64K bytes (externally expandable)

General-purpose registers

8 bits × 16 × 8 banks

Number of basic instructions 115

Instruction set

• 16-bit transfer/operation

• Multiplication/division (16 bits × 16 bits, 32 bits ÷ 16 bits)

• Bit manipulation

• String

• Sum-of-products operation (16 bits × 16 bits + 32 bits)

• Relative operation

I/O lines

Input

I/O

14 (of which 8 are shared with analog input)

49

31

49

Real-time pulse unit

• 16-bit timer × 1

10-bit dead time timer × 3

16-bit compare register × 4

2 kinds of output mode can be selected

Mode 0, set-reset output: 6 channels

Mode 1, buffer output: 6 channels

• 16-bit timer × 1

16-bit compare register × 1

• 16-bit timer × 1

16-bit capture register × 1

16-bit capture/compare register × 1

• 16-bit timer × 1

16-bit capture register × 2

16-bit capture/compare register × 1

• 16-bit timer × 1

16-bit compare register × 2

16-bit resolution PWM output: 1 channel

Real-time output port

PWM unit

Pulse outputs associated with real-time pulse unit: 4 lines

8-/9-/10-/12-bit resolution variable PWM output: 2 channels

10-bit resolution, 8 channels

A/D converter

Serial interface

Dedicated baud rate generator

UART (w/pin selection function): 1 channel

Clocked serial interface/SBI:

1 channel

Interrupt function

• External: 6, internal: 14 (of which 2 are multiplexed with external)

• 4 priority levels can be specified through software

• 3 types of interrupt processing modes selectable

(vectored interrupt, macro service, and context switching)

Package

Others

80-pin plastic QFP (14 × 20 mm)

• Watchdog timer

• Standby function (HALT and STOP modes)

5

µPD78363A, 78365A, 78366A, 78368A

DIFFERENCES BETWEEN µPD78363A, 78365A, 78366A, AND 78368A

Product name

µPD78363A

µPD78366A

32K bytes

2K bytes

µPD78368A

µPD78365A

Item

ROM 24K bytes

RAM 786 bytes

48K bytes

None

Internal ROM

Input 14 (of which 8 are multiplexed with analog input)

I/O lines

I/O

49

31

Port 4 (P40-P47)

Can be set in input or output mode in units

of 8 bits. In external memory expansion

mode, this port functions as multiplexed

address/data bus (AD0-AD7).

Always functions as multiplexed address/

data bus (AD0-AD7).

Can be set in input or output mode in

1-bit units. In external memory expansion

mode, this port functions as address bus

(A8-A15).

Always functions as address bus (A8-A15)

Port 5 (P50-P57)

Port 9 (P90-P93)

Can be set in input or output mode in

1-bit units. In external memory expansion

mode, P90 outputs RD strobe signal, and

P91 outputs WR strobe signal.

P90 always functions as RD strobe signal

output pin, and P91 always functions as WR

strobe signal output pin. P92 and P93

function as I/O port lines.

Memory expansion

mode register (MM)

Sets port 4 in input or output mode in units

of 8 bits. In external memory expansion

mode, sets memory expansion width of ports

4 and 5.

Always fixed to external memory expansion

mode.

Port 5 mode

Sets port 5 in input or output mode in

1-bit units.

None

register (PM5)

Setting of

• In ordinary operation mode:

MODE0, 1 = LL

• Always set as follows:

MODE0, 1 = HH

MODE0, MODE1

• In ROM-less mode:

MODE0, 1 = HH

6

µPD78363A, 78365A, 78366A, 78368A

CONTENTS

1. PIN FUNCTIONS ................................................................................................................................... 10

1.1 PORT PINS ..................................................................................................................................... 10

1.2 PINS OTHER THAN PORT PINS .................................................................................................. 11

1.3 PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS ....................................................... 13

2. CPU ARCHITECTURE ............................................................................................................ 15

2.1 MEMORY SPACE........................................................................................................................... 15

2.2 DATA MEMORY ADDRESSING.................................................................................................... 18

2.3 PROCESSOR REGISTERS ........................................................................................................... 20

2.3.1 Control Registers ................................................................................................................. 21

2.3.2 General-Purpose Registers ..................................................................................................22

2.3.3 Special Function Registers (SFR) ........................................................................................23

3. FUNCTIONAL BLOCKS........................................................................................................... 29

3.1 EXECUTION UNIT (EXU)............................................................................................................... 29

3.2 BUS CONTROL UNIT (BCU)......................................................................................................... 29

3.3 ROM/RAM ....................................................................................................................................... 29

3.4 PORT FUNCTIONS ........................................................................................................................ 30

3.5 CLOCK GENERATOR CIRCUIT ................................................................................................... 32

3.6 REAL-TIME PULSE UNIT (RPU) .................................................................................................. 34

3.7 REAL-TIME OUTPUT PORT (RTP) .............................................................................................. 42

3.8 A/D CONVERTER .......................................................................................................................... 43

3.9 SERIAL INTERFACE ..................................................................................................................... 44

3.10 PWM UNIT ...................................................................................................................................... 46

3.11 WATCHDOG TIMER (WDT) .......................................................................................................... 47

4. INTERRUPT FUNCTIONS................................................................................................................... 48

4.1 OUTLINE ......................................................................................................................................... 48

4.2 MACRO SERVICE .......................................................................................................................... 49

4.3 CONTEXT SWITCHING ................................................................................................................. 52

4.3.1 Context Switching Function by Interrupt Request ................................................................52

4.3.2 Context Switching Function by BRKCS Instruction ..............................................................53

4.3.3 Restoration from Context Switching .....................................................................................53

5. EXTERNAL DEVICE EXPANSION FUNCTION ............................................................................. 54

6. STANDBY FUNCTIONS ...................................................................................................................... 55

7. RESET FUNCTION ............................................................................................................................... 56

8. INSTRUCTION SET .............................................................................................................................. 57

9. EXAMPLE OF SYSTEM CONFIGURATION........................................................................... 71

10. ELECTRICAL SPECIFICATIONS............................................................................................ 72

8

µPD78363A, 78365A, 78366A, 78368A

11. PACKAGE DRAWING.............................................................................................................. 83

12. RECOMMENDED SOLDERING CONDITIONS ...................................................................... 84

APPENDIX A. DIFFERENCES BETWEEN µPD78366A AND µPD78328 ................................... 85

APPENDIX B. TOOLS ..................................................................................................................... 86

B.1 DEVELOPMENT TOOLS ............................................................................................................... 86

B.2 EMBEDDED SOFTWARE .............................................................................................................. 91

9

µPD78363A, 78365A, 78366A, 78368A

1. PIN FUNCTIONS

1.1

PORT PINS

Pin name

I/O

Function

Shared by:

RTP0-RTP3

PWM0

Port 0.

P00-P03

P04

8-bit I/O port.

Can be set in input or output mode in 1-bit units.

P05

TCUD/PWM1

TIUD/TO40

TCLRUD

P06

P07

Port 1.

8-bit I/O port.

P10-P17

I/O

–

Can be set in input or output mode in 1-bit units.

Port 2.

P20

P21

P22

P23

P24

P25

P30

P31

P32

P33

P34

P35

P36

NMI

INTP0

INTP1

INTP2

INTP3/TI

INTP4

TXD0

6-bit input port.

Input

Port 3.

7-bit I/O port.

RXD0

Can be set in input or output mode in 1-bit units.

SO/SB0

SI/SB1

SCK

I/O

TXD1

RXD1

Port 4.

8-bit I/O Port.

P40-P47

AD0-AD7

Can be set in input or output mode in 8-bit units.

Port 5.

8-bit I/O port.

P50-P57

P70-P77

P80-P85

I/O

Input

I/O

A8-A15

Can be set in input or output mode in 1-bit units.

Port 7.

ANI0-ANI7

TO00-TO05

8-bit input port

Port 8.

6-bit I/O port.

Can be set in input or output mode in 1-bit units.

P90

P91

P92

P93

RD

WR

–

Port 9.

I/O

4-bit I/O port.

Can be set in input or output mode in 1-bit units.

–

10

µPD78363A, 78365A, 78366A, 78368A

1.2

PINS OTHER THAN PORT PINS (1/2)

Pin name

I/O

Function

Shared by:

P00-P03

Real-time output port that outputs pulses in synchronization with trigger

signal from real-time pulse unit.

RTP0-RTP3 Output

P20

P21

NMI

Non-maskable interrupt request input.

External interrupt request input.

INTP0

P22

INTP1

Input

P23

INTP2

INTP3

INTP4

TI

P24/TI

P25

P24/INTP3

External count clock input to timer 1.

Count operation selection control signal input to up/down counter (timer

4).

Input

P05/PWM1

TCUD

P06/TO40

P07

TIUD

External count clock input to up/down counter (timer 4).

Clear signal input to up/down counter (timer 4).

TCLRUD

P80-P85

P06/TIUD

P70-P77

P30

TO00-TO05

Output

Pulse output from real-time pulse unit.

TO40

ANI0-ANI7

T^XD0

TXD1

RXD0

RXD1

SCK

Input

Analog input to A/D converter.

Output

Serial data output of asynchronous serial interface.

P35

P31

Input

Serial data input of asynchronous serial interface.

P36

P34

I/O

Serial clock input/output of clocked serial interface.

P33/SB1

P32/SB0

P32/SO

P33/SI

P04

SI

Input

Ouput

Serial data input of clocked serial interface in 3-line mode.

Serial data output of clocked serial interface in 3-line mode.

SO

SB0

I/O

Output

I/O

Serial data input/output of clocked serial interface in SBI mode.

PWM signal output.

SB1

PWM0

PWM1

P05/TCUD

Signal output indicating overflow of watchdog timer (generates non-

maskable interrupt).

–

WDTO

P40-P47

P50-P57

AD0-AD7

A8-A15

Multiplexed address/data bus when memory is externally expanded.

Address bus when memory is externally expanded.

Outputs timing signal at which address information output from AD0-AD7

and A8-A15 pins to access external memory is to be latched.

–

ASTB

Output

RD

P90

P91

Read strobe signal output to external memory.

Write strobe signal output to external memory.

WR

11

µPD78363A, 78365A, 78366A, 78368A

1.2

PINS OTHER THAN PORT PINS (2/2)

Pin name

I/O

Function

Shared by:

–

Control signal input to set operation mode. With µPD78363A, 78366A, and

78368A MODE0 and MODE1 are usually connected to VSS. With µPD78365A,

MODE0 and MODE1 are always connected to VDD.

MODE0

MODE1

Input

–

RESET

X1

Input

System reset input

Input

Crystal oscillator connecting pins for system clock. If a clock is externally

supplied, input it to pin X1. Leave pin X2 open.

X2

–

AV^REF

AVDD

AVSS

VDD

Input

A/D converter reference voltage input.

A/D converter analog power supply.

A/D converter GND.

–

Positive power supply

VSS

GND

IC

Internally connected. Connect this pin to VSS.

12

µPD78363A, 78365A, 78366A, 78368A

1.3

PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS

Table 1-1 shows the I/O circuit types of the respective pins, and recommended connections of the unused

pins. Figure 1-1 shows the circuits of the respective pins.

Table 1-1. Pin I/O Circuit Type and Recommended Connections of Unused Pins

P00/RTP0-P03/RTP3

P04/PWM0

P05/TCUD/PWM1

P06/TIUD/TO40

P07/TCLRUD

P10-P17

I/O circuit type

Recommended connections

Input : IndependentlyconnecttoVDD orVSS throughresistor

Output : Leave unconnected

5-A

2

P20/NMI

P21/INTP0

P22/INTP1

P23/INTP2

P24/INTP3/TI

P25/INTP4

P30/T^XD0

Connect to VSS

2-A

5-A

8-A

P31/R^XD0

P32/SO/SB0

P33/SI/SB1

P34/SCK

Input : IndependentlyconnecttoVDD orVSS throughresistor

Output : Leave unconnected

P35/T^XD1

P36/RXD1

5-A

P40/AD0-P47/AD7

P50/A8-P57/A15

P70/ANI0-P77/ANI7

P80/TO00-P85/TO05

P90/RD

9

Connect to VSS

5-A

Input : IndependentlyconnecttoVDD orVSS throughresistor

Output : Leave unconnected

P91/WR

P92, P93

5

19

1

ASTB

Connect to VSS

WDTO

MODE0, MODE1

RESET

–

2

Connect to VSS

Connect to VDD

Connect to VSS

AVREF, AVSS

AVDD

–

IC

13

µPD78363A, 78365A, 78366A, 78368A

Figure 1-1. Pin I/O Circuits

V^DD

Type 1

Type 5-A

VDD

Pull-up

enable

P-ch

V^DD

P-ch

IN

Data

IN/OUT

Output

disable

N-ch

Input

enable

Type 2

Type 8-A

V^DD

Pull-up

enable

P-ch

IN

V^DD

P-ch

Data

IN/OUT

Output

disable

N-ch

Schmitt trigger input with hysteresis characteristics

Type 2-A

Type 9

Comparator

+

V^DD

P-ch

N-ch

IN

Pull-up

enable

–

P-ch

V^ref

(Threshold voltage)

IN

Input

enable

Schmitt trigger input with hysteresis characteristics

Type 5

Type 19

V^DD

P-ch

Data

IN/OUT

OUT

Output

disable

N-ch

Intput

enable

14

µPD78363A, 78365A, 78366A, 78368A

2. CPU ARCHITECTURE

2.1

MEMORY SPACE

The µPD78366A can access a memory space of 64K bytes. Figures 2-1 through 2-3 show the memory map.

Figure 2-1. Memory Map (µPD78368A)

MODE0, 1 = LL

MODE0, 1 = HH

ROM-less mode

FFFFH

Special function register

(SFR)

General-purpose

register (128 × 8)

FEFFH

FE80H

(256 × 8)

FF00H

FEFFH

FE25H

FE06H

Macro service

control (32 × 8)

Main RAM

(256 × 8)

FF00H

FDFFH

Data memory

Peripheral RAM

(1792 × 8)

Data area

(768 × 8)

F700H

F6FFH

F700H

BFFFH

Memory space

(64 K × 8)

Program area

Note

Program memory

Data memory

External memory

1000H

0FFFH

(14080 × 8)

External memory

CALLF instruction entry area

(63232 × 8)

(2048 × 8)

0800H

07FFH

C000H

BFFFH

Program area

0080H

007FH

CALLT instruction table area

0FFFH

(64 × 8)

Program memory

Data memory

Internal ROM

(49152 × 8)

0040H

003FH

Vector table area

(64 × 8)

0000H

Note Accessed in external memory expansion mode.

Caution For word access (including stack operations) to the main RAM area (FE00H-FEFFH), the

address that specifies the operand must be an even value.

15

µPD78363A, 78365A, 78366A, 78368A

Figure 2-2. Memory Map (µPD78365A, 78366A)

MODE0, 1 = HH

MODE0, 1 = LL

PD78366A)

µ

PD78365A

PD78366A in ORM-less mode

(

µ

FFFFH

Special function register

(SFR)

General-purpose

register (128 × 8)

FEFFH

FE80H

(256 × 8)

FF00H

FEFFH

FE25H

FE06H

Macro service

control (32 × 8)

Main RAM

(256 × 8)

FF00H

FDFFH

Data memory

Peripheral RAM

(1792 × 8)

Data area

(2048 × 8)

F700H

F6FFH

F700H

7FFFH

Memory space

(64 K × 8)

Program area

Note

Program memory

Data memory

External memory

1000H

0FFFH

(30464 × 8)

External memory

CALLF instruction entry area

(63232 × 8)

(2048 × 8)

0800H

07FFH

8000H

7FFFH

Program area

0080H

007FH

CALLT instruction table area

0FFFH

(64 × 8)

Program memory

Data memory

Internal ROM

(32768 × 8)

0040H

003FH

Vector table area

(64 × 8)

0000H

Note Accessed in external memory expansion mode.

Caution For word access (including stack operations) to the main RAM area (FE00H-FEFFH), the

address that specifies the operand must be an even value.

16

µPD78363A, 78365A, 78366A, 78368A

Figure 2-3. Memory Map (µPD78363A)

MODE0, 1 = LL

MODE0, 1 = HH

ROM-less mode

FFFFH

Special function register

(SFR)

General-purpose

register (128 × 8)

FEFFH

FE80H

(256 × 8)

FF00H

FEFFH

FE25H

FE06H

Macro service

control (32 × 8)

Main RAM

(256 × 8)

FF00H

FDFFH

Data memory

Peripheral RAM

(512 × 8)

Data area

(768 × 8)

FC00H

FBFFH

FC00H

5FFFH

Memory space

(64 K × 8)

Program area

Note

Program memory

Data memory

External memory

1000H

0FFFH

(39936 × 8)

External memory

CALLF instruction entry area

(64512 × 8)

(2048 × 8)

0800H

07FFH

6000H

5FFFH

Program area

0080H

007FH

CALLT instruction table area

0FFFH

(64 × 8)

Program memory

Data memory

Internal ROM

(24576 × 8)

0040H

003FH

Vector table area

(64 × 8)

0000H

Note Accessed in external memory expansion mode.

Caution For word access (including stack operations) to the main RAM area (FE00H-FEFFH), the

address that specifies the operand must be an even value.

17

µPD78363A, 78365A, 78366A, 78368A

2.2

DATA MEMORY ADDRESSING

The µPD78366A is provided with many addressing modes that improve the operability of the memory and

can be used with high-level languages. Especially, an area of addresses F700H-FFFFH (In the µPD78363A,

FC00H-FFFFH) to which the data memory is mapped can be addressed in a mode peculiar to the functions

provided in this area, including special function registers (SFR) and general-purpose registers.

Figure 2-4. Data Memory Addressing (µPD78368A)

FFFFH

Special function

register

(SFR)

SFR addressing

FF20H

FF1FH

FF00H

FEFFH

General-purpose

register

Short direct addressing

Register addressing

FE80H

FE7FH

FE20H

FE1FH

Main RAM

FE00H

FDFFH

Direct addressing

Register indirect addressing

Based addressing

Peripheral RAM

Based indexed addressing

(with displacement)

F700H

F6FFH

External memory

6C00H

BFFFH

Note

Internal ROM

0000H

Note Is external memory in the ROMless mode.

Caution For word access (including stack oprations) to the main RAM area (FE00H-FEFFH), the address

that specifies the operand must be an even value.

18

µPD78363A, 78365A, 78366A, 78368A

Figure 2-5. Data Memory Addressing (µPD78365A, 78366A)

FFFFH

Special function

register

(SFR)

SFR addressing

FF20H

FF1FH

FF00H

FEFFH

General-purpose

register

Short direct addressing

Register addressing

FE80H

FE7FH

FE20H

FE1FH

Main RAM

FE00H

FDFFH

Direct addressing

Register indirect addressing

Based addressing

Peripheral RAM

Based indexed addressing

(with displacement)

F700H

F6FFH

External memory

8000H

7FFFH

Note

Internal ROM

0000H

Note Is external memory in the ROMless mode of the µPD78365A or µPD78366A.

Caution For word access (including stack oprations) to the main RAM area (FE00H-FEFFH), the address

that specifies the operand must be an even value.

19

µPD78363A, 78365A, 78366A, 78368A

Figure 2-6. Data Memory Addressing (µPD78363A)

FFFFH

Special function

register

(SFR)

SFR addressing

FF20H

FF1FH

FF00H

FEFFH

General-purpose

register

Short direct addressing

Register addressing

FE80H

FE7FH

FE20H

FE1FH

Main RAM

FE00H

FDFFH

Direct addressing

Register indirect addressing

Based addressing

Peripheral RAM

Based indexed addressing

(with displacement)

FC00H

FBFFH

External memory

6000H

5FFFH

Note

Internal ROM

0000H

Note Is external memory in the ROMless mode.

Caution For word access (including stack oprations) to the main RAM area (FE00H-FEFFH), the address

that specifies the operand must be an even value.

2.3

PROCESSOR REGISTERS

The µPD78366A is provided with the following three types of processor registers:

• Control registers

• General-purpose registers

• Special function registers (SFRs)

20

µPD78363A, 78365A, 78366A, 78368A

2.3.1 Control Registers

(1) Program counter (PC)

This is a 16-bit register that holds an address of the instruction to be executed next.

(2) Program status word (PSW)

This 16-bit register indicates the status of the CPU as a result of instruction execution.

(3) Stack pointer (SP)

This 16-bit register indicates the first address of the stack area (LIFO) of the memory.

(4) CPU control word (CCW)

This 8-bit register is used to control the CPU.

Figure 2-7. Configuration of Control Registers

15

0

PC

PSW

SP

7

0

CCW

Figure 2-8. Configuration of PSW

8

0

15

7

UF

S

RBS2

RBS1

RSS

RBS0

AC

0

PSW

Z

IE

P/V

0

CY

UF

: User flag

RBS0-RBS2: Register bank select flag

S

: Sign flag (MSB of execution result)

: Zero flag

Z

RSS

AC

IE

: Register set select flag

: Auxiliary carry flag

: Interrupt request enable flag

: Parity/overflow flag

: Carry flag

P/V

CY

Figure 2-9. Configuration of CCW

0

7

CCW

0

TPF

0

TPF

: Table position flag

21

µPD78363A, 78365A, 78366A, 78368A

2.3.2 General-Purpose Registers

The µPD78366A is provided with eight banks of general-purpose registers with one bank consisting of 8

words × 16 bits. Figure 2-10 shows the configuration of the general-purpose register banks. The general-

purpose registers are mapped to an area of addresses FE80H-FEFFH. Each of these registers can be used

as an 8-bit register. In addition, two registers can be used as one 16-bit register pair (refer to Figure 2-11 ).

These general-purpose registers facilitate complicated multitask processing.

Figure 2-10. Configuration of General-Purpose Register Banks

Bank 7

Bank 1

Bank 0

RP7

RP6

RP5

RP4

RP3

RP2

RP1

RP0

15

0

Figure 2-11. Processing Bits of General-Purpose Registers

8-bit processing

16-bit processing

FEFFH

RBNK0

RBNK1

RBNK2

RBNK3

RBNK4

RBNK5

RBNK6

RBNK7

R15

R13

R11

R9

R14

R12

R10

R8

(FH)

(DH)

(BH)

(9H)

(7H)

(5H)

(3H)

(1H)

RP7

RP6

RP5

RP4

RP3

RP2

RP1

RP0

(EH)

(CH)

(AH)

(8H)

(6H)

(4H)

(2H)

(0H)

R7

R6

R5

R4

R3

R2

R1

R0

FE80H

7

07

0

15

0

22

µPD78363A, 78365A, 78366A, 78368A

2.3.3 Special Function Registers (SFR)

Special function registers (SFRs) are registers assigned special functions such as mode registers and control

registers for internal peripheral hardware, and are mapped to a 256-byte address space at FF00H through

FFFFH.

Table 2-1 lists the SFRs. The meanings of the symbols in this table are as follows:

• Symbol ................................... Indicates the mnemonic symbol for an SFR.

This mnemonic can be coded in the operand field of an instruction.

• R/W ........................................ Indicates whether the SFR can be read or written.

R/W : Read/write

R

: Read only

: Write only

W

• Bit units for manipulation ...... Indicates bit units in which the SFR can be manipulated. The SFRs that

can be manipulated in 16-bit units can be coded as an sfrp operand.

Specify an even address for these SFRs.

The SFRs that can be manipulated in 1-bit units can be coded as the

operand of bit manipulation instructions.

• On reset ................................. Indicates the status of the register at RESET input.

Cautions 1. Do not access the addresses in the range FF00H through FFFFH to which no special

function register is allocated. If these addresses are accessed, malfunctioning may

occur.

2. Do not write data to the read-only registers. Otherwise, the internal circuit may not

operate normally.

3. When using read data as byte data, process undefined bit(s) first.

4. TOUT and TXS are write-only registers. Do no read these registers.

5. Bits 0, 1, and 4 of SBIC are write-only bits. When these bits are read, they are always

"0".

23

µPD78363A, 78365A, 78366A, 78368A

Table 2-1. List of Special Function Registers (1/5)

Bit units for

manipulation

Address

Special function register (SFR)

Symbol

R/W

On reset

1 bit

●

8 bits 16 bits

FF00H

FF01H

FF02H

FF03H

FF04H

FF05H

FF07H

FF08H

FF09H

FF10H

FF11H

FF12H

FF13H

FF14H

FF15H

FF16H

FF17H

FF18H

FF19H

FF1AH

FF1BH

FF1CH

FF1DH

FF1EH

FF1FH

FF20H

FF21H

FF23H

FF25H

FF28H

FF29H

FF2CH

FF2DH

FF2EH

FF2FH

FF30H

FF31H

FF32H

FF33H

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 7

Port 8

Port 9

P0

P1

P2

P3

●

–

R/W

R

●

Note

P4

P5

P7

P8

P9

R/W

R

●

Note

●

Compare register 00

Compare register 01

Compare register 02

Compare register 03

Buffer register CM00

Buffer register CM01

Buffer register CM02

Timer register 0

CM00

CM01

–

●

Undefined

CM02

R/W

CM03

BFCM00

BFCM01

BFCM02

TM0

R

0000H

FFH

Port 0 mode register

Port 1 mode register

Port 3 mode register

Port 5 mode register

Port 8 mode register

Port 9 mode register

PM0

PM1

PM3

●

–

×

111 1111B

FFH

R/W

Note

PM5

PM8

PM9

××11 1111B

×××× 1111B

Reload register

DTIME

–

●

Undefined

00H

Timer unit mode register 0

Timer unit mode register 1

TUM0

TUM1

●

–

R/W

Compare register 10

Timer register 1

CM10

TM1

–

●

Undefined

0000H

R

Note Not provided for the µPD78365A.

24

µPD78363A, 78365A, 78366A, 78368A

Table 2-1. List of Special Function Registers (2/5)

Bit units for

manipulation

Address

Special function register (SFR)

Symbol

R/W

On reset

1 bit

–

8 bits 16 bits

FF34H

FF35H

FF36H

FF37H

FF38H

FF39H

FF3AH

FF3BH

FF3CH

FF3DH

FF40H

FF43H

FF44H

FF45H

FF48H

FF4EH

FF4FH

FF50H

FF51H

FF52H

FF53H

FF54H

FF55H

FF56H

FF57H

FF58H

FF59H

FF5AH

FF5BH

FF5CH

FF5DH

FF5EH

FF5FH

FF60H

FF61H

FF62H

FF68H

Capture/compare register 20

Capture register 20

Timer register 2

CC20

CT20

–

●

Undefined

–

R

TM2

0000H

Buffer register CM03

BFCM03

Underfined

External interrupt mode register 0

External interrupt mode register 1

Port 0 mode control register

Port 3 mode control register

Pull-up resistor option register L

Pull-up resistor option register H

Port 8 mode control register

Sampling control register 0

INTM0

INTM1

PMC0

PMC3

PUOL

●

–

00H

×000 0000B

00H

R/W

PUOH

PMC8

SMPC0

SMPC1

××00 0000B

00H

Sampling control register 1

Capture/compare register 30

Capture register 30

Capture register 31

Timer register 3

CC30

CT30

CT31

TM3

–

●

Undefined

R

0000H

Undefined

0000H

Compare register 40

Compare register 41

Timer register 4

CM40

CM41

TM4

R/W

R

Timer control register 4

TMC4

TOUT

RTP

R/W

W

–

●

–

00H

Timer out register

–

××01 0101B

Undefined

Real-time output port register

Real-time output port mode register

Port read control register

A/D converter mode register

●

RTPM

PRDC

ADM

R/W

00H

25

µPD78363A, 78365A, 78366A, 78368A

Table 2-1. List of Special Function Registers (3/5)

Bit units for

manipulation

Address

Special function register (SFR)

Symbol

R/W

On reset

1 bit

●

–

8 bits 16 bits

FF70H

FF71H

FF72H

FF73H

FF74H

FF75H

FF76H

FF77H

FF78H

FF79H

FF7AH

FF7BH

FF7CH

FF7DH

FF7EH

FF7FH

FF80H

FF82H

FF84H

FF85H

FF86H

FF88H

FF8AH

FF8CH

FF8EH

FFA0H

FFA1H

FFA2H

FFA3H

Slave buffer register 0

SBUF0

SBUF1

SBUF2

SBUF3

SBUF4

SBUF5

MBUF0

MBUF1

MBUF2

MBUF3

MBUF4

MBUF5

TMC0

TMC1

TMC2

TMC3

CSIM

●

–

Slave buffer register 1

Slave buffer register 2

Slave buffer register 3

Slave buffer register 4

Slave buffer register 5

Undefined

Master buffer register 0

Master buffer register 1

Master buffer register 2

R/W

Master buffer register 3

Master buffer register 4

Master buffer register 5

Timer control register 0

Timer control register 1

Timer control register 2

Timer control register 3

00H

Clocked serial interface mode register

Serial bus interface control register

Baud rate generator control register

Baud rate generator compare register

Serial I/O shift register

Note

SBIC

R/W

BRGC

BRG

Undefined

R/W

SIO

●

–

Asynchronous serial interface mode register

Asynchronous serial interface status register

Serial receive buffer: UART

Serial transfer shift register: UART

PWM control register 0

ASIM

80H

00H

ASIS

R

RXB

Undefined

00H

TXS

–

W

PWMC0

PWMC1

PWM0L

●

PWM control register 1

PWM register 0L

R/W

Undefined

PWM register 0

PWM0

–

●

Note Bits 7 and 5

: read/write

Bits 6, 3, and 2 : read-only

Bits 4, 1, and 0 : write-only

26

µPD78363A, 78365A, 78366A, 78368A

Table 2-1. List of Special Function Registers (4/5)

Bit units for

manipulation

Address

Special function register (SFR)

Symbol

R/W

On reset

1 bit

8 bits 16 bits

FFA4H

FFA5H

FFA8H

FFAAH

FFACH

FFADH

FFB0H

FFB1H

FFB2H

FFB3H

FFB4H

FFB5H

FFB6H

FFB7H

FFB8H

FFB9H

FFBAH

FFBBH

FFBCH

FFBDH

FFBEH

FFBFH

FFC0H

FFC1H

FFC2H

PWM register 1L

PWM1L

PWM1

●

–

R/W

R

Undefined

PWM register 1

–

●

In-service priority register

Interrupt mode control register

Interrupt mask register 0L

ISPR

IMC

●

–

00H

80H

FFH

MK0L

R/W

Interrupt mask register 0

MK0

–

●

–

●

–

●

–

FFFFH

FFH

Interrupt mask register 0H

MK0H

A/D conversion result register 0

A/D conversion result register 0H

A/D conversion result register 1

A/D conversion result register 1H

A/D conversion result register 2

A/D conversion result register 2H

A/D conversion result register 3

A/D conversion result register 3H

A/D conversion result register 4

A/D conversion result register 4H

A/D conversion result register 5

A/D conversion result register 5H

A/D conversion result register 6

A/D conversion result register 6H

A/D conversion result register 7

ADCR0

ADCR0H

ADCR1

ADCR1H

ADCR2

ADCR2H

ADCR3

ADCR3H

ADCR4

ADCR4H

ADCR5

ADCR5H

ADCR6

ADCR6H

ADCR7

ADCR7H

●

–

●

–

●

–

●

–

●

–

●

–

●

–

R

Undefined

●

–

●

–

●

–

●

–

●

–

●

–

●

–

●

A/D conversion result register 7H

Standby control register

CPU control word

–

●

–

Note

STBC

0000 ×000B

CCW

R/W

●

–

00H

Note

Watchdog timer mode register

WDM

Note Can be written when a special instruction is executed.

27

µPD78363A, 78365A, 78366A, 78368A

Table 2-1. List of Special Function Registers (5/5)

Bit units for

manipulation

Address

Special function register (SFR)

Symbol

R/W

On reset

1 bit

8 bits 16 bits

FFC4H

FFC6H

FFC7H

FFD0H

|

Memory expansion mode register

Programmable wait control register

MM

●

–

Note

PWC

–

●

C0AAH

External SFR area

–

●

–

Undefined

FFDFH

FFE0H

FFE1H

FFE2H

FFE3H

FFE4H

FFE5H

FFE6H

FFE7H

FFE8H

FFE9H

FFEAH

FFEBH

FFECH

FFEDH

FFEEH

FFEFH

Interrupt control register (INTOV3)

Interrupt control register (INTP0/INTCC30)

Interrupt control register (INTP1)

Interrupt control register (INTP2)

Interrupt control register (INTP3/INTCC20)

Interrupt control register (INTP4)

Interrupt control register (INTTM0)

Interrupt control register (INTCM03)

Interrupt control register (INTCM10)

Interrupt control register (INTCM40)

Interrupt control register (INTCM41)

Interrupt control register (INTSER)

Interrupt control register (INTSR)

Interrupt control register (INTST)

Interrupt control register (INTCSI)

Interrupt control register (INTAD)

OVIC3

PIC0

●

–

PIC1

PIC2

PIC3

R/W

PIC4

TMIC0

CMIC03

CMIC10

CMIC40

CMIC41

SERIC

SRIC

43H

STIC

CSIIC

ADIC

Note The value of the MW register at reset time differs depending on the product.

µPD78363A : 60H

µPD78365A, 78366A : 20H

µPD78368A : 00H

28

µPD78363A, 78365A, 78366A, 78368A

3. FUNCTIONAL BLOCKS

3.1

EXECUTION UNIT (EXU)

EXU controls address computation, arithmetic and logical operations, and data transfer through microprogram.

EXU has an internal main RAM. This RAM can be accessed by instructions faster than the peripheral RAM.

3.2

BUS CONTROL UNIT (BCU)

BCU starts necessary bus cycles according to the physical address obtained by the execution unit (EXU).If

EXU does not request start of the bus cycle, an address is generated to prefetch an instruction. The prefetched

op code is stored in an instruction queue.

3.3

ROM/RAM

The internal ROM and RAM capacities differ depending on the product.

The µPD78363A has a 24-KB ROM and a 512-B peripheral RAM. The µPD78366A has a 32-KB ROM and

a 1792-B peripheral RAM. The µPD78368A has a 48-KB ROM and a 1792-B peripheral RAM. The µPD78365A

does not have a ROM and only has a 1792-B peripheral RAM.

Access to the ROM can be disabled by using the MODE0 and MODE1 pins, in which case an external memory

of 64 KB can be accessed.

29

µPD78363A, 78365A, 78366A, 78368A

3.4

PORT FUNCTIONS

The µPD78366A is provided with the ports shown in Figure 3-1 for various control operations.

The functions of each port are listed in Table 3-1. These ports function not only as digital ports but also as

input/output lines of the internal hardware.

Figure 3-1. Port Configuration

P00

P50

P57

Port 0

Port 5

Port 7

P07

P10

8

P70-P77

P80

Port 1

P17

P20

Port 8

Port 9

Port 2

Port 3

P85

P90

P25

P30

P93

P36

8

Port 4

P40-P47

30

µPD78363A, 78365A, 78366A, 78368A

Table 3-1. Functions of Each Port

Port

Port function

Multiplexed function

8-bit I/O port. Can be set in input or

output mode in 1-bit units.

In control mode, serves as real-time output port (RTP), or

input operation control signal of real-time pulse unit (RPU)

and output PWM signal.

Port 0

8-bit I/O port. Can be set in input or

output mode in 1-bit units.

Port 1

Port 2

Port 3

Port 4

—

6-bit input port.

Inputs external interrupt and count pulse of real-time pulse

unit (RPU) (fixed to the control mode).

7-bit I/O port. Can be set in input or

output in 1-bit units.

In control mode, inputs/outputs signals of serial interfaces

(UART, CSI).

8-bit I/O port. Can be set in input or

output mode in 8-bit units.

Address data bus (AD0-AD7) when memory is externally

expanded.

8-bit I/O port. Can be set in input or

output mode in 1-bit units.

Address bus (A8-A15) when memory is externally expanded.

Port 5

Port 7

8-bit input port.

Input analog signals to A/D converter (fixed to the control

mode).

6-bit I/O port. Can be set in input or

output mode in 1-bit units.

In control mode, outputs timer of real-time pulse unit (RPU).

Port 8

Port 9

4-bit I/O port. Can be set in input or

output mode in 1-bit units.

Outputs control signal when memory is externally expanded.

31

µPD78363A, 78365A, 78366A, 78368A

3.5

CLOCK GENERATOR CIRCUIT

The clock generator circuit generates and controls the internal system clock (CLK) that is supplied to the CPU.

Figure 3-2. Block Diagram of Clock Generator Circuit

Frequency

divider

Frequency

divider

X1

X2

System

cloock

oscillator

circuit

PLL

control

circuit

f

CLK

f

XX

Internal system

clock (CLK)

1/2

or

f

X

STOP mode

Remarks 1. fXX : crystal oscillation frequency

2. f^X: external clock frequency

3. fCLK: internal system clock frequency

By connecting an 8-MHz crystal resonator across the X1 and X2 pins, an internal system clock of up to 16

MHz (f^CLK) can be generated.

The system clock oscillation circuit oscillates by using the crystal resonator connected across the X1 and

X2 pins. It stops oscillation in standby mode.

An external clock can also be input. To do so, input the clock signal to the X1 pin and leave the X2 pin open.

Caution Do not set STOP mode when the external clock is used.

32

µPD78363A, 78365A, 78366A, 78368A

Figure 3-3. External Circuit of System Clock Oscillator Circuit

(a) crystal oscillator

PD78366A

(b) external clock

PD78366A

µ

V

X1

SS

X1

X2

Open X2

Cautions 1. Wire the portion enclosed by dotted line in Figure 3-3 as follows to avoid adverse

influences due to wiring capacity when using the system clock oscillation circuit.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal line. Make sure that the wiring is not close

to lines through which a high alternating current flows.

• Always keep the ground point of the capacitor of the oscillation circuit at the same

potential as V^SS. Do not ground the circuit to a ground pattern through which a high

current flows.

• Do not extract signals from the oscillator circuit.

2. To input an external clock, do not connect a load such as wiring capacitance to the X2

pin.

33

µPD78363A, 78365A, 78366A, 78368A

3.6

REAL-TIME PULSE UNIT (RPU)

The real-time pulse unit (RPU) can measure pulse intervals and frequencies, and output programmable

pulses (six channels of PWM control signals).

The RPU consists of five 16-bit timers (timers 0 through 4), of which one is provided with a 10-bit dead time

timer, which is ideal for inverter control. In addition, a function to turn off the output by the software or an external

interrupt is also provided.

Each timer has the following features:

•

Timer 0 : Controls the PWM period of the TO00 through TO05 pins. In addition, operates as a

general-purpose interval timer. Timer 0 has the following five operation modes:

• General-purpose interval timer mode

• PWM mode 0 (symmetrical triangular wave)

• PWM mode 0 (asymmetrical triangular wave)

• PWM mode 0 (saw-tooth wave)

• PWM mode 1

•

Timer 1 : Operates as a general-purpose interval timer.

Timers 2, 3 : Has a programmable input sampling circuit that rejects the noise of an input signal,

and a capture function.

•

Timer 4 : Operates as a general-purpose timer or an up-down counter. When operating as a general-

purpose timer, controls the PWM cycle of the TO40 output pin. Timer 4 has the following

two operation modes:

• General-purpose timer mode

• Up/down counter mode (UDC mode)

34

µPD78363A, 78365A, 78366A, 78368A

The RPU consists of the hardware shown in Table 3-2. Figures 3-4 through 3-12 show the block diagrams

of the respective timers.

Table 3-2. Configuration of Real-Time Pulse Unit (RPU)

Compare

register

coincidence

interrupt

Capture

trigger

Timer

output

Timer

clear

Timer register

Register

16-bit compare register (CM00)

16-bit compare register (CM01)

16-bit compare register (CM02)

16-bit compare register (CM03)

16-bit compare register (CM10)

16-bit capture/compare register (CC20)

16-bit capture register (CT20)

16-bit capture/compare register (CC30)

16-bit capture register (CT30)

16-bit capture register (CT31)

16-bit compare register (CM40)

16-bit compare register (CM41)

–

6

INTCM03

Timer 0 16-bit timer (TM0)

–

INTCM03

INTCM10

INTCC20

–

Timer 1 16-bit timer (TM1)

Timer 2 16-bit timer (TM2)

–

INTCM10

INTCC20

INTP3

INTP0

INTP1

INTP4

INTCC30

–

1

INTCC30

Timer 3 16-bit timer (TM3)

Timer 4 16-bit timer (TM4)

–

TCLRUD

INTCM40

INTCM41

–

35

µPD78363A, 78365A, 78366A, 78368A

Figure 3-4. Block Diagram of Timer 0 (PWM mode 0 ... symmetrical triangular wave,

asymmetrical triangular wave)

BFCM03

CM03

16

TM0

INTCM03

f

CLK

CLK/2

CLK/4

CLK/8

CLK/16

INTTM0

UP = 0

DOWN = 1

U/D

f

CLK

DTIME

10

ALVTO

16

Output off function

by external interrupt

and software

BFCM00

CM00

CM01

CM02

R

Underflow

DTM0

R

S

TO00

(U phase)

S

R

S

TO01

(U phase)

BFCM01

R

S

DTM1

R

S

TO02

(V phase)

R

S

TO03

(V phase)

BFCM02

R

S

DTM2

R

S

TO04

(W phase)

R

S

TO05

(W phase)

TM0

CM00-CM03

BFCM00-BFCM03: Buffer registers

: Timer register

ALVTO: Bit 2 of TUM0 register

U/D : Bit 3 of TMC0 register

: Compare registers

DTIME

: Reload register

DTM0-DTM2

: Dead time timers

Remark f^CLK: internal system clock

36

µPD78363A, 78365A, 78366A, 78368A

Figure 3-5. Block Diagram of Timer 0 (PWM mode 0 ... saw-tooth wave)

BFCM03

CM03

16

TM0

INTCM03

Clear

f

CLK

CLK/2

CLK/4

CLK/8

CLK/16

f

CLK

DTIME

10

ALVTO

16

Output off function

by external interrupt

and software

BFCM00

CM00

CM01

CM02

R

S

Underflow

DTM0

R

S

TO00

(U phase)

R

S

TO01

(U phase)

BFCM01

R

S

DTM1

R

S

TO02

(V phase)

R

S

TO03

(V phase)

BFCM02

R

S

DTM2

R

S

TO04

(W phase)

R

S

TO05

(W phase)

TM0

CM00-CM03

BFCM00-BFCM03: Buffer registers

: Timer register

: Compare registers

DTIME

: Reload register

DTM0-DTM2

ALVTO

: Dead time timers

: Bit 2 of TUM0 register

Remark f^CLK: internal system clock

37

µPD78363A, 78365A, 78366A, 78368A

Figure 3-6. Block Diagram of Timer 0 (PWM mode 1)

BFCM03

CM03

16

TM0

INTCM03

Clear

f

CLK

CLK/2

CLK/4

CLK/8

CLK/16

DTIME

10

f

CLK

16

6-bit buffer

register

6-bit buffer

register

BFCM00

MBUF1

MBUF0

MBUF3

MBUF2

MBUF5

MBUF4

Underflow

CM00

CM01

CM02

T

DTM0

DTM1

DTM2

SBUF1

SBUF0

SBUF3

SBUF2

SBUF5

SBUF4

BFCM01

BFCM02

6-bit write-only

register

TOUT

Output off function

by external interrupt

and software

TO00 TO02 TO04

(U phase) (V phase)(W phase)

TO01 TO03 TO05

(U phase) (V phase)(W phase)

TM0

CM00-CM03

BFCM00-BFCM03: Buffer registers

: Timer register

MBUF0-MBUF5 : Master buffer registers

SBUF0-SBUF5 : Slave buffer registers

: Compare registers

TOUT

: Timer out register

DTIME

: Reload register

DTM0-DTM2

: Dead time timers

Remark f^CLK: internal system clock

38

µPD78363A, 78365A, 78366A, 78368A

Figure 3-7. Block Diagram of Timer 0 (general-purpose interval timer mode)

Master buffer register

(MBUF0)

INTCM03

Compare register

CM03

6

16

Slave buffer register

(SBUF0)

Timer register

TM0

6

Clear

Timer out register

(TOUT)

Output off function by external

interrupt and software

TO00 TO02 TO04

TO01 TO03 TO05

Figure 3-8. Block Diagram of Timer 1

Clear

f

CLK/4

CLK/8

Timer register

TM1

f

CLK/16

TI

16

INTCM10

Compare register

CM10

Remark fCLK: internal system clock

39

µPD78363A, 78365A, 78366A, 78368A

Figure 3-9. Block Diagram of Timer 2

Clear

CLR2

f

CLK/2²

CLK/2³

CLK/2⁴

CLK/2⁵

CLK/2⁶

CLK/2⁸

CLK/2⁹

CLK/2¹⁰

Timer register TM2

16

4-point sampling

noise rejection

circuit

Capture/compare

register CC20

INTP3

INTP3/INTCC20

f

CLK

CLK/2²

CLK/2³

CLK/2⁴

CLK/2⁶

CLK/2⁷

CLK/2⁸

Capture register CT20

Remark fCLK: internal system clock

Figure 3-10. Block Diagram of Timer 3

Clear

CLR3

f

CLK/2²

CLK/2³

CLK/2⁴

CLK/2⁵

CLK/2⁶

CLK/2⁸

INTOV3

Timer register TM3

16

4-point sampling

noise rejection

circuit

Capture/compare

register CC30

INTP0

INTP1

INTP4

INTP0/INTCC30

f

CLK

CLK/2²

CLK/2³

CLK/2⁴

4-point sampling

noise rejection

circuit

INTP1

Capture register CT30

f

CLK

CLK/2²

CLK/2³

CLK/2⁴

4-point sampling

noise rejection

circuit

INTP4

Capture register CT31

f

CLK

CLK/2²

CLK/2³

CLK/2⁴

Remark fCLK: internal system clock

40

µPD78363A, 78365A, 78366A, 78368A

Figure 3-11. Block Diagram of Timer 4 (General-Purpose Timer Mode)

Clear

f

CLK

f

CLK/2

CLK/4

Timer register

TM4

f

CLK/8

f

CLK/16

INTCM40

f

CLK/32

16

ALV40

Compare register

S

R

Q

CM40

TO40

Compare register

CM41

INTCM41

Remark fCLK: internal system clock

Figure 3-12. Block Diagram of Timer 4 (UDC Mode)

Clear

TCLRUD

fCLK/4

f^CLK/8

f^CLK/16

OVF

UDF

Timer register

TM4

Pre-set

16

TIUD

Up/down

detector

Compare register

CM40

INTCM40

INTCM41

TCUD

Compare register

CM41

Remark fCLK: internal system clock

41

µPD78363A, 78365A, 78366A, 78368A

3.7

REAL-TIME OUTPUT PORT (RTP)

The real-time output port is a 4-bit port that can output the contents of the real-time output port register (RTP)

in synchronization with the trigger signal from the real-time pulse unit (RPU). It can output synchronization

pulses of multiple channels.

Also, PWM modulation can be applied to P00-P03.

Figure 3-13. Block Diagram of Real-Time Output Port

Internal bus

4

RTP

INTCM03 (from RPU)

4

INTCM10 (from RPU)

INTP0/INTCC30 (from RPU)

Software trigger

Output trigger

control circuit

RTPM

PWM0

PWM1

PWM signal

control circuit

Output latch

(P03-P00)

P03P02 P01P00

42

µPD78363A, 78365A, 78366A, 78368A

3.8

A/D CONVERTER

The µPD78366A contains a high-speed, high-resolution 10-bit analog-to-digital (A/D) converter (conversion

time 12.6 µs at an internal clock frequency of 16 MHz). Successive approximation type is adopted. This

converter is provided with eight analog input lines (ANI0-ANI7) and can perform various operations as the

application requires, in select, scan, and mixed modes.

When A/D conversion ends, an internal interrupt (INTAD) occurs. This interrupt can start a macro service

that executes automatic data transfer through hardware.

Figure 3-14. Block Diagram of A/D Converter

AV^DD

Sample & hold

ANI0

ANI1

AVREF

Resistor

string

ANI2

ANI3

AVSS

ANI4

ANI5

ANI6

ANI7

Comparator

0

9

10

SAR (10)

10

0

ADCR0

ADCR1

ADCR2

INTCM03

INTP2

Controller

ADCR3

ADCR4

(Start trigger)

ADCR5

ADCR6

ADCR7

ADM (8)

8

10

Internal bus

43

µPD78363A, 78365A, 78366A, 78368A

3.9

SERIAL INTERFACE

The µPD78366A is provided with the following two independent serial interfaces:

• Asynchronous serial interface (UART) (with pin selection function)

• Clocked serial interface

• 3-line serial I/O mode

• Serial bus interface mode (SBI mode)

Since the µPD78366A contains a baud rate generator (BRG), any serial transfer rate can be set regardless

of the operating clock frequency. The baud rate generator is a block to generate the shift clock for the transmit/

receive serial interface, and is used commonly with the two channels of the serial interfaces.

The serial transfer rate can be selected in a range of 110 bps to 38.4 Kbps by the mode register.

Figure 3-15. Block Diagram of Asynchronous Serial Interface

Internal bus

ASIM

Receive

buffer

RXE PS1 PS0 CL SL SPS SCK

RXB

SPS

ASIS

PE FE OVE

Receive

shift

register

Transfer

shift

register

R

X

D0

D1

TXS

RX

TXD0

TX

D1

Receive

control

parity

Transfer

control

parity

SPS

INTSER

INTST

check

append

INTSR

Transfer/

receive

baud rate

generator

output

1

—

16

—

16

fCLK/8

44

µPD78363A, 78365A, 78366A, 78368A

Figure 3-16. Block Diagram of Clocked Serial Interface

Internal bus

8

WUP

SBIC

ACKD

RELD

CMDD CMDT

CTXE CRXE

MOD2

ACKE

MOD1 MOD0

BSYE

ACKT

RELT

CLS0

CSIM

CLS1

RELT

CMDT

MOD1

MOD2

0

SO latch

7

SI/SB1

Q

D

Shift register (SIO)

SO/SB0

Busy/

acknow-

ledge

detector

circuit

MOD1

MOD2

MOD1

Bus release/

command/

acknowledge

detector

circuit

WUP

Interrupt

signal

generation

control

Serial

clock

counter

INTCSI

SCK

circuit

Baud rate

generator (BRG)

CLK/8

CLK/32

1/2

Serial clock

control circuit

f

CLS0

CLS1

Figure 3-17. Block Diagram of Baud Rate Generator

Internal bus

7

0

7

0

BRG

BRGC

Coincidence

1

—

2

Clear

f

CLK/2

Prescaler

TMBRG

Serial interface

45

µPD78363A, 78365A, 78366A, 78368A

3.10 PWM UNIT

The µPD78366A is provided with two lines that output 8-/9-/10-/12-bit resolution variable PWM signals. The

PWM output can be used as a digital-to-analog conversion output by connecting an external lowpass filter, and

ideal for controlling actuators such as motors.

An output of between 244 Hz and 62.5 kHz can be obtaind, depending on the combination of the count clock

(62.5 ns to 1 µs) and counter bit length (8, 9, 10, or 12) (at an internal clock frequency of 16 MHz).

Figure 3-18. Block Diagram of PWM Unit

7

8

9

f

CLK

Overflow

CLK/2

CLK/4

CLK/8

CLK/16

ALVn

11

Counter (12)

S

R

Q

0-7

0-8

0-9

PWMn

Coinci-

dence

0-11

Comparator (12)

Compare register CMPn (12)

PWM buffer register n (12)

Remark n = 0, 1

46

µPD78363A, 78365A, 78366A, 78368A

3.11 WATCHDOG TIMER (WDT)

The watchdog timer is a free running timer equipped with a non-maskable interrupt function to prevent

program hang-up or deadlock. When an error of the program is detected, the overflow interrupt (INTWDT) of

the watchdog timer occurs and the watchdog timer output pin (WDTO) goes low. By connecting this output pin

to the RESET pin, any malfunctioning of the application system due to program error can be prevented.

Figure 3-19. Block Diagram of Watchdog Timer

f

CLK/2⁹

CLK/2¹¹

CLK/2¹³

Overflow

Watchdog timer

(8 bits)

S

R

Q

WDTO

Clear

Timer

f

CLK

(5 bits)

Clear

Overflow

WDT CLR

WDT STOP

INTWDT

Oscillation

stabilization

time control circuit

47

µPD78363A, 78365A, 78366A, 78368A

4. INTERRUPT FUNCTIONS

4.1

OUTLINE

The µPD78366A is provided with powerful interrupt functions that can process interrupt requests from the

internal hardware peripherals and external sources. In addition, the following three interrupt processing modes

are available. In addition, four levels of interrupt priority can be specified.

• Vectored interrupt processing

• Macro service

• Context switching

Table 4-1. Interrupt Sources

Interrupt source

Trigger

Vector

table

address

Macro

service

Context

switching

Type

Note

Source unit

Name

NMI

–

NMI pin input

Watchdog timer

Overflow of timer 3

External

WDT

0002H

0004H

0006H

0008H

000AH

000CH

000EH

0010H

0012H

0014H

0016H

0018H

001AH

001CH

001EH

0020H

0022H

0024H

003EH

–

Non-

None

maskable

INTWDT

INTOV3

0

RPU

1

INTP0/INTCC30 INTP0 pin input/CC30 coincidence signal

External/RPU

2

INTP1

INTP2

INTP1 pin input

INTP2 pin input

External

3

4

INTP3/INTCC20 INTP3 pin input/CC20 coincidence signal

External/RPU

External

5

INTP4

INTTM0

INTCM03

INTCM10

INTCM40

INTCM41

INTSER

INTSR

INTP4 pin input

6

Underflow of timer 0

CM03 coincidence signal

CM10 coincidence signal

CM40 coincidence signal

CM41 coincidence signal

Receive error of UART

End of UART reception

End of UART transfer

End of CSI transfer/reception

End of A/D conversion

BRK instruction

7

Maskable

Provided Provided

8

RPU

9

10

11

12

13

14

15

–

UART

INTST

INTCSI

INTAD

CSI

A/D

–

None

BRK

Software

–

BRKCS

TRAP

BRKCS instruction

Provided

None

–

Illegal op code trap

003CH

0000H

Exception

Reset

–

None

–

RESET

Reset input

–

Note Default priority : Priority that takes precedence when two or more maskable interrupts occur at the

same time. 0 is the highest priority, and 15 is the lowest.

48

µPD78363A, 78365A, 78366A, 78368A

4.2

MACRO SERVICE

The µPD78366A has a total of five macro services. Each macro service is described below.

(1) Counter mode: EVTCNT

• Operation

(a) Increments or decrements an 8-bit macro service counter (MSC).

(b) A vector interrupt request is generated when MSC reaches 0.

MSC

+1/–1

• Application example: As event counter, or to measure number of times a value is captured

(2) Block transfer mode: BLKTRS

• Operation

(a) Transfers data block between a buffer and a SFR specified by SFR pointer (SFRP).

(b) The transfer source and destination can be in SFR or buffer area. The length of the transfer data

can be specified to be byte or word.

(c) The number of times the data is to be transferred (block size) is specified by MSC.

(d) MSC is auto decremented by one each time the macro service has been executed.

(e) When MSC reaches 0, a vector interrupt request is generated.

Buffer N

SFRP

MSC

–1

SFR

Buffer 1

Internal bus

• Application example: To transfer/receive data through serial interface

49

µPD78363A, 78365A, 78366A, 78368A

(3) Block transfer mode (with memory pointer): BLKTRS-P

• Operation

This is the block transfer mode in (2) above with a memory pointer (MEMP). The appended buffer

area of MEMP can be freely set on the memory space.

Remark Each time the macro service is executed, MEMP is auto incremented (by one for byte

data transfer and by two for word data transfer).

Buffer N

SFRP

–1

MSC

MEMP

+1/+2

SFR

Buffer 1

Internal bus

• Application example: Same as (2)

(4) Data differential mode: DTADIF

• Operation

(a) Calculates the difference between the contents of SFR (current value) specified by SFRP and the

contents of SFR saved to the last data buffer (LDB).

(b) Stores the result of the calculation in a predetermined buffer area.

(c) Stores the contents of the current value of the SFR in LDB.

(d) The number of times the data is to be transferred (block size) is specified by MSC. Each time the

macro service is executed, MSC is auto decremented by one.

(e) When MSC reaches 0, a vector interrupt request is generated.

Remark The differential calculation can be carried out only with 16-bit SFRs.

SFRP

MSC

–1

LDB

SFR

Buffer N

Buffer 1

Differential calculation

Internal bus

• Application example : To measure cycle and pulse width by the capture register of the real-time

pulse unit (RPU)

50

µPD78363A, 78365A, 78366A, 78368A

(5) Data differential mode (with memory pointer): DTADIF-P

• Operation

This is the data differential mode in (4) above with memory pointer (MEMP). By appending MEMP,

the buffer area in which the differential data is to be stored can be set freely on the memory space.

Remarks 1. The differential calculation can be carried out only with 16-bit SFRs.

2. The buffer is specified by the result of operation by MEMP and MSC^Note. MEMP is

not updated after the data has been transferred.

Note MEMP – (MSC × 2) + 2

SFRP

Buffer N

Buffer 1

–1

MSC

LDB

SFR

MEMP

Differential calculation

Internal bus

• Application example: Same as (4)

51

µPD78363A, 78365A, 78366A, 78368A

4.3

CONTEXT SWITCHING

This function is to select a specific register bank through the hardware, and to branch execution to a vector

address predetermined in the register bank. At the same time, it saves the present contents of the PC and PSW

to the register bank when an interrupt occurs, or when the BRKCS instruction is executed.

4.3.1 Context Switching Function by Interrupt Request

When a context switching enable flag corresponding to each maskable interrupt request is set to 1 in the EI

(interrupt enable) status, the context switching function can be started.

The context switching operation by an interrupt request is performed as follows:

(1) When an interrupt request is generated, a register bank to which the context is to be switched is specified

by the contents of the low-order 3 bits of the row address (even address) of the corresponding vector table.

(2) A predetermined vector address is transferred to the PC in the register bank to which the context is to

be switched, and the contents of the PC and PSW immediately before the switching takes place are saved

to the register bank.

(3) Execution branches to an address indicated by the contents of the PC newly set.

Figure 4-1. Operation of Context Switching

Register Bank

(0-7)

RP0

PC

Exchange

RP1

RP2

RP3

Save

RP4

PSW

RP5

RP6

RP7

52

µPD78363A, 78365A, 78366A, 78368A

4.3.2 Context Switching Function by BRKCS Instruction

The context switching function can be started by the BRKCS instruction.

The operation of context switching by an interrupt request is as follows:

(1) An 8-bit register is specified by the operand of the BRKCS instruction, and the register bank to which

the context is to be switched is specified by the contents of this register (only the low-order 3 bits of 8 bits

are valid).

(2) The vector address predetermined in the register bank to which the context is to be switched is transferred

to the PC, and at the same time, the contents of the PC and PSW immediately before the switching takes

place are saved to the register bank.

(3) Execution branches to the contents of the PC newly set.

4.3.3 Restoration from Context Switching

To restore from the switched context, one of the following two instructions are used. Which instruction is

to be executed is determined by the source that has started the context switching.

Table 4-2. Instructions to Restore from Context Switching

Restore instruction

RETCS

Context switching starting source

Occurrence of interrupt

RETCSB

Execution of BRKCS instruction

53

µPD78363A, 78365A, 78366A, 78368A

5. EXTERNAL DEVICE EXPANSION FUNCTION

The µPD78366A can connect external devices (data memory, program memory, and peripheral devices) in

addition to the internal ROM and RAM areas. To connect an external device, the address/data bus and read/

write strobe signals are controlled by using ports 4, 5, and 9.

Table 5-1. Pin Function with External Device Connected

Pin function with external device connected

Function

Multiplexed address/data bus

Address bus

Name

AD0-AD7

A8-A15

RD

P40-P47

P50-P57

P90

Read strobe

P91

Write strobe

WR

ASTB

Address strobe

ASTB

54

µPD78363A, 78365A, 78366A, 78368A

6. STANDBY FUNCTIONS

The µPD78366A is provided with standby functions to reduce the power consumption of the system. The

standby functions can be effected in the following two modes:

• HALT mode ..... In this mode, the operating clock of the CPU is stopped. By using this mode in

combination with an ordinary operation mode, the µPD78366A operates

intermittently to reduce the total power consumption of the system.

• STOP mode .... In this mode, the oscillator is stopped, and therefore the entire system is stopped.

Therefore, power consumption can be minimized with only a leakage current

flowing.

Each mode is set through software. Figure 6-1 shows the transition of the status in the standby modes (STOP

and HALT modes).

Figure 6-1. Transition of Standby Status

Ordinary

STOP

HALT

55

µPD78363A, 78365A, 78366A, 78368A

7. RESET FUNCTION

When a low level is input to the RESET pin, the system is reset, and each hardware enters the initial status

(reset status). When the RESET pin goes high, the reset status is released, and program execution is started.

Initialize the contents of each register through program as necessary.

Especially, change the number of cycles of the programmable wait control register as necessary.

The RESET pin is equipped with a noise rejecter circuit of analog delay to prevent malfunctioning due to noise.

Cautions 1. While the RESET pin is active (low level), all the pins go into a high-impedance state

(except WDTO, AV^REF, AVDD, AVSS, VDD, VSS, X1, and X2 pins).

2. When an external RAM is connected, do not connect a pull-up resistor to the P90/RD and

P91/WR pins, because the P90/RD and P91/WR pins may go into a high-impedance state,

resulting in destruction of the contents of the external RAM. In addition, signal contention

occurs on the address/data bus, resulting in damage to the input/output circuit.

Figure 7-1. Accepting Reset Signal

RESET input

Analog

delay

Analog

delay

Analog

delay

Reset

accepted

Reset

released

Rejected

as noise

To effect reset on when power is applied, make sure that sufficient time elapses to stabilize the oscillation

after the power is applied until the reset signal is accepted, as shown in Figure 7-2.

Figure 7-2. Reset on Power Application

V

DD

RESET

Oscillation

stabilization

time

Analog

delay

Reset

released

56

µPD78363A, 78365A, 78366A, 78368A

8. INSTRUCTION SET

Write an operand in the operand field of each instruction according to the description of the instruction

(for details, refer to the Assembler Specifications). Some instructions have two or more operands. Select

one of them. Uppercase characters, +, –, #, $, !, [, and ] are keywords and must be written as is.

Write an appropriate numeric value or label as immediate data. To write a label, be sure to write #, $,

!, [, or ].

Table 8-1. Operand Representation and Description

Representation

Description

r

R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15

r1

r2

R0, R1, R2, R3, R4, R5, R6, R7

C, B

rp

RP0, RP1, RP2, RP3, RP4, RP5, RP6, RP7

DE, HL, VP, UP

rp1

rp2

sfr

Special function register symbol (Refer to Table 2-1.)

sfrp

Special function register symbol (register that can be manipulated in 16-bit units. Refer to Table

2-1.)

RP0, RP1, RP2, RP3, RP4, RP5/PSW, RP6, RP7

post

(More than one symbol can be written. However, RP5 can be written only for PUSH and POP

instructions, and PSW can be written only for PUSHU and POPU instructions.)

[DE], [HL], [DE+], [HL+], [DE–], [HL–], [VP], [UP]

; register indirect mode

[DE + A], [HL + A], [DE + B], [HL + B], [VP + DE], [VP + HL] ; based indexed mode

[DE + byte], [HL + byte], [VP + byte], [UP + byte], [SP + byte] ; based mode

mem

word[A], word[B], word[DE], word[HL]

; indexed mode

saddr

FE20H-FF1FH immediate data or label

saddrp

FE20H-FF1EH immediate data (however, bit0 = 0) or label (manipulated in 16-bit units)

$ addr16

! addr16

0000H-FDFFH immediate data or label; relative addressing

0000H-FDFFH immediate data or label; immediate addressing

(However, up to FFFFH can be written for MOV instruction. Only FE00H-FEFFH can be written

for MOVTBLW instruction.)

addr11

addr5

800H-FFFH immediate data or label

Note

40H-7EH immediate data (however, bit0 = 0)

or label

word

byte

bit

16-bit immediate data or label

8-bit immediate data or label

3-bit immediate data or label

3-bit immediate data (0-7)

n

Note Do not access bit0 = 1 (odd address) in word units.

Remarks 1. rp and rp1 are the same in terms of register name that can be written but are different in code

to be generated.

2. r, r1, rp, rp1, and post can be written in absolute name (R0-R15, RP0-RP7) and function name

(X, A, C, B, E, D, L, H, AX, BC, DE, HL, VP, and UP).

3. Immediate addressing can address the entire space. Relative addressing can address only a

range of –128 to +127 from the first address of the next instruction.

57

µPD78363A, 78365A, 78366A, 78368A

Flag

Mnemonic

Operand

Byte

Operation

S

Z

AC P/V CY

r1, #byte

2

3

2

1

2

3

2

r1 ← byte

(saddr) ← byte

sfr ← byte

r ← r1

saddr, #byte

Note

sfr

, #byte

r, r1

A, r1

A ← r1

A, saddr

saddr, A

saddr, saddr

A, sfr

A ← (saddr)

(saddr) ← A

(saddr) ← (saddr)

A ← sfr

sfr, A

sfr ← A

A, mem

1-4 A ← (mem)

1-4 (mem) ← A

MOV

mem, A

A, [saddrp]

[saddrp], A

A, !addr16

!addri16, A

PSWL, #byte

PSWH, #byte

PSWL, A

PSWH, A

A, PSWL

A, PSWH

A, r1

2

4

3

2

1

2

A ← ((saddrp))

((saddrp)) ← A

A ← (addr16)

(addr16) ← A

PSW^L← byte

PSW^H← byte

PSWL ← A

PSWH ← A

A ← PSW^L

A ← PSWH

A ↔ r1

×

r, r1

r ↔ r1

A, mem

2-4 A ↔ (mem)

XCH

A, saddr

A, sfr

2

3

2

3

A ↔ (saddr)

A ↔ sfr

A, [saddrp]

saddr, saddr

A ↔ ((saddrp))

(saddr) ↔ (saddr)

Note When STBC or WDM is written as sfr, this instruction is treated as a dedicated instruction whose number

of bytes is different from that of this instruction.

Remark For symbols in flag, refer to the table below.

Symbol

Remarks

(Blank)

No change

Cleared to 0

Set to 1

0

1

×

Set/cleared according to result

P/V flag functions as parity flag

P/V flag operates as overflow flag

Value previously saved is restored

P

V

R

58

µPD78363A, 78365A, 78366A, 78368A

Flag

Mnemonic

Operand

Byte

Operation

S

Z

AC P/V CY

rp1, #word

3

4

2

3

2

4

rp1 ← word

saddrp, #word

sfrp, #word

rp, rp1

(saddrp) ← word

sfrp ← word

rp ← rp1

AX, saddrp

saddrp, AX

saddrp, saddrp

AX, sfrp

AX ← (saddrp)

(saddrp) ← AX

(saddrp) ← (saddrp)

AX ← sfrp

MOVW

sfrp, AX

sfrp ← AX

rp1, !addr16

!addr16, rp1

AX, mem

mem, AX

AX, saddrp

AX, sfrp

rp1 ← (addr16)

(addr16) ← rp1

2-4 AX ← (mem)

2-4 (mem) ← AX

2

3

2

AX ↔ (saddrp)

AX ↔ sfrp

XCHW

saddrp, saddrp

rp, rp1

(saddrp) ↔ (saddrp)

rp ↔ rp1

AX, mem

A, #byte

2-4 AX ↔ (mem)

2

3

4

2

3

A, CY ← A + byte

×

V

×

saddr, #byte

sfr, #byte

r, r1

(saddr), CY ← (saddr) + byte

sfr, CY ← sfr + byte

r, CY ← r + r1

ADD

A, saddr

A, CY ← A + (saddr)

A, CY ← A + sfr

A, sfr

saddr, saddr

A, mem

(saddr), CY ← (saddr) + (saddr)

2-4 A, CY ← A + (mem)

mem, A

2-4 (mem), CY ← (mem) + A

A, #byte

2

3

4

2

3

A, CY ← A + byte + CY

saddr, #byte

sfr, #byte

r, r1

(saddr), CY ← (saddr) + byte + CY

sfr, CY ← sfr + byte + CY

r, CY ← r + r1 + CY

ADDC

A, saddr

A, CY ← A + (saddr) + CY

A, CY ← A + sfr + CY

A, sfr

saddr, saddr

A, mem

(saddr), CY ← (saddr) + (saddr) + CY

2-4 A, CY ← A + (mem) + CY

mem, A

2-4 (mem), CY ← (mem) + A + CY

59

µPD78363A, 78365A, 78366A, 78368A

Flag

Mnemonic

Operand

Byte

Operation

S

×

Z

×

AC P/V CY

A, #byte

2

3

4

2

3

A, CY ← A – byte

×

V

P

×

saddr, #byte

sfr, #byte

r, r1

(saddr), CY ← (saddr) – byte

sfr, CY ← sfr – byte

r, CY ← r – r1

SUB

A, saddr

A, sfr

A, CY ← A – (saddr)

A, CY ← A – sfr

saddr, saddr

A, mem

mem, A

A, #byte

saddr, #byte

sfr, #byte

r, r1

(saddr), CY ← (saddr) – (saddr)

2-4 A, CY ← A – (mem)

2-4 (mem), CY ← (mem) – A

2

3

4

2

3

A, CY ← A – byte – CY

(saddr), CY ← (saddr) – byte – CY

sfr, CY ← sfr – byte – CY

r, CY ← r – r1 – CY

SUBC

A, saddr

A, sfr

A, CY ← A – (saddr) – CY

A, CY ← A – sfr – CY

saddr, saddr

A, mem

mem, A

A, #byte

saddr, #byte

sfr, #byte

r, r1

(saddr), CY ← (saddr) – (saddr) – CY

2-4 A, CY ← A – (mem) – CY

2-4 (mem), CY ← (mem) – A – CY

2

3

4

2

3

A ← A byte

(saddr) ← (saddr) byte

sfr ← sfr byte

r ← r r1

AND

A, saddr

A, sfr

A ← A (saddr)

A ← A sfr

saddr, saddr

A, mem

mem, A

(saddr) ← (saddr) (saddr)

2-4 A ← A (mem)

2-4 (mem) ← (mem)

A

60

µPD78363A, 78365A, 78366A, 78368A

Flag

Mnemonic

Operand

Byte

Operation

S

×

Z

×

AC P/V CY

A, #byte

2

3

4

2

3

A ← A byte

P

saddr, #byte

sfr, #byte

r, r1

(saddr) ← (saddr) byte

sfr ← sfr byte

r, ← r r1

OR

A, saddr

A, sfr

A ← A (saddr)

A ← A sfr

saddr, saddr

A, mem

mem, A

A, #byte

saddr, #byte

sfr, #byte

r, r1

(saddr) ← (saddr) (saddr)

2-4 A ← A (mem)

2-4 (mem) ← (mem) ⁄ A

2

3

4

2

3

A ← A byte

(saddr) ← (saddr) byte

sfr ← sfr byte

r ← r r1

XOR

A, saddr

A, sfr

A ← A (saddr)

A ← A sfr

saddr, saddr

A, mem

mem, A

A, #byte

saddr, #byte

sfr, #byte

r, r1

(saddr) ← (saddr) (saddr)

2-4 A ← A (mem)

2-4 (mem) ← (mem)

A

2

3

4

2

3

A – byte

×

V

×

(saddr) – byte

sfr – byte

r – r1

CMP

A, saddr

A, sfr

A – (saddr)

A – sfr

saddr, saddr

A, mem

mem, A

(saddr) – (saddr)

2-4 A – (mem)

2-4 (mem) – A

61

µPD78363A, 78365A, 78366A, 78368A

Flag

Mnemonic

Operand

Byte

Operation

S

×

Z

×

AC P/V CY

AX, #word

3

4

5

2

3

4

5

2

3

4

5

2

3

2

AX, CY ← AX + word

×

V

×

saddrp, #word

sfrp, #word

rp, rp1

(saddrp), CY ← (saddrp) + word

sfrp, CY ← sfrp + word

rp, CY ← rp + rp1

ADDW

AX, saddrp

AX, sfrp

AX, CY ← AX + (saddrp)

AX, CY ← AX + sfrp

saddrp, saddrp

AX, #word

saddrp, #word

sfrp, #word

rp, rp1

(saddrp), CY ← (saddrp) + (saddrp)

AX, CY ← AX – word

(saddrp), CY ← (saddrp) – word

sfrp, CY ← sfrp – word

rp, CY ← rp – rp1

SUBW

AX, saddrp

AX, sfrp

AX, CY ← AX – (saddrp)

AX, CY ← AX – sfrp

saddrp, saddrp

AX, #word

saddrp, #word

sfrp, #word

rp, rp1

(saddrp), CY ← (saddrp) – (saddrp)

AX – word

(saddrp) – word

sfrp – word

CMPW

rp – rp1

AX, saddrp

AX, sfrp

AX – (saddrp)

AX – sfrp

saddrp, saddrp

r1

(saddrp) – (saddrp)

MULU

DIVUW

MULUW

DIVUX

AX ← AX × r1

r1

AX (quotient), r1 (remainder) ← AX ÷ r1

AX (high-order 16 bits), rp1 (low-order 16 bits) ← AX × rp1

AXDE (quotient), rp1 (remainder) ← AXDE ÷ rp1

rp1

MULW

MACW

rp1

n

2

3

AX (high-order 16 bits), rp1 (low-order 16 bits) ← AX × rp1

AXDE ← (B) × (C) + AXDE

B ← B + 2, C ← C + 2, n ← n – 1

End if n = 0 or P/V = 1

×

V

×

AXDE ← (B) × (C) + AXDE

B ← B + 2, C ← C + 2, n ← n – 1

if overflow (P/V = 1) then

AXDE ← 7FFFFFFFH

n

3

4

MACSW

SACW

if underflow (P/V = 1) then

AXDE ← 80000000H

end if n = 0 or P/V = 1

AX ← AX + | (DE) – (HL) |

DE ← DE + 2 HL ← HL + 2 C ← C – 1

end if C = 0 or cy = 1

[DE + ], [HL + ]

62

µPD78363A, 78365A, 78366A, 78368A

Flag

Mnemonic

Operand

Byte

4

Operation

S

Z

AC P/V CY

(addr16 + 2) ← (addr16), n ← n – 1

addr16 ←addr16 – 2, End if n = 0

r1 ← r1 + 1

MOVTBLW

INC

!addr16, n

r1

1

2

1

2

1

3

1

3

2

×

V

(saddr) ← (saddr) + 1

saddr

r1

r1 ← r1 – 1

DEC

saddr

rp2

(saddr) ← (saddr) – 1

rp2 ← rp2 + 1

INCW

DECW

(saddrp) ← (saddrp) + 1

saddrp

rp2

rp2 ← rp2 – 1

(saddrp) ← (saddrp) – 1

saddrp

r1, n

ROR

ROL

(CY, r1⁷← r10, r1m–1 ← r1m) × n times

(CY, r1⁰← r17, r1m+1 ← r1m) × n times

(CY ← r1⁰, r17 ← CY, r1m–1 ← r1m) × n times

(CY ← r17, r10 ← CY, r1m+1 ← r1m) × n times

(CY ← r1⁰, r17 ← 0, r1m–1 ← r1m) × n times

(CY ← r17, r10 ← 0, r1m+1 ← r1m) × n times

P

×

RORC

ROLC

SHR

×

0

SHL

(CY ← rp10, rp115 ← 0, rp1m–1 ← rp1m)

× n times

SHRW

SHLW

rp1, n

2

×

0

P

×

(CY ← rp1¹⁵, rp10 ← 0, rp1m+1 ← rp1m)

× n times

A3–0 ← (rp1)3–0

(rp1)7–4 ← A3–0

,

ROR4

ROL4

[rp1]

2

(rp1)3–0 ← (rp1)7–4

A3–0 ← (rp1)7–4

(rp1)3–0 ← A3–0

,

(rp1)7–4 ← (rp1)3–0

ADJBA

ADJBS

Decimal Adjust Accumelator

2

1

×

0

P

×

When A7 = 0, X ← A, A ← 00H

When A7 = 1, X ← A, A ← FFH

CVTBW

Remarks 1. n of the shift rotate instruction indicates the number of times the shift rotate instruction is

executed.

2. The address of the table shift instruction ranges from FE00H to FEFFH.

63

µPD78363A, 78365A, 78366A, 78368A

Flag

Mnemonic

Operand

Byte

Operation

S

Z

AC P/V CY

CY, saddr.bit

CY, sfr.bit

3

2

3

2

3

2

3

2

CY ← (saddr.bit)

CY ← sfr.bit

×

CY, A.bit

CY ← A.bit

CY, X.bit

CY ← X.bit

CY, PSWH.bit

CY, PSWL.bit

saddr.bit, CY

sfr.bit, CY

CY ← PSW^H.bit

CY ← PSWL.bit

(saddr.bit) ← CY

sfr.bit ← CY

MOV1

A.bit, CY

A.bit ← CY

X.bit, CY

X.bit ← CY

PSWH.bit, CY

PSWL.bit, CY

CY, saddr.bit

CY, /saddr.bit

CY, sfr.bit

PSW^H.bit ← CY

PSWL.bit ← CY

CY ← CY (saddr.bit)

CY ← CY sfr.bit

×

CY, /sfr.bit

CY, A.bit

CY ← CY

A.bit

CY, /A.bit

AND1

CY, X.bit

CY ← CY X.bit

CY, /X.bit

CY, PSWH.bit

CY, /PSWH.bit

CY, PSWL.bit

CY, /PSWL.bit

CY, saddr.bit

CY, /saddr.bit

CY, sfr.bit

CY ← CY

PSW^H.bit

PSWL.bit

CY ← CY (saddr.bit)

CY ← CY sfr.bit

CY, /sfr.bit

CY, A.bit

CY ← CY sfr.bit

CY ← CY

A.bit

CY, /A.bit

OR1

CY, X.bit

CY ← CY X.bit

CY, /X.bit

CY, PSWH.bit

CY, /PSWH.bit

CY, PSWL.bit

CY, /PSWL.bit

CY ← CY

PSW^H.bit

PSWL.bit

64

µPD78363A, 78365A, 78366A, 78368A

Flag

Mnemonic

Operand

Byte

Operation

S

Z

AC P/V CY

CY, saddr.bit

CY, sfr.bit

CY, A.bit

CY, X.bit

CY, PSWH.bit

CY, PSWL.bit

saddr.bit

sfr.bit

3

2

3

2

3

2

3

2

1

CY ← CY (saddr.bit)

CY ← CY sfr.bit

×

CY ← CY

A.bit

XOR1

CY ← CY X.bit

CY ← CY

PSWH.bit

PSW^L.bit

(saddr.bit) ← 1

sfr.bit ← 1

A.bit

A.bit ← 1

SET1

CLR1

NOT1

X.bit

X.bit ← 1

PSWH.bit

PSWL.bit

saddr.bit

sfr.bit

PSW^H.bit ← 1

PSW^L.bit ← 1

(saddr.bit) ← 0

sfr.bit ← 0

×

A.bit

A.bit ← 0

X.bit

X.bit ← 0

PSWH.bit

PSWL.bit

saddr.bit

sfr.bit

PSW^H.bit ← 0

PSWL.bit ← 0

(saddr.bit) ← (saddr.bit)

sfr.bit ← sfr.bit

A.bit ← A.bit

X.bit ← X.bit

PSW^H.bit ← PSWH.bit

PSWL.bit ← PSWL.bit

CY ← 1

×

A.bit

X.bit

PSWH.bit

PSWL.bit

CY

×

1

0

×

SET1

CLR1

NOT1

CY

CY ← 0

CY

CY ← CY

65

µPD78363A, 78365A, 78366A, 78368A

Flag

Mnemonic

Operand

Byte

Operation

S

Z

AC P/V CY

(SP – 1) ← (PC + 3)H, (SP – 2) ← (PC + 3)L

PC ← addr16, SP ← SP – 2

,

CALL

!addr16

3

2

(SP – 1) ← (PC + 2)

H

,

(SP – 2) ← (PC + 2)

L

,

CALLF

!addr11

[addr5]

PC15 – 11 ← 00001, PC10 – 0 ← addr11, SP ← SP – 2

(SP – 1) ← (PC + 1)H, (SP – 2) ← (PC + 1)L

PCH ← (TPF, 00000000, addr5 + 1),

,

CALLT

CALL

1

PCL ← (TPF, 00000000, addr5 ), SP ← SP – 2

(SP – 1) ← (PC + 2)^H, (SP – 2) ← (PC + 2)L

PCH ← rp1H, PCL ← rp1L, SP ← SP – 2

,

rp1

2

(SP – 1) ← (PC + 2)H, (SP – 2) ← (PC + 2)L

PCH ← (rp1 + 1), PCL ← (rp1), SP ← SP – 2

,

[rp1]

(SP – 1) ← PSWH, (SP – 2) ← PSWL

(SP – 3) ← (PC + 1)H, (SP – 4) ← (PC + 1)L

PCL ← (003EH), PCH ← (003FH),

SP ← SP – 4, IE ← 0

,

BRK

1

RET

1

PCL ← (SP), PCH ← (SP + 1), SP ← SP + 2

PCL ← (SP), PCH ← (SP +1)

PSW^L← (SP + 2), PSWH ← (SP + 3)

SP ← SP + 4

RETB

R

PCL ← (SP), PCH ← (SP + 1)

PSW^L← (SP + 2), PSWH ← (SP + 3)

SP ← SP + 4

RETI

1

3

(SP – 1) ← sfrH

(SP – 2) ← sfrL

SP ← SP – 2

sfrp

PUSH

{(SP – 1) ← postH, (SP – 2) ← postL, SP ← SP

– 2} × n times

post

PSW

post

2

1

2

(SP – 1) ← PSWH, (SP – 2) ← PSWL, SP ← SP – 2

{(UP – 1) ← postH, (UP – 2) ← postL, UP ← UP

– 2} × n times

PUSHU

sfrL ← (SP)

sfrp

3

sfrH ← (SP + 1)

SP ← SP + 2

POP

{postL ← (SP), postH ← (SP + 1), SP ← SP + 2}

× n times

post

PSW

post

2

1

2

PSWL ← (SP), PSWH ← (SP + 1), SP ← SP + 2

R

{postL ← (UP),postH ← (UP + 1), UP ← UP + 2}

× n times

POPU

SP, #word

SP, AX

AX, SP

SP

4

2

SP ← word

SP ← AX

MOVW

AX ← SP

SP ← SP + 1

SP ← SP – 1

INCW

SP

DECW

Remark n of the stack manipulation instruction is the number of registers written as post.

66

µPD78363A, 78365A, 78366A, 78368A

Flag

Mnemonic

Operand

Byte

Operation

S

×

Z

×

AC P/V CY

CHKL

sfr

3

2

(pin level) (signal level before output buffer)

A ← (pin level) (signal level before output buffer)

PC ← addr16

P

CHKLA

!addr16

rp1

PC^H← rp1H, PCL← rp1L

BR

[rp1]

PCH ← (rp1 + 1), PCL ← (rp1)

PC ← PC + 2 + jdisp8

$addr16

BC

BL

$addr16

2

PC ← PC + 2 + jdisp8 if CY = 1

PC ← PC + 2 + jdisp8 if CY = 0

PC ← PC + 2 + jdisp8 if Z = 1

PC ← PC + 2 + jdisp8 if Z = 0

PC ← PC + 2 + jdisp8 if P/V = 1

PC ← PC + 2 + jdisp8 if P/V = 0

BNC

BNL

BZ

BE

BNZ

BNE

BV

BPE

BNV

BPO

BN

$addr16

2

3

4

3

4

3

PC ← PC + 2 + jdisp8 if S = 1

BP

$addr16

PC ← PC + 2 + jdisp8 if S = 0

BGT

BGE

BLT

BLE

BH

$addr16

PC ← PC + 3 + jdisp8 if (P/V S) ⁄ Z = 0

PC ← PC + 3 + jdisp8 if P/V S= 0

PC ← PC + 3 + jdisp8 if P/V S = 1

PC ← PC + 3 + jdisp8 if (P/V S) ⁄ Z = 1

PC ← PC + 3 + jdisp8 if Z CY = 0

PC ← PC + 3 + jdisp8 if Z CY = 1

PC ← PC + 3 + jdisp8 if (saddr.bit) = 1

PC ← PC + 4 + jdisp8 if sfr.bit = 1

PC ← PC + 3 + jdisp8 if A.bit = 1

PC ← PC + 3 + jdisp8 if X.bit = 1

PC ← PC + 3 + jdisp8 if PSW^H.bit = 1

PC ← PC + 3 + jdisp8 if PSWL.bit = 1

PC ← PC + 4 + jdisp8 if (saddr.bit) = 0

PC ← PC + 4 + jdisp8 if sfr.bit = 0

PC ← PC + 3 + jdisp8 if A.bit = 0

PC ← PC + 3 + jdisp8 if X.bit = 0

PC ← PC + 3 + jdisp8 if PSWH.bit = 0

PC ← PC + 3 + jdisp8 if PSWL.bit = 0

$addr16

BNH

$addr16

saddr.bit, $addr16

sfr.bit, $addr16

A.bit, $addr16

X.bit, $addr16

PSWH.bit, $addr16

PSWL.bit, $addr16

saddr.bit, $addr16

sfr.bit, $addr16

A.bit, $addr16

X.bit, $addr16

PSWH.bit, $addr16

PSWL.bit, $addr16

BT

BF

67

µPD78363A, 78365A, 78366A, 78368A

Flag

Mnemonic

Operand

Byte

Operation

S

Z

AC P/V CY

PC ← PC + 4 + jdisp8 if (saddr.bit) = 1

saddr.bit, $addr16

sfr.bit, $addr16

A.bit, $addr16

X.bit, $addr16

PSWH.bit, $addr16

PSWL.bit, $addr16

saddr.bit, $addr16

sfr.bit, $addr16

A.bit, $addr16

X.bit, $addr16

PSWH.bit, $addr16

PSWL.bit, $addr16

r2, $addr16

4

3

4

3

2

3

2

3

4

then reset (saddr.bit)

PC ← PC + 4 + jdisp8 if sfr.bit = 1

then reset sfr.bit

PC ← PC + 3 + jdisp8 if A.bit = 1

then reset A.bit

BTCLR

PC ← PC + 3 + jdisp8 if X.bit = 1

then reset X.bit

PC ← PC + 3 + jdisp8 if PSW^H.bit = 1

then reset PSWH.bit

PC ← PC + 3 + jdisp8 if PSW^L.bit = 1

×

then reset PSWL.bit

PC ← PC + 4 + jdisp8 if (saddr.bit) = 0

then set (saddr.bit)

PC ← PC + 4 + jdisp8 if sfr.bit = 0

then set sfr.bit

PC ← PC + 3 + jdisp8 if A.bit = 0

then set A.bit

BFSET

PC ← PC + 3 + jdisp8 if X.bit = 0

then set X.bit

PC ← PC + 3 + jdisp8 if PSW^H.bit = 0

then set PSW^H.bit

PC ← PC + 3 + jdisp8 if PSWL.bit = 0

×

then set PSWL.bit

r2 ← r2 – 1,

then PC ← PC + 2 + jdisp8 if 2 ≠ 0

DBNZ

(saddr) ← (saddr) – 1,

saddr, $addr16

RBn

then PC ← PC + 3 + jdisp8 if (saddr) ≠ 0

PCH ↔ R5, PCL ↔ R4, R7 ← PSWH

,

BRKCS

RETCS

R6 ← PSWL, ← RBS2 – 0 ← n, RSS ← 0, IE ← 0

PCH ← R5, PCL ← R4, R5, R4 ← addr16

PSWH ← R7, PSWL ← R6

R

!addr16

PCH ← R5, PCL ← R4, R5, R4 ← addr16

PSWH ← R7, PSWL ← R6

!addr16

RETCSB

68

µPD78363A, 78365A, 78366A, 78368A

Flag

Mnemonic

Operand

Byte

Operation

S

Z

AC P/V CY

(DE+) ← A, C ← C – 1

[DE+], A

2

End if C = 0

MOVM

(DE–) ← A, C ← C – 1

[DE–], A

End if C = 0

(DE+) ← (HL+), C ← C – 1

End if C = 0

[DE+], [HL+]

[DE–], [HL–]

[DE+], A

MOVBK

XCHM

(DE–) ← (HL–), C ← C – 1

End if C = 0

(DE+) ↔ A, C ← C – 1

End if C = 0

(DE–) ↔ A, C ← C – 1

End if C = 0

[DE–], A

(DE+) ↔ (HL+), C ← C – 1

[DE+], [HL+]

[DE–], [HL–]

[DE+], A

End if C = 0

XCHBK

(DE–) ↔ (HL–), C ← C – 1

End if C = 0

(DE+) – A, C ← C – 1

End if C = 0 or Z = 0

×

V

×

CMPME

CMPBKE

CMPMNE

CMPBKNE

CMPMC

CMPBKC

(DE–) – A, C ← C – 1

[DE–], A

End if C = 0 or Z = 0

(DE+) – (HL+), C ← C – 1

[DE+], [HL+]

[DE–], [HL–]

[DE+], A

End if C = 0 or Z = 0

(DE–) – (HL–), C ← C – 1

End if C = 0 or Z = 0

(DE+) – A, C ← C – 1

End if C = 0 or Z = 1

(DE–) – A, C ← C – 1

[DE–], A

End if C = 0 or Z = 1

(DE+) – (HL+), C ← C – 1

End if C = 0 or Z = 1

[DE+], [HL+]

[DE–], [HL–]

[DE+], A

(DE–) – (HL–), C ← C – 1

End if C = 0 or Z = 1

(DE+) – A, C ← C – 1

End if C = 0 or CY = 0

(DE–) – A, C ← C – 1

End if C = 0 or CY = 0

[DE–], A

(DE+) – (HL+), C ← C – 1

[DE+], [HL+]

[DE–], [HL–]

End if C = 0 or CY = 0

(DE–) – (HL–), C ← C – 1

End if C = 0 or CY = 0

69

µPD78363A, 78365A, 78366A, 78368A

Flag

Mnemonic

Operand

Byte

Operation

S

Z

AC P/V CY

(DE+) – A, C ← C – 1

[DE+], A

2

×

V

×

End if C = 0 or CY = 1

CMPMNC

(DE–) – A, C ← C – 1

[DE–], A

×

End if C = 0 or CY = 1

(DE+) – (HL+), C ← C – 1

End if C = 0 or CY = 1

[DE+], [HL+]

[DE–], [HL–]

CMPBKNC

(DE–) – (HL–), C ← C – 1

End if C = 0 or CY = 1

Note

STBC, #byte

WDM, #byte

4

1

2

1

STBC ← byte

MOV

SWRS

SEL

Note

WDM ← byte

RSS ← RSS

RBn

RBS2 – 0 ← n, RSS ← 0

RBS2 – 0 ← n, RSS ← 1

No Operation

RBn, ALT

NOP

EI

IE ← 1 (Enable Interruptt)

IE ← 0 (Disable Interrupt)

DI

Note If the op code of the STBC register and WDM register manipulation instructions is wrong, an op code

trap interrupt occurs.

Operation on trap:

(SP – 1) ← PSW^H, (SP – 2) ← PSWL,

(SP – 3) ← (PC – 4)H, (SP – 4) ← (PC – 4)L,

PC^L← (003CH), PCH ← (003DH),

SP ← SP – 4, IE ← 0

70

µPD78363A, 78365A, 78366A, 78368A

9. EXAMPLE OF SYSTEM CONFIGURATION

Controlling outdoor apparatus of inverter air conditioner

µ PD78366A

Real-time pulse unit

CM03

Dead time setting register

16-bit timer

CM00

U/D

U

TO00

TO01

Inverter

V

TO02

TO03

Pulse generation

circuit

CM01

CM02

W

TO04

TO05

(Analog signal)

AC power

supply monitor

ANI0

P40

P41

P42

P43

ROM 32K bytes

RAM 2K bytes

ANI1

ANI2

ANI3

ANI4

External temperature

Thermal exchange

temperature

4-way valve

2-way valve

10-bit A/D

converter

General-

purpose port

Outlet temperature

Outdoor fan

motor

Inlet temperature

P00

P01

P02

P03

Stepping

motor

(electronic

expansion

valve)

NMI

DC monitor

Programmable

interrupt

controller

Real-time

output port

INTP1

Compressor motor

temperature monitor

RX

D

Indoor apparatus

controller

Serial

interface

TX

D

71

µPD78363A, 78365A, 78366A, 78368A

10. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25 ˚C)

Parameter

Symbol

VDD

Test conditions

Rating

Unit

V

Power supply voltage

–0.5 to +7.0

AVDD

AVSS

V^I

–0.5 to VDD + 0.5

–0.5 to +0.5

V

Input voltage

Pins other than

–0.5 to VDD + 0.5

V

P70/ANI0-P77/ANI7

Output voltage

VO

IOL

–0.5 to VDD + 0.5

V

Low-level output current

Note

20

mA

Output pins other than

those in the note

4.0

Total of all output pins

All output pins

200

–3.0

mA

V

High-level output current

IOH

Total of all output pins

P70/ANI0-P77/ANI7 pins

–25

Analog input voltage

VIAN

AVREF

TA

AVSS – 0.5 to AVDD + 0.5

–40 to +85

A/D converter reference input voltage

Operating ambient temperature

Storage temperature

V

˚C

Tstg

–60 to +150

Note P00/RTP0-P03/RTP3, P04/PWM0, P05/TCUD/PWM1, P06/TIUD/TO40, P07/TCLRUD, P10-P17, and

P80/TO00-P85/TO05 pins.

Caution Product quality may suffer if the absolute rating is exceeded for any parameter, even

momentarily. In other words, an absolute maxumum rating is a value at which the

possibility of psysical damage to the product cannnot be ruled out. Care must therefore

be taken to ensure that the these ratings are not exceeded during use of the product.

Recommended Operating Conditions

Oscillation frequency

TA

VDD

3 MHz ≤ fXX ≤ 8 MHz

–40 to +85 ˚C

+5.0 V ± 10 %

Capacitance (TA = 25 ˚C, VSS = VDD = 0 V)

Parameter

Input capacitance

Output capacitance

I/O capacitance

Symbol

CI

Test conditions

MIN.

TYP.

MAX.

20

Unit

pF

f = 1 MHz

0 V except measured pins

CO

20

pF

CIO

20

pF

72

µPD78363A, 78365A, 78366A, 78368A

Oscillator Characteristics (TA = –40 to +85 ˚C, VDD = +5 V ± 10 %, VSS = 0 V)

Resonator

Recommended circuit

Parameter

MIN.

3

MAX.

8

Unit

Ceramic resonator or

crystal resonator

Oscillation frequency (fXX)

MHz

V

SS

X1

X2

C1

C2

External clock

X1 input frequency (fX)

X1 rise/fall time (tXR, tXF)

3

0

8

MHz

ns

X1

X2

30

Leave unconnected

HCMOS

inverter

X1 input high-/low-level

width (tWXH, tWXL)

40

170

ns

Caution When using system clock oscillation circuits, to reduce the effect of the wiring

capacitouce, etc, wire the area indicated by dotted-line as follows:

•

Make the wiring as short as possible.

Do not allow the wiring to intersect other signal lines. Keep it away from other lines in which

varying high currents flow.

•

Make sure that the ground point of the oscillation circuit capacitor is always at the same

electric potential as V^SS. Do not allow the wiring to be grounded to a ground pattern in which

very high currents are flowing.

Do not extract signals from the oscillation circuit.

73

µPD78363A, 78365A, 78366A, 78368A

DC Characteristics (TA = –40 to +85 ˚C, VDD = +5 V ± 10 %, VSS = 0 V)

Parameter

Symbol

VIL1

Test conditions

MIN.

0

TYP.

MAX.

0.8

Unit

V

Low-level input voltage

Note 1

Note 2

Note 1

Note 2

Note 3

Note 4

Note 5

VIL2

0

0.2VDD

V

High-level input voltage

Low-level output voltage

VIH1

VIH2

VOL1

VOL2

VOL3

VOH

2.2

V

0.8VDD

V

IOL = 2.0 mA

IOL = 15 mA

IOL = 10 mA

0.45

1.5

V

1.5

V

High-level output voltage

Input leakage current

Output leakage current

VDD supply current

IOH = –400 µA

V

DD – 1.0

V

ILI

0 V ≤ VI ≤ VDD, AVDD = VDD

0 V ≤ VO ≤ VDD, AVDD = VDD

Operating mode

±10

120

70

µA

mA

V

ILO

IDD1

70

45

IDD2

HALT mode

Data retention voltage

Data retention current

VDDDR

IDDDR

STOP mode

2.5

15

STOP mode

VDDDR = 2.5 V

2

10

50

µA

kΩ

VDDDR = 5.0 V ± 10 %

10

60

Pull-up resistance

R^L

VI = 0 V

150

Notes 1. Pins other than those specified in Note 2.

2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2, P24/INTP3/TI, P25/INTP4, P32/

SO/SB0, P33/SI/SB1 and P34/SCK pins.

3. Pins other than those specified in Notes 4 and 5.

4. P80/TO00-P85/TO05 pins (When I^OL= 15 mA is in operation, up to three pins can be ON

simultaneously.)

5. P00/RTP0-P03/RTP3, P04/PWM0, P05/TCUD/PWM1, P06/TIUD/TO40 and P07/TCLRUD pins

(When I^OL= 10 mA is in operation, up to four pins can be ON simultaneously.) as well as P10-P17

pins (When IOL = 10 mA is in operation, up to four pins can be ON simultaneously.).

Caution When the P80-P85, P00-P07, and P10-P17 pins are not used under the conditions specified

in Notes 4 and 5, they have the same characteristics as in Note 3.

74

µPD78363A, 78365A, 78366A, 78368A

AC Characteristics (T

A

= –40 to +85 ˚C, VDD = +5 V

±

10 %, VSS = 0 V, C

L

= 100 pF, fXX = 8 MHz)

Read/Write Operation (when general-purpose memory is connected)

Parameter

Symbol

tCYK

Test conditions

MIN.

62.5

7

MAX.

166.7

Unit

ns

System clock cycle time

Address setup time (vs. ASTB ↓)

Address hold time (vs. ASTB ↓)

RD ↓ → address float time

Address → data input time

RD ↓ → data input time

ASTB ↓ → RD ↓ delay time

Data hold time (vs. RD ↑)

RD ↑ → address active time

RD low-level width

tSAST

tHSTA

tFRA

11

24

100

49

tDAID

tDRID

tDSTR

tHRID

tDRA

15

0

17

63

14

tWRL

ASTB high-level width

tWSTH

tDWOD

tDSTW

tDWST

tSODW

tHWOD

tWWL

WR ↓ → data output time

ASTB ↓ → WR ↓ delay time

WR ↑ → ASTB ↑ delay time

Data setup time (vs. WR ↑)

Data hold time (vs. WR ↑)

WR low-level width

21

15

78

57

8

63

tCYK-dependent Bus Timing Definition

Parameter

tSAST

Arithmetic expression

MIN./MAX.

MIN.

Unit

(0.5 + a) T – 24

0.5T – 20

ns

tHSTA

tWSTH

tDSTR

tWRL

MIN.

(0.5 + a) T – 17

0.5T – 16

MIN.

(1.5 + n) T – 30

(2.5 + a + n) T – 56

(1.5 + n) T – 44

0.5T – 14

MIN.

tDAID

MAX.

MIN.

tDRID

tDRA

tDSTW

tDWST

tWWL

0.5T – 16

MIN.

1.5T – 15

MIN.

(1.5 + n) T – 30

0.5T – 10

MIN.

tDWOD

tSODW

MAX.

MIN.

(1 + n) T – 5

Remarks 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency.)

2. a becomes 1 when the address wait is inserted. Otherwise, it becomes 0.

3. n refers to the number of wait cycles that is inserted by specifying the PWC register.

4. Only the bus timings indicated in this table depend on t^CYK.

75

µPD78363A, 78365A, 78366A, 78368A

Serial Operation (TA = –40 to +85 ˚C, VDD = +5 V ± 10 %, VSS = 0 V)

Parameter

Symbol

Test conditions

Internal 8 dividing

MIN.

500

210

80

MAX.

Unit

ns

Serial clock cycle time

tCYSK

SCK output

SCK input

SCK output

SCK input

SCK output

SCK input

External clock

Serial clock low-level

width

tWSKL

tWSKH

Internal 8 dividing

External clock

Serial clock high-level

width

Internal 8 dividing

External clock

SI setup time (vs. SCK ↑)

SI hold time (vs. SCK ↑)

SCK ↓ → SO delay time

tSRXSK

tHSKRX

tDSKTX

80

R = 1 kΩ, C = 100 pF

210

Up/Down Counter Operation (TA = –40 to +85 ˚C, VDD = +5 V ± 10 %, VSS = 0 V)

Parameter

Symbol

Test conditions

MIN.

2T

4T

2T

4T

2T

T

MAX.

Unit

ns

TIUD high-/low-level

width

t

WTIUH, tWTIUL Other than mode 4

Mode 4

ns

TCUD high-/low-level

width

t

WTCUH, tWTCUL Other than mode 4

ns

Mode 4

ns

TCLRUD high-/low-level width

TCUD setup time (vs. TIUD ↑)

TCUD hold time (vs. TIUD ↑)

TIUD setup time (vs. TCUD)

TIUD hold time (vs. TCUD)

TIUD & TCUD cycle time

WCLUH, tWCLUL

ns

tSTCU

tHTCU

tS4TIU

tH4TIU

tCYC

Mode 3

ns

Mode 3

T

ns

Mode 4

2T

ns

Mode 4

ns

Other than mode 4

Mode 4

4

2

MHz

tCYC4

Remark T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency.)

76

µPD78363A, 78365A, 78366A, 78368A

Other Operations (TA = –40 to +85 ˚C, VDD = +5 V ± 10 %, VSS = 0 V)

Parameter

Symbol

Test conditions

MIN.

2

MAX.

Unit

µs

ns

µs

ns

µs

ns

µs

ns

µs

ns

µs

NMI high-/low-level width tWNIH, tWNIL

RESET high-/low-level width

t

WRSH, tWRSL

1.5

250

1.0

2.0

4.0

250

1.0

2.0

4.0

250

1.0

250

1.0

2.0

4.0

16.0

32.0

64.0

250

1.0

2.0

4.0

INTP0 high-/low-level

width

tWI0H, tWI0L Ts = T

Ts = 4T

Ts = 8T

Ts = 16T

INTP1 high-/low-level

width

tWI1H, tWI1L Ts = T

Ts = 4T

Ts = 8T

Ts = 16T

INTP2 high-/low-level

width

tWI2H, tWI2L Ts = T

Ts = 4T

INTP3(TI) high-/low-

level width

tWI3H, tWI3L Ts = T

Ts = 4T

Ts = 8T

Ts = 16T

Ts = 64T

Ts = 128T

Ts = 256T

tWI4H, tWI4L Ts = T

Ts = 4T

INTP4 high-/low-level

width

Ts = 8T

Ts = 16T

Remarks 1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency.)

2. Ts refers to the input sampling frequency. INTP0-INTP4 can be selected to programmable.

77

µPD78363A, 78365A, 78366A, 78368A

A/D Converter Characteristics (TA = –40 to +85 ˚C, VDD = +5 V ± 10 %, VSS = AVSS = 0 V,

V^DD– 0.5 V ≤ AVDD ≤ VDD)

Parameter

Resolution

Symbol

Test conditions

MIN.

10

TYP.

MAX.

Unit

bit

Note 1

Total error

4.5 V ≤ AVREF ≤ AVDD

±0.4

±0.7

±1/2

%FSR

LSB

tCYK

3.4 V ≤ AVREF ≤ AVDD

Quantization error

Conversion time

tCONV

tSAMP

62.5 ns ≤ tCYK < 80 ns

80 ns ≤ tCYK ≤ 166.6 ns

62.5 ns ≤ tCYK < 80 ns

80 ns ≤ tCYK ≤ 166.6 ns

4.5 V ≤ AVREF ≤ AVDD

3.4 V ≤ AVREF ≤ AVDD

4.5 V ≤ AVREF ≤ AVDD

3.4 V ≤ AVREF ≤ AVDD

4.5 V ≤ AVREF ≤ AVDD

3.4 V ≤ AVREF ≤ AVDD

208

169

24

tCYK

Sampling time

tCYK

20

tCYK

Note 1

Zero-scale error

±1.5

±2.5

±4.5

LSB

V

Note 1

Full-scale error

±2.5

±4.5

Note 1

Nonlinearity error

±2.5

±4.5

Note 2

Analog input voltage

VIAN

RAN

–0.3

3.4

AVREF + 0.3

Analog input impedance

When not sampling

When sampling

10

MΩ

Note 3

Reference voltage

AVREF1 current

AVREF

AIREF

AIDD

AVDD

3.0

6.0

10

V

1.0

2.0

2

mA

µA

AVDD supply current

Operating mode

A/D converter data

retention current

AIDDDR

STOP mode

AVDDDR = 2.5 V

AVDDDR = 5 V ± 10 %

10

50

Notes 1. The quantization error is excluded.

2. When –0.3 V ≤ V^IAN≤ 0 V, the conversion result becomes 000H.

When 0 V < VIAN < AVREF, the conversion is performed with the 10-bit resolution.

When AVREF ≤ VIAN ≤ +0.3 V, the conversion result becomes 3FFH.

3. The analog input impedance at the time of sampling is the same as the equivalent circuit shown

below. (The values in the diagram are TYP. values; they are not guaranteed values)

1 kΩ

Analog input pin

25 pF

4 pF

(Input

capacitance

included)

78

µPD78363A, 78365A, 78366A, 78368A

Cautions1. When using the P70/ANI0-P77/ANI7 pins for both digital and analog inputs, the previ-

ously described characteristics are not guaranteed. Therefore, ensure that all of the

eight P70/ANI0-P77/ANI7 pins are used either for analog input or digital input.

2. When using the P70/ANI0-P77/ANI7 pins as digital input, make sure to set that AV^DD= VDD,

and AV^SS= VSS.

AC Timing Test Point

V

DD

0.8 VDD or 2.2 V

0.2 V^DDor 0.8 V

0.8 V^DDor 2.2 V

0.2 V^DDor 0.8 V

Test point

0 V

79

µPD78363A, 78365A, 78366A, 78368A

Read Operation

t

CYK

(CLK)

A8-A15

(Output)

High-order address

t

DAID

t

SAST

AD0-AD7

(Input/output)

Hi-Z

Low-order address (Output)

Data (Input)

Low-order address (Output)

t

WSTH

t

HRID

ASTB

(Output)

t

HSTA

t

FRA

RD

(Output)

t

DSTR

t

DRID

t

DRA

t

WRL

Write Operation

(CLK)

A8-A15

(Output)

High-order address

Undefined

High-order address

t

SAST

AD0-AD7

(Output)

Low-order address (Output)

Data (Output)

Low-order address (Output)

t

WSTH

t

HWOD

ASTB

(Output)

t

HSTA

t

DWST

WR

(Output)

t

DSTW

t

DWOD

t

SODW

t

WWL

80

µPD78363A, 78365A, 78366A, 78368A

Serial Operation

t

CYSK

t

WSKH

t

WSKL

SCK

SO

SI

t

DSKTX

t

SRXSK

t

HSKRX

Up/Down Counter (Timer 4) Input Timing

t

WTIUH

TIUD

t

WTIUL

t

STCU

t

HTCU

t

WTCUL

TCUD

t

WTCUH

t

WCLUH

TCLRUD

t

WCLUL

TIUD

t

S4TIU

t

H4TIU

t

S4TIU

t

H4TIU

TCUD

81

µPD78363A, 78365A, 78366A, 78368A

Interrupt Input Timing

t

WNIH

t

WNIL

0.8 VDD

0.2 VDD

NMI

t

WInH

t

WInL

0.8 V^DD

INTPn

0.2 VDD

Remark n = 0 to 4

Reset Input Timing

t

WRSH

t

WRSL

0.8 VDD

0.2 VDD

RESET

82

µPD78363A, 78365A, 78366A, 78368A

11. PACKAGE DRAWING

80 PIN PLAS TIC QFP (14×20)

A

B

41

40

64

65

detail of lead end

25

24

80

1

G

H

M

N

I

J

K

L

P80GF-80-3B9-2

NOTE

ITEM

A

B

MILLIMETERS

INCHES

Each lead centerline is located within 0.15

mm (0.006 inch) of its true position (T.P.) at

maximum material condition.

±

23.6 0.4

0.929 0.016

+0.009

–0.008

±

20.0 0.2

0.795

+0.009

–0.008

±

C

14.0 0.2

0.551

±

0.693 0.016

D

F

17.6 0.4

1.0

0.8

0.039

G

H

I

0.031

+0.004

–0.005

±

0.35 0.10

0.014

0.15

0.006

J

0.8 (T.P.)

0.031 (T.P.)

+0.008

±

K

L

1.8 0.2

0.071

–0.009

+0.009

±

0.031

0.8 0.2

–0.008

+0.10

–0.05

+0.004

–0.003

0.15

M

N

P

0.006

0.15

2.7

0.006

0.106

±

Q

S

0.1 0.1

±

0.004 0.004

3.0 MAX.

0.119 MAX.

83

µPD78363A, 78365A, 78366A, 78368A

12. RECOMMENDED SOLDERING CONDITIONS

These products should be soldered and mounted under the conditions recommended below.

For details of recommended soldering conditions, refer to the information document Semiconductor Device

Mounting Technology Manual (C10535E).

For soldering methods and conditions other than those recommended, please contact your NEC sales

representative.

Table 12-1. Surface Mount Type Soldering Conditions

µPD78363AGF-×××-3B9: 80-Pin Plastic QFP (14 × 20 mm)

µPD78365AGF-3B9

: 80-Pin Plastic QFP (14 × 20 mm)

µPD78366AGF-×××-3B9: 80-Pin Plastic QFP (14 × 20 mm)

µPD78368AGF-×××-3B9: 80-Pin Plastic QFP (14 × 20 mm)

Recommended

Soldering method

Infrared reflow

Soldering conditions

condition symbol

IR35-00-3

VP15-00-3

WS60-00-1

Package peak temperature: 235 ˚C, Duration: 30 sec. max. (210 ˚C or

above) Number of times: 3 max.

VPS

Package peak temperature: 215 ˚C, Duration: 40 sec. max. (200 ˚C or

above) Number of times: 3 max.

Wave soldering

Solder bath temperature: 260 ˚C or less, Time: 10 sec. max.,

Number of times: 1, Pre-heating temperature: 120 ˚C max. (Package

surface temperature)

–

Partial heating

Pin temperature: 300 ˚C or less

Duration: 3 sec. max. (per side of device)

Caution Use of more than one soldering method should be avoided (except in the case of partial

heating).

84

µPD78363A, 78365A, 78366A, 78368A

APPENDIX A. DIFFERENCES BETWEEN µPD78366A AND µPD78328

Product name

µPD78366A

µPD78328

Item

Minimum instruction

execution time

internal clock : 8 MHz,

external clock : 16 MHz

internal clock : 16 MHz

external clock : 8 MHz

125 ns

250 ns

32K bytes

2K bytes

16K bytes

512 bytes

ROM

RAM

Internal

memory

64K bytes (can be externally expanded)

Memory space

General-purpose

registers

8 bits × 16 × 8 banks

Number of basic

instructions

115

111

Instruction set

• 16-bit transfer/operation

• Multiplication/division (16 bits × 16 bits, 32 bits ÷ 16 bits)

• Bit manipulation

• String

• Sum-of-products operation

(16 bits × 16 bits + 32 bits)

• Relative operation

—

11 (of which 8 are multiplexed with analog

input)

Input

14 (of which 8 are multiplexed with analog

input)

I/O lines

I/O

41

49

• 16-bit timer × 3

• 16-bit timer × 5

Real-time pulse unit

• 16-bit compare register × 14

• 16-bit capture/compare register × 1

• Two output modes selectable

Mode 0, set-reset output : 6 channels

• 16-bit compare register × 7

• 16-bit capture register × 3

• 16-bit capture/compare register × 2

• Two output modes selectable

Mode 0, set-reset output : 6 channels

toggle output

: 1 channel

: 8 channels

Mode 1, buffer output

: 6 channels

• 16-bit resolution PWM output: 1 channel

4 (buffer output in 4-bit units)

4/8 (buffer output in 4-/8-bit units)

Real-time output port

PWM unit

8-bit resolution PWM output: 1 channel

8-/9-/10-/12-bit resolution variable PWM

output: 2 channels

10-bit resolution, 8 channels

A/D converter

Serial interface

Dedicated baud rate generator

UART (with pin selection function)

: 1 channel

Dedicated baud rate generator

UART

: 1 channel

Clocked serial interface/SBI : 1 channel

• External: 6, internal: 14 (2 multiplexed

with external)

• External: 4, internal: 17

Interrupt function

• 3 programmable priority levels

• 4 programmable priority levels

• Three processing selectable

(vectored interrupt/macro service/context switching)

Test source

None

Internal: 1

PLL control circuit

Provided (external 8 MHz → internal: 16 MHz) None

• 64-pin plastic shrink DIP

• 64-pin plastic QFP (14 × 20 mm)

• 80-pin plastic QFP (14 × 20 mm)

Package

• Watchdog timer

Others

• Standby functions (HALT mode, STOP mode)

85

µPD78363A, 78365A, 78366A, 78368A

APPENDIX B. TOOLS

B.1 DEVELOPMENT TOOLS

The following development tools are available to support the system development using µPD78366A :

Language Processor

78K/III series

A relocatable assembler, that can be used commonly for the 78K/III series products. Since this

assembler is provided with macro functions, it enhances the developmnt efficency. A structured

assembler, that can explicitly describe the program control structure, is also supplied, so that

the program productivity and maintainability can be improved.

relocatable assembler

(RA78K3)

Host machine

Order code (product name)

OS

Supply media

3.5" 2HD

5" 2HD

µS5A13RA78K3

µS5A10RA78K3

PC-9800 series

MS-DOS^TM

PC DOS^TM

IBM PC/AT^TMand its

compatible model

HP9000 series 700^TM

SPARC station^TM

NEWS^TM

3.5" 2HC

5" 2HC

µS7B13RA78K3

µS7B10RA78K3

µS3P16RA78K3

µS3K15RA78K3

µS3R15RA78K3

HP-UX^TM

DAT

SunOS^TM

Cartridge tape

(QIC-24)

NEWS-OS^TM

78K/III series

C compiler

(CC78K3)

This is a C compiler that can be commonly used for 78K/III series.

This program converts the program written in C language to object codes microcomputer can

execute. When using this compiler, the 78K/III series relocatable assembler (RA78K3) is

necessary.

Host machine

Order code (product name)

OS

MS-DOS

PC DOS

Supply media

3.5" 2HD

5" 2HD

µS5A13CC78K3

µS5A10CC78K3

PC-9800 series

IBM PC/AT and its

compatible model

HP9000 series 700

SPARC station

NEWS

3.5" 2HC

5" 2HC

µS7B13CC78K3

µS7B10CC78K3

µS3P16CC78K3

µS3K15CC78K3

µS3R15CC78K3

HP-UX

DAT

SunOS

Cartridge tape

(QIC-24)

NEWS-OS

Remark The operations of the relocatable assembler and C compiler are guaranteed only on the specified

host machine and OS described above.

86

µPD78363A, 78365A, 78366A, 78368A

PROM Writing Tools

This is a PROM programmer that can program PROM-contained single-chip microcontrollers

in standalone mode or under control of a host machine when the accessory board and an

optional programmer adapter are connected. It can also program representative PROMs from

256K-bit to 4M-bit models.

PG-1500

PROM programmer adapters that writes a program to the µPD78P368A on a general-purpose

PROM programmer such as the PG-1500.

PA-78P368GF

PA-78P368KL

PA-78P368GF: for µPD78P368AGF

PA-78P368KL : for µPD78P368AKL

PG-1500

controller

Connects the PG-1500 and a host machine with a serial intrface and a parallel interface to control

the PG-1500 from the host machine.

Host machine

Order code (part number)

OS

Supply media

3.5" 2HD

5" 2HD

µS5A13PG1500

µS5A10PG1500

PC-9800 series

MS-DOS

PC DOS

IBM PC/AT and

3.5" 2HC

µS7B13PG1500

µS7B10PG1500

compatible machines

Remark The operation of the PG-1500 controller is guaranteed only on the above host machine and OS.

Debugging Tools (When IE Controller Is Used)

IE-78350-R

In-circuit emulator that can be used to develop and debug application systems. Connected to

a host machine for debugging.

IE-78365-R-EM1 I/O emulation board that emulates the peripheral functions of the target device such as I/O ports.

Emulation probe that connects the IE-78350-R to the target system. One conversion socket,

EV-9200G-80, used to connect the target system is supplied as an accessory.

EP-78365GF-R

EV-9200G-80

Program that controls the IE-78350-R on the host machine. It can automatically execute

commands, enhancing debugging efficiency.

IE-78350-R

control program

(IE controller)

Host machine

Order code (part number)

OS

Supply media

3.5" 2HD

5" 2HD

µS5A13IE78365A

µS5A10IE78365A

PC-9800 series

MS-DOS

PC DOS

IBM PC/AT and

3.5" 2HC

µS7B13IE78365A

µS7B10IE78365A

compatible machines

Remark The operation of the IE controller is guaranteed only on the above host machine and OS.

87

µPD78363A, 78365A, 78366A, 78368A

Debugging Tools (When Integrated Debugger Is Used)

In-circuit emulation that can be used to develop and debug the application system. Connected

to a host machine for debugging.

IE-784000-R

Emulation board that emulates the peripheral functions of the target device such as I/O ports.

I/O emulation board that emulates the peripheral functions of the target device such as I/O ports.

Emulation probe connecting the IE-784000-R to the target system. One conversion socket, EV-

9200G-80, used to connect the target system is supplied as an accessory.

Interface adapter to connect PC-9800 series (except notebook type personal computer) as the

host machine.

IE-78350-R-EM-A

IE-78365-R-EM1

EP-78365GF-R

EV-9200G-80

IE-70000-98-IF-B

Interface adapter and cable to connect PC-9800 series notebook type personal computer as the

host machine.

IE-70000-98N-IF

Interface adapter and cable to connect IBM PC as the host machine.

Interface board to connect EWS as the host machine.

IE-70000-PC-IF-B

IE-78000-R-SV3

Integrated debugger

(ID78K3)

Program controlling the in-circuit emulator for the 78K/III series. Used in combination with a

device file (DF78365). Can debug a program coded in the C language, structured assembly

language, or assembly language at source program level. Can also split the screen of the host

machine into windows on each of which information is displayed, enhancing debugging

efficiency.

Host machine

Order code (part number)

OS

Supply media

3.5" 2HD

5" 2HD

PC-9800 series

MS-DOS

+

µSAA13ID78K3

µSAA10ID78K3

µSAB13ID78K3

µSAB10ID78K3

µSBB13ID78K3

µSBB10ID78K3

Windows^TM

IBM PC/AT and compatible

PC DOS

+

3.5" 2HC

5" 2HC

machines (Japanese Windows

)

Windows

IBM PC/AT and compatible

3.5" 2HC

5" 2HC

machines (English Windows

)

File containing information peculiar to device. Use in combination with an assembler (RA78

K3), C compiler (CC78K3), and integrated debugger (ID78K3).

Device File

(DF78365)

Host machine

Order code (part number)

OS

Supply media

3.5" 2HD

5" 2HD

PC-9800 series

MS-DOS

µS5A13DF78365

µS5A10DF78365

µS7B13DF78365

µS7B10DF78365

IBM PC/AT and compatible

machines

PC DOS

3.5" 2HC

5" 2HC

Remark The operation of the integrated debugger and device file is guaranteed only on the above host

machine and OS.

89

µPD78363A, 78365A, 78366A, 78368A

B.2 EMBEDDED SOFTWARE

The following embedded software is available for enhancing the efficiency of program development and

maintenance.

REAL-TIME OS

Real-time OS

Note

RX78K/III is intended to implement a multi-tasking environment for use in the control field where

real-time capability is a must. It can allocate the idle time of the CPU to other processing to

improve the overall performance of the system.

(RX78K/III)

RX78K/III provides system calls conforming to the µITRON specification.

The RX78K/III package supplies a tool (configurator) to create the nucleus of RX78K/III and

multiple information tables.

Host machine

Order code (part number)

OS

Supply media

3.5" 2HD

5" 2HD

PC-9800 series

MS-DOS

Pending

IBM PC/AT and compatible

machines

PC DOS

3.5" 2HC

5" 2HC

Note Under development

Caution Before purchasing this product, you are requested to conclude a contract licensing use by

filling out a specified form.

Remark When using the RX78K/III real-time OS, the RA78K3 assembler package (optional) is necessary.

91

µPD78363A, 78365A, 78366A, 78368A

Fuzzy Inference Development Support System

Fuzzy knowledge data Program that supports input/editing and evaluation (simulation) of fuzzy knowledge (fuzzy rules

creation tool

and membership functions).

Host machine

(FE9000, FE9200)

Order code (part number)

OS

Supply media

3.5" 2HD

5" 2HD

PC-9800 series

MS-DOS

µS5A13FE9000

µS5A10FE9000

µS7B13FE9200

µS7B10FE9200

IBM PC/AT and compatible

machines

PC DOS

+

3.5" 2HC

5" 2HC

Windows

Translator

Program that converts the fuzzy knowledge data obtained by using the fuzzy knowledge data

creation tool into assembler source program for the RA78K/III.

Note

(FT78K3)

Host machine

Order code (part number)

OS

Supply media

3.5" 2HD

5" 2HD

PC-9800 series

MS-DOS

µS5A13FT78K3

µS5A10FT78K3

µS7B13FT78K3

µS7B10FT78K3

IBM PC/AT and compatible

machines

PC DOS

3.5" 2HC

5" 2HC

Program that executes fuzzy inference when linked with the fuzzy knowledge data converted

by the translator.

Fuzzy inference module

Note

(FI78K/III)

Host machine

Order code (part number)

OS

Supply media

3.5" 2HD

5" 2HD

PC-9800 series

MS-DOS

µS5A13FI78K3

µS5A10FI78K3

µS7B13FI78K3

µS7B10FI78K3

IBM PC/AT and compatible

machines

PC DOS

3.5" 2HC

5" 2HC

Support software that evaluates and adjusts the fuzzy knowledge data at the hardware level by

using an in-circuit emulator.

Fuzzy inference debugger

(FD78K/III)

Host machine

Order code (part number)

OS

Supply media

3.5" 2HD

5" 2HD

PC-9800 series

MS-DOS

µS5A13FD78K3

µS5A10FD78K3

µS7B13FD78K3

µS7B10FD78K3

IBM PC/AT and compatible

machines

PC DOS

3.5" 2HC

5" 2HC

Note Under development

92

µPD78363A, 78365A, 78366A, 78368A

[MEMO]

93

µPD78363A, 78365A, 78366A, 78368A

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction

of the gate oxide and ultimately degrade the device operation. Steps must

be taken to stop generation of static electricity as much as possible, and

quickly dissipate it once, when it has occurred. Environmental control must

be adequate. When it is dry, humidifier should be used. It is recommended

to avoid using insulators that easily build static electricity. Semiconductor

devices must be stored and transported in an anti-static container, static

shielding bag or conductive material. All test and measurement tools

including work bench and floor should be grounded. The operator should

be grounded using wrist strap. Semiconductor devices must not be touched

with bare hands. Similar precautions need to be taken for PW boards with

semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input

level may be generated due to noise, etc., hence causing malfunction. CMOS

device behave differently than Bipolar or NMOS devices. Input levels of

CMOS devices must be fixed high or low by using a pull-up or pull-down

circuitry. Each unused pin should be connected to V^DDor GND with a

resistor, if it is considered to have a possibility of being an output pin. All

handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Produc-

tion process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset

function have not yet been initialized. Hence, power-on does not guarantee

out-pin levels, I/O settings or contents of registers. Device is not initialized

until the reset signal is received. Reset operation must be executed imme-

diately after power-on for devices having reset function.

94

µPD78363A, 78365A, 78366A, 78368A

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC

product in your application, please contact the NEC office in your country to obtain a list of authorized

representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California

Tel: 800-366-9782

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

NEC Electronics (Germany) GmbH

Benelux Office

Eindhoven, The Netherlands

Tel: 040-2445845

Fax: 800-729-9288

Fax: 2886-9022/9044

Fax: 040-2444580

NEC Electronics (Germany) GmbH

Duesseldorf, Germany

Tel: 0211-65 03 02

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

NEC Electronics (France) S.A.

Velizy-Villacoublay, France

Tel: 01-30-67 58 00

Fax: 0211-65 03 490

Tel: 02-528-0303

Fax: 02-528-4411

Fax: 01-30-67 58 99

NEC Electronics (UK) Ltd.

Milton Keynes, UK

Tel: 01908-691-133

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130

Tel: 253-8311

NEC Electronics (France) S.A.

Spain Office

Madrid, Spain

Fax: 01908-670-290

Fax: 250-3583

Tel: 01-504-2787

NEC Electronics Italiana s.r.1.

Milano, Italy

Tel: 02-66 75 41

Fax: 01-504-2860

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-719-2377

NEC Electronics (Germany) GmbH

Scandinavia Office

Fax: 02-66 75 42 99

Fax: 02-719-5951

Taeby, Sweden

Tel: 08-63 80 820

NEC do Brasil S.A.

Sao Paulo-SP, Brasil

Tel: 011-889-1680

Fax: 011-889-1689

Fax: 08-63 80 388

J96. 8

95

µPD78363A, 78365A, 78366A, 78368A

MS-DOS and windows are either registered trademarks or trademarks of Microsoft

Corporation in the United states and/or other countries.

PC/AT and PC DOS are trademarks of IBM Corporation.

HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

SunOS is a trademark of Sun Microsystems, Inc.

NEWS and NEWS-OS are trademarks of Sony Corporation.

TRON is an abbreviation of The Realtime Operating system Nucleus.

ITRON is an abbreviation of Industrial TRON.

The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products

may be prohibited without governmental license. To export or re-export some or all of these products from a country other than

Japan may also be prohibited without a license from that country. Please call an NEC sales representative.

Lisence not needed

: µPD78365A

The customer must judge the need for license : µPD78363A, 78366A, 78368A

No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in

this document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property

rights of third parties by or arising from use of a device described herein or any other liability arising from use

of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other

intellectual property rights of NEC Corporation or others.

While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,

the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or

property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety

measures in its design, such as redundancy, fire-containment, and anti-failure features.

NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a

customer designated "quality assurance program" for a specific application. The recommended applications of

a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device

before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic

equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade,

they should contact an NEC sales representative in advance.

Anti-radioactive design is not implemented in this product.

M4 96.5

2


型号：	UPD78368AGF
厂家：	NEC
描述：	16/8-BIT SINGLE-CHIP MICROCONTROLLERS 8分之16位单芯片微控制器产品微控制器
文件：	总96页 (文件大小：490K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD78368AGF [NEC]

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