UPD703116GJ(A)-XXX-UEN [NEC]
RISC Microcontroller, 32-Bit, MROM, 50MHz, MOS, PQFP144, 20 X 20 MM, FINE PITCH, PLASTIC, LQFP-144;
| 型号： | UPD703116GJ(A)-XXX-UEN |
| 厂家： | 
NEC |
| 描述： | RISC Microcontroller, 32-Bit, MROM, 50MHz, MOS, PQFP144, 20 X 20 MM, FINE PITCH, PLASTIC, LQFP-144 时钟 微控制器 外围集成电路 |
| 文件： | 总52页 (文件大小：491K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
V850E/IA1TM
32-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), and 70F3116(A1) are products of the V850
SeriesTM of 32-bit single-chip microcontrollers for real-time control applications. These microcontrollers integrate a
32-bit CPU, ROM, RAM, an interrupt controller, timers such as a 3-phase sine wave PWM timer for motor, a serial
interface, an FCAN controller, an A/D converter, a DMA controller, and other functions on a single chip.
The µPD70F3116, 70F3116(A), and 70F3116(A1) are products that substitute flash memory for the internal mask
ROM of the µPD703116, 703116(A), and 703116(A1). This enables users to perform on-board program writing and
erasure, making this product effective for evaluation during system development, small-lot production of multiple
devices, and rapid production start.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850E/IA1 Hardware User’s Manual: U14492E
V850E1 Architecture User’s Manual: U14559E
FEATURES
{ Number of instructions: 83
{ Minimum instruction execution time: 20 ns
(with a 50 MHz internal clock)
{ General-purpose registers: 32 bits × 32 registers
{ Instruction set suitable for control applications
{ Internal memory
{ Powerful serial interface (with dedicated on-chip
baud rate generator)
• Asynchronous serial interfaces: 3 ch
• Clocked serial interfaces: 2 ch
{ Automotive LAN (FCAN controller): 1 ch
{ NBD (Non Break Debug) function
• RAM monitor function
• Mask ROM: 256 KB (µPD703116)
• Flash memory: 256 KB (µPD70F3116)
• RAM: 10 KB
• Event detection function
{
{
{
{
{
10-bit resolution A/D converter: 8 inputs × 2 circuits
Sophisticated internal interrupt controller
DMA controller: 4 ch
I/O lines: Total 83
Clock generator
{ Memory access control (supporting SRAM and ROM)
{ Real-time pulse unit suitable for control applications
• 16-bit timers for 3-phase sine wave PWM inverter
control: 2 ch
• 16-bit up/down counter/timers for 2-phase encoder
input: 2 ch
• 16-bit general-purpose timer/counters: 2 ch
• 16-bit general-purpose timer/event counter: 1 ch
• 16-bit interval timer: 1 ch
{ Power-saving functions
{
µPD70F3116, 70F3116(A), 70F3116(A1)
• Can be replaced with mask ROM-incorporated
µPD703116, 703116(A), or 703116(A1) for mass
production
Unless otherwise specified, the µPD703116 or 70F3116 is used in this document as the representative product.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U15299EJ2V0DS00 (2nd edition)
Date Published June 2002 N CP(K)
Printed in Japan
2001, 2002
©
The mark
shows major revised points.
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
APPLICATIONS
•
•
µPD703116, 70F3116: Consumer equipment (inverter air conditioners, etc.)
Industrial equipment (motor control, general-purpose inverters, etc.)
µPD703116(A), 703116(A1), 70F3116(A), 70F3116(A1): Automobile applications (electrical power steering,
electric car control, etc.)
ORDERING INFORMATION
Part No.
Package
Quality Grade
Standard
Standard
Special
µPD703116GJ-xxx-UEN
µPD70F3116GJ-UEN
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
µPD703116GJ(A)-xxx-UEN
µPD703116GJ(A1)-xxx-UEN
µPD70F3116GJ(A)-UEN
µPD70F3116GJ(A1)-UEN
Special
Special
Special
Remark xxx: ROM code suffix
Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Differences between µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), and 70F3116(A1)
Part No.
µPD703116
µPD703116(A) µPD703116(A1)
µPD70F3116
µPD70F3116(A) µPD70F3116(A1)
Item
Quality grade
Standard grade Special grade
Standard grade Special grade
50
Maximum operating 50
frequency (MHz)
32
32
Operating ambient
temperature (TA)
−40 to +85°C
−40 to +110°C
−40 to +85°C
−40 to +110°C
2
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
PIN CONFIGURATION (TOP VIEW)
• 144-pin plastic LQFP (fine pitch) (20 × 20)
µPD703116GJ-×××-UEN, 703116GJ(A)-×××-UEN, 703116GJ(A1)-×××-UEN,
µPD70F3116GJ-UEN, 70F3116GJ(A)-UEN, 70F3116GJ(A1)-UEN
ANI07
1
108
107
106
105
104
103
102
101
100
99
TIUD11/TO11/P13
TCLR10/INTP101/P12
TCUD10/INTP100/P11
TIUD10/TO10/P10
PCM4
AVDSDS
AV
3
2
AVREF1
ANI10
ANI11
ANI12
ANI13
ANI14
ANI15
ANI16
ANI17
4
5
6
HLDRQ/PCM3
HLDAK/PCM2
CLKOUT/PCM1
WAIT/PCM0
PCT7
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
98
ASTB/PCT6
PCT5
97
_
TRIG DBG
96
RD/PCT4
_
AD3 DBG
95
PCT3
_
AD2 DBG
94
PCT2
_
Note 1
AD1 DBG
93
UWR/PCT1
LWR/PCT0
_
AD0 DBG
92
CLK DBG
90
VDD5
V
SYNC
91
_
NSoSt5e 2
RESET
89
CVDSDS
CV
87
88
CS7/PCS7
CS6/PCS6
CS5/PCS5
CS4/PCS4
CS3/PCS3
CS2/PCS2
CS1/PCS1
CS0/PCS0
A23/PDH7
A22/PDH6
A21/PDH5
A20/PDH4
A19/PDH3
A18/PDH2
A17/PDH1
A16/PDH0
X1
X2
86
85
CKSEL
84
MODE0
MODE1
MODE2
SI0/P40
SO0/P41
SCK0/P42
SI1/P43
SO1/P44
SCK1/P45
CRXD/P46
CTXD/P47
83
82
81
80
79
78
77
76
75
74
73
Notes 1. Incorporated in µPD70F3116 only.
µPD703116 is as follows.
TRIG_DBG: IC1, AD0_DBG to AD3_DBG: IC2, SYNC: IC3, CLK_DBG: IC4
2. µPD703116: IC5
µPD70F3116: VPP
Cautions 1. When using the µPD70F3116 in normal mode, connect the VPP pin to VSS5.
2. When using the µPD703116, the processing when the IC1 to IC5 pins are unused is as
follows.
IC1 to IC4 pins: Leave open.
IC5 pin: Independently connect to VSS5 via a resistor.
3
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
PIN IDENTIFICATION
A16 to A23:
Address bus
P20 to P27:
P30 to P37:
P40 to P47:
PCM0 to PCM4:
PCS0 to PCS7:
PCT0 to PCT7:
PDH0 to PDH7:
PDL0 to PDL15:
RD:
Port 2
AD0 to AD15:
Address/data bus
Port 3
AD0_DBG to AD3_DBG: Debug address/data bus
Port 4
ADTRG0, ADTRG1:
ANI00 to ANI07,
ANI10 to ANI17:
ASCK1, ASCK2:
ASTB:
A/D trigger input
Analog input
Port CM
Port CS
Port CT
Asynchronous serial clock
Address strobe
Port DH
Port DL
AVDD:
Analog power supply
Analog reference voltage
Analog ground
Read strobe
Reset
AVREF0, AVREF1:
AVSS:
RESET:
RXD0 to RXD2:
SCK0, SCK1:
SI0, SI1:
Receive data
Serial clock
Serial input
Serial output
Debug synchronization
Timer clear
CKSEL:
Clock generator operating mode select
Debug clock
CLK_DBG:
CLKOUT:
Clock output
SO0, SO1:
CRXD:
Receive data for controller area network SYNC:
CS0 to CS7:
CTXD:
Chip select
TCLR10, TCLR11,
Transmit data for controller area network TCLR2, TCLR3:
CVDD:
Clock generator power supply
Clock generator ground
Emergency shut off
TCUD10, TCUD11:
TI2, TI3:
Timer control pulse input
Timer input
CVSS:
ESO0, ESO1:
HLDAK:
TIUD10, TIUD11:
TO000 to TO005,
TO010 to TO015,
TO10, TO11,
TO21 to TO24, TO3:
TRIG_DBG:
TXD0 to TXD2:
UWR:
Timer count pulse input
Timer output
Hold acknowledge
HLDRQ:
Hold request
IC1 to IC5:
Internally connected
INTP0 to INTP6,
INTP100, INTP101,
INTP110, INTP111,
INTP20 to INTP25,
INTP30, INTP31:
LWR:
Interrupt request from peripherals
Debug trigger
Transmit data
Upper write strobe
Power supply
VDD3, VDD5:
Lower write strobe
Mode
VPP:
Programming power supply
Ground
MODE0 to MODE2:
NMI:
VSS3, VSS5:
Non-maskable interrupt request
WAIT:
Wait
X1, X2:
Crystal
P00 to P07:
P10 to P15:
Port 0
Port 1
4
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
INTERNAL BLOCK DIAGRAM
NMI
INTP0 to INTP6
ROM
CPU
BCU
MEMC
Instruction
queue
PC
INTC
HLDRQ
HLDAK
CS0 to CS7
SRAMC
INTP20 to INTP25
INTP30, INTP31
INTP100, INTP101
INTP110, INTP111
Note 1
32-bit
barrel
shifter
Multiplier
32×32 64
ROMC
RD
ASTB
RPU
ESO0, ESO1
TM0: 2 ch
TM1: 2 ch
TM2: 2 ch
TM3: 1 ch
TM4: 1 ch
UWR
TO000 to TO005,
TO010 to TO015
System
register
LWR
WAIT
A16 to A23
TIUD10/TO10,
TCUD10, TCLR10
TIUD11/TO11,
TCUD11, TCLR11
AD0 to AD15
General-
purpose
registers
32bits×32
ALU
RAM
TI2, TCLR2, TO21 to TO24
TI3/TCLR3, TO3
10 KB
SIO
TXD0
RXD0
UART0
BRG0
DMAC
TXD1
RXD1
ASCK1
UART1
BRG1
TXD2
RXD2
ASCK2
UART2
BRG2
SO0
SI0
CSI0
CKSEL
SCK0
SO1
SI1
BRG3
CSI1
CLKOUT
X1
Ports
ADC0
ADC1
CG
X2
SCK1
CTXD
CV
CVSDSD
FCAN
CRXD
MODE0 to MODE2
RESET
V
VDD5
VSS5
VDD3
System
controller
CLK_DBG
SYNC
AD0_DBG to AD3_DBG
TRIG_DBG
NBDNote 3
Note 2
VSPSP3
Note 4
Notes 1. µPD703116: 256 KB (mask ROM)
µPD70F3116: 256 KB (flash memory)
2. Incorporated in µPD70F3116 only.
µPD703116 is as follows.
TRIG_DBG: IC1, AD0_DBG to AD3_DBG: IC2, SYNC: IC3, CLK_DBG: IC4
3. µPD70F3116 only.
4. µPD70F3116 only.
In the µPD703116, the VPP pin is assigned as the IC5 pin.
5
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
CONTENTS
1. DIFFERENCES BETWEEN PRODUCTS..............................................................................................7
2. PIN FUNCTIONS...................................................................................................................................8
2.1 Port Pins ......................................................................................................................................................8
2.2 Non-Port Pins ............................................................................................................................................11
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins.........................................................14
3. ELECTRICAL SPECIFICATIONS.......................................................................................................17
3.1 Normal Operation Mode............................................................................................................................17
3.2 Flash Memory Programming Mode (µPD70F3116 only) ........................................................................44
4. PACKAGE DRAWING.........................................................................................................................46
5. RECOMMENDED SOLDERING CONDITIONS..................................................................................47
APPENDIX NOTES ON TARGET SYSTEM DESIGN ..............................................................................48
6
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
1. DIFFERENCES BETWEEN PRODUCTS
Item
µPD703116
Mask ROM
256 KB
µPD703116(A) µPD703116(A1)
µPD70F3116
µPD70F3116(A) µPD70F3116(A1)
Internal ROM
Flash memory
Internal RAM
10 KB
NBD (Non Break
Debug) function
Not provided
(IC1 to IC4)
Provided
(TRIG_DBG, AD0_DBG to AD3_DBG, SYNC,
CLK_DBG)
Flash memory
Not provided (IC5)
Not provided
Provided (VPP)
programming pin
Flash memory
Provided
programming mode
(MODE0 = H/L, MODE1 = H, MODE2 = L, VPP = 7.8 V)
Quality grade
Standard grade Special grade
Standard grade Special grade
Electrical
The maximum operating frequency, operating ambient temperature, and current consumption differ (refer to
specifications
3. ELECTRICAL SPECIFICATIONS).
Other
The noise immunity and noise radiation differ because the circuit scale and mask layout are different.
Cautions 1. There are differences in noise immunity and noise radiation between the mask ROM version
and flash memory version. When pre-producing an application set with the flash memory
version and then mass-producing it with the mask ROM version, be sure to conduct
sufficient evaluation for commercial samples (not engineering samples) of the mask ROM
version.
2. When switching from the flash memory version to the mask ROM version, write the same
code to the free area of the internal ROM.
7
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
2. PIN FUNCTIONS
2.1 Port Pins
(1/3)
Alternate Function
NMI
Pin Name
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P35
P36
P37
I/O
Function
Input
Port 0
8-bit input-only port
ESO0/INTP0
ESO1/INTP1
ADTRG0/INTP2
ADTRG1/INTP3
INTP4
INTP5
INTP6
I/O
Port 1
TIUD10/TO10
TCUD10/INTP100
TCLR10/INTP101
TIUD11/TO11
TCUD11/INTP110
TCLR11/INTP111
TI2/INTP20
TO21/INTP21
TO22/INTP22
TO23/INTP23
TO24/INTP24
TCLR2/INTP25
TI3/TCLR3/INTP30
TO3/INTP31
RXD0
6-bit I/O port
Input/output can be specified in 1-bit units.
I/O
Port 2
8-bit I/O port
Input/output can be specified in 1-bit units.
I/O
Port 3
8-bit I/O port
TXD0
Input/output can be specified in 1-bit units.
RXD1
TXD1
ASCK1
RXD2
TXD2
ASCK2
8
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
(2/3)
Pin Name
I/O
I/O
Function
Alternate Function
SI0
P40
P41
P42
P43
P44
P45
P46
P47
Port 4
8-bit I/O port
SO0
Input/output can be specified in 1-bit units.
SCK0
SI1
SO1
SCK1
CRXD
CTXD
WAIT
CLKOUT
HLDAK
HLDRQ
PCM0
PCM1
PCM2
PCM3
PCM4
PCT0
PCT1
PCT2
PCT3
PCT4
PCT5
PCT6
PCT7
PCS0
PCS1
PCS2
PCS3
PCS4
PCS5
PCS6
PCS7
PDH0
PDH1
PDH2
PDH3
PDH4
PDH5
PDH6
PDH7
I/O
I/O
Port CM
5-bit I/O port
Input/output can be specified in 1-bit units.
−
Port CT
LWR
UWR
8-bit I/O port
Input/output can be specified in 1-bit units.
−
−
RD
−
−
ASTB
I/O
Port CS
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7
A16
A17
A18
A19
A20
A21
A22
A23
8-bit I/O port
Input/output can be specified in 1-bit units.
I/O
Port DH
8-bit I/O port
Input/output can be specified in 1-bit units.
9
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
(3/3)
Pin Name
PDL0
I/O
I/O
Function
Alternate Function
AD0
Port DL
8-/16-bit I/O port
PDL1
PDL2
PDL3
PDL4
PDL5
PDL6
PDL7
PDL8
PDL9
PDL10
PDL11
PDL12
PDL13
PDL14
PDL15
AD1
Input/output can be specified in 1-bit units.
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
10
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
2.2 Non-Port Pins
(1/3)
Alternate Function
Pin Name
TO000
I/O
Function
Output Timer 00 pulse signal output
−
−
TO001
TO002
TO003
TO004
TO005
TO010
TO011
TO012
TO013
TO014
TO015
TO10
−
−
−
−
Output Timer 01 pulse signal output
−
−
−
−
−
−
Output Timer 10 or 11 pulse signal output
Output Timer 2 pulse signal output
P10/TIUD10
P13/TIUD11
P21/INTP21
P22/INTP22
P23/INTP23
P24/INTP24
P27/INTP31
P01/INTP0
P02/INTP1
P10/TO10
P13/TO11
P11/INTP100
P14/INTP110
P12/INTP101
P15/INTP111
P20/INTP20
P26/INTP30/TCLR3
P25/INTP25
P26/INTP31/TI3
P01/ESO0
P02/ESO1
P03/ADTRG0
P04/ADTRG1
P05
TO11
TO21
TO22
TO23
TO24
TO3
Output Timer 3 pulse signal output
ESO0
ESO1
TIUD10
TIUD11
TCUD10
TCUD11
TCLR10
TCLR11
TI2
Input
Input
Input
Input
Input
Input
Input
Timer 00 or 01 output stop signal input
External count clock input to up/down counter (timer 10 or 11)
Count operation switching signal to up/down counter (timer 10 or 11)
Clear signal input to up/down counter (timer 10 or 11)
Timer 2 or 3 external count clock input
TI3
TCLR2
TCLR3
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
Timer 2 or 3 clear signal input
External maskable interrupt request input
P06
P07
11
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
(2/3)
Pin Name
INTP100
I/O
Function
Alternate Function
Input
External maskable interrupt request input and timer 10 external capture
trigger input
P11/TCUD10
INTP101
INTP110
INTP111
INTP20
INTP21
INTP22
INTP23
INTP24
INTP25
INTP30
INTP31
SO0
P12/TCLR10
Input
Input
External maskable interrupt request input and timer 11 external capture
trigger input
P14/TCUD11
P15/TCLR11
External maskable interrupt request input and timer 2 external capture
trigger input
P20/TI2
P21/TO21
P22/TO22
P23/TO23
P24/TO24
P25/TCLR2
Input
External maskable interrupt request input and timer 3 external capture
trigger input
P26/TI3/TCLR3
P27/TO3
P41
P44
P40
P43
P42
P45
P31
P33
P36
P30
P32
P35
P34
P37
P47
P46
−
Output Serial transmit data output (3-wire) of CSI0 and CSI1
SO1
SI0
Input
I/O
Serial receive data input (3-wire) of CSI0 and CSI1
Serial clock I/O (3-wire) of CSI0 and CSI1
SI1
SCK0
SCK1
TXD0
Output Serial transmit data output of UART0 to UART2
TXD1
TXD2
RXD0
Input
I/O
Serial receive data input of UART0 to UART2
Serial clock I/O of UART1 and UART2
RXD1
RXD2
ASCK1
ASCK2
CTXD
Output FCAN serial transmit data output
CRXD
Input
Input
FCAN serial receive data input
Analog input to A/D converter
ANI00 to ANI07
ANI10 to ANI17
ADTRG0
ADTRG1
NMI
−
Input
External trigger input to A/D converter
P03/INTP2
P04/INTP3
P00
−
Input
Input
Non-maskable interrupt request input
Specifies V850E/IA1 operation mode
MODE0
MODE1
MODE2
VPPNote 1
−
−
−
−
Power application for flash memory write
Internal connection pins
−
IC1 to IC5Note 2
−
Notes 1. µPD70F3116 only
2. µPD703116 only
12
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
(3/3)
Pin Name
WAIT
I/O
Function
Alternate Function
PCM0
Input
Control signal input to insert wait in bus cycle
HLDAK
HLDRQ
LWR
Output Bus hold acknowledge output
Input Bus hold request input
PCM2
PCM3
Output External data lower byte write strobe signal output
Output External data higher byte write strobe signal output
Output External data bus read strobe signal output
Output External data bus address strobe signal output
Output Chip select signal output
PCT0
UWR
PCT1
RD
PCT4
ASTB
PCT6
CS0
PCS0
CS1
PCS1
CS2
PCS2
CS3
PCS3
CS4
PCS4
CS5
PCS5
CS6
PCS6
CS7
PCS7
AD0 to AD15
A16 to A23
RESET
X1
I/O
16-bit address/data bus for external memory
PDL0 to PDL15
Output Higher 8-bit address bus for external memory
PDH0 to PDH7
Input
Input
−
System reset input (3 V interface, 5 V tolerance)
−
Crystal resonator connection pin for system clock oscillation (3 V interface).
Input to X1 pin when providing clocks from outside.
−
X2
−
CLKOUT
CKSEL
AVREF0
AVREF1
AVDD
Output System clock output
PCM1
Input
Input specifying clock generator operation mode
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Input
Reference voltage input for A/D converter 0
Reference voltage input for A/D converter 1
Positive power supply for A/D converter
Input
−
−
AVSS
Ground potential for A/D converter
CVDD
−
Positive power supply for dedicated clock generator
Ground potential for dedicated clock generator
Positive power supply for peripheral interface
Ground potential for peripheral interface
CVSS
−
VDD5
−
VSS5
−
VDD3
−
3.3 V positive power supply pin for internal CPU
Ground pin for internal CPU
VSS3
−
CLK_DBGNote
SYNCNote
AD0_DBGNote
AD1_DBGNote
AD2_DBGNote
AD3_DBGNote
TRIG_DBGNote
Input
Input
I/O
Debugging interface clock input (3.3 V interface)
Debugging interface command synchronization input (3.3 V interface)
Command interface input for debugging (3.3 V interface)
Output Address match trigger signal output for debugging (3.3 V interface)
Note µPD70F3116 only
13
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 2-1.
The I/O circuit configuration of each type is schematically shown in Figure 2-1.
It is recommended that 1 to 10 kΩ resistors be used when connecting to VDD5, VSS5, CVDD, CVSS, or AVSS via a
resistor.
Table 2-1. Types of Pin I/O Circuits and Recommended Connection (1/2)
Pin
I/O Circuit Type
2
Recommended Connection
Connect directly to VSS5.
P00/NMI
P01/ESO0/INTP0
P02/ESO1/INTP1
P03/ADTRG0/INTP2
P04/ADTRG1/INTP3
P05/INTP4 to P07/INTP6
P10/TIUD10/TO10
P11/TCUD10/INTP100
P12/TCLR10/INTP101
P13/TIUD11/TO11
P14/TCUD11/INTP110
P15/TCLR11/INTP111
P20/TI2/INTP20
P21/TO21/INTP21 to P24/TO24/INTP24
P25/TCLR2/INTP25
P26/TI3/TCLR3/INTP30
P27/TO3/INTP31
P30/RXD0
5-AC
Input: Independently connect to VDD5 or VSS5 via a resistor.
Output: Leave open.
P31/TXD0
5
P32/RXD1
5-AC
5
P33/TXD1
P34/ASCK1
5-AC
P35/RXD2
P36/TXD2
5
P37/ASCK2
5-AC
P40/SI0
P41/SO0
5
P42/SCK0
5-AC
P43/SI1
P44/SO1
5
P45/SCK1
5-AC
P46/CRXD
P47/CTXD
5
14
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
Table 2-1. Types of Pin I/O Circuits and Recommended Connection (2/2)
Pin
I/O Circuit Type
5
Recommended Connection
PCM0/WAIT
PCM1/CLKOUT
PCM2/HLDAK
PCM3/HLDRQ
PCM4
Input: Independently connect to VDD5 or VSS5 via a resistor.
Output: Leave open.
PCT0/LWR
PCT1/UWR
PCT2
PCT3
PCT4/RD
PCT5
PCT6/ASTB
PCT7
PCS0/CS0
PCS1/CS1
PCS2/CS2
PCS3/CS3
PCS4/CS4
PCS5/CS5
PCS6/CS6
PCS7/CS7
PDH0/A16 to PDH7/A23
PDL0/AD0 to PDL15/AD15
AD0_DBG to AD3_DBGNote 1
TRIG_DBGNote 1
CLK_DBGNote 1
SYNCNote 1
5-AC
Independently connect to CVDD or CVSS via a resistor.
3
2
Leave open (low-level output).
Independently connect to CVSS via a resistor.
Independently connect to CVDD via a resistor.
IC1 to IC4Note 2
−
7
4
2
Leave open.
ANI00 to ANI07, ANI10 to ANI17
TO000 to TO005, TO010 to TO015
MODE0 to MODE2
VPPNote 1
Connect to AVSS.
Leave open.
−
Connect to VSS5.
IC5Note 2
Independently connect to VSS5 via a resistor.
RESET
−
−
CKSEL
X2
−
−
−
−
Leave open.
AVSS
Connect to VSS5.
Connect to VSS5.
Connect to VDD5.
AVREF0, AVREF1
AVDD
Notes 1. µPD70F3116 only
2. µPD703116 only
15
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
Figure 2-1. Pin I/O Circuits
Type 2
Type 5
VDD
Data
P-ch
IN
IN/OUT
Output
disable
N-ch
Input
enable
Schmitt-triggered input with hysteresis characteristics
Type 3
Type 5-AC
VDD
Data
VDD
P-ch
IN/OUT
P-ch
Output
disable
N-ch
OUT
N-ch
Input
enable
Type 4
Type 7
VDD
Data
P-ch
P-ch
N-ch
OUT
Comparator
+
_
IN
Output
disable
N-ch
VREF (threshold voltage)
Push-pull output with possible high-impedance output
(P-ch, N-ch both off)
16
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
3. ELECTRICAL SPECIFICATIONS
3.1 Normal Operation Mode
Absolute Maximum Ratings (TA = 25°C)
Parameter
Symbol
VDD3
VDD5
CVDD
CVSS
AVDD
AVSS
VI1
Conditions
Ratings
−0.5 to +4.6
Unit
V
Power supply voltage
VDD3 pin
VDD5 pin
CVDD pin
CVSS pin
AVDD pin
AVSS pin
−0.5 to +7.0
V
−0.5 to +4.6
V
−0.5 to +0.5
−0.5 to VDD5 + 0.5Note 1
V
V
−0.5 to +0.5
V
Input voltage
Other than X1 pin and pins for NBDNote 2
VPP pin, µPD70F3116Note 3
Pins for NBDNote 2
−0.5 to VDD5 + 0.5Note 1
−0.5 to +8.5
−0.5 to VDD3 + 0.5Note 1
V
VI2
V
VI3
V
VI4
RESET pin (when VDD3 is supplied)
X1 pin
−0.5 to +6.0
V
Clock input voltage
Analog input voltage
VK
−0.5 to VDD3 + 1.0Note 1
−0.5 to VDD5 + 0.5Note 1
−0.5 to AVDD + 0.5Note 1
−0.5 to VDD5 + 0.5Note 1
−0.5 to AVDD + 0.5Note 1
15
V
VIAN
ANI00 to ANI07 pins,
ANI10 to ANI17 pins
AVREF0 pin,
AVDD > VDD5
VDD5 ≥ AVDD
AVDD > VDD5
VDD5 ≥ AVDD
V
V
Analog reference input voltage
Output current, low
AVREF
V
AVREF1 pin
V
IOL
Per pin for TO000 to TO005 and
TO010 to TO015 pins
mA
Per pin other than for TO000 to
TO005 and TO010 to TO015 pins
4.0
mA
Total for all pins
Per pin
210
−4.0
mA
mA
mA
Output current, high
IOH
Total for all pins
−100
Operating ambient temperature
TA
µPD703116, 703116(A),
µPD70F3116, 70F3116(A)
−40 to +85
°C
µPD703116(A1), 70F3116(A1)
−40 to +110
−65 to +150
°C
°C
Storage temperature
Tstg
17
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
Notes 1. Be sure not to exceed the absolute maximum ratings (MAX. value) of each power supply voltage.
2. CLK_DBG, SYNC, AD0_DBG to AD3_DBG pins (µPD70F3116 only)
3. Make sure that the following conditions of the VPP voltage application timing are satisfied when the
flash memory is written.
• When power supply voltage rises
VPP must exceed VDD3 and VDD5 10 µs or more after VDD3 and VDD5 have reached the lower-limit
value (VDD3: 3.0 V, VDD5: 4.5 V) of the operating voltage range.
• When power supply voltage drops
VDD3 and VDD5 must be lowered 10 µs or more after VPP falls below the lower-limit value (VDD3: 3.0
V, VDD5: 4.5 V) of the operating voltage range of VDD3 and VDD5.
4.5 V
VDD5
0 V
µ
10 s or
more
µ
10 s or
more
3.0 V
0 V
VDD3
µ
10 s or
more
µ
10 s or
more
VPP
4.5 V
VPP
3.0 V
0 V
Cautions 1. Do not directly connect output (or I/O) pins of IC products to each other, or to VDD, VCC, and
GND. Open drain pins or open collector pins, however, can be directly connected to each
other. Direct connection of the output pins between an IC product and an external circuit is
possible, if the output pins can be set to the high-impedance state and the output timing of
the external circuit is designed to avoid output conflict.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily
for any parameter. That is, the absolute maximum ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be
used under conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions shown below for DC characteristics and AC characteristics are
within the range for normal operation and quality assurance.
18
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
Capacitance (TA = 25°C, VDD3 = VDD5 = VSS3 = VSS5 = 0 V)
Parameter
Input capacitance
Symbol
CI
Conditions
MIN.
TYP.
MAX.
15
Unit
pF
fC = 1 MHz
Unmeasured pins returned to 0 V.
I/O capacitance
CIO
15
pF
Output capacitance
CO
15
pF
Operating Conditions
Operation Mode
Internal System Clock Frequency (fXX)
Operating Ambient
Temperature (TA)
Power Supply Voltage
VDD3 VDD5
Direct mode
PLL mode
µPD703116, 703116(A),
70F3116, 70F3116(A)
4 to 25 MHz
−40 to +85°C
3.3 V 0.3 V
5.0 V 0.5 V
µPD703116(A1), 70F3116(A1)
4 to 16 MHz
4 to 50 MHz
−40 to +110°C
−40 to +85°C
3.3 V 0.3 V
3.3 V 0.3 V
5.0 V 0.5 V
5.0 V 0.5 V
µPD703116, 703116(A),
70F3116, 70F3116(A)
µPD703116(A1), 70F3116(A1)
4 to 32 MHz
−40 to +110°C
3.3 V 0.3 V
5.0 V 0.5 V
Caution When interfacing to the external devices using the CLKOUT signal, make the internal system
clock frequency (fXX) 32 MHz or lower.
19
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
Clock Oscillator Characteristics (TA = −40 to +85°C: µPD703116, 703116(A), 70F3116, 70F3116(A),
TA = −40 to +110°C: µPD703116(A1), 70F3116(A1))
(a) Ceramic resonator or crystal resonator connection
X1
X2
R
d
C1
C2
Parameter
Symbol
fX
Conditions
MIN.
4
TYP.
MAX.
6.4
Unit
Oscillation frequency
MHz
Remarks 1. Connect the oscillator as close to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area indicated by the broken lines.
3. For the resonator selection and oscillator constant, customers are required to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
(b) External clock input
X1
X2
Open
High-speed CMOS inverter
External clock
Cautions 1. Connect the high-speed CMOS inverter as closely to the X1 pin as possible.
2. Thoroughly evaluate the matching between the V850E/IA1 and the high-speed CMOS
inverter.
20
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
Recommended Oscillator Constant
(a) Ceramic resonator
(i) Murata Mfg. Co., Ltd (TA = −40 to +85°C: µPD703116, 703116(A), 70F3116, 70F3116(A),
TA = −40 to +110°C: µPD703116(A1), 70F3116(A1))
Type
Product Name
Oscillation
Frequency
Recommended Circuit Constant
Recommended Voltage
Range
fX (MHz)
4.0
C1 (pF)
On-chip
On-chip
C2 (pF)
On-chip
On-chip
Rd (Ω)
MIN. (V)
3.0
MAX. (V)
3.6
Surface mount
CSTCR4M00G55-R0
CSTCR6M00G55-R0
0
0
6.0
3.0
3.6
Caution This oscillator constant is a reference value based on evaluation under a specific environment
by the resonator manufacturer.
If optimization of oscillator characteristics is necessary in the actual application, apply to the
resonator manufacturer for evaluation on the implementation circuit.
The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use
the V850E/IA1 so that the internal operating conditions are within the specifications of the DC
and AC characteristics.
21
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
DC Characteristics (TA = –40 to +85°C: µPD703116, 703116(A), 70F3116, 70F3116(A),
TA = –40 to +110°C: µPD703116(A1), 70F3116(A1),
VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V) (1/2)
Parameter
Symbol
VIH1
VIH2
VIH3
VIH4
VIH5
VIH6
VIL1
Conditions
Pins for bus controlNote 1
MIN.
2.2
TYP.
MAX.
VDD5
Unit
V
Input voltage, high
Pins for NBDNote 2
Port pinsNote 3
0.8VDD3
0.7VDD5
0.8VDD5
0.8VDD3
0.8VDD3
0
VDD3
V
VDD5
V
Port pins other than Notes 1, 2, 3
X1 pin
VDD5
V
VDD3 +0.3
5.5
V
RESET pin
V
Input voltage, low
Pins for bus controlNote 1
Pins for NBDNote 2
Port pinsNote 3
0.8
V
VIL2
0
0.2VDD3
0.3VDD5
0.2VDD5
0.15VDD3
0.2VDD3
V
VIL3
0
V
VIL4
Port pins other than Notes 1, 2, 3
X1 pin
0
V
VIL5
–0.5
0
V
VIL6
RESET pin
V
Output voltage, high
Output voltage, low
VOH1
Pins other than
IOH = –2.5 mA
VDD5 –1.0
V
Note 4
VOH2
VOL1
Pins for NBDNote 4
PWM outputNote 5
IOH = –2.5 mA
IOL = 15 mA
IOL = 2.5 mA
IOL = 2.5 mA
VDD3 –1.0
V
V
V
V
2.0
0.4
0.4
VOL2
Pins other than
Notes 4, 5
VOL3
ILIH
Pins for NBDNote 4
IOL = 2.5 mA
0.4
10
V
Input leakage current, high
Input leakage current, low
Output leakage current, high
Output leakage current, low
VI = VDD5
µA
µA
µA
µA
µA
ILIL
VI = 0 V
–10
10
ILOH
ILOL
ILIAN
VO = VDD5
VO = 0 V
–10
10
Analog pin input leakage
current
ANI00 to ANI07, ANI10 to ANI17 pins
Notes 1. AD0/PDL0 to AD15/PDL15, A16/PDH0 to A23/PDH7, LWR/PCT0, UWR/PCT1, PCT2, PCT3,
RD/PCT4, PCT5, ASTB/PCT6, PCT7, WAIT/PCM0, CLKOUT/PCM1, HLDAK/PCM2, HLDRQ/PCM3,
PCM4, CS0/PCS0 to CS7/PCS7 pins
•
2. CLK_DBG, SYNC, AD0_DBG to AD3_DBG pins (µPD70F3116 only)
3. P31/TXD0, P33/TXD1, P36/TXD2, P41/SO0, P44/SO1, P47/CTXD pins
4. AD0_DBG to AD3_DBG, TRIG_DBG pins (µPD70F3116 only)
5. TO000 to TO005, TO010 to TO015 pins
22
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
DC Characteristics (TA = –40 to +85°C: µPD703116, 703116(A), 70F3116, 70F3116(A),
TA = –40 to +110°C: µPD703116(A1), 70F3116(A1),
VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V) (2/2)
Parameter
Symbol
IDD1
Conditions
MIN.
TYP.
MAX.
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
Power supply In
µPD703116
µPD70F3116
µPD703116
µPD70F3116
VDD3 + CVDD
VDD5
Note 2
Note 3
Note 2
Note 3
Note 2
Note 3
Note 2
Note 3
1.9fXX + 2.8 2.5fXX + 5.0
currentNote 1
normal
0.8fXX + 0.8
2.4fXX + 12
30
1.0fXX
3.6fXX + 18
50
mode
VDD3 + CVDD
VDD5
In HALT
mode
IDD2
VDD3 + CVDD
VDD5
0.9fXX + 6.8 1.8fXX + 4.0
20
1.2fXX
20
40
2.3fXX
40
VDD3 + CVDD
VDD5
In IDLE
mode
IDD3
VDD3 + CVDD
VDD5
3.0
0.5
20
10
Note 3
2.0
In STOP IDD4
mode
VDD3 + CVDD
−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +110°C
Note 3
1200
3500
120
20
µA
VDD5
10
µA
Notes 1. Value in the PLL mode
2. Determine the value by calculating fXX from the operating conditions.
3. The current of the TO000 to TO005 and TO010 to TO015 pins is not included.
Remarks 1. fXX: Internal system clock frequency (MHz)
2. An example of calculating the power supply current is shown below.
• Power supply current (TYP.) of the µPD70F3116 in normal mode when fXX = 32 MHz
VDD3 + CVDD: IDD1 = 2.4fXX + 12 = 2.4 × 32 + 12 = 88.8 mA
VDD5:
IDD1 = 30 mA
23
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
Data Retention Characteristics (TA = –40 to +85°C: µPD703116, 703116(A), 70F3116, 70F3116(A),
TA = –40 to +110°C: µPD703116(A1), 70F3116(A1))
Parameter
Symbol
VDDDR
HVDDDR
IDDDR
Conditions
MIN.
1.5
TYP.
MAX.
3.6
Unit
V
Data retention voltage
STOP mode, VDD3 = VDDDR
STOP mode, VDD5 = HVDDDR
3.6
5.5
V
Data retention current
VDD3 =
VDDDR
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +110°C
20
20
10
1200
3500
120
µA
µA
µA
µs
µs
ms
HIDDDR
tRVD
VDD5 = HVDDDR
Note 1
Power supply voltage rise time
Power supply voltage fall time
200
200
0
tFVD
Power supply voltage retention
time (from STOP mode setting)
tHVD
STOP release signal input time
Data retention input voltage, high
tDREL
0
ns
V
VIHDR
Note 2
Note 3
Note 2
Note 3
0.8HVDDDR
HVDDDR
VDDDR
0.8VDDDR
V
Data retention input voltage, low
VILDR
0
0
0.2HVDDDR
0.2VDDDR
V
V
Notes 1. The current of the TO000 to TO005 and TO010 to TO015 pins is not included.
2. P00/NMI, P01/ESO0/INTP0, P02/ESO1/INTP1, P03/ADTRG0/INTP2, P04/ADTRG1/INTP3, P05/INTP4 to
P07/INTP6, P10/TIUD10/TO10, P11/TCUD10/INTP100, P12/TCLR10/INTP101, P13/TIUD11/TO11,
P14/TCUD11/INTP110, P15/TCLR11/INTP111, P20/TI2/INTP20, P21/TO21/INTP21 to
P24/TO24/INTP24, P25/TCLR2/INTP25, P26/TI3/TCLR3/INTP30, P27/TO3/INTP31, P30/RXD0,
P32/RXD1, P34/ASCK1, P35/RXD2, P37/ASCK2, P40/SI0, P42/SCK0, P43/SI1, P45/SCK1, P46/CRXD,
MODE0 to MODE2, CKSEL, RESET pins
3. CLK_DBG, SYNC, AD0_DBG to AD3_DBG pins (µPD70F3116 only)
Remark The TYP. value is a reference value for when TA = 25°C.
STOP mode setting
V
DDDR, HVDDDR
V
DD3, VDD5
t
FVD
tRVD
t
HVD
t
DREL
V
V
IHDR
RESET (input)
STOP mode release interrupt (NMI, etc.)
(released by falling edge)
IHDR
STOP mode release interrupt (NMI, etc.)
(released by rising edge)
V
ILDR
24
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
AC Characteristics (TA = –40 to +85°C: µPD703116, 703116(A), 70F3116, 70F3116(A),
TA = –40 to +110°C: µPD703116(A1), 70F3116(A1),
VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V,
output pin load capacitance: CL = 50 pF)
AC test input test points
(a) Other than (b) to (d) below
V
DD5
0.8VDD5
0.2VDD5
0.8VDD5
0.2VDD5
Test points
0 V
(b) AD0/PDL0 to AD15/PDL15, A16/PDH0 to A23/PDH7, LWR/PCT0, UWR/PCT1, PCT2, PCT3, RD/PCT4, PCT5,
ASTB/PCT6, PCT7, WAIT/PCM0, CLKOUT/PCM1, HLDAK/PCM2, HLDRQ/PCM3, PCM4, CS0/PCS0 to
CS7/PCS7 pins
V
DD5
2.2 V
0.8 V
2.2 V
0.8 V
Test points
0 V
(c) CLK_DBGNote, SYNCNote, AD0_DBG to AD3_DBGNote, RESET pins
Note µPD70F3116 only
V
DD3
0.8VDD3
0.2VDD3
0.8VDD3
0.2VDD3
Test points
0 V
(d) X1 pin
V
DD3
0.8VDD3
0.8VDD3
Test points
0.15VDD3
0.15VDD3
0 V
25
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
AC test output test points
(a) Pins other than (b) below
V
DD5
0.8VDD5
0.2VDD5
0.8VDD5
0.2VDD5
Test points
0 V
(b) AD0_DBG to AD3_DBG, TRIG_DBG pins (µPD70F3116 only)
V
DD3
0.8VDD3
0.2VDD3
0.8VDD3
Test points
0.2VDD3
0 V
Load conditions
DUT
(Device under test)
CL = 50 pF
Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration,
insert a buffer or other element to reduce the device’s load capacitance to 50 pF or lower.
26
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
(1) Clock timing (1/2)
(TA = –40 to +85°C: µPD703116, 703116(A), 70F3116, 70F3116(A),
TA = –40 to +110°C: µPD703116(A1), 70F3116(A1),
VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V,
output pin load capacitance: CL = 50 pF)
Parameter
X1 input cycle
Symbol
Conditions
MIN.
31.25
156
20
MAX.
125
250
125
250
Unit
ns
<1>
tCYX
Direct mode
Note 1
PLL mode
Direct mode
PLL mode
Direct mode
PLL mode
Direct mode
PLL mode
Direct mode
PLL mode
Direct mode
PLL mode
Note 2
ns
Note 2
ns
156
6
ns
X1 input high-level width
X1 input low-level width
X1 input rise time
<2>
<3>
<4>
<5>
−
tWXH
tWXL
tXR
ns
50
ns
6
ns
50
ns
4
ns
10
4
ns
X1 input fall time
tXF
ns
10
50
32
32
250
250
250
ns
CPU operation frequency
fXX
4
4
MHz
MHz
MHz
ns
Note 1
CLKOUT signal usedNote 3
4
CLKOUT output cycle
<6>
tCYK
Note 2
20
Note 1
31.25
31.25
0.5T – 9
0.5T – 11
ns
CLKOUT signal usedNote 3
ns
CLKOUT high-level width
CLKOUT low-level width
CLKOUT rise time
<7>
<8>
tWKH
tWKL
tKR
ns
ns
<9>
11
9
ns
CLKOUT fall time
<10>
<11>
tKF
ns
Delay time from X1↓ to CLKOUT
tDXK
Direct mode
40
ns
Notes 1. –40°C ≤ T
2. –40°C ≤ T
A
A
≤ +110°C
≤ +85°C
3. When interfacing to the external devices using the CLKOUT signal, make the internal system clock
frequency (fXX) 32 MHz or lower.
Remark T = tCYK
27
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
(1) Clock timing (2/2)
<1>
<2>
<3>
<5>
<4>
X1
(PLL mode)
<1>
<3>
<2>
<4>
<5>
X1
(direct mode)
<11>
<11>
CLKOUT (output)
<9>
<10>
<7>
<8>
<6>
(2) Output waveform (except for CLKOUT)
(TA = –40 to +85°C: µPD703116, 703116(A), 70F3116, 70F3116(A),
TA = –40 to +110°C: µPD703116(A1), 70F3116(A1),
VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V,
output pin load capacitance: CL = 50 pF)
Parameter
Output rise time
Output fall time
Symbol
<12> tOR
<13> tOF
Conditions
MIN.
MAX.
15
Unit
ns
15
ns
<13>
<12>
Signals other than
CLKOUT
28
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
(3) Reset timing
(TA = –40 to +85°C: µPD703116, 703116(A), 70F3116, 70F3116(A),
TA = –40 to +110°C: µPD703116(A1), 70F3116(A1),
VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V,
output pin load capacitance: CL = 50 pF)
Parameter
Symbol
<14> tWRSH
<15> tWRSL
Conditions
MIN.
500
MAX.
Unit
ns
RESET pin high-level width
RESET pin low-level width
At power-on and at STOP mode
release
500 + TOS
ns
Other than at power-on and at
STOP mode release
500
ns
Caution Thoroughly evaluate the oscillation stabilization time.
Remark TOS: Oscillation stabilization time
<14>
<15>
RESET (input)
29
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
(4) Multiplex bus timing
(a) CLKOUT asynchronous (TA = –40 to +85°C: µPD703116, 703116(A), 70F3116, 70F3116(A),
TA = –40 to +110°C: µPD703116(A1), 70F3116(A1),
VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V,
output pin load capacitance: CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ns
Address setup time (to ASTB↓)
Address hold time (from ASTB↓)
Address float delay time from RD↓
Data input setup time from address
<16>
tSAST
tHSTA
tFRDA
tSAID
(0.5 + wAS)T – 16
(0.5 + wAH)T – 15
<17>
<18>
<19>
ns
11
ns
(2 + w + wAS +wAH)T
– 40
ns
Data input setup time from RD ↓
<20>
tSRDID
(1 + w)T – 40
ns
ns
ns
ns
ns
ns
Delay time from ASTB↓ to RD, LWR, UWR↓
Data input hold time (from RD↑)
<21> tDSTRDWR
(0.5 + wAH)T – 15
0
<22>
<23>
tHRDID
tDRDA
Address output time from RD↑
(1 + i)T – 15
0.5T – 15
Delay time from RD, LWR, UWR ↑ to ASTB↑
Delay time from RD↑ to ASTB↓
<24> tDRDWRST
<25> tDRDST
(1.5 + i + wAS)T
– 15
RD, LWR, UWR low-level width
ASTB high-level width
<26> tWRDWRL
(1 + w)T – 22
ns
ns
ns
ns
ns
ns
<27>
<28>
<29>
<30>
<31>
tWSTH
tDWROD
tSODWR
tHWROD
tSAWT1
(1 + wAS)T – 15
Data output time from LWR, UWR↓
Data output setup time (to LWR, UWR↑)
Data output hold time (from LWR, UWR↑)
WAIT setup time (to address)
10
(1 + w)T – 25
T – 20
w ≥ 1
(1.5 + wAS +wAH)T
– 40
<32>
tSAWT2
(1.5 + w + wAS+wAH)T
– 40
ns
WAIT hold time (from address)
<33>
<34>
<35>
<36>
tHAWT1
tHAWT2
tSSTWT1
tSSTWT2
w ≥ 1
w ≥ 1
(0.5 + w + wAS+wAH)T
(1.5 + w + wAS+wAH)T
ns
ns
ns
ns
WAIT setup time (to ASTB↓)
(1 +wAH)T – 32
(1 + w +wAH)T
– 32
WAIT hold time (from ASTB↓)
<37>
<38>
<39>
<40>
<41>
<42>
<43>
<44>
tHSTWT1
tHSTWT2
tWHQH
tWHAL
w ≥ 1
(w +wAH)T
(1 + w +wAH)T
T + 10
T – 15
–12
ns
ns
ns
ns
ns
ns
ns
ns
HLDRQ high-level width
HLDAK low-level width
Delay time from address float to HLDAK↓
Delay time from HLDAK↑ to bus output↑
Delay time from HLDRQ↓ to HLDAK↓
Delay time from HLDRQ↑ to HLDAK↑
tDFHA
tDHAC
–7
tDHQHA1
tDHQHA2
2T
0.5T
1.5T + 30
Remarks 1. T = tCYK
2. w: Number of wait clocks inserted in the bus cycle
The sampling timing changes when a programmable wait is inserted.
3. i: Number of idle states inserted after the read cycle (0 or 1)
4. wAS: Number of address setup wait states (0 or 1)
5. wAH: Number of address hold wait states (0 or 1)
6. Observe at least either of the data input hold time tHKID or tHRDID
.
30
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
(b) CLKOUT synchronous (TA = –40 to +85°C: µPD703116, 703116(A), 70F3116, 70F3116(A),
TA = –40 to +110°C: µPD703116(A1), 70F3116(A1),
VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V,
output pin load capacitance: CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Delay time from CLKOUT↑ to address
Delay time from CLKOUT↑ to address float
Delay time from CLKOUT↓ to ASTB
Delay time from CLKOUT↑ to RD, LWR, UWR
Data input setup time (to CLKOUT↑)
Data input hold time (from CLKOUT↑)
Delay time from CLKOUT↑ to data output
WAIT setup time (to CLKOUT↓)
<45>
tDKA
tFKA
–7
19
<46>
<47>
<48>
<49>
<50>
<51>
<52>
<53>
<54>
<55>
<56>
<57>
–12
15
tDKST
tDKRDWR
tSIDK
–3 + wAHT
19 + wAHT
19
–5
21
5
tHKID
tDKOD
tSWTK
tHKWT
tSHQK
tHKHQ
tDKHA
tDKF
19
21
5
WAIT hold time (from CLKOUT↓)
HLDRQ setup time (to CLKOUT↓)
HLDRQ hold time (from CLKOUT↓)
Delay time from CLKOUT↑ to HLDAK
Delay time from CLKOUT↑ to address float
21
5
19
19
Remarks 1. T = tCYK
2. wAH: Number of address hold wait states (0 or 1)
3. Observe at least either of the data input hold time tHKID or tHRDID
.
31
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
(c) Read cycle (CLKOUT synchronous/asynchronous, 1 wait)
T1
T2
TW
T3
CLKOUT (output)
<45>
A16 to A23 (output)
<19>
<46>
<49> <50>
Data
Hi-Z
AD0 to AD15 (I/O)
ASTB (output)
Address
<47>
<47>
<22>
<16>
<17>
<27>
<48>
<21>
<24>
<48>
<18>
<20>
<23>
<25>
RD (output)
<26>
<52> <53>
<35> <52> <53>
<37>
<36>
<38>
WAIT (input)
<31>
<33>
<32>
<34>
Remark LWR and UWR are high level.
32
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
(d) Write cycle (CLKOUT synchronous/asynchronous, 1 wait)
T1
T2
TW
T3
CLKOUT (output)
A16 to A23 (output)
AD0 to AD15 (I/O)
<45>
<51>
Address
Data
<47>
<16>
<47>
<17>
ASTB (output)
<27>
<24>
<48>
<48>
<21>
<28>
<29>
<30>
LWR (output)
UWR (output)
<26>
<52> <53>
<35> <52> <53>
<37>
<36>
<38>
WAIT (input)
<31>
<33>
<32>
<34>
Remark RD is high level.
33
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
(e) Bus hold
TH
TH
TH
TI
CLKOUT (output)
<54>
<54> <55>
<39>
HLDRQ (input)
<56>
<56>
<43>
<44>
HLDAK (output)
A16 to A23 (output)
AD0 to AD15 (I/O)
ASTB (output)
<41>
<42>
<40>
<57>
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Data
RD (output)
LWR (output), UWR (output)
34
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
(5) Interrupt timing
(TA = –40 to +85°C: µPD703116, 703116(A), 70F3116, 70F3116(A),
TA = –40 to +110°C: µPD703116(A1), 70F3116(A1),
VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V,
output pin load capacitance: CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
500
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NMI high-level width
NMI low-level width
INTPn high-level width
<58>
tWNIH
tWNIL
tWITH
<59>
<60>
500
n = 0 to 6
500
n = 100, 101, 110, 111, 30, 31
5T + 10
500
n = 20 to 25 (when analog filter specified)
n = 20 to 25 (when digital filter specified)
n = 0 to 6
5T + 10
500
INTPn low-level width
<61>
tWITL
n = 100, 101, 110, 111, 30, 31
5T + 10
500
n = 20 to 25 (when analog filter specified)
n = 20 to 25 (when digital filter specified)
5T + 10
Remark T: Digital filter sampling clock
T can be selected by setting the following registers.
• INTP100, INTP101:
Can be selected from fXXTM10, fXXTM10/2, fXXTM10/4, and fXXTM10/8 by setting the NRC101 and NRC100
bits of the timer 10 noise elimination time select register (NRC10) (fXXTM10: clock selected with the timer
1/timer 2 clock select register (PRM02)).
• INTP110, INTP111:
Can be selected from fXXTM11, fXXTM11/2, fXXTM11/4, and fXXTM11/8 by setting the NRC111 and NRC110
bits of the timer 11 noise elimination time select register (NRC11) (fXXTM11: clock selected with the
PRM02 register).
• INTP30:
Can be selected from fXXTM3/2, fXXTM3/4, fXXTM3/8, and fXXTM3/16 by setting the NRC31 and NRC30 bits
of the timer 3 noise elimination time select register (NRC3) (fXXTM3: clock selected with the timer 3 clock
select register (PRM03)).
• INTP31:
Can be selected from fXXTM3/32, fXXTM3/64, fXXTM3/128, and fXXTM3/256 by setting the NRC33 and
NRC32 bits of the timer 3 noise elimination time select register (NRC3) (fXXTM3: clock selected with the
PRM03 register).
<58>
<59>
NMI (input)
<60>
<61>
INTPn (input)
Remark n = 0 to 6, 100, 101, 110, 111, 20 to 25, 30, 31
35
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
(6) Timer input timing
(TA = –40 to +85°C: µPD703116, 703116(A), 70F3116, 70F3116(A),
TA = –40 to +110°C: µPD703116(A1), µPD70F3116(A1),
VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V,
output pin load capacitance: CL = 50 pF)
Parameter
Symbol
tWUDH, tWUDL
Conditions
n = 10, 11
MIN.
MAX.
Unit
ns
TIUDn, TCUDn high-/low-level width
TIUDn, TCUDn input time difference
TCLRn high-/low-level width
<62>
<63>
<64>
5T + 10
2T + 10
5T + 10
tPHUD
n = 10, 11
ns
tWTCH, tWTCL
n = 10, 11, 2 (other than for
through input), 3
ns
n = 2 (for through inputNote
)
2T + 10
5T + 10
ns
ns
TIn high-/low-level width
<65>
tWTIH, tWTIL
n = 2 (other than for
through input), 3
n = 2 (for through inputNote
)
2T + 10
ns
Note When setting the timer 2 count clock/control edge select register 0 (CSE0)’s CESE1 bit to 1 and CESE0 bit to 0.
Remarks 1. T: Digital filter sampling clock
T can be selected by setting the following registers.
• When using TIUDn, TCUDn, and TCLRn (n = 10, 11), the following cycles can be selected by
setting the NRCn1 and NRCn0 bits of timer n noise elimination time select register (NRCn).
When fXX/2 is selected for the timer n basic clock: fXX/2, fXX/4, fXX/8, fXX/16
When fXX/4 is selected for the timer n basic clock: fXX/4, fXX/8, fXX/16, fXX/32
• When using TCLR2 and TI2, the following cycles can be selected by setting the PRM2 bit of the
timer 1/timer 2 clock select register (PRM02).
When fXX/2 is selected for the timer 2 basic clock: fXX/2
When fXX/4 is selected for the timer 2 basic clock: fXX/4
• When using TCLR3 and TI3, the following cycles can be selected by setting the NRC31 and NRC30
bits of timer 3 noise elimination time select register (NRC3).
When fXX is selected for the timer 3 basic clock: fXX/2, fXX/4, fXX/8, fXX/16
When fXX/2 is selected for the timer 3 basic clock: fXX/4, fXX/8, fXX/16, fXX/32
2. fXX: Internal system clock frequency
<62>
<62>
TIUDm (input)
<63>
<62>
<63>
<63>
<62>
<63>
TCUDm (input)
TCLRn (input)
<64>
<65>
<64>
<65>
TIx (input)
Remark m = 10, 11 n = 10, 11, 2, 3 x = 2, 3
36
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
(7) Timer operating frequency
(TA = –40 to +85°C: µPD703116, 703116(A), 70F3116, 70F3116(A),
TA = –40 to +110°C: µPD703116(A1), 70F3116(A1),
VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V,
output pin load capacitance: CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
40
Unit
MHz
MHz
MHz
MHz
MHz
Timer 00, 01 operating frequency
T0
–40°C ≤ TA ≤ +85°C
–40°C ≤ TA ≤ +110°C
32
Timer 10, 11 operating frequency
Timer 20, 21 operating frequency
Timer 3 operating frequency
T1
T2
T3
16
16
32
(8) CSI timing (1/2)
(a) Master mode
(TA = –40 to +85°C: µPD703116, 703116(A), 70F3116, 70F3116(A),
TA = –40 to +110°C: µPD703116(A1), 70F3116(A1),
VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V,
output pin load capacitance: CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
SCKn cycle
<66>
tCYSK1
tWSK1H
tWSK1L
tSSISK
Output
Output
Output
200
0.5tCYSK1 − 25
0.5tCYSK1 − 25
35
ns
ns
ns
ns
ns
ns
ns
SCKn high-level width
<67>
<68>
<69>
<70>
<71>
<72>
SCKn low-level width
SIn setup time (to SCKn↑)
SIn hold time (from SCKn↑)
SOn output delay time (from SCKn↓)
SOn output hold time (from SCKn↑)
tHSKSI
tDSKSO
tHSKSO
30
30
0.5tCYSK1 − 20
Remark n = 0, 1
(b) Slave mode
(TA = –40 to +85°C: µPD703116, 703116(A), 70F3116, 70F3116(A),
TA = –40 to +110°C: µPD703116(A1), 70F3116(A1),
VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V,
output pin load capacitance: CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
SCKn cycle
<66>
tCYSK1
tWSK1H
tWSK1L
tSSISK
Input
Input
Input
200
90
90
50
50
ns
ns
ns
ns
ns
ns
ns
SCKn high-level width
<67>
<68>
<69>
<70>
<71>
<72>
SCKn low-level width
SIn setup time (to SCKn↑)
SIn hold time (from SCKn↑)
SOn output delay time (from SCKn↓)
SOn output hold time (from SCKn↑)
tHSKSI
tDSKSO
tHSKSO
55
tWSK1H
Remark n = 0, 1
37
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
(8) CSI timing (2/2)
<66>
<68>
<67>
SCKn (I/O)
SIn (input)
<70>
<69>
Input data
<71>
<72>
SOn (output)
Output data
Remarks 1. The broken lines indicate high impedance.
2. n = 0, 1
38
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
(9) UART0 timing
(TA = –40 to +85°C: µPD703116, 703116(A), 70F3116, 70F3116(A),
TA = –40 to +110°C: µPD703116(A1), 70F3116(A1),
VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V,
output pin load capacitance: CL = 50 pF)
Parameter
Symbol
fBRG
Conditions
MIN.
MAX.
25
Unit
UART0 baud rate generator input
frequency
MHz
Remark fBRG (UART0 baud rate generator input frequency) can be selected from fXX, fXX/2, fXX/4, fXX/8, fXX/16,
fXX/32, fXX/64, fXX/128, fXX/256, fXX/512, fXX/1024, and fXX/2048 by setting the TPS3 to TPS0 bits of clock
select register 0 (CKSR0) (fXX: Internal system clock frequency).
39
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
(10) UART1, UART2 timing (1/2)
(a) Clocked master mode
(TA = –40 to +85°C: µPD703116, 703116(A), 70F3116, 70F3116(A),
TA = –40 to +110°C: µPD703116(A1), 70F3116(A1),
VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V,
output pin load capacitance: CL = 50 pF)
Parameter
Symbol
<73> tCYSK0
<74> tWSK0H
<75> tWSK0L
<76> tSRXSK
<77> tHSKRX
<78> tDSKTX
<79> tHSKTX
Conditions
Output
MIN.
1000
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ASCKn cycle
ASCKn high-level width
Output
k T – 20
k T – 20
1.5 T + 35
0
ASCKn low-level width
Output
RXDn setup time (to ASCKn↑)
RXDn hold time (from ASCKn↑)
TXDn output delay time (from ASCKn↓)
TXDn output hold time (from ASCKn↑)
T + 10
(k + 1)T – 20
Remarks 1. T = 2tCYK
2. k: Setting value of prescaler compare register n (PRSCMn) of UARTn
3. n = 1, 2
(b) Clocked slave mode
(TA = –40 to +85°C: µPD703116, 703116(A), 70F3116, 70F3116(A),
TA = –40 to +110°C: µPD703116(A1), 70F3116(A1),
VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V,
output pin load capacitance: CL = 50 pF)
Parameter
Symbol
<73> tCYSK0
<74> tWSK0H
<75> tWSK0L
<76> tSRXSK
<77> tHSKRX
<78> tDSKTX
<79> tHSKTX
Conditions
Input
MIN.
1000
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ASCKn cycle
ASCKn high-level width
Input
Input
4 T + 80
4 T + 80
T + 10
T + 10
ASCKn low-level width
RXDn setup time (to ASCKn↑)
RXDn hold time (from ASCKn↑)
TXDn output delay time (from ASCKn↓)
TXDn output hold time (from ASCKn↑)
2.5 T + 45
k T + 1.5 T
Remarks 1. T = 2tCYK
2. k: Setting value of PRSCMn register of UARTn
3. n = 1, 2
40
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
(10) UART1, UART2 timing (2/2)
<73>
<75>
<74>
ASCKn (I/O)
RXDn (input)
<77>
<76>
Input data
<78>
<79>
TXDn (output)
Output data
Remark n = 1, 2
41
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
(11) NBD timing (µPD70F3116 only)
(TA = 0 to +40°C, VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V,
output pin load capacitance: CL = 100 pF)
Parameter
Symbol
<80> tNDCYC
<81> tNDL
Conditions
MIN.
80
35
5
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
NBD cycle
NBD cycle low-level width
NBD data output delay time
NBD data output hold time
NBD data input setup time
NBD data input hold time
SYNC input setup time
SYNC input hold time
<82> tNDD
<83> tNDHD
<84> tNDS
<85> tNDH
<86> tNDSYS
<87> tNDSYH
tNDCYC –20
2
20
5
20
5
<80>
<81>
CLK_DBG (input)
<82>
<83>
AD0_DBG to AD3_DBG (output)
AD0_DBG to AD3_DBG (input)
SYNC (input)
<85>
<84>
<86>
<87>
42
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
A/D Converter Characteristics (TA = –40 to +85°C: µPD703116, 703116(A), 70F3116, 70F3116(A),
TA = −40 to +110°C: µPD703116(A1), 70F3116(A1),
VDD3 = CVDD = 3.0 to 3.6 V, AVDD = VDD5= 5 V 0.5 V, AVSS = VSS3 = VSS5 = CVSS = 0 V,
output pin load capacitance: CL = 50 pF)
Parameter
Symbol
Conditions
MIN.
10
TYP.
MAX.
Unit
bit
Resolution
−
−
Overall errorNote 1
5
1/2
10
LSB
LSB
µs
Quantization error
−
Conversion time
tCONV
tSAMP
−
5
Sampling time
833
ns
Zero-scale errorNote 1
Full-scale errorNote 1
3
LSB
LSB
LSB
LSB
V
−
3
Differential linearity errorNote 1
Integral linearity errorNote 1
Analog input voltage
Analog reference voltage
AVREFn input currentNote 2
AVDD power supply currentNote 2
−
3
−
5
VIAN
AVREF
AIREF
AIDD
−0.3
AVREFn + 0.3
AVREFn = AVDD
4.5
5.5
2
V
1
3
mA
mA
6
Notes 1. The quantization error ( 0.5 LSB) is not included.
2. The V850E/IA1 incorporates two A/D converters. This is the rated value for one converter.
Remarks 1. LSB: Least Significant Bit
2. n = 0, 1
43
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
3.2 Flash Memory Programming Mode (µPD70F3116 only)
Basic Characteristics (TA = 0 to 70°C (during rewrite),
TA = −40 to +85°C (except during rewrite): µPD70F3116, 70F3116(A),
TA = −40 to +110°C (except during rewrite): µPD70F3116(A1),
VDD3 = CVDD = 3.0 to 3.6 V, VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V)
Parameter
Operating frequency
VPP supply voltage
Symbol
fX
Conditions
MIN.
4
TYP.
MAX.
50
Unit
MHz
V
VPP1
During flash memory
programming
7.5
7.8
8.1
VPPL
VPPM
VPPH
VPP low-level detection
VPP, VDD3 level detection
0.8VDD3
0.65VDD3
7.5
VDD3
1.2VDD3
VDD3 + 0.3
8.1
V
V
V
VPP high-voltage level
detection
7.8
VDD3 supply current
VPP supply current
IDD1
IPP
VPP = VPP1
VPP = 7.8 V
Note 1
4.5fx
100
mA
mA
Step erase time
tER
0.398
0.99
0.4
1
0.402
40
s
Overall erase time per area
tERA
When the step erase time
s/area
= 0.4 s, Note 2
Write-back time
tWB
Note 3
1.01
300
ms
Number of write-backs per
write-back command
CWB
When the write-back time
Count/write
-back
= 1 ms, Note 4
command
Number of erase/write-backs
Step writing time
CERWB
tWT
16
22
Count
µs
Note 5
18
20
20
Overall writing time per word
tWTW
When the step writing
time = 20 µs (1 word = 4
bytes), Note 6
200
µs/word
Number of rewrites per area
CERWR
1 erase + 1 write after
100
Count/area
erase = 1 rewrite, Note 7
Notes 1. The recommended setting value of the step erase time is 0.4 s.
2. The prewrite time prior to erasure and the erase verify time (write-back time) are not included.
3. The recommended setting value of the write-back time is 1 ms.
4. Write-back is executed once by the issuance of the write-back command. Therefore, the retry count
must be the maximum value minus the number of commands issued.
5. The recommended setting value of the step writing time is 20 µs.
6. 20 µs is added to the actual writing time per word. The internal verify time during and after the writing
is not included.
7. When writing initially to shipped products, it is counted as one rewrite for both “erase to write” and
“write only”.
Example (P: Write, E: Erase)
Shipped product → P → E → P → E → P: 3 rewrites
Shipped product → E → P → E → P → E → P: 3 rewrites
Remarks 1. When the PG-FP3 is used, a time parameter required for writing/erasing by downloading
parameter files is automatically set. Do not change the settings unless otherwise specified.
2. Area 0 = 00000H to 1FFFFH, area 1 = 20000H to 3FFFFH
44
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
Serial Write Operation Characteristics (TA = 0 to 70°C, VDD3 = CVDD = 3.0 to 3.6 V,
VDD5 = 5 V 0.5 V, VSS3 = VSS5 = CVSS = 0 V)
Parameter
Symbol
<88>
Conditions
MIN.
TYP.
MAX.
Unit
µs
µs
ns
ms
µs
µs
µs
µs
µs
VDD3, VDD5↑ to VPP↑ set time
VPP↑ to RESET↑ set time
RESET↑ to VPP count start time
Count execution time
tDRPSR
tPSRRF
tRFOF
tCOUNT
tCH
10
1
<89>
<90>
<91>
<92>
<93>
<94>
<95>
<96>
VPP = 7.8 V
10T + 1500
15
VPP counter high-level width
VPP counter low-level width
VPP counter rise time
1
1
tCL
tR
1
1
VPP counter fall time
tF
VPP↓ to VDD3, VDD5↓ reset time
tPFDR
10
Remark T = tCYK
4.5 V
VDD5
0 V
<96>
<88>
3.0 V
0 V
VDD3
<88>
<96>
<91>
<90>
<93>
<92>
<94>
VPP
V
DD5
DD3
VPP
V
<95>
0 V
<89>
VDD5
RESET
(input)
0 V
45
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
4. PACKAGE DRAWING
144-PIN PLASTIC LQFP (FINE PITCH) (20x20)
A
B
108
109
73
72
detail of lead end
S
C
D
R
Q
144
1
37
36
F
M
G
H
J
I
K
P
S
L
S
N
M
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
22.0 0.2
20.0 0.2
20.0 0.2
22.0 0.2
1.25
G
H
1.25
0.22 0.05
I
0.08
J
0.5 (T.P.)
1.0 0.2
0.5 0.2
K
L
+0.03
0.17
M
−0.07
N
P
Q
0.08
1.4
0.10 0.05
+4°
3°
R
S
−3°
1.5 0.1
S144GJ-50-UEN
46
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
5. RECOMMENDED SOLDERING CONDITIONS
These products should be soldered and mounted under the following recommended conditions.
For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC sales
representative.
Table 5-1. Surface Mounting Type Soldering Conditions
µPD703116GJ-xxx-UEN:
144-pin plastic LQFP (fine pitch) (20 × 20)
µPD703116GJ(A)-xxx-UEN: 144-pin plastic LQFP (fine pitch) (20 × 20)
µPD703116GJ(A1)-xxx-UEN: 144-pin plastic LQFP (fine pitch) (20 × 20)
µPD70F3116GJ-UEN:
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
144-pin plastic LQFP (fine pitch) (20 × 20)
µPD70F3116GJ(A)-UEN:
µPD70F3116GJ(A1)-UEN:
Soldering Method
Soldering Conditions
Recommended
Condition
Symbol
Infrared reflow
VPS
Package peak temperature: 230°C, Time: 30 seconds max. (at 210°C or higher),
Count: Two times or less, Exposure limit: 3 daysNote (after that, prebake at 125°C for
10 hours)
IR30-103-2
VP15-103-2
–
Package peak temperature: 215°C, Time: 25 to 40 seconds (at 200°C or higher),
Count: Two times or less, Exposure limit: 3 daysNote (after that, prebake at 125°C for
10 to 72 hours)
Partial heating
Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together.
47
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
APPENDIX NOTES ON TARGET SYSTEM DESIGN
The following shows a diagram of the connection conditions between the in-circuit emulator option board and
conversion connector. Design your system making allowances for conditions such as the form of parts mounted on
the target system based on this configuration.
Appendix-1. 144-pin Plastic LQFP (Fine Pitch) (20 × 20)
Side view
In-circuit emulator
In-circuit emulator
IE-V850E-MC
option board
IE-703116-MC-EM1
Conversion connector
YQGUIDE
YQPACK144SD
206.26 mm
Note
NQPACK144SD
Target system
Note YQSOCKET144SDN (sold separately) can be inserted here to adjust the height (height: 3.2 mm).
Top view
IE-V850E-MC
Target system
IE-703116-MC-EM1
YQPACK144SD, NQPACK144SD,
YQGUIDE
Connection condition diagram
IE-703116-MC-EM1
Connect to IE-V850E-MC
75 mm
YQGUIDE
YQPACK144SD
NQPACK144SD
13.3 mm
31.84 mm
17.99 mm
Target system
21.58 mm
27.205 mm
48
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
[MEMO]
49
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Reference document: Electrical Characteristics for Microcomputer (U15170J)Note
Note This document number is that of the Japanese version.
V850E/IA1 and V850 Series are trademarks of NEC Corporation.
50
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
• Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
• Branch The Netherlands
Eindhoven, TheNetherlands
Tel: 040-244 58 45
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 040-244 45 80
• Branch Sweden
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China
Tel: 021-6841-1138
Fax: 11-6462-6829
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 01
Fax: 021-6841-1137
• United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Fax: 0211-65 03 327
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
• Sucursal en España
Madrid, Spain
Fax: 02-2719-5951
Tel: 091-504 27 87
Fax: 091-504 28 60
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 253-8311
• Succursale Française
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 250-3583
Fax: 01-30-67 58 99
J02.4
51
Data Sheet U15299EJ2V0DS
µPD703116, 703116(A), 703116(A1), 70F3116, 70F3116(A), 70F3116(A1)
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
License not needed:
µPD70F3116, 70F3116(A), 70F3116(A1)
The customer must judge the need for license: µPD703116, 703116(A), 703116(A1)
•
The information in this document is current as of April, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
相关型号：
UPD703116GJ(A)-XXX-UEN-A
RISC Microcontroller, 32-Bit, MROM, 50MHz, CMOS, PQFP144, 20 X 20 MM, FINE PITCH, LEAD FREE, PLASTIC, LQFP-144
NEC
UPD703116GJ(A1)-XXX-UEN
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