UPD703130 [NEC]
MOS INTEGRATED CIRCUIT; MOS集成电路
| 型号： | UPD703130 |
| 厂家： | 
NEC |
| 描述： | MOS INTEGRATED CIRCUIT |
| 文件： | 总72页 (文件大小：588K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD703130
V850E/MS2TM
32-BIT SINGLE-CHIP MICROCONTROLLER
TM
µ
The PD703130 is a member of the V850 Family of 32-bit single-chip microcontrollers designed for real-time
control operations. These microcontrollers provide on-chip features, including a 32-bit CPU, RAM, interrupt
controller, real-time pulse unit, serial interface, A/D converter, and DMA controller.
µ
The PD703130 is a ROMless version product.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850E/MS2 User’s Manual Hardware:
U14985E
V850E/MS1TM User’s Manual Architecture: U12197E
FEATURES
•
•
•
•
•
Number of instructions: 81
Minimum instruction execution time 30 ns (@ 33 MHz operation)
×
General-purpose registers 32 bits 32
Instruction set suitable for control applications
Internal memory ROM: None
RAM: 4 KB
•
•
•
•
•
•
•
Advanced on-chip interrupt controller
Real-time pulse unit suitable for control operations
Powerful serial interface (on-chip dedicated baud rate generator)
On-chip clock generator
10-bit resolution A/D converter: 4 channels
DMA controller: 4 channels
Power saving functions
APPLICATIONS
•
•
Optical storage equipment (DVD players, etc.)
System control for digital consumer equipment, etc.
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U15390EJ1V0DS00 (1st edition)
Date Published April 2001 N CP(K)
Printed in Japan
2001
©
µPD703130
ORDERING INFORMATION
Maximum Operating
Frequency
Part Number
Package
Internal ROM
None
µPD703130GC-8EU
100-pin plastic LQFP (fine pitch) (14 × 14)
33 MHz
PIN CONFIGURATION (TOP VIEW)
100-pin plastic LQFP (fine pitch) (14 × 14)
•
µPD703130GC-8EU
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
D1
D0
A8
2
A9
3
V
DD
A10
4
INTP103/DMARQ3/P07
INTP102/DMARQ2/P06
INTP101/DMARQ1/P05
INTP100/DMARQ0/P04
TCLR10/P02
A11
5
A12
6
A13
7
A14
8
A15
9
TO100/P00
A16/P60
A17/P61
A18/P62
A19/P63
A20/P64
A21/P65
A22/P66
A23/P67
HVDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS
INTP113/DMAAK3/P17
INTP112/DMAAK2/P16
INTP111/DMAAK1/P15
INTP110/DMAAK0/P14
TCLR11/P12
TO110/P10
TCLR12/P102
TO120/P100
ANI3/P73
CS0/P80
CS3/RAS3/P83
CS4/RAS4/IOWR/P84
CS5/RAS5/IORD/P85
LCAS/LWR/P90
UCAS/UWR/P91
RD/P92
ANI2/P72
ANI1/P71
ANI0/P70
AVDD
AVSS
AVREF
WE/P93
2
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
PIN NAMES
A0 to A23:
ANI0 to ANI3:
DD
Address bus
P20, P22 to P27:
P33, P34:
Port 2
Port 3
Port 5
Port 6
Port 7
Port 8
Port 9
Port 10
Port X
Analog input
AV
AV
AV
:
Analog power supply
Analog reference voltage
Analog ground
P50 to P57:
P60 to P67:
P70 to P73:
P80, P83 to P85:
P90 to P97:
P100, P102:
PX6, PX7:
REF
:
SS
:
BCYST:
CKSEL
Bus cycle start timing
Clock generator operating mode select
Clock output
:
CLKOUT:
CS0, CS3 to CS5:
Chip select
DD
CV
CV
:
Clock generator power supply
Clock generator ground
Data bus
RAS3 to RAS5:
RD:
Row address strobe
Read
SS
:
D0 to D15:
RESET:
Reset
DMAAK0 to DMAAK3
:
DMA acknowledge
RXD0, RXD1:
SCK0, SCK1:
SI0, SI1:
Receive data
Serial clock
Serial input
Serial output
DMARQ0 to DMARQ3: DMA request
HLDAK:
HLDRQ:
DD
Hold acknowledge
Hold request
SO0, SO1:
HV
:
Power supply for external pins
TCLR10 to TCLR12: Timer clear
INTP100 to INTP103, : Interrupt request from peripherals
TI13:
Timer input
INTP110 to INTP113,
INTP130
TO100, TO110:
TO120
Timer output
IORD:
I/O read strobe
TXD0, TXD1:
UCAS:
Transmit data
IOWR:
LCAS:
I/O write strobe
Upper column address strobe
Upper write strobe
Power supply for internal unit
Ground
Lower column address strobe
Lower write strobe
Mode
UWR:
DD
:
LWR:
V
SS
MODE0, MODE2:
NMI:
V
:
Non-maskable interrupt request
Output enable
WAIT:
WE:
Wait
OE:
Write enable
P00, P02, P04 to P07: Port 0
P10, P12, P14 to P17: Port 1
X1, X2:
Crystal
3
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
INTERNAL BLOCK DIAGRAM
CPU
BCU
HLDRQ
NMI
HLDAK
INTP100 to INTP103
INTC
CS0,CS3 to CS5
RAS3 to RAS5
IOWR
IORD
BCYST
Instruction
queue
INTP110 to INTP113
DRAMC
INTP130
Multiplier
(32 × 32→64)
PC
WE
RD
OE
Barrel
shifter
System
registers
PageROM
controller
TO100,TO110,
RPU
TO120
RAM
4 KB
UWR/UCAS
LWR/LCAS
WAIT
A0 to A23
D0 to D15
DMARQ0 to DMARQ3
DMAAK0 to DMAAK3
General-purpose
registers
ALU
(32 bits
× 32)
TCLR10 to TCLR12
TI13
DMAC
SIO
SO0/TXD0
SI0/RXD0
SCK0
UART0/CSI0
BRG0
SO1/TXD1
SI1/RXD1
SCK1
UART1/CSI1
BRG1
CKSEL
CLKOUT
X1
Port
CG
X2
CVDD
CVSS
ANI0 to ANI3
AVREF
ADC
AVSS
AVDD
System
MODE0,MODE2
RESET
controller
V
V
DD
SS
4
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
CONTENTS
1. DIFFERENCES BETWEEN V850E/MS2 AND V850E/MS1............................................................
6
2. PIN FUNCTIONS .............................................................................................................................
2.1 Port Pins .................................................................................................................................
2.2 Non-Port Pins.........................................................................................................................
7
7
9
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins..................................... 11
3. ELECTRICAL SPECIFICATIONS ................................................................................................... 14
4. PACKAGE DRAWING..................................................................................................................... 68
5. RECOMMENDED SOLDERING CONDITIONS............................................................................. 69
5
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
1. DIFFERENCES BETWEEN V850E/MS2 AND V850E/MS1
Product Name
V850E/MS2
V850E/MS1
µPD703100-33
None
Item
µPD703130
µPD703102-33
128 KB (mask ROM)
Internal ROM
None
Maximum
operating
frequency
33 MHz
33 MHz
Memory space
64 MB linear (only 22 MB supports on-chip
CS signal)
64 MB linear
Chip select output
Interrupt function
I/O lines
4 spaces
8 spaces
External: 10, internal: 35
Input: 5, I/O: 52
External: 25, internal: 47
Input: 9, I/O: 114
Timer
16-bit timer/event counter: 4 channels
16-bit timer: 2 channels
16-bit timer/event counter: 6 channels
16-bit timer: 2 channels
Serial interface
CSI/UART: 2 channels
CSI: 2 channels
Dedicated baud rate generator: 2 channels
CSI/UART: 2 channels
Dedicated baud rate generator: 3 channels
A/D converter
Package
Other
10-bit resolution × 4 channels
10-bit resolution × 8 channels
100-pin plastic LQFP (fine-pitch) (14 × 14)
144-pin plastic LQFP (fine-pitch) (20 × 20)
Noise tolerance and noise radiation will differ due to differences in circuit scale and mask layout.
6
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
2. PIN FUNCTIONS
2.1 Port Pins
(1/2)
Pin Name
P00
I/O
I/O
Function
Alternate Function
Port 0
TO100
6-bit I/O port
P02
P04
P05
P06
P07
P10
P12
P14
P15
P16
P17
P20
P22
P23
P24
P25
P26
P27
P33
P34
TCLR10
Input/output can be specified in 1-bit units.
INTP100/DMARQ0
INTP101/DMARQ1
INTP102/DMARQ2
INTP103/DMARQ3
TO110
I/O
Port 1
6-bit I/O port
TCLR11
Input/output can be specified in 1-bit units.
INTP110/DMAAK0
INTP111/DMAAK1
INTP112/DMAAK2
INTP113/DMAAK3
NMI
Input
I/O
Port 2
P20 is an input only port.
TXD0/SO0
When a valid edge is input, this pin operates as NMI input. Also, bit 0
of the P2 register indicates the NMI input status.
P22 to P27 are 6-bit I/O port.
RXD0/SI0
SCK0
Input/output can be specified in 1-bit units.
TXD1/SO1
RXD1/SI1
SCK1
I/O
I/O
I/O
Port 3
TI13
2-bit I/O port
INTP130
Input/output can be specified in 1-bit units.
P50 to P57
P60 to P67
P70 to P73
Port 5
D8 to D15
8-bit I/O port
Input/output can be specified in 1-bit units.
Port 6
A16 to A23
ANI0 to ANI3
8-bit I/O port
Input/output can be specified in 1-bit units.
Input
I/O
Port 7
4-bit input only port
P80
P83
P84
P85
Port 8
CS0
4-bit I/O port
CS3/RAS3
Input/output can be specified in 1-bit units.
CS4/RAS4/IOWR
CS5/RAS5/IORD
7
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(2/2)
Pin Name
P90
I/O
I/O
Function
Alternate Function
Port 9
LCAS/LWR
UCAS/UWR
RD
8-bit I/O port
P91
P92
P93
P94
P95
P96
P97
P100
P102
Input/output can be specified in 1-bit units.
WE
BCYST
OE
HLDAK
HLDRQ
TO120
TCLR12
I/O
I/O
Port 10
2-bit I/O port
Input/output can be specified in 1-bit units.
PX6
PX7
Port X
WAIT
2-bit I/O port
CLKOUT
Input/output can be specified in 1-bit units.
8
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
2.2 Non-Port Pins
(1/2)
Pin Name
TO100
I/O
Function
Pulse signal output for timers 10 to 12
Alternate Function
Output
P00
TO110
P10
TO120
P100
TCLR10
TCLR11
TCLR12
TI13
Input
External clear signal input for timers 10 to 12
P02
P12
P102
Input
Input
External count clock input for timer 13
P33
INTP100
INTP101
INTP102
INTP103
INTP110
INTP111
INTP112
INTP113
INTP130
External maskable interrupt request input, shared as external capture
trigger input for timer 10
P04/DMARQ0
P05/DMARQ1
P06/DMARQ2
P07/DMARQ3
P14/DMAAK0
P15/DMAAK1
P16/DMAAK2
P17/DMAAK3
P34
Input
External maskable interrupt request input, shared as external capture
trigger input for timer 11
Input
External maskable interrupt request input, shared as external capture
trigger input for timer 13
SO0
Output
Serial transmit data output (3-wire) for CSI0 and CSI1
Serial receive data input (3-wire) for CSI0 and CSI1
Serial clock I/O (3-wire) for CSI0 and CSI1
Serial transmit data output for UART0 and UART1
Serial receive data input for UART0 and UART1
16-bit data bus for external memory
P22/TXD0
P25/TXD1
P23/RXD0
P26/RXD1
P24
SO1
SI0
Input
I/O
SI1
SCK0
SCK1
TXD0
TXD1
RXD0
RXD1
D0 to D7
D8 to D15
A0 to A15
A16 to A23
LWR
P27
Output
Input
I/O
P22/SO0
P25/SO1
P23/SI0
P26/SI1
–
P50 to P57
–
Output
24-bit address bus for external memory
P60 to P67
P90/LCAS
P91/UCAS
P92
Output
Output
Output
Output
Output
Lower byte write-enable signal output for external data bus
Higher byte write-enable signal output for external data bus
Read strobe signal output for external data bus
Write enable signal output for DRAM
UWR
RD
WE
P93
OE
Output enable signal output for DRAM
P95
9
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(2/2)
Pin Name
LCAS
I/O
Function
Alternate Function
Output
Output
Output
Column address strobe signal output for DRAM’s lower data
Column address strobe signal output for DRAM’s higher data
Row address strobe signal output for DRAM
P90/LWR
UCAS
RAS3
RAS4
RAS5
BCYST
CS0
P91/UWR
P83/CS3
P84/CS4/IOWR
P85/CS5/IORD
P94
Output
Output
Strobe signal output indicating start of bus cycle
Chip select signal output
P80
CS3
P83/RAS3
P84/RAS4/IOWR
P85/RAS5/IORD
PX6
CS4
CS5
WAIT
IOWR
IORD
Input
Output
Output
Input
Control signal input for inserting waits in bus cycle
DMA write strobe signal output
P84/RAS4/CS4
P85/RAS5/CS5
DMA read strobe signal output
DMARQ0 to
DMARQ3
DMA request signal input
P04/INTP100 to
P07/INTP103
DMAAK0 to
DMAAK3
Output
DMA acknowledge signal output
P14/INTP110 to
P17/INTP113
HLDAK
HLDRQ
ANI0 to ANI3
NMI
Output
Input
Input
Input
Output
Input
Bus hold acknowledge output
Bus hold request input
P96
P97
Analog input to A/D converter
Non-maskable interrupt request input
System clock output
P70 to P73
P20
PX7
–
CLKOUT
CKSEL
Input for specifying clock generator’s operation mode
Specify operation modes
MODE0,
MODE2
Input
–
RESET
X1
Input
System reset input
–
–
–
–
–
–
–
–
–
–
–
Input
Connecting resonator for system clock. Input is via X1 when using an
external clock.
X2
–
AVREF
AVDD
AVSS
CVDD
CVSS
VDD
Input
Reference voltage input for A/D converter
Positive power supply for A/D converter
Ground potential for A/D converter
–
–
–
–
–
–
–
Positive power supply for dedicated clock generator
Ground potential for dedicated clock generator
Positive power supply (power supply for internal units)
Positive power supply (power supply for external pins)
Ground potential
HVDD
VSS
10
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-1 shows the I/O circuit type of each pin and recommended connection of unused pins. Figure 2-1 shows
the various circuit types using partially abridged diagrams.
DD
SS
Ω
When connecting to V or V via a resistor, a resistance value in the range of 1 to 10 k is recommended.
Table 2-1. I/O Circuit Type of Each Pin and Recommended Connection of Unused Pins (1/2)
Pin
I/O Circuit Type
5
Recommended Connection of Unused Pins
P00/TO100
Input:
Independently connect to HVDD or VSS via a resistor
Output: Leave open
P02/TCLR10
P04/INTP100/DMARQ0 to
P07/INTP103/DMARQ3
P10/TO110
P12/TCLR11
P14/INTP110/DMAAK0 to
P17/INTP113/DMAAK3
P20/NMI
2
5
Connect directly to VSS
P22/TXD0/SO0
P23/RXD0/SI0
P24/SCK0
Input:
Independently connect to HVDD or VSS via a resistor
Output: Leave open
P25/TXD1/SO1
P26/RXD1/SI1
P27/SCK1
P33/TI13
P34/INTP130
P50/D8 to P57/D15
P60/A16 to P67/A23
P70/ANI0 to P73/ANI3
P80/CS0, to P83/CS3/RAS3
9
5
Connect directly to VSS
Input:
Independently connect to HVDD or VSS via a resistor
Output: Leave open
P84/CS4/RAS4/IOWR,
P85/CS5/RAS5/IORD
P90/LCAS/LWR
P91/UCAS/UWR
P92/RD
P93/WE
P94/BCYST
P95/OE
P96/HLDAK
P97/HLDRQ
P100/TO120
P102/TCLR12
11
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
Table 2-1. I/O Circuit Type of Each Pin and Recommended Connection of Unused Pins (2/2)
Pin
I/O Circuit Type
5
Recommended Connection of Unused Pins
PX6/WAIT
PX7/CLKOUT
A0 to A15
D0 to D7
CKSEL
Input:
Independently connect to HVDD or VSS via a resistor
Output: Leave open
4
5
1
2
–
RESET
MODE0, MODE2
AVREF, AVSS
AVDD
–
–
Connect directly to VSS
Connect directly to HVDD
12
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
Figure 2-1. Pin I/O Circuits
Type 1
Type 5
V
DD
V
DD
Data
P-ch
IN/OUT
P-ch
IN
Output
disable
N-ch
N-ch
Input
enable
Type 2
Type 9
P-ch
Comparator
IN
+
–
IN
N-ch
V
REF (threshold voltage)
Input enable
Schmitt-triggered input with hysteresis characteristics
Type 4
VDD
Data
P-ch
OUT
Output
disable
N-ch
Push-pull output with possible high-impedance output
(P-ch, N-ch both off)
Caution Replace VDD by HVDD when referencing the circuit diagrams shown above.
13
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
3. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Symbol
VDD
Condition
Rating
Unit
V
Power supply voltage
VDD pin
−0.5 to +4.6
−0.5 to +7.0
−0.5 to +4.6
−0.5 to +0.5
HVDD
CVDD
CVSS
AVDD
AVSS
VI
HVDD pin, HVDD ≥ VDD
CVDD pin
V
V
CVSS pin
V
−0.5 to HVDD + 0.5Note
AVDD pin
V
V
AVSS pin
−0.5 to +0.5
−0.5 to HVDD + 0.5Note
−0.5 to VDD + 1.0Note
4.0
Input voltage
Except X1 pin
X1, VDD = 3.0 to 3.6 V
1 pin
V
Clock input voltage
Output current, low
VK
V
IOL
mA
mA
mA
mA
V
Total of all pins
1 pin
100
Output current, high
IOH
−4.0
Total of all pins
HVDD = 5.0 V 10%
−100
−0.5 to HVDD + 0.5Note
−0.5 to HVDD + 0.5Note
−0.5 to AVDD + 0.5Note
−0.5 to HVDD + 0.5Note
−0.5 to AVDD + 0.5Note
−40 to +85
Output voltage
VO
V
Analog input voltage
IAN
P70/ANI0 to P73
pins
AVDD > HVDD
V
HVDD ≥ AVDD
V
A/D converter reference input
voltage
AV
REF
AVDD > HVDD
V
HVDD ≥ AVDD
V
Operating ambient temperature
Storage temperature
TA
°C
°C
Tstg
−60 to +150
Note
Be sure not to exceed the absolute maximum ratings (MAX. value) of the each power supply voltage.
Cautions 1. Do not make direct connections of the output (or input/output) pins of the IC product with
each other, and also avoid direct connections to VDD, VCC, or GND. However, the open drain
pins or the open collector pins can be directly connected to each other. A direct connection
can also be made for an external circuit designed with timing specifications that prevent
conflicting output from pins subject to a high-impedance state.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions shown below for DC characteristics and AC characteristics are
within the range for normal operation and quality assurance.
14
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
Capacitance (TA = 25°C, VDD = HVDD = CVDD = VSS = 0 V)
Parameter
Input capacitance
Symbol
Condition
MIN.
TYP.
MAX.
15
Unit
pF
I
C
c
f = 1 MHz
Unmeasured pins returned to 0 V.
IO
C
I/O capacitance
15
pF
O
C
Output capacitance
15
pF
Operating Conditions
Operation Mode
Internal Operating Clock Frequency (fX)
Operating Ambient
Power Supply Voltage
A
DD
DD
)
Temperature (T )
(V , HV
DD
V = 3.0 to 3.6 V,
Direct mode
10 to 33 MHzNote 1
20 to 33 MHz Note 3
−40 to +85°C
−40 to +85°C
DD
HV = 5.0 V 10%
PLL modeNote 2
Notes 1.
2.
Set the input clock frequency used in direct mode to 20 to 66 MHz.
The internal operating clock frequency in PLL mode is the value for 5 operation. When used for 1 or
1/2× operation as set by the CKDIVn (n = 0, 1) bit of the CKC register, operation at a frequency of 20
MHz or less is possible.
×
×
3.
Set the input clock frequency used in PLL mode to 4.0 to 6.6 MHz.
15
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
Recommended Oscillator
(a) Ceramic resonator
(i) Murata Mfg. Co., Ltd. (TA = −40 to +85°C)
X1
X2
Rd
C1
C2
Oscillation
Stabilization
Time (MAX.)
TOST (ms)
Manu-
Part Number
Oscillation Recommended Circuit Constant
Oscillation Voltage
Range
facturer
Frequency
fXX (MHz)
C1 (pF) C2 (pF)
Rd (kΩ) MIN. (V)
MAX. (V)
Murata
Mfg.
CSTS400MG06Note
4.0
On-chip
On-chip
0
3.0
3.6
0.6
(CSTLS4M00G56-B0)
CSTCR4M00G55-R0
4.0
5.0
On-chip
On-chip
On-chip
On-chip
0
0
3.0
3.0
3.6
3.6
0.6
0.6
CSTS0500MG06Note
(CSTLS5M00G56-B0)
CSTCR5M00G55-R0
5.0
6.6
On-chip
On-chip
On-chip
On-chip
0
0
3.0
3.0
3.6
3.6
0.6
0.6
CSTS066MG06Note
(CSTLS6M60G56-B0)
CSTCR6M60G55-R0
6.6
On-chip
On-chip
0
3.0
3.6
0.6
Note
The part number will be changed to the part number in the parentheses from June 2001.
Cautions 1. Connect the oscillator as close to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area enclosed by broken lines.
3. Sufficiently evaluate the matching between the µPD703130 and the resonator.
16
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(ii) TDK (TA = −40 to +85°C)
X1
X2
Rd
C1
C2
Oscillation
Frequency
fXX (MHz)
Manu-
Part Number
Recommended Circuit Constant
Oscillation
Oscillation
facturer
Voltage Range
Stabilization Time
(MAX.) TOST (ms)
C1 (pF)
C2 (pF)
On-chip
On-chip
On-chip
Rd (kΩ)
MIN. (V) MAX. (V)
TDK
FCR4.0MC5
FCR5.0MC5
FCR6.0MC5
4.0
5.0
6.0
On-chip
On-chip
On-chip
0
0
0
3.0
3.0
3.0
3.6
3.6
3.6
0.73
0.68
0.58
Cautions 1. Connect the oscillator as closely to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area enclosed by broken lines.
3. Sufficiently evaluate the matching between the µPD703130 and the resonator.
(iii) Kyocera Corporation (TA = −20 to +80°C)
X1
X2
Rd
C1
C2
Oscillation
Frequency
fXX (MHz)
Type
Part Number
Recommended Circuit Constant
Oscillation
Oscillation
Voltage Range
Stabilization Time
(MAX.) TOST (ms)
C1 (pF)
On-chip
On-chip
On-chip
On-chip
On-chip
On-chip
C2 (pF)
On-chip
On-chip
On-chip
On-chip
On-chip
On-chip
Rd (kΩ)
MIN. (V) MAX. (V)
Lead
KBR-4.0MKC
KBR-5.0MKC
KBR-6.0MKC
PBRC4.00HR
PBRC5.00HR
PBRC6.00HR
4.0
5.0
6.0
4.0
5.0
6.0
0
0
0
0
0
0
3.0
3.0
3.0
3.0
3.0
3.0
3.6
3.6
3.6
3.6
3.6
3.6
0.80
0.70
0.76
0.80
0.70
0.76
SMD
Cautions 1. Connect the oscillator as close to the X1 and X2 pins as possible.
2. Do not wire any other signal lines in the area enclosed by broken lines.
3. Sufficiently evaluate the matching between the µPD703130 and the resonator.
17
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(b) External clock input (TA = –40 to +85°C)
X1
X2
Open
External clock
Caution Input CMOS-level voltage to the X1 pin.
18
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
DC Characteristics (TA = –40 to +85°C, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 10%, VSS = 0 V)
Parameter
Symbol
VIH
Condition
Except Note 1
MIN.
2.2
TYP.
MAX.
HVDD + 0.3
HVDD + 0.3
+0.8
Unit
V
Input voltage, high
Note 1
0.8HVDD
−0.5
V
Input voltage, low
VIL
Except Note 1 and Note 2
Note 1
V
−0.5
0.2HVDD
VDD + 0.3
0.15VDD
V
Clock input voltage, high
Clock input voltage, low
VXH
VXL
X1 pin
0.8VDD
−0.3
V
X1 pin
V
Schmitt-triggered input
threshold voltage
HVT+
Note 1, rising edge
Note 1, falling edge
IOH = −2.5 mA
IOH = −100 µA
IOL = 2.5 mA
3.0
2.0
V
−
HVT
V
Output voltage, high
VOH
0.7HVDD
V
HVDD − 0.4
V
Output voltage, low
VOL
ILIH
0.45
10
V
Input leakage current, high
Input leakage current, low
Output leakage current, high
Output leakage current, low
V
V
I = HVDD, except Note 2
I = 0 V, except Note 2
µA
µA
µA
µA
mA
mA
mA
mA
mA
µA
µA
µA
ILIL
−10
ILOH
ILOL
IDD1
VO = HVDD
VO = 0 V
10
−10
Power supply
current
Normal
mode
VDD + CVDD
HVDD
2.0 × fx
1.5 × fx
1.4 × fx
0.7 × fx
1.4
3.0 × fx
2.5 × fx
1.8 × fx
1.2 × fx
2.5
HALT mode
IDLE mode
IDD2
IDD3
IDD4
VDD + CVDD
HVDD
VDD + CVDD
HVDD
20
100
STOP
mode
VDD + CVDD
HVDD
20
100
10
50
Notes 1. P20/NMI, MODE0, MODE2, CKSEL, RESET
2. When the P70/ANI0 to P73/ANI3 pins are used as analog input.
Remarks 1. TYP. values are reference values for when TA = 25°C, VDD = CVDD = 3.3 V, and HVDD = 5.0 V.
2. Direct mode: fX = 10 to 33 MHz
PLL mode: fX = 20 to 33 MHz
3. The unit for fX is MHz.
19
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
Data Hold Characteristics (TA = –40 to +85°C)
Parameter
Data hold voltage
Symbol
Condition
MIN.
1.5
TYP.
30
MAX.
3.6
Unit
V
DDDR
DD
DDDR
V
STOP mode, V = V
DDDR
DDDR
HV
STOP mode,
V
5.5
V
DD
DDDR
HV = HV
DDDR
DD
DDDR
µ
A
Data hold current
I
V
= V
150
RVD
µ
s
Power supply voltage rise
time
t
200
FVD
HVD
µ
Power supply voltage fall time
t
200
0
s
Power supply voltage hold
time (from STOP mode
setting)
t
ms
DREL
IHDR
STOP mode release signal
input time
t
0
ns
V
DDDR
DDDR
HV
Data hold input voltage, high
V
V
P20/NMI, MODE0, MODE2,
CKSEL, RESET
0.8HV
ILDR
DDDR
Data hold input voltage, low
P20/NMI, MODE0, MODE2,
CKSEL, RESET
0
0.2HV
V
Remark
A
°
TYP. values are reference values for when T = 25 C.
STOP mode setting
3.0 V
VDDDR
VDD
tFVD
tRVD
tHVD
tDREL
HVDD
VIHDR
RESET (Input)
NMI (Input)
VIHDR
(Released by falling edge)
NMI (Input)
(Released by rising edge)
VILDR
20
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
AC Characteristics(TA = –40 to +85°C, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 10%, VSS = 0 V, output pin load
capacitance: CL = 50 pF)
AC Test Input Test Points
(a) P20/NMI, MODE0, MODE2, CKSEL, RESET
HVDD
0.8HVDD
0.2HVDD
0.8HVDD
0.2HVDD
Test
points
Input signal
0 V
(b) Pins other than those listed in (a) above
2.4 V
2.2 V
0.8 V
2.2 V
0.8 V
Test
points
Input signal
0.4 V
AC Test Output Test Points
2.4 V
2.4 V
0.8 V
Test
points
Output signal
0.8 V
Load Condition
DUT
(Device under test)
CL = 50 pF
Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration,
insert a buffer or other element to reduce the device's load capacitance 50 pF.
21
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(1) Clock timing
Parameter
Symbol
<1>
Condition
Direct mode
MIN.
15
150
5
MAX.
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
X1 input cycle
tCYX
tWXH
tWXL
tXR
PLL mode
Direct mode
PLL mode
Direct mode
PLL mode
Direct mode
PLL mode
Direct mode
PLL mode
250
X1 input high-level width
X1 input low-level width
X1 input rise time
X1 input fall time
<2>
<3>
<4>
<5>
50
5
50
4
10
4
tXF
10
100
CLKOUT output cycle
CLKOUT high-level width
CLKOUT low-level width
CLKOUT rise time
<6>
<7>
<8>
<9>
<10>
tCYK
tWKH
tWKL
tKR
30
0.5T – 7
0.5T – 4
5
5
CLKOUT fall time
tKF
Remark
CYK
T = t
<1>
<2>
<3>
<4>
<5>
X1
(PLL mode)
<1>
<3>
<2>
<4>
X1
(Direct mode)
<5>
CLKOUT (Output)
<9>
<10>
<7>
<8>
<6>
22
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(2) Output waveform (other than X1, CLKOUT)
Parameter
Output rise time
Output fall time
Symbol
<12> tOR
<13> tOF
Condition
MIN.
MAX.
10
Unit
ns
10
ns
<12>
<13>
Signals other than X1, CLKOUT
(3) Reset timing
Parameter
RESET high-level width
RESET low-level width
Symbol
Condition
MIN.
MAX.
Unit
ns
<14>
<15>
tWRSH
500
WRSL
When power supply is on, and
STOP mode has been released
500 + T
OS
ns
t
Other than when power supply is
on, and STOP mode has been
released
500
ns
Remark
OS
T
: Oscillation stabilization time
<14>
<15>
RESET (Input)
23
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(4) SRAM, external ROM, or external I/O access timing
(a) Access timing (SRAM, external ROM, or external I/O) (1/2)
Parameter
Symbol
<16> tDKA
Condition
MIN.
2
MAX.
10
Unit
ns
Address, CSn output delay time (from
CLKOUT ↓)
Address, CSn output hold time (from
<17>
<18>
<19>
<20>
<21>
<22>
<23>
tHKA
2
2
2
2
2
2
2
10
14
14
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
CLKOUT ↓)
RD, IORD ↓ delay time
(from CLKOUT ↑)
tDKRDL
tHKRDH
tDKWRL
tHKWRH
tDKBSL
tHKBSH
RD, IORD ↑ delay time
(from CLKOUT ↑)
UWR, LWR, IOWR ↓ delay time (from
CLKOUT ↑)
UWR, LWR, IOWR ↑ delay time (from
CLKOUT ↑)
BCYST ↓ delay time (from CLKOUT
↓)
BCYST ↑ delay time (from CLKOUT
↓)
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
<24>
<25>
<26>
tSWK
tHKW
tSKID
15
2
ns
ns
ns
Data input setup time
18
(to CLKOUT ↑)
Data input hold time
<27>
<28>
<29>
tHKID
tDKOD
tHKOD
2
2
2
ns
ns
ns
(from CLKOUT ↑)
Data output delay time
10
10
(from CLKOUT ↓)
Data output hold time
(from CLKOUT ↓)
Remarks 1.
2.
HKID
HRDID
Maintain at least one of the data input hold times t
n = 0, 3 to 5
and t
.
24
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(a) Access timing (SRAM, external ROM, or external I/O) (2/2)
T1
TW
T2
CLKOUT (Output)
<16>
<22>
<17>
A0 to A23 (Output)
CSn (Output)
<23>
BCYST (Output)
<18>
<20>
<19>
RD, IORD (Output)
[Read time]
<21>
UWR, LWR, IOWR (Output)
[Write time]
<26>
<27>
D0 to D15 (I/O)
[Read time]
<28>
<29>
D0 to D15 (I/O)
[Write time]
<25>
<24>
<25>
<24>
WAIT (Input)
Remarks 1.
This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero.
2.
3.
The broken lines indicate high impedance.
n = 0, 3 to 5
25
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(b) Read timing (SRAM, external ROM, or external I/O) (1/2)
Parameter
Symbol
<30>
Condition
MIN.
MAX.
Unit
Data input setup time (to address)
Data input setup time (to RD)
RD, IORD low-level width
tSAID
tSRDID
tWRDL
tWRDH
tDARD
(1.5 + wD + w)T – 28
(1 + wD + w)T – 32
ns
ns
ns
ns
ns
<31>
<32>
<33>
<34>
(1 + wD + w)T – 10
T – 10
RD, IORD high-level width
Delay time from address, CSn to RD,
0.5T – 10
IORD ↓
Delay time from RD, IORD ↑ to
<35>
tDRDA
(0.5 + i)T – 10
ns
address
Data input hold time (from RD, IORD )
↑
<36>
<37>
tHRDID
0
ns
ns
Delay time from RD, IORD ↑ to data
tDRDOD
(0.5 + i)T – 10
output
Note
Note
Note
WAIT setup time (to address)
WAIT setup time (to BCYST ↓)
WAIT hold time (from BCYST ↑)
<38>
<39>
<40>
tSAW
tSBSW
tHBSW
T – 25
T – 25
ns
ns
ns
0
Note
For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1.
CYK
T = t
2.
3.
4.
5.
6.
w: The number of waits due to WAIT.
D
w : The number of waits due to the DWC1 and DWC2 registers.
i: The number of idle states that are inserted when a write cycle follows a read cycle.
HKID
HRDID
Maintain at least one of the data input hold times, t
n = 0, 3 to 5
or t
.
26
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(b) Read timing (SRAM, external ROM, or external I/O) (2/2)
T1
TW
T2
CLKOUT (Output)
A0 to A23 (Output)
CSn (Output)
UWR, LWR, IOWR (Output)
<33>
<32>
<35>
<37>
RD, IORD (Output)
<34>
<31>
<30>
<36>
D0 to D15 (I/O)
<38>
WAIT (Input)
<39>
<40>
BCYST (Output)
Remarks 1.
This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero.
2.
3.
The broken lines indicate high impedance.
n = 0, 3 to 5
27
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(c) Write timing (SRAM, external ROM, or external I/O) (1/2)
Parameter
Symbol
<38>
Condition
Note
MIN.
MAX.
T – 25
T – 25
Unit
ns
WAIT setup time (to address)
WAIT setup time (to BCYST ↓)
WAIT hold time (from BCYST ↑)
tSAW
tSBSW
tHBSW
tDAWR
Note
<39>
<40>
<41>
ns
Note
0
ns
Delay time from address, CSn to
0.5T – 10
ns
UWR, LWR, IOWR ↓
D
Address setup time (to UWR, LWR,
<42>
<43>
tSAWR
(1.5 + w + w)T – 10
ns
ns
IOWR ↑)
Delay time from UWR, LWR, IOWR ↑
to address
tDWRA
0.5T – 10
T – 10
UWR, LWR, IOWR high-level width
UWR, LWR, IOWR low-level width
<44>
<45>
<46>
tWWRH
tWWRL
tSODWR
ns
ns
ns
D
(1 + w + w)T – 10
D
Data output setup time
(1.5 + w + w)T – 10
(to UWR, LWR, IOWR ↑)
Data output hold time
<47>
tHWROD
0.5T – 10
ns
(from UWR, LWR, IOWR ↑)
Note
For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1.
CYK
T = t
2.
3.
4.
w: The number of waits due to WAIT.
D
w : The number of waits due to the DWC1 and DWC2 registers.
n = 0, 3 to 5
28
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(c) Write timing (SRAM, external ROM, or external I/O) (2/2)
T1
TW
T2
CLKOUT (Output)
A0 to A23 (Output)
CSn (Output)
RD, IORD (Output)
<42>
<43>
<41>
<44>
<45>
UWR, LWR, IOWR (Output)
<46>
<47>
D0 to D15 (I/O)
<38>
WAIT (Input)
<39>
<40>
BCYST (Output)
Remarks 1.
This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero.
2.
3.
The broken lines indicate high impedance.
n = 0, 3 to 5
29
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(d) DMA flyby transfer timing (SRAM → external I/O transfer) (1/2)
Parameter
Symbol
<24> tSWK
tHKW
Condition
MIN.
15
MAX.
Unit
ns
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
RD low-level width
<25>
<32>
2
ns
tWRDL
(1 + w
D
+ w
F
+ w)
T
ns
–
10
RD high-level width
<33>
<34>
<35>
<37>
<38>
<39>
<40>
<41>
<42>
<43>
<44>
<45>
<48>
tWRDH
tDARD
tDRDA
T – 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Delay time from address, CSn to RD ↓
Delay time from RD ↑ to address
Delay time from RD ↑ to data output
WAIT setup time (to address)
WAIT setup time (to BCYST ↓)
WAIT hold time (from BCYST ↑)
Delay time from address to IOWR ↓
Address setup time (to IOWR ↑)
Delay time from IOWR ↑ to address
IOWR high-level width
0.5T – 10
(0.5 + i)T – 10
(0.5 + i)T – 10
tDRDOD
tSAW
Note
Note
Note
T – 25
T – 25
tSBSW
tHBSW
tDAWR
tSAWR
tDWRA
tWWRH
tWWRL
tDWRRD
0
0.5T – 10
D
(1.5 + w + w)T – 10
0.5T – 10
T – 10
D
IOWR low-level width
(1 + w + w)T – 10
Delay time from IOWR ↑ to RD ↑
wF = 0
wF = 1
0
T – 10
Delay time from DMAAKm ↓ to IOWR ↓ <49>
Delay time from IOWR ↑ to DMAAKm ↑ <50>
tDDAWR
tDWRDA
0.5T – 10
(0.5 + wF)T – 10
Note
For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1.
CYK
T = t
2.
3.
4.
5.
6.
w: The number of waits due to WAIT.
D
w : The number of waits due to the DWC1 and DWC2 registers.
F
w : The number of waits that are inserted for a source-side access during a DMA flyby transfer.
i: The number of idle states that are inserted when a write cycle follows a read cycle.
n = 0, 3 to 5, m = 0 to 3
30
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(d) DMA flyby transfer timing (SRAM → external I/O transfer) (2/2)
T1
TW
T2
CLKOUT (Output)
A0 to A23 (Output)
CSn (Output)
<33>
<32>
<35>
RD (Output)
UWR, LWR (Output)
DMAAKm (Output)
IORD (Output)
<34>
<48>
<49>
<41>
<50>
<43>
<42>
<45>
<44>
IOWR (Output)
<37>
D0 to D15 (I/O)
WAIT (Input)
<38>
<24>
<25>
<24>
<25>
<40>
<39>
BCYST (Output)
Remarks 1.
F
This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero and w = 0.
2.
3.
The broken lines indicate high impedance.
n = 0, 3 to 5, m = 0 to 3
31
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(e) DMA flyby transfer timing (external I/O → SRAM transfer) (1/2)
Parameter
Symbol
<24> tSWK
tHKW
Condition
MIN.
15
MAX.
Unit
ns
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
IORD low-level width
<25>
<32>
2
ns
tWRDL
(1 + wD + wF + w)T
– 10
ns
IORD high-level width
<33>
<34>
tWRDH
tDARD
T – 10
ns
ns
Delay time from address, CSn to
0.5T – 10
IORD ↓
Delay time from IORD ↑ to address
Delay time from IORD ↑ to data output
WAIT setup time (to address)
<35>
<37>
<38>
<39>
<40>
<41>
tDRDA
tDRDOD
tSAW
(0.5 + i)T – 10
(0.5 + i)T – 10
ns
ns
ns
ns
ns
ns
Note
Note
Note
T – 25
T – 25
WAIT setup time (to BCYST ↓)
WAIT hold time (from BCYST ↑)
tSBSW
tHBSW
tDAWR
0
Delay time from address to UWR,
0.5T – 10
LWR ↓
D
Address setup time (to UWR, LWR ↑)
<42>
<43>
tSAWR
tDWRA
(1.5 + w + w)T – 10
ns
ns
Delay time from UWR, LWR to
address
0.5T – 10
UWR, LWR high-level width
UWR, LWR low-level width
<44>
<45>
tWWRH
tWWRL
tDWRRD
T – 10
ns
ns
ns
ns
ns
ns
D
(1 + w + w)T – 10
Delay time from UWR, LWR↑ to IORD ↑ <48>
wF = 0
wF = 1
0
T – 10
Delay time from DMAAKm ↓ to IORD ↓
Delay time from IORD ↑ to DMAAKm ↑
<51>
<52>
tDDARD
tDRDDA
0.5T – 10
0.5T – 10
Note
For first WAIT sampling when the number of waits due to the DWC1 and DWC2 registers is zero.
Remarks 1.
CYK
T = t
2.
3.
4.
5.
6.
w: The number of waits due to WAIT.
D
w : The number of waits due to the DWC1 and DWC2 registers.
F
w : The number of waits that are inserted for a source-side access during a DMA flyby transfer.
i: The number of idle states that are inserted when a write cycle follows a read cycle.
n = 0, 3 to 5, m = 0 to 3
32
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(e) DMA flyby transfer timing (external I/O → SRAM transfer) (2/2)
T1
TW
T2
CLKOUT (Output)
A0 to A23 (Output)
CSn (Output)
<42>
<45>
<43>
<41>
<44>
UWR, LWR (Output)
<48>
RD (Output)
<51>
<52>
DMAAKm (Output)
IOWR (Output)
IORD (Output)
D0 to D15 (I/O)
WAIT (Input)
<34>
<33>
<32>
<35>
<37>
<38>
<24>
<25>
<24>
<25>
<40>
<39>
BCYST (Output)
Remarks 1.
F
This is the timing when the number of waits due to the DWC1 and DWC2 registers is zero and w = 0.
2.
3.
The broken lines indicate high impedance.
n = 0, 3 to 5, m = 0 to 3
33
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(5) Page ROM access timing (1/2)
Parameter
Symbol
<24>
Condition
MIN.
15
2
MAX.
Unit
ns
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
tSWK
tHKW
tSKID
<25>
<26>
ns
Data input setup time
18
ns
(to CLKOUT ↑)
Data input hold time
<27>
<30>
tHKID
2
ns
(from CLKOUT ↑)
Off-page data input setup time (to
address)
tSAID
(1.5 + wD + w)T – 28
(1 + wD + w)T – 32
ns
Off-page data input setup time (to RD)
Off-page RD low-level width
RD high-level width
<31>
<32>
<33>
<36>
<37>
<53>
tSRDID
tWRDL
ns
ns
ns
ns
ns
ns
(1 + wD + w)T – 10
0.5T – 10
tWRDH
tHRDID
tDRDOD
tWORDL
Data input hold time (from RD)
Delay time from RD ↑ to data output
On-page RD low-level width
0
(0.5 + i)T – 10
(1.5 + wPR + w)T
– 10
On-page data input setup time
(to address)
<54>
<55>
tSOAID
(1.5 + wPR + w)T – 28
(1.5 + wPR + w)T – 32
ns
ns
On-page data input setup time (to RD)
tSORDID
Remarks 1.
CYK
T = t
2.
3.
4.
5.
6.
w: The number of waits due to WAIT.
D
w : The number of waits due to the DWC1 and DWC2 registers.
PR
w
: The number of waits due to the PRC register.
i: The number of idle states that are inserted when a write cycle follows a read cycle.
HKID
HRDID
Maintain at least one of the data input hold times, t
or t
.
34
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(5) Page ROM access timing (2/2)
T1
TDW
TW
T2
TO1 TPRW
TW
TO2
CLKOUT (Output)
Off-page addressNote
CSn (Output)
On-page addressNote
UWR, LWR (Output)
RD (Output)
<26>
<30>
<31>
<54>
<33>
<53>
<55>
<32>
<37>
<36>
<27>
<36>
<27>
<26>
<25>
D0 to D15 (I/O)
WAIT (Input)
<25>
<24>
<24>
<25>
<24>
<25>
<24>
BCYST (Output)
Note
On-page and off-page addresses are as follows.
PRC Register
On-page Addresses
Off-page Addresses
MA5
MA4
MA3
0
0
0
1
0
0
1
1
0
1
1
1
A0, A1
A0 to A2
A0 to A3
A0 to A4
A2 to A23
A3 to A23
A4 to A23
A5 to A23
Remarks 1.
This is the timing for the following case.
Number of waits due to the DWC1 and DWC2 registers (TDW): 1
Number of waits due to the PRC register (TPRW): 1
The broken lines indicate high impedance.
n = 0, 3 to 5
2.
3.
35
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(6) DRAM access timing
(a) Read timing (high-speed page DRAM access, normal access: off-page) (1/3)
Parameter
Symbol
<24>
Condition
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
Data input setup time (to CLKOUT ↑)
Data input hold time (from CLKOUT ↑)
Delay time from OE ↑ to data output
Row address setup time
tSWK
tHKW
tSKID
tHKID
tDRDOD
tASR
15
<25>
<26>
<27>
<37>
<56>
<57>
<58>
<59>
<60>
2
18
2
(0.5 + i)T – 10
(0.5 + wRP)T – 10
(0.5 + wRH)T – 10
0.5T – 10
Row address hold time
tRAH
tASC
tCAH
tRC
Column address setup time
Column address hold time
(1.5 + wDA + w)T – 10
Read/write cycle time
(3 + wRP + wRH + wDA + w)
T
–
10
RAS precharge time
RAS pulse time
<61>
<62>
tRP
(0.5 + wRP)T – 10
ns
ns
tRAS
(2.5 + wRH + wDA + w)T
– 10
RAS hold time
<63>
<64>
<65>
<66>
<67>
tRSH
tRAL
tCAS
tCRP
tCSH
(1.5 + wDA + w)T – 10
(2 + wDA + w)T – 10
(1 + wDA + w)T – 10
(1 + wRP)T – 10
ns
ns
ns
ns
ns
Column address read time for RAS
CAS pulse width
CAS-RAS precharge time
CAS hold time
(2 + wRH + wDA + w)T
– 10
WE setup time
<68>
<69>
<70>
<71>
<72>
tRCS
tRRH
tRCH
tCPN
tOEA
(2 + wRP + wRH)T – 10
0.5T – 10
ns
ns
ns
ns
WE hold time (from RAS ↑)
WE hold time (from CAS ↑)
CAS precharge time
T – 10
(2 + wRP + wRH)T – 10
Output enable access time
(2 + wRP + wRH + wDA + w)
T
ns
–
28
RAS access time
<73>
tRAC
(2 + wRH + wDA + w)
T
ns
–
28
Access time from column address
CAS access time
<74>
<75>
tAA
(1.5 + wDA + w)T – 28
(1 + wDA + w)T – 28
ns
ns
tCAC
Remarks 1.
CYK
T = t
2.
3.
w: The number of waits due to WAIT.
RP
w
: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4.
5.
6.
RH
w
: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
DA
w
: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
i: The number of idle states that are inserted when a write cycle follows a read cycle.
36
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(a) Read timing (high-speed page DRAM access, normal access: off-page) (2/3)
Parameter
RAS column address delay time
RAS-CAS delay time
Symbol
<76>
Condition
MIN.
(0.5 + wRH)T – 10
(1 + wRH)T – 10
0
MAX.
Unit
ns
tRAD
tRCD
tOEZ
<77>
<78>
ns
Output buffer turn-off delay time (from
ns
OE ↑)
Output buffer turn-off delay time (from
<79>
tOFF
0
ns
CAS ↑)
Remarks 1.
2.
CYK
T = t
RH
w
: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
37
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(a) Read timing (high-speed page DRAM access, normal access: off-page) (3/3)
TRPW
T1
TRHW
<57>
T2
TDAW
TW
T3
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<58>
<56>
<59>
Row address
Column address
<63>
<64>
<76>
<61>
<62>
<60>
<67>
<77>
<65>
<66>
UCAS (Output)
LCAS (Output)
<69>
<70>
<71>
<68>
<73>
<75>
WE (Output)
OE (Output)
<79>
<74>
<27>
<72>
<37>
<78>
<26>
D0 to D15 (I/O)
<24>
<25>
<24>
<25>
WAIT (Input)
Remarks 1.
This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
The broken lines indicate high impedance.
2.
3.
n = 3 to 5
38
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
[MEMO]
39
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(b) Read timing (high-speed page DRAM access: on-page) (1/2)
Parameter
Symbol
<26>
Condition
MIN.
18
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data input setup time (to CLKOUT ↑)
Data input hold time (from CLKOUT ↑)
Delay time from OE ↑ to data output
Column address setup time
Column address hold time
RAS hold time
tSKID
tHKID
tDRDOD
tASC
tCAH
tRSH
tRAL
<27>
<37>
<58>
<59>
<63>
<64>
<65>
<68>
<69>
<70>
<72>
<74>
<75>
<78>
2
(0.5 + i)T – 10
(0.5 + wCP)T – 10
(1.5 + wDA)T – 10
(1.5 + wDA)T – 10
(2 + wCP + wDA)T – 10
(1 + wDA)T – 10
(1 + wCP)T – 10
0.5T – 10
Column address read time for RAS
CAS pulse width
tCAS
tRCS
tRRH
tRCH
tOEA
tAA
WE setup time (to CAS ↓)
WE hold time (from RAS ↑)
WE hold time (from CAS ↑)
Output enable access time
Access time from column address
CAS access time
T – 10
(1 + wCP + wDA)T – 28
(1.5 + wCP + wDA
T – 28
ns
ns
ns
ns
)
tCAC
tOEZ
(1 + wDA)T – 28
Output buffer turn-off delay time (from
0
0
OE ↑)
Output buffer turn-off delay time (from
<79>
tOFF
ns
CAS ↑)
Access time from CAS precharge
CAS precharge time
<80>
<81>
<82>
<83>
tACP
tCP
(2 + wCP + wDA)T – 28
ns
ns
ns
ns
(1 + wCP)T – 10
High-speed page mode cycle time
RAS hold time for CAS precharge
tPC
(2 + wCP + wDA)T – 10
tRHCP
(2.5 + wCP + wDA)
T – 10
Remarks 1.
2.
CYK
T = t
CP
w
: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3.
4.
DA
w
: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
i: The number of idle states that are inserted when a write cycle follows a read cycle.
40
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(b) Read timing (high-speed page DRAM access: on-page) (2/2)
TCPW
TO1
TDAW
TO2
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<58>
<59>
<63>
Column address
<64>
<83>
<81>
<65>
<82>
UCAS (Output)
LCAS (Output)
<69>
<70>
<68>
WE (Output)
OE (Output)
<75>
<79>
<37>
<72>
<26>
<74>
<80>
<78>
<27>
D0 to D15 (I/O)
WAIT (Input)
Remarks 1.
This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
The broken lines indicate high impedance.
2.
3.
n = 3 to 5
41
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(c) Write timing (high-speed page DRAM access, normal access: off-page) (1/2)
Parameter
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
Row address setup time
Symbol
<24>
Condition
MIN.
15
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
tSWK
tHKW
tASR
tRAH
tASC
tCAH
tRC
<25>
<56>
<57>
<58>
<59>
<60>
2
(0.5 + wRP)T – 10
(0.5 + wRH)T – 10
0.5T – 10
Row address hold time
Column address setup time
Column address hold time
Read/write cycle time
(1.5 + wDA + w)T – 10
(3 + wRP + wRH + wDA + w)T
– 10
RAS precharge time
RAS pulse time
<61>
<62>
tRP
(0.5 + wRP)T – 10
ns
ns
tRAS
(2.5 + wRH + wDA + w)T
– 10
RAS hold time
<63>
<64>
<65>
<66>
<67>
tRSH
tRAL
tCAS
tCRP
tCSH
(1.5 + wDA + w)T – 10
(2 + wDA + w)T – 10
(1 + wDA + w)T – 10
(1 + wRH)T – 10
ns
ns
ns
ns
ns
Column address read time (from RAS )
↑
CAS pulse width
CAS-RAS precharge time
CAS hold time
(2 + wRH + wDA + w)T
– 10
CAS precharge time
<71>
<76>
<77>
<84>
tCPN
tRAD
tRCD
tWCS
(2 + wRP + wRH)T – 10
(0.5 + wRH)T – 10
(1 + wRH)T – 10
ns
ns
ns
ns
RAS column address delay time
RAS-CAS delay time
WE setup time (to CAS ↓)
(1 + wRP + wRH )T
– 10
WE hold time (from CAS ↓)
Data setup time (to CAS ↓)
Data hold time (from CAS ↓)
<85>
<86>
<87>
tWCH
tDS
(1 + wDA + w)T – 10
ns
ns
ns
(1.5 + wRP + wRH)
T – 10
tDH
(1.5 + wDA + w)T – 10
Remarks 1.
CYK
T = t
2.
3.
w: The number of waits due to WAIT.
RP
w
: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4.
5.
RH
w
: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
DA
w
: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
42
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(c) Write timing (high-speed page DRAM access, normal access: off-page) (2/2)
TRPW
T1
TRHW
<57>
T2
TDAW
TW
T3
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<58>
<56>
<59>
Row address
Column address
<63>
<64>
<76>
<61>
<62>
<60>
<67>
<77>
<65>
<66>
UCAS (Output)
LCAS (Output)
<71>
OE (Output)
WE (Output)
<84>
<85>
<86>
<87>
D0 to D15 (I/O)
<24>
<25>
<24>
<25>
WAIT (Input)
Remarks 1.
This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
The broken lines indicate high impedance.
2.
3.
n = 3 to 5
43
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(d) Write timing (high-speed page DRAM access: on-page) (1/2)
Parameter
Symbol
<58>
Condition
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
CP
Column address setup time
Column address hold time
RAS hold time
tASC
tCAH
tRSH
tRAL
tCAS
tCP
(0.5 + w )T – 10
<59>
<63>
<64>
<65>
<81>
<83>
(1.5 + wDA)T – 10
(1.5 + wDA)T – 10
(2 + wCP + wDA)T – 10
(1 + wDA)T – 10
Column address read time (from RAS )
↑
CAS pulse width
CAS precharge time
(1 + wCP)T – 10
RAS hold time for CAS precharge
tRHCP
(2.5 + wCP + wDA)T
– 10
CP
WE setup time (to CAS ↓)
WE hold time (from CAS ↓)
Data setup time (to CAS ↓)
Data hold time (from CAS ↓)
WE read time (from RAS ↑)
WE read time (from CAS ↑)
Data setup time (to WE ↓)
Data hold time (from WE ↓)
WE pulse width
<84>
<85>
<86>
<87>
<88>
<89>
<90>
<91>
<92>
tWCS
tWCH
tDS
wCP ≥ 1
w
T – 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1 + wDA)T – 10
(0.5 + wCP)T – 10
(1.5 + wDA)T – 10
(1.5 + wDA)T – 10
(1 + wDA)T – 10
0.5T – 10
tDH
tRWL
tCWL
tDSWE
tDHWE
tWP
wCP = 0
wCP = 0
wCP = 0
wCP = 0
wCP = 0
(1.5 + wDA)T – 10
(1 + wDA)T – 10
Remarks 1.
2.
CYK
T = t
CP
w
: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3.
DA
w
: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
44
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(d) Write timing (high-speed page DRAM access: on-page) (2/2)
TCPW
TO1
TDAW
TO2
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<58>
<59>
<63>
Column address
<64>
<83>
<81>
<65>
UCAS (Output)
LCAS (Output)
<89>
<88>
OE (Output)
WE (Output)
<84>
<85>
<92>
<91>
<90>
<86>
<87>
D0 to D15 (I/O)
WAIT (Input)
Remarks 1.
This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the CPCxx bit of the DRCn register (TCPW ): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
The broken lines indicate high impedance.
2.
3.
n = 3 to 5
45
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(e) Read timing (EDO DRAM) (1/3)
Parameter
Symbol
<26>
Condition
MIN.
18
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data input setup time (to CLKOUT ↑)
Data input hold time (from CLKOUT ↑)
Delay time from OE ↑ to data output
Row address setup time
tSKID
tHKID
tDRDOD
tASR
tRAH
tASC
tCAH
tRP
<27>
<37>
<56>
<57>
<58>
<59>
<61>
<64>
<66>
<67>
<68>
<69>
<70>
<73>
<74>
<75>
2
(0.5 + i)T – 10
(0.5 + wRP)T – 10
(0.5 + wRH)T – 10
0.5T – 10
Row address hold time
Column address setup time
Column address hold time
RAS precharge time
(0.5 + wDA)T – 10
(0.5 + wRP)T – 10
(2 + wCP + wDA)T – 10
(1 + wRP)T – 10
Column address read time (from RAS
CAS-RAS precharge time
CAS hold time
↑
)
tRAL
tCRP
tCSH
tRCS
tRRH
tRCH
tRAC
tAA
(1.5 + wRH + wDA)
T – 10
WE setup time (to CAS ↓)
WE hold time (from RAS ↑)
WE hold time (from CAS ↑)
RAS access time
(2 + wRP + wRH)T – 10
0.5T – 10
1.5T – 10
(2 + wRH + wDA
)
T – 28
ns
ns
ns
ns
ns
ns
Access time from column address
CAS access time
(1.5 + wDA)T – 28
(1 + wDA)T – 28
tCAC
tRAD
tRCD
tOEZ
Delay time from RAS to column address <76>
(0.5 + wRH)T – 10
(1 + wRH)T – 10
0
RAS-CAS delay time
<77>
<78>
Output buffer turn-off delay time (from
OE)
Access time from CAS precharge
CAS precharge time
<80>
<81>
<83>
<93>
<94>
<95>
<96>
<97>
<98>
tACP
tCP
tRHCP
tHPC
(1.5 + wCP + wDA)
T – 28
ns
ns
ns
ns
ns
ns
ns
ns
ns
(0.5 + wCP)T – 10
(2 + wCP + wDA)T – 10
(1 + wDA + wCP)T – 10
RAS hold time for CAS precharge
Read cycle time
RAS pulse width
tRASP
tHCAS
tOCH1
tOCH2
tDHC
(2.5 + wRH + wDA)
T – 10
CAS pulse width
(0.5 + wDA)T – 10
(2 + wRH + wDA)T – 10
(0.5 + wDA)T – 10
0
CAS hold time from OE
Off-page
On-page
Data input hold time (from CAS ↓)
Remarks 1.
2.
CYK
T = t
RP
w
: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3.
4.
5.
6.
RH
w
: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
DA
w
: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
CP
w
: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
i: The number of idle states that are inserted when a write cycle follows a read cycle.
46
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(e) Read timing (EDO DRAM) (2/3)
Parameter
Symbol
<99> tOEA1
Condition
MIN.
MAX.
Unit
ns
Output enable access
time
Off-page
On-page
(2 + wRP + wRH + wDA)T
– 28
<100>
tOEA2
(1 + wCP + wDA
)
T – 28
ns
Remarks 1.
2.
CYK
T = t
RP
w
: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3.
4.
5.
RH
w
: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10
to 13).
DA
w
: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
CP
w
: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
47
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(e) Read timing (EDO DRAM) (3/3)
TRPW
T1
TRHW
T2
TDAW TCPW
TB
TDAW
TE
CLKOUT (Output)
<58>
<57>
<56>
<59>
A0 to A23 (Output)
RASn (Output)
Row address
<76>
Column address
Column address
<64>
<74>
<61>
<94>
<67>
<77>
<83>
<75>
<66>
<95>
<93>
<81>
UCAS (Output)
LCAS (Output)
<69>
<70>
<68>
<95>
<80>
WE (Output)
OE (Output)
<97>
<96>
<100> <26>
<37>
Note
<75>
<98>
<27>
<27>
<78>
<74>
<26>
D0 to D15 (I/O)
BCYST (Output)
WAIT (Input)
Data
Data
<73>
<99>
Note
For on-page access from another cycle during the RASn low-level signal.
Remarks 1.
This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
The broken lines indicate high impedance.
2.
3.
n = 3 to 5
48
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
[MEMO]
49
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(f) Write timing (EDO DRAM) (1/2)
Parameter
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS precharge time
Symbol
<56>
Condition
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
tASR
tRAH
tASC
tCAH
tRP
(0.5 + wRP)T – 10
(0.5 + wRH)T – 10
0.5T – 10
<57>
<58>
<59>
<61>
<63>
<64>
(0.5 + wDA)T – 10
(0.5 + wRP)T – 10
(1.5 + wDA)T – 10
(2 + wCP + wDA)T – 10
RAS hold time
tRSH
tRAL
Column address read time
(from RAS ↑)
CAS-RAS precharge time
CAS hold time
<66>
<67>
<76>
<77>
<81>
<83>
<85>
<87>
<88>
tCRP
tCSH
tRAD
tRCD
tCP
(1 + wRP)T – 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1.5 + wRH + wDA)
T – 10
Delay time from RAS to column address
RAS-CAS delay time
(0.5 + wRH)T – 10
(1 + wRH)T – 10
CAS precharge time
(0.5 + wCP)T – 10
(2 + wCP + wDA)T – 10
(1 + wDA)T – 10
RAS hold time for CAS precharge
WE hold time (from CAS ↓)
Data hold time (from CAS ↓)
tRHCP
tWCH
tDH
(0.5 + wDA)T – 10
(1.5 + wDA)T – 10
WE read time
On-page
On-page
On-page
tRWL
wCP = 0
wCP = 0
wCP = 0
(from RAS ↑)
WE read time
<89>
tCWL
(0.5 + wDA)T – 10
ns
(from CAS ↑)
WE pulse width
Write cycle time
RAS pulse width
CAS pulse width
<92>
<93>
tWP
tHPC
(1 + wDA)T – 10
ns
ns
ns
ns
ns
ns
ns
ns
(1 + wDA + wCP)T – 10
<94>
tRASP
tHCAS
tWCS1
tWCS2
tDS1
(2.5 + wRH + wDA
(0.5 + wDA)T – 10
(1 + wRP + wRH
T – 10
wCPT – 10
(1.5 + wRP + wRH
T – 10
(0.5 + wCP)T – 10
)
T – 10
<95>
WE setup time
Off-page
On-page
Off-page
On-page
<101>
<102>
<103>
<104>
)
(to CAS ↓)
wCP ≥ 1
Data setup time
)
(to CAS ↓)
tDS2
Remarks 1.
2.
CYK
T = t
RP
w
: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
3.
4.
5.
RH
w
: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
DA
w
: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
CP
w
: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
50
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(f) Write timing (EDO DRAM) (2/2)
TRPW
T1
TRHW
T2
TDAW TCPW
TB
TDAW
TE
CLKOUT (Output)
<58>
<57>
<56>
<59>
<58>
<59>
A0 to A23 (Output)
RASn (Output)
Row address
<76>
Column address
Column address
<64>
<61>
<94>
<67>
<77>
<83>
<66>
<95>
<89>
<81>
<63>
UCAS (Output)
LCAS (Output)
<93>
<88>
<95>
RD (Output)
OE (Output)
<102>
<85>
<101>
<85>
<92>
WE (Output)
D0 to D15 (I/O)
BCYST (Output)
WAIT (Input)
<103>
<87>
<104>
<87>
Data
Data
Remarks 1.
This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
The broken lines indicate high impedance.
2.
3.
n = 3 to 5
51
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) → external I/O transfer) (1/3)
Parameter
Symbol
<24> tSWK
tHKW
Condition
MIN.
MAX.
Unit
ns
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
Delay time from OE ↑ to data output
Delay time from address to IOWR ↓
Address setup time (to IOWR ↑)
15
2
<25>
<37>
<41>
<42>
ns
tDRDOD
tDAWR
tSAWR
(0.5 + i)T – 10
(0.5 + wRP)T – 10
ns
ns
RP
RH
DA
(2 + w + w + w
+
ns
w)T – 10
Delay time from IOWR ↑ to address
Delay time from IOWR ↑ to RD ↑
<43>
<48>
tDWRA
0.5T – 10
0
ns
ns
ns
ns
tDWRRD
wF = 0
wF = 1
T – 10
RH
DA
IOWR low-level width
<50>
tWWRL
(2 + w + w + w)T
– 10
Row address setup time
Row address hold time
<56>
<57>
<58>
<59>
tASR
tRAH
tASC
tCAH
(0.5 + wRP)T – 10
(0.5 + wRH)T – 10
0.5T – 10
ns
ns
ns
ns
Column address setup time
Column address hold time
(1.5 + wDA + wF + w)T
– 10
Read/write cycle time
<60>
tRC
(3 + wRP + wRH + wDA +
wF + w)T – 10
ns
RAS precharge time
RAS hold time
<61>
<63>
tRP
(0.5 + wRP)T – 10
ns
ns
tRSH
(1.5 + wDA + wF + w)T
– 10
Column address read time for RAS
CAS pulse width
<64>
<65>
tRAL
(2 + wCP + wDA + w
F
+
ns
ns
w)T – 10
tCAS
(1 + wDA + wF + w)T
– 10
CAS-RAS precharge time
CAS hold time
<66>
<67>
tCRP
tCSH
(1 + wRP)T – 10
ns
ns
(2 + wRH + wDA + w
F
+
w)T – 10
Remarks 1.
CYK
T = t
2.
3.
w: The number of waits due to WAIT.
RP
w
: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4.
5
RH
w
: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
DA
. w : The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
6.
CP
w
: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
7.
8.
F
w : The number of waits that are inserted for a source-side access during a DMA flyby transfer.
i: The number of idle states that are inserted when a write cycle follows a read cycle.
52
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) → external I/O transfer) (2/3)
Parameter
WE setup time (to CAS ↓)
WE hold time (from RAS ↑)
WE hold time (from CAS ↑)
CAS precharge time
Symbol
<68>
Condition
MIN.
(2 + wRP + wRH)T – 10
0.5T – 10
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
tRCS
tRRH
tRCH
tCPN
tRAD
tRCD
tOEZ
<69>
<70>
<71>
1.5T – 10
(2 + wRP + wRH)T – 10
(0.5 + wRH)T – 10
(1 + wRH)T – 10
0
Delay time from RAS to column address <76>
RAS-CAS delay time
<77>
<78>
Output buffer turn-off delay time (from
OE ↑)
Output buffer turn-off delay time (from
<79>
tOFF
0
ns
CAS ↑)
CAS precharge time
<81>
<82>
tCP
tPC
(0.5 + wCP)T – 10
ns
ns
High-speed page mode cycle time
(2 + wCP + wDA + w
F
+ w)
T
–
10
RAS hold time for CAS precharge
RAS pulse width
<83>
<94>
<96>
<97>
tRHCP
tRASP
tOCH1
tOCH2
(2.5 + wCP + wDA + w
F
+ w)
T
ns
ns
ns
ns
–
10
(2.5 + wRH + wDA + w
F
+ w)T
– 10
CAS hold time from OE
Off-page
On-page
(2.5 + wRP + wRH + wDA +
wF + w)T – 10
(from CAS ↑)
(1.5 + wCP + wDA + w
F
+ w)
T
–
10
Delay time from DMAAKm ↓ to CAS ↓
Delay time from IOWR ↓ to CAS ↓
<105>
<106>
tDDACS
tDRDCS
(1.5 + wRH)T – 10
(1 + wRH)T – 10
ns
ns
Remarks 1.
CYK
T = t
2.
3.
w: The number of waits due to WAIT.
CP
w
: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4.
5.
6.
DA
w
: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
RH
w
: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
RP
w
: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
7.
8.
F
w : The number of waits that are inserted for a source-side access during a DMA flyby transfer.
m = 0 to 3
53
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(g) DMA flyby transfer timing (DRAM (EDO, high-speed page) → external I/O transfer) (3/3)
TRPW T1 TRHW T2 TDAW TW
T3 TCPW TO1 TDAW TW TO2
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<58>
<57>
<56>
<59>
Column address
<94>
Row address
<76>
Column address
<64>
<61>
<60>
<69>
<77>
<65>
<83>
<63>
<66>
<67>
<81>
UCAS (Output)
LCAS (Output)
<70>
<71>
<82>
<48>
<96>
<79>
RD (Output)
OE (Output)
<105>
<97>
DMAAKm (Output)
WE (Output)
<68>
IORD (Output)
IOWR (Output)
D0 to D15 (I/O)
WAIT (Input)
<106>
<42>
<43>
<78>
<37>
<41>
<50>
<24>
Data
Data
<25>
<24>
<24>
<25>
<25>
BCYST (Output)
Remarks 1. This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
Number of waits that are inserted for a source-side access during a DMA flyby transfer: 0
2. The broken lines indicate high impedance.
3. n = 3 to 5, m = 0 to 3
54
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (1/3)
Parameter
Symbol
<24>
Condition
MIN.
15
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WAIT setup time (to CLKOUT ↓)
WAIT hold time (from CLKOUT ↓)
IORD low-level width
tSWK
tHKW
tWRDL
tWRDH
tDARD
tDRDA
tASR
<25>
<32>
<33>
<34>
<35>
<56>
<57>
<58>
<59>
<60>
2
(2 + wRH + wDA + wF + w)T – 10
T – 10
IORD high-level width
Delay time from address to IORD ↑
Delay time from IORD ↑ to address
Row address setup time
0.5T – 10
(0.5 + i)T – 10
(0.5 + wRP)T – 10
(0.5 + wRH)T – 10
0.5T – 10
Row address hold time
tRAH
Column address setup time
Column address hold time
Read/write cycle time
tASC
tCAH
(1.5 + wDA + wF)T – 10
tRC
(3 + wRP + wRH + wDA + wF + w)T
– 10
RAS precharge time
RAS hold time
<61>
<63>
<64>
<65>
<66>
<67>
<71>
tRP
tRSH
tRAL
tCAS
tCRP
tCSH
tCPN
tRAD
tRCD
tCP
(0.5 + wRP)T – 10
(1.5 + wDA + wF)T – 10
(2 + wCP + wDA + wF + w)T – 10
(1 + wDA + wF)T – 10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Column address read time for RAS
CAS pulse width
CAS-RAS precharge time
CAS hold time
(1 + wRP)T – 10
F
(2 + wRH + wDA + w + w)T – 10
CAS precharge time
(2 + wRP + wRH + w)T – 10
(0.5 + wRH)T – 10
Delay time from RAS to column address <76>
RAS-CAS delay time
<77>
<81>
<82>
<83>
<85>
<88>
(1 + wRH + w)T – 10
CAS precharge time
(0.5 + wCP + w)T – 10
(2 + wCP + wDA + wF + w)T – 10
(2.5 + wCP + wDA + w)T – 10
(1 + wDA)T – 10
High-speed page mode cycle time
RAS hold time for CAS precharge
WE hold time (from CAS ↓)
WE read time (from RAS ↑)
tPC
tRHCP
tWCH
tRWL
wCP = 0
(1.5 + wDA + w)T – 10
Remarks 1.
CYK
T = t
2.
3.
w: The number of waits due to WAIT.
RH
w
: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4.
5.
6.
DA
w
: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
RP
w
: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
CP
w
: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
7.
8.
F
w : The number of waits that are inserted for a source-side access during a DMA flyby transfer.
i: The number of idle states that are inserted when a write cycle follows a read cycle.
55
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (2/3)
Parameter
WE read time (from CAS ↑)
WE pulse width
Symbol
<89> tCWL
tWP
Condition
wCP = 0
wCP = 0
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
(1 + wDA + w)T – 10
(1 + wDA + w)T – 10
(2.5 + wRH + wDA + wF + w)T – 10
(1 + wRH + wRP + w)T – 10
wCPT – 10
<92>
<94>
RAS pulse width
tRASP
tWCS1
tWCS2
tDDACS
WE setup time
Off-page
On-page
<101>
<102>
<105>
wCP = 0
(to CAS ↓)
wCP ≥ 1
Delay time from DMAAKm ↓ to CAS
(1.5 + wRH + w)T – 10
↓
Delay time from IORD ↓ to CAS ↓
Delay time from WE ↑ to IORD ↑
<106>
<107>
tDRDCS
tDWERD
(1 + wRH + w)T – 10
ns
ns
ns
wF = 0
wF = 1
0
T – 10
Remarks 1.
CYK
T = t
2.
3.
w: The number of waits due to WAIT.
RH
w
: The number of waits due to the RHCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
4.
5.
6.
DA
w
: The number of waits due to the DACxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
RP
w
: The number of waits due to the RPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
CP
w
: The number of waits due to the CPCxx bit of the DRCn register (n = 0 to 3, xx = 00 to 03, 10 to
13).
7.
8.
F
w : The number of waits that are inserted for a source-side access during a DMA flyby transfer.
m = 0 to 3
56
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(h) DMA flyby transfer timing (external I/O → DRAM (EDO, high-speed page) transfer) (3/3)
TRPW T1 TRHW TW
T2 TDAW T3 TCPW TW
TO1 TDAW TO2
CLKOUT (Output)
A0 to A23 (Output)
RASn (Output)
<56>
<61>
<57>
<58>
<59>
Row address
Column address
Column address
<76>
<64>
<94>
<60>
<77>
<65>
<66>
<67>
<81>
<63>
UCAS (Output)
LCAS (Output)
<71>
<82>
<83>
RD (Output)
OE (Output)
<102>
<88>
<89>
<101>
<105>
<85>
WE (Output)
<92>
DMAAKm (Output)
IOWR (Output)
IORD (Output)
D0 to D15 (I/O)
WAIT (Input)
<106>
<107>
<35>
<34>
<32>
<24>
<25>
<33>
Data
Data
<24>
<24>
<25>
<25>
BCYST (Output)
Remarks 1.
This is the timing for the following case (n = 0 to 3, xx = 00 to 03, 10 to 13).
Number of waits due to the RPCxx bit of the DRCn register (TRPW): 1
Number of waits due to the RHCxx bit of the DRCn register (TRHW): 1
Number of waits due to the DACxx bit of the DRCn register (TDAW): 1
Number of waits due to the CPCxx bit of the DRCn register (TCPW): 1
Number of waits that are inserted for a source-side access during a DMA flyby transfer: 0
The broken lines indicate high impedance.
2.
3.
n = 3 to 5, m = 0 to 3
57
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(i) CBR refresh timing
Parameter
RAS precharge time
RAS pulse width
Symbol
<61>
Condition
MIN.
(1.5 + wRRW)T – 10
(1.5 + w
MAX.
Unit
ns
tRP
RCWNote)T – 10
<62>
<108>
<110>
<113>
tRAS
tCHR
tRPC
tCSR
ns
(1.5 + w
RCWNote)T – 10
ns
CAS hold time
RAS precharge CAS hold time
CAS setup time
(0.5 + wRRW)T – 10
T – 10
ns
ns
Note
RCW
At least one clock cycle is inserted by default for w
regardless of the settings of the RCW0 to RCW2
bits of the RWC register.
Remarks 1.
CYK
T = t
2.
3.
RRW
w
w
: The number of waits due to the RRW0 and RRW1 bits of the RWC register.
: The number of waits due to the RCW0 to RCW2 bits of the RWC register.
RCW
TRRW
T1
T2
TRCWNote
TRCW
<62>
T3
TI
CLKOUT (Output)
RASn (Output)
<61>
<110>
<110>
<113>
<108>
UCAS (Output)
LCAS (Output)
Note
This TRCW is always inserted regardless of the settings of the RCW0 to RCW2 bits of the RWC register.
Remarks 1.
2.
This is the timing for the following case.
Number of waits due to the RRW0 and RRW1 bits of the RWC register (TRRW): 1
Number of waits due to the RCW0 to RCW2 bits of the RWC register (TRCW): 2
n = 3 to 5
58
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(j) CBR self-refresh timing
Parameter
CAS hold time
Symbol
<114> tCHS
<115> tRPS
Condition
MIN.
−5
MAX.
Unit
ns
RAS precharge time
(1 + 2wSRW)T – 10
ns
Remarks 1.
2.
CYK
T = t
SRW
w
: The number of waits due to the SRW0 to SRW2 bits of the RWC register.
TRRW
TH
TH
TH
TRCW
TH
TI
TSRW
TSRW
CLKOUT (Output)
RASn (Output)
<115>
<114>
UCAS (Output)
LCAS (Output)
Output signals
other than above
Remarks 1.
This is the timing for the following case.
Number of waits due to the RRW0 and RRW1 bits of the RWC register (TRRW): 1
Number of waits due to the RCW0 to RCW2 bits of the RWC register (TRCW): 1
Number of waits due to the SRW0 to SRW2 bits of the RWC register (TSRW): 2
The broken lines indicate high impedance.
2.
3.
n = 3 to 5
59
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(7) DMAC timing
Parameter
Symbol
Condition
MIN.
MAX.
Unit
ns
DMARQn setup time (to CLKOUT ↑)
DMARQn hold time (from CLKOUT ↑)
<116>
tSDRK
tHKDR1
tHKDR2
tDKDA
15
<117>
<118>
<119>
2
ns
Until DMAAKn ↓
ns
DMAAKn output delay time
2
10
10
10
10
ns
(from CLKOUT ↓)
DMAAKn output hold time
<120>
<121>
<122>
tHKDA
tDKTC
tHKTC
2
2
2
ns
ns
ns
(from CLKOUT ↓)
TCn output delay time
(from CLKOUT ↓)
TCn output hold time
(from CLKOUT ↓)
Remark
n = 0 to 3
CLKOUT (Output)
DMARQn (Input)
DMAAKn (Output)
TCn (Output)
<117>
<116>
<118>
<116>
<119>
<120>
<122>
<121>
Remark
n = 0 to 3
60
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
[MEMO]
61
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(8) Bus hold timing (1/2)
Parameter
Symbol
<123> tSHRK
tHKHR
Condition
MIN.
15
MAX.
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
HLDRQ setup time (to CLKOUT ↑)
HLDRQ hold time (from CLKOUT ↑)
Delay time from CLKOUT ↓ to HLDAK
HLDRQ high-level width
<124>
<125>
<126>
<127>
2
tDKHA
2
tWHQH
tWHAL
tDKCF
T + 17
T – 8
HLDAK low-level width
Delay time from CLKOUT ↓ to bus float <128>
Delay time from HLDAK ↑ to bus output <129>
10
tDHAC
0
Delay time from HLDRQ ↓ to HLDAK ↓
Delay time from HLDRQ ↑ to HLDAK ↑
<130>
<131>
tDHQHA1
tDHQHA2
2.5T
0.5T
1.5T
Remark
CYK
T = t
62
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(8) Bus hold timing (2/2)
T1
T2
T3
TI
TH
TH
TH
TI
T1
CLKOUT (Output)
HLDRQ (Input)
HLDAK (Output)
A0 to A23 (Output)
D0 to D15 (I/O)
CSn/RASm (Output)
BCYST (Output)
RD (Output)
<123>
<124>
<123>
<123>
<124>
<123>
<126>
<125>
<128>
<125>
<131>
<130>
<127>
<129>
Address
Undefined
Data
WE (Output)
UCAS (Output)
LCAS (Output)
WAIT (Input)
Remarks 1.
2.
The broken lines indicate high impedance.
n = 0, 3 to 5, m = 3 to 5
63
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(9) Interrupt timing
Parameter
NMI high-level width
NMI low-level width
Symbol
<132>
Condition
MIN.
500
MAX.
Unit
ns
tWNIH
tWNIL
tWITH
tWITL
<133>
<134>
<135>
500
ns
INTPn high-level width
INTPn low-level width
4T + 10
4T + 10
ns
ns
Remarks 1.
2.
n = 100 to 103, 110 to 113, 130
CYK
T = t
<132>
<133>
<135>
NMI (Input)
<134>
INTPn (Input)
Remark
n = 100 to 103, 110 to 113, 130
(10) RPU timing
Parameter
Symbol
Condition
MIN.
MAX.
Unit
ns
TI13 high-level width
TI13 low-level width
<136>
tWTIH
tWTIL
tWTCH
tWTCL
3T + 18
3T + 18
3T + 18
3T + 18
<137>
<138>
<139>
ns
TCLR1n high-level width
TCLR1n low-level width
ns
ns
Remarks 1.
2.
n = 0 to 2
CYK
T = t
<136>
<137>
<139>
TI13 (Input)
<138>
TCLR1n (Input)
Remark
n = 0 to 2
64
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(11) UART0, UART1 timing (clock-synchronized or master mode only)
Parameter
Symbol
<140>
Condition
Output
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
SCKn cycle
tCYSK0
tWSK0H
tWSK0L
tSRXSK
tHSKRX
tDSKTX
tHSKTX
250
SCKn high-level width
<141>
<142>
<143>
<144>
<145>
<146>
Output
0.5tCYSK0 – 20
SCKn low-level width
Output
0.5tCYSK0 – 20
RXDn setup time (to SCKn ↑)
RXDn hold time (from SCKn ↑)
TXDn output delay time (from SCKn ↓)
TXDn output hold time (from SCKn ↑)
30
0
20
0.5tCYSK0 – 5
Remark
n = 0, 1
<140>
<142>
<141>
SCKn (I/O)
<143>
<144>
RXDn (Input)
Input data
<145>
<146>
TXDn (Output)
Output data
Remarks 1.
2.
The broken lines indicate high impedance.
n = 0, 1
65
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
(12) CSI0, CSI1 timing
(a) Master mode
Parameter
SCKn cycle
Symbol
<147>
Condition
Output
MIN.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
tCYSK1
tWSK1H
tWSK1L
tSSISK
100
SCKn high-level width
<148>
<149>
<150>
<151>
<152>
<153>
Output
0.5tCYSK1 – 20
SCKn low-level width
Output
0.5tCYSK1 – 20
SIn setup time (to SCKn ↑)
SIn hold time (from SCKn ↑)
SOn output delay time (from SCKn ↓)
SOn output hold time (from SCKn ↑)
30
0
tHSKSI
tDSKSO
tHSKSO
20
0.5tCYSK1 – 5
Remark
n = 0, 1
(b) Slave mode
Parameter
Symbol
Condition
Input
MIN.
100
30
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
SCKn cycle
<147>
<148>
<149>
<150>
<151>
<152>
<153>
tCYSK1
tWSK1H
tWSK1L
tSSISK
SCKn high-level width
Input
SCKn low-level width
Input
30
SIn setup time (to SCKn ↑)
SIn hold time (from SCKn ↑)
SOn output delay time (from SCKn ↓)
SOn output hold time (from SCKn ↑)
10
tHSKSI
10
tDSKSO
tHSKSO
30
tWSK1H
Remark
n = 0, 1
SCKn (I/O)
Sln (Input)
<147>
<149>
<148>
<150>
<151>
Input data
<152>
<153>
SOn (Output)
Output data
Remarks 1.
2.
The broken lines indicate high impedance.
n = 0, 1
66
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
A/D Converter Characteristics (TA = –40 to +85°C, VDD = CVDD = 3.0 to 3.6 V, HVDD = 5.0 V 10%, VSS = 0 V,
HVDD – 0.5 V ≤ AVDD ≤ HVDD, output pin load capacitance: CL = 50 pF)
Parameter
Symbol
Condition
MIN.
10
TYP.
MAX.
Unit
bit
Resolution
–
–
Overall error
4
1/2
10
LSB
LSB
µs
Quantization error
Conversion time
Sampling time
–
tCONV
tSAMP
5
Conversion
clockNote/6
ns
Zero scale error
–
–
4
LSB
LSB
LSB
V
Scale error
4
3
Linearity error
–
Analog input voltage
Analog input resistance
AVREF input voltage
AVREF input current
VIAN
RAN
AVREF
AIREF
AI
−0.3
AVREF + 0.3
2
MΩ
V
AVREF = AVDD
4.5
5.5
2.0
6
mA
mA
DD
DD
AV current
Note
Conversion clock is the number of clocks set by the ADM1 register.
67
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
4. PACKAGE DRAWING
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A
B
75
76
51
50
detail of lead end
S
C
D
R
Q
100
1
26
25
F
M
G
J
H
I
K
P
S
N
S
L
M
NOTE
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
C
D
F
16.00 0.20
14.00 0.20
14.00 0.20
16.00 0.20
1.00
G
1.00
+0.05
0.22
H
−0.04
I
J
0.08
0.50 (T.P.)
1.00 0.20
0.50 0.20
K
L
+0.03
0.17
M
−0.07
N
P
Q
0.08
1.40 0.05
0.10 0.05
+7°
3°
R
−3°
S
1.60 MAX.
S100GC-50-8EU, 8EA-2
68
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
5. RECOMMENDED SOLDERING CONDITIONS
TBD
69
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Electrical Characteristics for Microcomputer (U15170JNote
This document number is that of Japanese version.
)
Reference materials
Note
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
V850E/MS1, V850E/MS2, and V850 Family are trademarks of NEC Corporation.
70
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.
Benelux Office
Hong Kong
Eindhoven, The Netherlands
Tel: 040-2445845
Tel: 2886-9318
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-3067-5800
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 01-3067-5899
Fax: 0211-65 03 490
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 253-8311
NEC Electronics (France) S.A.
Madrid Office
Madrid, Spain
Tel: 091-504-2787
Fax: 091-504-2860
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 250-3583
Fax: 01908-670-290
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: 02-66 75 41
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Fax: 02-2719-5951
Fax: 02-66 75 42 99
Tel: 08-63 80 820
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 08-63 80 388
Fax: 11-6462-6829
J01.2
71
Preliminary Data Sheet U15390EJ1V0DS
µPD703130
• The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M5 98. 8
相关型号：
UPD703131AGJ-XXX-UEN-A
RISC Microcontroller, 32-Bit, MROM, 80MHz, CMOS, PQFP144, 20 X 20 MM, LEAD FREE, PLASTIC, LQFP-144
NEC
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