UPD43256BGW-A12X-9KL [NEC]
256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT EXTENDED TEMPERATURE OPERATION; 256K - BIT的CMOS静态RAM 32K - WORD 8位扩展工作温度
| 型号： | UPD43256BGW-A12X-9KL |
| 厂家： | 
NEC |
| 描述： | 256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT EXTENDED TEMPERATURE OPERATION |
| 文件： | 总20页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
μPD43256B-X
256K-BIT CMOS STATIC RAM
32K-WORD BY 8-BIT
EXTENDED TEMPERATURE OPERATION
Description
The μPD43256B-X is a high speed, low power, and 262,144 bits (32,768 words by 8 bits) CMOS static RAM.
The μPD43256B-X is an extended-operating-temperature version of the μPD43256B (X version : TA = –25 to +85°C).
And A and B versions are low voltage operations. Battery backup is available.
The μPD43256B-X is packed in 28-pin PLASTIC TSOP (I) (8 x 13.4 mm).
Features
• 32,768 words by 8 bits organization
• Fast access time: 70, 85, 100, 120, 150 ns (MAX.)
• Operating ambient temperature: TA = –25 to +85 °C
• Low voltage operation (A version: VCC = 3.0 to 5.5 V, B version: VCC = 2.7 to 5.5 V)
• Low VCC data retention: 2.0 V (MIN.)
• /OE input for easy application
Part number
Access time
Operating supply Operating ambient
Supply current
ns (MAX.)
voltage
V
temperature
°C
At operating
mA (MAX.)
At standby
At data retention
μA (MAX.) Note1
μA (MAX.)
μPD43256B-xxX
−25 to +85
70, 85
4.5 to 5.5
3.0 to 5.5
2.7 to 5.5
45
50
2
85Note2, 100, 120Note2
100, 120Note2, 150Note2
μPD43256B-AxxX
μPD43256B-BxxXNote2
40
Notes 1. TA ≤ 40 °C, VCC = 3.0 V
2. 100 ns (MAX.) (VCC = 4.5 to 5.5 V)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M11012EJ6V0DS00 (6th edition)
Date Published June 2006 NS CP (K)
Printed in Japan
1995
μPD43256B-X
Ordering Information
Part number
Package
Access time
ns (MAX.)
Operating supply Operating ambient
Remark
voltage
V
temperature
°C
μPD43256BGW-70X-9JL
μPD43256BGW-85X-9JL
μPD43256BGW-A85X-9JL
μPD43256BGW-A10X-9JL
μPD43256BGW-A12X-9JL
μPD43256BGW-B10X-9JL
μPD43256BGW-B12X-9JL
μPD43256BGW-B15X-9JL
μPD43256BGW-70X-9KL
μPD43256BGW-85X-9KL
μPD43256BGW-A85X-9KL
μPD43256BGW-A10X-9KL
μPD43256BGW-A12X-9KL
μPD43256BGW-B10X-9KL
μPD43256BGW-B12X-9KL
μPD43256BGW-B15X-9KL
μPD43256BGW-70X-9JL-A
μPD43256BGW-85X-9JL-A
μPD43256BGW-A85X-9JL-A
μPD43256BGW-A10X-9JL-A
μPD43256BGW-A12X-9JL-A
μPD43256BGW-B10X-9JL-A
μPD43256BGW-B12X-9JL-A
μPD43256BGW-B15X-9JL-A
μPD43256BGW-70X-9KL-A
μPD43256BGW-85X-9KL-A
μPD43256BGW-A85X-9KL-A
μPD43256BGW-A10X-9KL-A
μPD43256BGW-A12X-9KL-A
μPD43256BGW-B10X-9KL-A
μPD43256BGW-B12X-9KL-A
μPD43256BGW-B15X-9KL-A
28-pin PLASTIC TSOP(I)
(8x13.4) (Normal bent)
70
85
4.5 to 5.5
–25 to +85
85
3.0 to 5.5
A version
B version
100
120
100
120
150
70
2.7 to 5.5
28-pin PLASTIC TSOP(I)
(8x13.4) (Reverse bent)
4.5 to 5.5
3.0 to 5.5
85
85
A version
B version
100
120
100
120
150
70
2.7 to 5.5
28-pin PLASTIC TSOP(I)
(8x13.4) (Normal bent)
4.5 to 5.5
3.0 to 5.5
85
85
A version
B version
100
120
100
120
150
70
2.7 to 5.5
28-pin PLASTIC TSOP(I)
(8x13.4) (Reverse bent)
4.5 to 5.5
3.0 to 5.5
85
85
A version
B version
100
120
100
120
150
2.7 to 5.5
Remark Products with -A at the end of the part number are lead-free products.
Data Sheet M11012EJ6V0DS
2
μPD43256B-X
Pin Configurations (Marking Side)
/xxx indicates active low signal.
28-pin PLASTIC TSOP(I) (8x13.4) (Normal bent)
[μPD43256BGW-xxX-9JL]
[μPD43256BGW-AxxX-9JL]
[μPD43256BGW-BxxX-9JL]
[μPD43256BGW-xxX-9JL-A]
[μPD43256BGW-AxxX-9JL-A]
[μPD43256BGW-BxxX-9JL-A]
/OE
A11
A9
A8
A13
/WE
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
VCC
A14
A12
A7
A6
A5
9
10
11
12
13
14
A4
A3
A1
A2
28-pin PLASTIC TSOP(I) (8x13.4) (Reverse bent)
[μPD43256BGW-xxX-9KL]
[μPD43256BGW-AxxX-9KL]
[μPD43256BGW-BxxX-9KL]
[μPD43256BGW-xxX-9KL-A]
[μPD43256BGW-AxxX-9KL-A]
[μPD43256BGW-BxxX-9KL-A]
A10
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
/OE
A11
A9
A8
A13
/WE
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
VCC
A14
A12
A7
A6
A5
A1
A2
A4
A3
A0 - A14
I/O1 - I/O8
/CS
:
:
:
:
Address inputs
Data inputs / outputs
Chip Select
/OE
VCC
:
:
Output Enable
Power supply
Ground
GND
:
/WE
Write Enable
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M11012EJ6V0DS
3
μPD43256B-X
Block Diagram
A0
Address
buffer
Row
decoder
Memory cell array
262,144 bits
A14
I/O1
I/O8
Sense amplifier / Switching circuit
Column decoder
Input data
controller
Output data
controller
Address buffer
/CS
/OE
/WE
V
CC
GND
Truth Table
/CS
H
/OE
×
/WE
×
Mode
I/O
Supply current
Not selected
Output disable
Write
High impedance
ISB
ICCA
L
H
H
L
×
L
DIN
L
L
H
Read
DOUT
Remark × : VIH or VIL
Data Sheet M11012EJ6V0DS
4
μPD43256B-X
Electrical Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
VCC
VT
Condition
Rating
Unit
–0.5Note to +7.0
–0.5Note to VCC + 0.5
–25 to +85
V
V
Input / Output voltage
Operating ambient temperature
Storage temperature
TA
°C
°C
Tstg
–55 to +125
Note –3.0 V (MIN.) (Pulse width : 50 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol Condition
μPD43256B-xxX
μPD43256B-AxxX
μPD43256B-BxxX
Unit
MIN.
4.5
MAX.
5.5
MIN.
3.0
MAX.
5.5
MIN.
2.7
MAX.
5.5
Supply voltage
VCC
VIH
VIL
TA
V
V
High level input voltage
2.4
VCC+0.5
+0.6
2.4
VCC+0.5
+0.4
2.4
VCC+0.5
+0.4
Low level input voltage
–0.3 Note
–0.3 Note
–0.3 Note
V
Operating ambient temperature
–25
+85
–25
+85
–25
+85
°C
Note –3.0 V (MIN.) (Pulse width: 50 ns)
Capacitance (TA = 25°C, f = 1 MHz)
Parameter
Input capacitance
Symbol
CIN
Test conditions
MIN.
TYP.
MAX.
Unit
pF
VIN = 0 V
VI/O = 0 V
5
8
Input / Output capacitance
CI/O
pF
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These parameters are periodically sampled and not 100% tested.
Data Sheet M11012EJ6V0DS
5
μPD43256B-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2)
μPD43256B-xxX
Parameter
Symbol
Test condition
Unit
MIN.
–1.0
–1.0
TYP.
MAX.
+1.0
+1.0
μA
μA
Input leakage current
I/O leakage current
ILI
VIN = 0 V to VCC
ILO
VI/O = 0 V to VCC, /OE = VIH or
/CS = VIH or /WE = VIL
Operating supply current
ICCA1
ICCA2
ICCA3
/CS = VIL, Minimum cycle time, II/O = 0 mA
/CS = VIL, II/O = 0 mA
45
15
15
mA
/CS ≤ 0.2 V, Cycle = 1 MHz,
II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V
Standby supply current
High level output voltage
Low level output voltage
ISB
ISB1
/CS = VIH
3
mA
μA
V
/CS ≥ VCC − 0.2 V
1.0
50
VOH1
VOH2
VOL
IOH = –1.0 mA
IOH = –0.1 mA
IOL = 2.1 mA
2.4
VCC–0.5
0.4
V
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These DC characteristics are in common regardless of package types.
Data Sheet M11012EJ6V0DS
6
μPD43256B-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2)
μPD43256B-AxxX
μPD43256B-BxxX
Parameter
Symbol
Test condition
Unit
MIN. TYP. MAX. MIN. TYP. MAX.
μA
μA
Input leakage current
I/O leakage current
ILI
VIN = 0 V to VCC
–1.0
–1.0
+1.0
+1.0
–1.0
–1.0
+1.0
+1.0
ILO
VI/O = 0 V to VCC, /OE = VIH or
/CS = VIH or /WE = VIL
μPD43256B-A85X
μPD43256B-A10X
μPD43256B-A12X
μPD43256B-B10X
μPD43256B-B12X
μPD43256B-B15X
VCC ≤ 3.3 V
Operating supply current
ICCA1 /CS = VIL,
45
40
40
–
–
mA
Minimum cycle time,
–
II/O = 0 mA
–
40
40
40
25
15
10
15
10
3
–
–
–
ICCA2
ICCA3
ISB
/CS = VIL, II/O = 0 mA
15
–
VCC ≤ 3.3 V
/CS ≤ 0.2 V, Cycle = 1 MHz, II/O = 0 mA,
VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V VCC ≤ 3.3 V
/CS = VIH
15
–
Standby supply current
3
mA
VCC ≤ 3.3 V
–
2
/CS ≥ VCC − 0.2 V
μA
ISB1
1.0
50
–
1.0
50
25
VCC ≤ 3.3 V
IOH = –1.0 mA, VCC ≥ 4.5 V
High level output voltage
Low level output voltage
VOH1
2.4
2.4
2.4
2.4
V
IOH = –0.5 mA, VCC < 4.5 V
VOH2 IOH = –0.02 mA
VCC–
VCC–
0.1
0.1
IOL = 2.1 mA, VCC ≥ 4.5 V
VOL
0.4
0.4
0.1
0.4
0.4
0.1
V
IOL = 1.0 mA, VCC < 4.5 V
IOL = 0.02 mA
VOL1
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These DC characteristics are in common regardless of package types.
Data Sheet M11012EJ6V0DS
7
μPD43256B-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[μPD43256B-70X, μPD43256B-85X]
Input Waveform (Rise and Fall Time ≤ 5 ns)
2.4 V
1.5 V
Test points
1.5 V
0.6 V
Output Waveform
1.5 V
Test points
1.5 V
Output Load
AC characteristics should be measured with the following output load conditions.
Figure 1
Figure 2
(tAA, tACS, tOE, tOH)
(tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW)
+5 V
+5 V
1.8 kΩ
1.8 kΩ
I/O (Output)
I/O (Output)
990 Ω
990 Ω
100 pF
5 pF
C
L
C
L
Remark CL includes capacitance of the probe and jig, and stray capacitance.
[μPD43256B-A85X, μPD43256B-A10X, μPD43256B-A12X, μPD43256B-B10X, μPD43256B-B12X, μPD43256B-B15X]
Input Waveform (Rise and Fall Time ≤ 5 ns)
2.4 V
1.5 V
Test points
1.5 V
0.4 V
Output Waveform
1.5 V
Test points
1.5 V
Output Load
AC characteristics should be measured with the following output load conditions.
tAA, tACS, tOE, tOH
tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW
1TTL + 50 pF
1TTL + 5 pF
Data Sheet M11012EJ6V0DS
8
μPD43256B-X
Read Cycle (1/2)
VCC ≥ 4.5 V
Parameter
Symbol
Unit
Con-
μPD43256B-70X
μPD43256B-85X
μPD43256B-AxxX
μPD43256B-BxxX
dition
MIN.
70
MAX.
MIN.
85
MAX.
MIN.
100
MAX.
Read cycle time
tRC
tAA
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
70
70
35
85
85
40
100
100
50
Note
/CS access time
tACS
tOE
/OE access time
Output hold from address change
/CS to output in low impedance
/OE to output in low impedance
/CS to output in high impedance
/OE to output in high impedance
Note See the output load.
tOH
10
10
5
10
10
5
10
10
5
tCLZ
tOLZ
tCHZ
tOHZ
30
30
30
30
35
35
Remark These AC characteristics are in common regardless of package types and L, LL versions.
Read Cycle (2/2)
VCC ≥ 3.0 V
μPD43256B- μPD43256B- μPD43256B- μPD43256B- μPD43256B- μPD43256B-
A85X A10X A12X B10X B12X B15X
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
VCC ≥ 2.7 V
Parameter
Symbol
Unit Con-
dition
Read cycle time
tRC
85
100
120
100
120
150
ns
Address access
time
tAA
85
100
120
100
120
150
ns Note
/CS access time
tACS
tOE
85
50
100
60
120
60
100
60
120
60
150
70
ns
ns
ns
/OE access time
Output hold from
address change
/CS to output in
low impedance
/OE to output in
low impedance
/CS to output in
high impedance
/OE to output in
high impedance
tOH
10
10
5
10
10
5
10
10
5
10
10
5
10
10
5
10
10
5
tCLZ
tOLZ
tCHZ
tOHZ
ns
ns
ns
ns
35
35
35
35
40
40
35
35
40
40
50
50
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
Data Sheet M11012EJ6V0DS
9
μPD43256B-X
Read Cycle Timing Chart
tRC
Address (Input)
/CS (Input)
tAA
tOH
tACS
tCHZ
tCLZ
/OE (Input)
I/O (Output)
tOHZ
t
OE
t
OLZ
High impedance
Data out
Remark In read cycle, /WE should be fixed to high level.
Data Sheet M11012EJ6V0DS
10
μPD43256B-X
Write Cycle (1/2)
VCC ≥ 4.5 V
Parameter
Symbol
Unit
Con-
μPD43256B-70X
μPD43256B-85X
μPD43256B-AxxX
μPD43256B-BxxX
dition
MIN.
70
60
60
55
30
5
MAX.
MIN.
85
70
70
60
35
5
MAX.
MIN.
100
80
80
70
40
5
MAX.
Write cycle time
tWC
tCW
tAW
tWP
tDW
tDH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/CS to end of write
Address valid to end of write
Write pulse width
Data valid to end of write
Data hold time
Address setup time
tAS
0
0
0
Write recovery time
tWR
tWHZ
tOW
0
0
0
/WE to output in high impedance
Output active from end of write
Note See the output load.
30
30
35
Note
5
5
5
Remark These AC characteristics are in common regardless of package types and L, LL versions.
Write Cycle (2/2)
VCC ≥ 3.0 V
μPD43256B- μPD43256B- μPD43256B- μPD43256B- μPD43256B- μPD43256B-
A85X A10X A12X B10X B12X B15X
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
VCC ≥ 2.7 V
Parameter
Symbol
Unit Con-
dition
Write cycle time
tWC
tCW
tAW
85
70
70
100
70
120
90
100
70
120
90
150
100
100
ns
ns
ns
/CS to end of write
Address valid to
end of write
70
90
70
90
Write pulse width
tWP
60
60
60
60
80
70
60
60
80
70
90
80
ns
ns
Data valid to end
of write
tDW
Data hold time
tDH
tAS
5
0
0
5
0
0
5
0
0
5
0
0
5
0
0
5
0
0
ns
Address setup time
Write recovery time
ns
tWR
tWHZ
ns
/WE to output in
high impedance
Output active
35
35
40
35
40
40
ns Note
tOW
5
5
5
5
5
5
ns
from end of write
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
Data Sheet M11012EJ6V0DS
11
μPD43256B-X
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
Address (Input)
/CS (Input)
t
CW
t
AW
t
AS
t
WP
t
WR
/WE (Input)
t
OW
t
WHZ
t
DW
t
DH
High
High
I/O (Input / Output)
Indefinite data out
Data in
Indefinite data out
impe-
dance
impe-
dance
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are
opposite in phase with output signals.
Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE.
2. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance.
3. If /CS changes to low level at the same time or after the change of /WE to low level, the I/O pins
will remain high impedance state.
Data Sheet M11012EJ6V0DS
12
μPD43256B-X
Write Cycle Timing Chart 2 (/CS Controlled)
t
WC
Address (Input)
t
AS
t
CW
/CS (Input)
/WE (Input)
t
AW
t
WP
t
WR
t
DW
t
DH
High impedance
High
Data in
I/O (Input)
impedance
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are
opposite in phase with output signals.
Remark Write operation is done during the overlap time of a low level /CS and a low level /WE.
Data Sheet M11012EJ6V0DS
13
μPD43256B-X
Low VCC Data Retention Characteristics (TA = −25 to +85 °C)
Parameter
Symbol
VCCDR
ICCDR
tCDR
Test Condition
/CS ≥ VCC − 0.2 V
MIN.
2.0
TYP.
0.5
MAX.
5.5
Unit
Data retention supply voltage
Data retention supply current
Chip deselection to data retention mode
Operation recovery time
V
20Note
VCC = 3.0 V, /CS ≥ VCC − 0.2 V
μA
ns
ms
0
5
tR
Note 2 μA (TA ≤ 40 °C), 7 μA (TA ≤ 70 °C)
Data Retention Timing Chart
tCDR
Data retention mode
t
R
VCC
4.5 VNote
/CS
VIH (MIN.)
V
CCDR (MIN.)
/CS ≥ VCC – 0.2 V
VIL (MAX.)
GND
Note A version : 3.0 V, B version : 2.7 V
Remark The other pins (Address, /OE, /WE, I/O) can be in high impedance state.
Data Sheet M11012EJ6V0DS
14
μPD43256B-X
Package Drawings
28-PIN PLASTIC TSOP(I) (8x13.4)
1
28
detail of lead end
S
R
Q
14
15
P
I
A
J
G
S
B
C
H
M
M
D
L
N
S
K
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
A
B
C
8.0 0.1
0.6 MAX.
0.55 (T.P.)
2. "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.)
+0.08
D
0.22
−0.07
1.0
G
H
I
12.4 0.2
11.8 0.1
0.8 0.2
J
+0.025
0.145
K
−0.015
L
M
N
P
0.5 0.1
0.08
0.10
13.4 0.2
0.1 0.05
Q
+7°
3°
R
S
−3°
1.2 MAX.
P28GW-55-9JL-2
Data Sheet M11012EJ6V0DS
15
μPD43256B-X
28-PIN PLASTIC TSOP(I) (8x13.4)
1
28
detail of lead end
Q
R
14
15
S
K
M
N
M
D
S
L
H
C
B
S
G
J
I
A
P
NOTE
ITEM MILLIMETERS
1. Each lead centerline is located within 0.08 mm of
A
B
C
8.0 0.1
its true position (T.P.) at maximum material condition.
0.6 MAX.
0.55 (T.P.)
2. "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.)
+0.08
D
0.22
−0.07
1.0
G
H
I
12.4 0.2
11.8 0.1
0.8 0.2
J
+0.025
0.145
K
−0.015
L
M
N
P
0.5 0.1
0.08
0.10
13.4 0.2
0.1 0.05
Q
+7°
3°
R
S
−3°
1.2 MAX.
P28GW-55-9KL-2
Data Sheet M11012EJ6V0DS
16
μPD43256B-X
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the μPD43256B-X.
Types of Surface Mount Device
μPD43256BGW-xxX-9JL
μPD43256BGW-xxX-9KL
μPD43256BGW-AxxX-9JL
μPD43256BGW-AxxX-9KL
μPD43256BGW-BxxX-9JL
μPD43256BGW-BxxX-9KL
μPD43256BGW-xxX-9JL-A
μPD43256BGW-xxX-9KL-A
μPD43256BGW-AxxX-9JL-A
: 28-pin PLASTIC TSOP(I) (8x13.4) (Normal bent)
: 28-pin PLASTIC TSOP(I) (8x13.4) (Reverse bent)
: 28-pin PLASTIC TSOP(I) (8x13.4) (Normal bent)
: 28-pin PLASTIC TSOP(I) (8x13.4) (Reverse bent)
: 28-pin PLASTIC TSOP(I) (8x13.4) (Normal bent)
: 28-pin PLASTIC TSOP(I) (8x13.4) (Reverse bent)
: 28-pin PLASTIC TSOP(I) (8x13.4) (Normal bent)
: 28-pin PLASTIC TSOP(I) (8x13.4) (Reverse bent)
: 28-pin PLASTIC TSOP(I) (8x13.4) (Normal bent)
μPD43256BGW-AxxX-9KL-A : 28-pin PLASTIC TSOP(I) (8x13.4) (Reverse bent)
μPD43256BGW-BxxX-9JL-A : 28-pin PLASTIC TSOP(I) (8x13.4) (Normal bent)
μPD43256BGW-BxxX-9KL-A : 28-pin PLASTIC TSOP(I) (8x13.4) (Reverse bent)
Data Sheet M11012EJ6V0DS
17
μPD43256B-X
Revision History
Edition/
Page
Previous
Type of
revision
Location
Description
Date
This
(Previous edition → This edition)
edition
p.1
edition
p.1
6th edition/
Jun. 2006
Deletion
−
Description of Version X has been deleted.
Data Sheet M11012EJ6V0DS
18
μPD43256B-X
NOTES FOR CMOS DEVICES
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
1
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
Data Sheet M11012EJ6V0DS
19
μPD43256B-X
•
The information in this document is current as of June, 2006. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
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