UPD43256BGW-A85X-9JL [NEC]
256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT EXTENDED TEMPERATURE OPERATION; 256K - BIT的CMOS静态RAM 32K - WORD 8位扩展工作温度
| 型号： | UPD43256BGW-A85X-9JL |
| 厂家： | 
NEC |
| 描述： | 256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT EXTENDED TEMPERATURE OPERATION |
| 文件： | 总20页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
PD43256B-X
µ
256K-BIT CMOS STATIC RAM
32K-WORD BY 8-BIT
EXTENDED TEMPERATURE OPERATION
Description
The µPD43256B-X is a high speed, low power, and 262,144 bits (32,768 words by 8 bits) CMOS static RAM.
The µPD43256B-X is an extended-operating-temperature version of the µPD43256B (X version : TA = –25 to +85
°C). And A and B versions are low voltage operations. Battery backup is available.
The µPD43256B-X is packed in 28-pin plastic TSOP (I) (8 x 13.4 mm).
Features
• 32,768 words by 8 bits organization
• Fast access time: 70, 85, 100, 120, 150 ns (MAX.)
• Operating ambient temperature: TA = –25 to +85 °C
• Low voltage operation (A version: VCC = 3.0 to 5.5 V, B version: VCC = 2.7 to 5.5 V)
• Low VCC data retention: 2.0 V (MIN.)
• /OE input for easy application
Part number
Access time
ns (MAX.)
Operating supply Operating ambient
Supply current
At standby
voltage
V
temperature
°C
At operating
mA (MAX.)
At data retention
µA (MAX.) Note1
µA (MAX.)
•
µPD43256B-xxX
µPD43256B-AxxX
70, 85
4.5 to 5.5
3.0 to 5.5
2.7 to 5.5
−25 to +85
45
50
2
85Note2, 100, 120Note2
µPD43256B-BxxXNote2 100, 120Note2, 150Note2
40
Notes 1. TA ≤ 40 °C, VCC = 3.0 V
2. 100 s (MAX.) (VCC = 4.5 to 5.5 V)
Version X
This Data sheet can be applied to the version X. Each version is identified with its lot number. Letter X in the fifth
character position in a lot number signifies version X.
JAPAN
D43256B-X
Lot number
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
The mark ★ shows major revised points.
Document No. M11012EJ4V0DSJ1 (4th edition)
Date Published December 2000 NS CP (K)
Printed in Japan
©
1995
µPD43256B-X
Ordering Information
•
Part number
Package
Access time
ns (MAX.)
Operating supply Operating ambient
Remark
voltage
V
temperature
°C
µPD43256BGW-70X-9JL
µPD43256BGW-85X-9JL
µPD43256BGW-A85X-9JL
µPD43256BGW-A10X-9JL
µPD43256BGW-A12X-9JL
µPD43256BGW-B10X-9JL
µPD43256BGW-B12X-9JL
µPD43256BGW-B15X-9JL
µPD43256BGW-70X-9KL
µPD43256BGW-85X-9KL
µPD43256BGW-A85X-9KL
µPD43256BGW-A10X-9KL
µPD43256BGW-A12X-9KL
µPD43256BGW-B10X-9KL
µPD43256BGW-B12X-9KL
µPD43256BGW-B15X-9KL
28-PIN PLASTIC TSOP(I)
(8x13.4) (Normal bent)
70
85
4.5 to 5.5
–25 to +85
85
3.0 to 5.5
A version
B version
100
120
100
120
150
70
2.7 to 5.5
28-PIN PLASTIC TSOP(I)
(8x13.4) (Reverse bent)
4.5 to 5.5
3.0 to 5.5
85
85
A version
B version
100
120
100
120
150
2.7 to 5.5
Data Sheet M11012EJ4V0DS
2
µPD43256B-X
Pin Configurations (Marking Side)
•
/xxx indicates active low signal.
28-PIN PLASTIC TSOP(I) (8x13.4) (Normal bent)
[µPD43256BGW-xxX-9JL]
[µPD43256BGW-AxxX-9JL]
[µPD43256BGW-BxxX-9JL]
/OE
A11
A9
A8
A13
/WE
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
V
CC
A14
A12
A7
A6
A5
9
10
11
12
13
14
A4
A3
A1
A2
28-PIN PLASTIC TSOP(I) (8x13.4) (Reverse bent)
[µPD43256BGW-xxX-9KL]
[µPD43256BGW-AxxX-9KL]
[µPD43256BGW-BxxX-9KL]
A10
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
/OE
A11
A9
A8
A13
/WE
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
A14
A12
A7
A6
A5
A1
A2
A4
A3
A0 - A14
: Address inputs
I/O1 - I/O8 : Data inputs / outputs
/CS
/WE
/OE
VCC
: Chip Select
: Write Enable
: Output Enable
: Power supply
: Ground
GND
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M11012EJ4V0DS
3
µPD43256B-X
Block Diagram
A0
Address
buffer
Row
decoder
Memory cell array
262,144 bits
A14
I/O1
I/O8
Sense amplifier / Switching circuit
Column decoder
Input data
controller
Output data
controller
Address buffer
/CS
/OE
/WE
V
CC
GND
Truth Table
/CS
H
/OE
×
/WE
×
Mode
I/O
Supply current
Not selected
Output disable
Write
High impedance
ISB
ICCA
L
H
H
L
×
L
DIN
L
L
H
Read
DOUT
Remark × : VIH or VIL
Data Sheet M11012EJ4V0DS
4
µPD43256B-X
Electrical Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
VCC
VT
Condition
Rating
Unit
–0.5Note to +7.0
–0.5Note to VCC + 0.5
–25 to +85
V
V
Input / Output voltage
Operating ambient temperature
Storage temperature
TA
°C
°C
Tstg
–55 to +125
Note –3.0 V (MIN.) (Pulse width : 50 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol Condition
µPD43256B-xxX
µPD43256B-AxxX
µPD43256B-BxxX
Unit
MIN.
4.5
MAX.
5.5
MIN.
3.0
MAX.
5.5
MIN.
2.7
MAX.
5.5
Supply voltage
VCC
VIH
VIL
TA
V
V
High level input voltage
2.4
VCC+0.5
+0.6
2.4
VCC+0.5
+0.4
2.4
VCC+0.5
+0.4
Low level input voltage
–0.3 Note
–25
–0.3 Note
–25
–0.3 Note
–25
V
Operating ambient temperature
+85
+85
+85
°C
Note –3.0 V (MIN.) (Pulse width: 50 ns)
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Input capacitance
Symbol
CIN
Test conditions
MIN.
TYP.
MAX.
Unit
pF
VIN = 0 V
VI/O = 0 V
5
8
Input / Output capacitance
CI/O
pF
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These parameters are periodically sampled and not 100% tested.
Data Sheet M11012EJ4V0DS
5
µPD43256B-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2)
Parameter
Symbol
Test condition
µPD43256B-xxX
Unit
MIN.
–1.0
–1.0
TYP.
MAX.
+1.0
+1.0
Input leakage current
I/O leakage current
ILI
VIN = 0 V to VCC
µA
µA
ILO
VI/O = 0 V to VCC, /OE = VIH or
/CS = VIH or /WE = VIL
/CS = VIL, Minimum cycle time, II/O = 0 mA
/CS = VIL, II/O = 0 mA
/CS ≤ 0.2 V, Cycle = 1 MHz,
II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V
/CS = VIH
•
Operating supply current
ICCA1
ICCA2
ICCA3
45
15
15
mA
Standby supply current
High level output voltage
Low level output voltage
ISB
ISB1
3
mA
µA
V
/CS ≥ VCC − 0.2 V
1.0
50
VOH1
VOH2
VOL
IOH = –1.0 mA
2.4
IOH = –0.1 mA
VCC–0.5
IOL = 2.1 mA
0.4
V
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These DC characteristics are in common regardless of package types.
Data Sheet M11012EJ4V0DS
6
µPD43256B-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2)
Parameter
Symbol
Test condition
µPD43256B-AxxX
µPD43256B-BxxX
Unit
MIN. TYP. MAX. MIN. TYP. MAX.
Input leakage current
I/O leakage current
ILI
VIN = 0 V to VCC
–1.0
–1.0
+1.0
+1.0
–1.0
–1.0
+1.0
+1.0
µA
µA
ILO
VI/O = 0 V to VCC, /OE = VIH or
/CS = VIH or /WE = VIL
Operating supply current
ICCA1 /CS = VIL,
µPD43256B-A85X
45
40
40
–
–
mA
Minimum cycle time, µPD43256B-A10X
–
II/O = 0 mA
µPD43256B-A12X
µPD43256B-B10X
µPD43256B-B12X
µPD43256B-B15X
VCC ≤ 3.3 V
–
40
40
40
25
15
10
15
10
3
–
–
–
ICCA2
/CS = VIL, II/O = 0 mA
15
–
VCC ≤ 3.3 V
ICCA3 /CS ≤ 0.2 V, Cycle = 1 MHz, II/O = 0 mA,
VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V VCC ≤ 3.3 V
15
–
Standby supply current
ISB
/CS = VIH
3
mA
µA
V
VCC ≤ 3.3 V
VCC ≤ 3.3 V
–
2
ISB1
/CS ≥ VCC − 0.2 V
1.0
50
–
1.0
50
25
High level output voltage
Low level output voltage
VOH1 IOH = –1.0 mA, VCC ≥ 4.5 V
IOH = –0.5 mA, VCC < 4.5 V
VOH2 IOH = –0.02 mA
2.4
2.4
2.4
2.4
VCC–
0.1
VCC–
0.1
VOL
IOL = 2.1 mA, VCC ≥ 4.5 V
0.4
0.4
0.1
0.4
0.4
0.1
V
IOL = 1.0 mA, VCC < 4.5 V
VOL1 IOL = 0.02 mA
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These DC characteristics are in common regardless of package types.
Data Sheet M11012EJ4V0DS
7
µPD43256B-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[µPD43256B-70X, µPD43256B-85X]
Input Waveform (Rise and Fall Time ≤ 5 ns)
2.4 V
1.5 V
Test points
1.5 V
0.6 V
Output Waveform
1.5 V
Test points
1.5 V
Output Load
AC characteristics should be measured with the following output load conditions.
Figure 1
Figure 2
(tAA, tACS, tOE, tOH)
(tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW)
+5 V
+5 V
1.8 kΩ
1.8 kΩ
I/O (Output)
I/O (Output)
990 Ω
990 Ω
100 pF
5 pF
CL
CL
Remark CL includes capacitance of the probe and jig, and stray capacitance.
[µPD43256B-A85X, µPD43256B-A10X, µPD43256B-A12X, µPD43256B-B10X, µPD43256B-B12X, µPD43256B-B15X]
Input Waveform (Rise and Fall Time ≤ 5 ns)
2.4 V
1.5 V
Test points
1.5 V
0.4 V
Output Waveform
1.5 V
Test points
1.5 V
•
Output Load
AC characteristics should be measured with the following output load conditions.
tAA, tACS, tOE, tOH
1TTL + 50 pF
tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW
1TTL + 5 pF
Data Sheet M11012EJ4V0DS
8
µPD43256B-X
Read Cycle (1/2)
Parameter
Symbol
VCC ≥ 4.5 V
Unit
Con-
•
µPD43256B-70X
µPD43256B-85X
µPD43256B-AxxX
µPD43256B-BxxX
dition
MIN.
70
MAX.
MIN.
85
MAX.
MIN.
100
MAX.
Read cycle time
tRC
tAA
tACS
tOE
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
70
70
35
85
85
40
100
100
50
Note
/CS access time
/OE access time
Output hold from address change
/CS to output in low impedance
/OE to output in low impedance
/CS to output in high impedance
/OE to output in high impedance
Note See the output load.
tOH
10
10
5
10
10
5
10
10
5
tCLZ
tOLZ
tCHZ
tOHZ
30
30
30
30
35
35
Remark These AC characteristics are in common regardless of package types and L, LL versions.
Read Cycle (2/2)
Parameter
Symbol
VCC ≥ 3.0 V
µPD43256B- µPD43256B- µPD43256B- µPD43256B- µPD43256B- µPD43256B-
A85X A10X A12X B10X B12X B15X
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
VCC ≥ 2.7 V
Unit Con-
dition
Read cycle time
tRC
tAA
85
100
120
100
120
150
ns
Address access
time
85
100
120
100
120
150
ns Note
/CS access time
tACS
tOE
85
50
100
60
120
60
100
60
120
60
150
70
ns
ns
ns
/OE access time
Output hold from
address change
/CS to output in
low impedance
/OE to output in
low impedance
/CS to output in
high impedance
/OE to output in
high impedance
tOH
10
10
5
10
10
5
10
10
5
10
10
5
10
10
5
10
10
5
tCLZ
tOLZ
tCHZ
tOHZ
ns
ns
ns
ns
35
35
35
35
40
40
35
35
40
40
50
50
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
Data Sheet M11012EJ4V0DS
9
µPD43256B-X
Read Cycle Timing Chart
t
RC
Address (Input)
/CS (Input)
t
AA
t
OH
t
ACS
t
CHZ
t
CLZ
/OE (Input)
I/O (Output)
t
OHZ
t
OE
t
OLZ
High impedance
Data out
Remark In read cycle, /WE should be fixed to high level.
Data Sheet M11012EJ4V0DS
10
µPD43256B-X
Write Cycle (1/2)
Parameter
Symbol
VCC ≥ 4.5 V
Unit
Con-
µPD43256B-70X
µPD43256B-85X
µPD43256B-AxxX
µPD43256B-BxxX
dition
•
MIN.
70
60
60
55
30
5
MAX.
MIN.
85
70
70
60
35
5
MAX.
MIN.
100
80
80
70
40
5
MAX.
Write cycle time
tWC
tCW
tAW
tWP
tDW
tDH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/CS to end of write
Address valid to end of write
Write pulse width
Data valid to end of write
Data hold time
Address setup time
tAS
0
0
0
Write recovery time
tWR
tWHZ
tOW
0
0
0
/WE to output in high impedance
Output active from end of write
Note See the output load.
30
30
35
Note
5
5
5
Remark These AC characteristics are in common regardless of package types and L, LL versions.
Write Cycle (2/2)
Parameter
Symbol
VCC ≥ 3.0 V
µPD43256B- µPD43256B- µPD43256B- µPD43256B- µPD43256B- µPD43256B-
A85X A10X A12X B10X B12X B15X
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
VCC ≥ 2.7 V
Unit Con-
dition
Write cycle time
tWC
tCW
tAW
85
70
70
100
70
120
90
100
70
120
90
150
100
100
ns
ns
ns
/CS to end of write
Address valid to
end of write
70
90
70
90
Write pulse width
tWP
tDW
60
60
60
60
80
70
60
60
80
70
90
80
ns
ns
Data valid to end
of write
Data hold time
tDH
tAS
tWR
tWHZ
5
0
0
5
0
0
5
0
0
5
0
0
5
0
0
5
0
0
ns
Address setup time
Write recovery time
ns
ns
/WE to output in
high impedance
Output active
35
35
40
35
40
40
ns Note
tOW
5
5
5
5
5
5
ns
from end of write
Note See the output load.
Remark These AC characteristics are in common regardless of package types.
Data Sheet M11012EJ4V0DS
11
µPD43256B-X
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
Address (Input)
/CS (Input)
t
CW
t
AW
t
AS
t
WP
t
WR
/WE (Input)
t
OW
t
WHZ
t
DW
t
DH
High
High
I/O (Input / Output)
Indefinite data out
Data in
Indefinite data out
impe-
dance
impe-
dance
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are
opposite in phase with output signals.
Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE.
2. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
read operation is executed. Therefore /OE should be at high level to make the I/O pins high
impedance.
3. If /CS changes to low level at the same time or after the change of /WE to low level, the I/O pins
will remain high impedance state.
Data Sheet M11012EJ4V0DS
12
µPD43256B-X
Write Cycle Timing Chart 2 (/CS Controlled)
t
WC
Address (Input)
t
AS
t
CW
/CS (Input)
/WE (Input)
t
AW
t
WP
t
WR
t
DW
t
DH
High impedance
High
Data in
I/O (Input)
impedance
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are
opposite in phase with output signals.
Remark Write operation is done during the overlap time of a low level /CS and a low level /WE.
Data Sheet M11012EJ4V0DS
13
µPD43256B-X
Low VCC Data Retention Characteristics (TA = −25 to +85 °C)
Parameter
Symbol
Test Condition
MIN.
2.0
TYP.
0.5
MAX.
5.5
Unit
V
Data retention supply voltage
Data retention supply current
Chip deselection to data retention mode
Operation recovery time
VCCDR /CS ≥ VCC − 0.2 V
ICCDR
tCDR
tR
VCC = 3.0 V, /CS ≥ VCC − 0.2 V
20Note
µA
ns
0
5
ms
Note 2 µA (TA ≤ 40 °C), 7 µA (TA ≤ 70 °C)
Data Retention Timing Chart
t
CDR
Data retention mode
t
R
VCC
4.5 VNote
/CS
V
IH (MIN.)
V
CCDR (MIN.)
/CS ≥ VCC – 0.2 V
V
IL (MAX.)
GND
Note A version : 3.0 V, B version : 2.7 V
Remark The other pins (Address, /OE, /WE, I/O) can be in high impedance state.
Data Sheet M11012EJ4V0DS
14
µPD43256B-X
Package Drawings
•
28-PIN PLASTIC TSOP(I) (8x13.4)
1
28
detail of lead end
S
R
Q
14
15
P
I
A
J
G
S
B
C
H
M
M
D
L
N
S
K
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
A
B
C
8.0±0.1
0.6 MAX.
0.55 (T.P.)
2. "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.)
+0.08
D
0.22
−0.07
1.0
G
H
I
12.4±0.2
11.8±0.1
0.8±0.2
J
+0.025
0.145
K
−0.015
L
M
N
P
0.5±0.1
0.08
0.10
13.4±0.2
0.1±0.05
Q
+7°
3°
R
S
−3°
1.2 MAX.
P28GW-55-9JL-2
Data Sheet M11012EJ4V0DS
15
µPD43256B-X
28-PIN PLASTIC TSOP(I) (8x13.4)
1
28
detail of lead end
Q
R
14
15
S
K
M
N
M
D
S
L
H
C
B
S
G
J
I
A
P
NOTE
ITEM MILLIMETERS
1. Each lead centerline is located within 0.08 mm of
A
B
C
8.0±0.1
its true position (T.P.) at maximum material condition.
0.6 MAX.
0.55 (T.P.)
2. "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.)
+0.08
D
0.22
−0.07
1.0
G
H
I
12.4±0.2
11.8±0.1
0.8±0.2
J
+0.025
0.145
K
−0.015
L
M
N
P
0.5±0.1
0.08
0.10
13.4±0.2
0.1±0.05
Q
+7°
3°
R
S
−3°
1.2 MAX.
P28GW-55-9KL-2
Data Sheet M11012EJ4V0DS
16
µPD43256B-X
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the µPD43256B-X.
Types of Surface Mount Device
µ
µ
µ
µ
µ
µ
: 28-PIN PLASTIC TSOP(I) (8x13.4) (Normal bent)
PD43256BGW-xxX-9JL
PD43256BGW-xxX-9KL
PD43256BGW-AxxX-9JL
PD43256BGW-AxxX-9KL
PD43256BGW-BxxX-9JL
PD43256BGW-BxxX-9KL
: 28-PIN PLASTIC TSOP(I) (8x13.4) (Reverse bent)
: 28-PIN PLASTIC TSOP(I) (8x13.4) (Normal bent)
: 28-PIN PLASTIC TSOP(I) (8x13.4) (Reverse bent)
: 28-PIN PLASTIC TSOP(I) (8x13.4) (Normal bent)
: 28-PIN PLASTIC TSOP(I) (8x13.4) (Reverse bent)
Data Sheet M11012EJ4V0DS
17
µPD43256B-X
[MEMO]
Data Sheet M11012EJ4V0DS
18
µPD43256B-X
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet M11012EJ4V0DS
19
µPD43256B-X
•
The information in this document is current as of December, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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