UPD23C64000JLGY-XXX-MJH-A [NEC]
MASK ROM, 4MX16, 100ns, MOS, PDSO48, 12 X 18 MM, LEAD FREE, PLASTIC, TSOP1-48;
| 型号： | UPD23C64000JLGY-XXX-MJH-A |
| 厂家： | 
NEC |
| 描述： | MASK ROM, 4MX16, 100ns, MOS, PDSO48, 12 X 18 MM, LEAD FREE, PLASTIC, TSOP1-48 有原始数据的样本ROM 光电二极管 |
| 文件： | 总20页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
μPD23C64000JL
64M-BIT MASK-PROGRAMMABLE ROM
8M-WORD BY 8-BIT (BYTE MODE) / 4M-WORD BY 16-BIT (WORD MODE)
Description
The μPD23C64000JL is a 67,108,864 bits mask-programmable ROM. The word organization is selectable (BYTE
mode : 8,388,608 words by 8 bits, WORD mode : 4,194,304 words by 16 bits).
The active levels of OE (Output Enable Input) can be selected with mask-option.
The μPD23C64000JL is packed in 48-pin PLASTIC TSOP (I) and 44-pin PLASTIC SOP.
Features
• Word organization
8,388,608 words by 8 bits (BYTE mode)
4,194,304 words by 16 bits (WORD mode)
• Operating supply voltage : VCC = 2.7 to 3.6 V
Operating
supply voltage
VCC
Package
Access time
ns (MAX.)
Power supply current
(Active mode)
Standby current
(CMOS level input)
μA (MAX.)
mA (MAX.)
3.0 V ± 0.3 V
TSOP (I)
SOP
100
120
90
40
35
55
50
30
3.3 V ± 0.3 V
TSOP (I)
SOP
100
Remark The access time and power supply current vary depending on the package type.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M16084EJ5V0DS00 (5th edition)
Date Published February 2006 NS CP (K)
Printed in Japan
2002
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
μPD23C64000JL
Ordering Information
Part number
Package
μPD23C64000JLGY-xxx-MJH
μPD23C64000JLGY-xxx-MKH
μPD23C64000JLGX-xxx
48-pin PLASTIC TSOP (I) (12 × 18) (Normal bent)
48-pin PLASTIC TSOP (I) (12 × 18) (Reverse bent)
44-pin PLASTIC SOP (15.24 mm (600))
μPD23C64000JLGY-xxx-MJH-A
μPD23C64000JLGY-xxx-MKH-A
μPD23C64000JLGX-xxx-A
48-pin PLASTIC TSOP (I) (12 × 18) (Normal bent)
48-pin PLASTIC TSOP (I) (12 × 18) (Reverse bent)
44-pin PLASTIC SOP (15.24 mm (600))
<R>
<R>
<R>
Remarks 1. xxx : ROM code suffix No.
2. Products with -A at the end of the part number are lead-free products.
<R>
2
Data Sheet M16084EJ5V0DS
μPD23C64000JL
Pin Configurations
/xxx indicates active low signal.
48-pin PLASTIC TSOP (I) (12 × 18) (Normal bent)
[ μPD23C64000JLGY-xxx-MJH ]
<R>
[ μPD23C64000JLGY-xxx-MJH-A ]
Marking Side
WORD, /BYTE
A16
A15
A14
A13
A12
A11
A10
A9
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
GND
O15, A−1
O7
2
3
4
5
O14
O6
6
7
O13
O5
8
9
O12
O4
A8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A19
A21
A20
A18
A17
A7
V
CC
CC
V
NC
O11
O3
O10
A6
O2
A5
O9
A4
O1
A3
O8
A2
O0
A1
/OE or OE or DC
GND
A0
/CE
GND
A0 to A21
: Address inputs
O0 to O7, O8 to O14 : Data outputs
O15, A−1
: Data output 15 (WORD mode),
LSB Address input (BYTE mode)
: Mode select
WORD, /BYTE
/CE
: Chip Enable
/OE or OE
VCC
: Output Enable
: Supply voltage
: Ground
GND
NC Note
: No Connection
: Don’t Care
DC
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the 1-pin index mark.
3
Data Sheet M16084EJ5V0DS
μPD23C64000JL
48-pin PLASTIC TSOP (I) (12 × 18) (Reverse bent)
[ μPD23C64000JLGY-xxx-MKH ]
<R>
[ μPD23C64000JLGY-xxx-MKH-A ]
Marking Side
GND
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
WORD, /BYTE
A16
A15
A14
A13
A12
A11
A10
A9
GND
O15, A−1
3
O7
4
O14
5
O6
6
O13
7
O5
8
O12
9
O4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A8
VCC
A19
A21
A20
A18
A17
A7
VCC
NC
O11
O3
O10
O2
A6
O9
A5
O1
A4
O8
A3
O0
/OE or OE or DC
GND
A2
A1
A0
GND
/CE
A0 to A21
: Address inputs
O0 to O7, O8 to O14 : Data outputs
O15, A−1
: Data Output 15 (WORD mode),
LSB Address input (BYTE mode)
: Mode select
WORD, /BYTE
/CE
: Chip Enable
/OE or OE
VCC
: Output Enable
: Supply voltage
: Ground
GND
NC Note
: No Connection
: Don’t Care
DC
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the 1-pin index mark.
4
Data Sheet M16084EJ5V0DS
μPD23C64000JL
44-pin PLASTIC SOP (15.24 mm (600))
[ μPD23C64000JLGX-xxx ]
<R>
[ μPD23C64000JLGX-xxx-A ]
Marking Side
A21
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A20
A19
A8
1
A18
2
A17
3
A7
A9
4
A6
A10
A11
A12
A13
A14
A15
A16
5
A5
6
A4
7
A3
8
A2
9
A1
10
11
12
13
14
15
16
17
18
19
20
21
22
A0
/CE
WORD, /BYTE
GND
GND
O15, A−1
O7
/OE or OE or DC
O0
O8
O14
O6
O1
O9
O13
O5
O2
O10
O3
O12
O4
O11
VCC
A0 to A21
: Address inputs
O0 to O7, O8 to O14 : Data outputs
O15, A−1
: Data Output 15 (WORD mode),
LSB Address input (BYTE mode)
: Mode select
WORD, /BYTE
/CE
: Chip Enable
/OE or OE
VCC
: Output Enable
: Supply voltage
GND
: Ground
DC
: Don’t Care
Remark Refer to Package Drawings for the 1-pin index mark.
5
Data Sheet M16084EJ5V0DS
μPD23C64000JL
Input / Output Pin Functions
Pin name
Input / Output
Input
Function
WORD, /BYTE
The pin for switching WORD mode and BYTE mode.
High level : WORD mode (4M-word by 16-bit)
Low level : BYTE mode (8M-word by 8-bit)
Address input pins.
A0 to A21
Input
(Address inputs)
A0 to A21 are used differently in the WORD mode and the BYTE mode.
WORD mode (4M-word by 16-bit)
A0 to A21 are used as 22 bits address signals.
BYTE mode (8M-word by 8-bit)
A0 to A21 are used as the upper 22 bits of total 23 bits of address signal.
(The least significant bit (A−1) is combined to O15.)
Data output pins.
O0 to O7, O8 to O14
(Data outputs)
Output
O0 to O7, O8 to O14 are used differently in the WORD mode and the BYTE
mode.
WORD mode (4M-word by 16-bit)
The lower 15 bits of 16 bits data outputs to O0 to O14.
(The most significant bit (O15) combined to A−1.)
BYTE mode (8M-word by 8-bit)
8 bits data outputs to O0 to O7 and also O8 to O14 are high impedance.
O15, A−1 are used differently in the WORD mode and the BYTE mode.
WORD mode (4M-word by 16-bit)
O15, A−1
Output, Input
(Data output 15,
LSB Address input)
The most significant output data bus (O15).
BYTE mode (8M-word by 8-bit)
The least significant address bus (A−1).
/CE
Input
Input
Chip activating signal.
(Chip Enable)
When the OE is active, output states are following.
High level: High-Z
Low level : Data out
/OE or OE or DC
(Output Enable, Don't Care)
VCC
Output enable signal. The active level of OE is mask option. The active level of
OE can be selected from high active, low active and Don’t care at order.
Supply voltage
–
–
–
GND
NC
Ground
Not internally connected (The signal can be connected).
6
Data Sheet M16084EJ5V0DS
μPD23C64000JL
Block Diagram
O8
O9
O10 O11 O12 O13 O14 O15, A−1
O2
O3 O4
O5 O6 O7
O0
O1
A0
A1
A2
A3
A4
A5
Output Buffer
Y-Selector
WORD, /BYTE
/OE or OE or DC
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
Memory Cell Matrix
4,194,304 words by 16 bits /
8,388,608 words by 8 bits
/CE
A18
A19
A20
A21
7
Data Sheet M16084EJ5V0DS
μPD23C64000JL
Mask Option
The active levels of output enable pin (/OE or OE or DC) are mask programmable and optional, and can be selected
from among "0" "1" "×" shown in the table below.
Option
/OE or OE or DC
OE active level
0
1
×
/OE
OE
DC
L
H
Don’t care
Operation modes for each option are shown in the tables below.
Operation mode (Option : 0)
/CE
L
/OE
L
Mode
Active
Output state
Data out
High-Z
H
H
H or L
Standby
High-Z
Operation mode (Option : 1)
/CE
L
OE
L
Mode
Active
Output state
High-Z
H
Data out
High-Z
H
H or L
Standby
Operation mode (Option : ×)
/CE
L
DC
Mode
Active
Output state
Data out
High-Z
H or L
H or L
H
Standby
Remark L : Low level input
H : High level input
8
Data Sheet M16084EJ5V0DS
μPD23C64000JL
Electrical Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
VCC
VI
Condition
Rating
Unit
V
–0.3 to +4.6
Input voltage
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
–10 to +70
V
Output voltage
VO
V
Operating ambient temperature
Storage temperature
TA
°C
°C
Tstg
–65 to +150
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Capacitance (TA = 25 °C)
Parameter
Input capacitance
Output capacitance
Symbol
CI
Test condition
MIN.
TYP.
MAX.
10
Unit
pF
f = 1 MHz
CO
12
pF
DC Characteristics (TA = −10 to +70 °C, VCC = 2.7 to 3.6 V)
Parameter
High level input voltage
Low level input voltage
Symbol
VIH
Test condition
MIN.
2.0
TYP.
MAX.
VCC + 0.3
+0.5
Unit
V
VIL
VCC = 3.0 V ± 0.3 V
–0.3
–0.3
2.4
V
VCC = 3.3 V ± 0.3 V
IOH = –100 μA
+0.8
High level output voltage
Low level output voltage
Input leakage current
Output leakage current
Power supply current
VOH
VOL
ILI
V
V
IOL = 2.1 mA
0.4
+10
+10
40
VI = 0 V to VCC
–10
–10
μA
μA
mA
ILO
VO = 0 V to VCC, Chip deselected
ICC1
/CE = VIL
VCC = 3.0 V ± 0.3 V TSOP (I)
(Active mode),
IO = 0 mA
SOP
VCC = 3.3 V ± 0.3 V TSOP (I)
SOP
35
55
50
Standby current
ICC3
/CE = VCC – 0.2 V (Standby mode)
30
μA
9
Data Sheet M16084EJ5V0DS
μPD23C64000JL
AC Characteristics (TA = −10 to +70 °C, VCC = 2.7 to 3.6 V)
Parameter
Symbol
Test condition
VCC = 3.0 V ± 0.3 V
MIN. TYP. MAX.
VCC = 3.3 V ± 0.3 V
MIN. TYP. MAX.
Unit
ns
Address access time
tACC
TSOP (I)
100
120
10
90
100
10
SOP
Address skew time
tSKEW
tCE
Note
ns
ns
Chip enable access time
TSOP (I)
SOP
100
120
25
90
100
25
Output enable access time
Output hold time
tOE
tOH
tDF
tWB
ns
ns
ns
ns
0
0
0
0
Output disable time
25
25
90
WORD, /BYTE access time
TSOP (I)
SOP
100
120
100
Note tSKEW indicates the following three types of time depending on the condition.
1) When switching /CE from high level to low level, tSKEW is the time from the /CE low level input point until the
next address is determined.
2) When switching /CE from low level to high level, tSKEW is the time from the address change start point to the
/CE high level input point.
3) When /CE is fixed to low level, tSKEW is the time from the address change start point until the next address is
determined.
Since specs are defined for tSKEW only when /CE is active, tSKEW is not subject to limitations when /CE is
switched from high level to low level following address determination, or when the address is changed after /CE
is switched from low level to high level.
Remark tDF is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to
high impedance state output.
AC Test Conditions
Input waveform (Rise / Fall Time ≤ 5 ns)
1.4 V
Test points
1.4 V
Output waveform
1.4 V
Test points
1.4 V
Output load
1 TTL + 100 pF
10
Data Sheet M16084EJ5V0DS
μPD23C64000JL
Cautions on power application
To ensure normal operation, always apply power using /CE following the procedure shown below.
1) Input a high level to /CE during and after power application.
2) Hold the high level input to /CE for 200 ns or longer (wait time).
3) Start normal operation after the wait time has elapsed.
Power Application Timing Chart 1 (When /CE is made high at power application)
Wait time
Normal operation
/CE (Input)
200 ns or longer
V
CC
Power Application Timing Chart 2 (When /CE is made high after power application)
Wait time
Normal operation
/CE (Input)
200 ns or longer
V
CC
Caution Other signals can be either high or low during the wait time.
11
Data Sheet M16084EJ5V0DS
μPD23C64000JL
Read Cycle Timing Chart
t
SKEW
t
SKEW
tSKEW
A0 to A21,
(Input)
A−1 Note1
t
ACC
t
ACC
tACC
/CE (Input)
Note2
Note2
tDF
t
CE
t
DF
/OE or OE (Input)
t
OE
t
OH
t
OH
tOH
High-Z
High-Z
O0 to O7,
(Input)
Data out
Data out
Data out
O8 to O15 Note3
Notes 1. During WORD mode, A−1 is O15.
2. tDF is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to
high impedance state output.
3. During BYTE mode, O8 to O14 are high impedance and O15 is A−1.
WORD, /BYTE Switch Timing Chart
High-Z
High-Z
A–1 (Input)
(Input)
WORD, /BYTE
t
OH
tACC
tOH
tWB
O0 to O7 (Output)
O8 to O15 (Output)
Data Out
Data Out
High-Z
Data Out
Data Out
t
DF
Data Out
Remark Chip Enable (/CE) and Output Enable (/OE or OE) : Active.
12
Data Sheet M16084EJ5V0DS
μPD23C64000JL
Package Drawings
48-PIN PLASTIC TSOP(I) (12x18)
detail of lead end
1
48
F
G
R
Q
L
24
25
S
E
P
I
A
J
C
S
B
M
M
D
N
S
K
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
E
F
G
I
12.0 0.1
0.45 MAX.
0.5 (T.P.)
0.22 0.05
0.1 0.05
1.2 MAX.
1.0 0.05
16.4 0.1
0.8 0.2
0.145 0.05
0.5
2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
J
K
L
M
N
P
0.10
0.10
18.0 0.2
+5°
3°
Q
−3°
R
S
0.25
0.60 0.15
S48GY-50-MJH1-1
13
Data Sheet M16084EJ5V0DS
μPD23C64000JL
48-PIN PLASTIC TSOP(I) (12x18)
detail of lead end
1
48
E
S
L
Q
R
G
24
25
S
F
K
N
S
M
A
D
M
B
C
I
J
P
NOTES
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
C
D
E
F
G
I
12.0 0.1
0.45 MAX.
0.5 (T.P.)
0.22 0.05
0.1 0.05
1.2 MAX.
1.0 0.05
16.4 0.1
0.8 0.2
0.145 0.05
0.5
2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
J
K
L
M
N
P
0.10
0.10
18.0 0.2
+5°
3°
Q
−3°
R
S
0.25
0.60 0.15
S48GY-50-MKH1-1
14
Data Sheet M16084EJ5V0DS
μPD23C64000JL
44-PIN PLASTIC SOP (15.24 mm (600))
44
23
detail of lead end
P
1
22
A
H
I
F
J
G
S
B
C
N
S
L
K
D
M
M
E
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
+0.4
27.83
A
−0.05
B
C
0.78 MAX.
1.27 (T.P.)
+0.08
0.42
D
−0.07
E
F
G
H
I
0.15 0.1
3.0 MAX.
2.7 0.05
16.04 0.3
13.24 0.1
1.4 0.2
J
+0.08
0.22
K
−0.07
L
M
N
0.8 0.2
0.12
0.10
+7°
3°
P
−3°
P44GX-50-600A-4
15
Data Sheet M16084EJ5V0DS
μPD23C64000JL
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the μPD23C64000JL.
Types of Surface Mount Device
μPD23C64000JLGY-xxx-MJH : 48-pin PLASTIC TSOP (I) (12 × 18) (Normal bent)
μPD23C64000JLGY-xxx-MKH : 48-pin PLASTIC TSOP (I) (12 × 18) (Reverse bent)
μPD23C64000JLGX-xxx
: 44-pin PLASTIC SOP (15.24 mm (600))
<R>
<R>
<R>
μPD23C64000JLGY-xxx-MJH-A : 48-pin PLASTIC TSOP (I) (12 × 18) (Normal bent)
μPD23C64000JLGY-xxx-MKH-A : 48-pin PLASTIC TSOP (I) (12 × 18) (Reverse bent)
μPD23C64000JLGX-xxx-A
: 44-pin PLASTIC SOP (15.24 mm (600))
16
Data Sheet M16084EJ5V0DS
μPD23C64000JL
Revision History
Edition/
Page
Previous
Type of
revision
Location
Description
Date
This
(Previous edition → This edition)
edition
p.2
edition
p.1
5h edition/
Feb. 2006
Addition
Addition
Addition
Ordering Information
Pin Configuration
Recommended Soldering
Conditions
Lead-free products have been added
Lead-free products have been added
Lead-free products have been added
pp.3-5
p.16
pp.2-4
p.15
17
Data Sheet M16084EJ5V0DS
μPD23C64000JL
[MEMO]
18
Data Sheet M16084EJ5V0DS
μPD23C64000JL
NOTES FOR CMOS DEVICES
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
1
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
19
Data Sheet M16084EJ5V0DS
μPD23C64000JL
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
•
The information in this document is current as of February, 2006. The information is subject to
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•
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The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
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M8E 02. 11-1
相关型号：
UPD23C64000JLGY-XXX-MKH
64M-BIT MASK-PROGRAMMABLE ROM 8M-WORD BY 8-BIT (BYTE MODE) / 4M-WORD BY 16-BIT (WORD MODE)
NEC
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