UPD23C64040ALGY-XXX-MJ [ETC]
x8 or x16 ROM (Mask Programmable) ; x8或x16 ROM （掩模可编程）\n
| 型号： | UPD23C64040ALGY-XXX-MJ |
| 厂家： | 
ETC |
| 描述： | x8 or x16 ROM (Mask Programmable)
|
| 文件： | 总16页 (文件大小：98K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD23C64040AL
64M-BIT MASK-PROGRAMMABLE ROM
8M-WORD BY 8-BIT (BYTE MODE) / 4M-WORD BY 16-BIT (WORD MODE)
PAGE ACCESS MODE
Description
The µPD23C64040AL is a 67,108,864 bits mask-programmable ROM. The word organization is selectable (BYTE
mode : 8,388,608 words by 8 bits, WORD mode : 4,194,304 words by 16 bits).
The active levels of OE (Output Enable Input) can be selected with mask-option.
The µPD23C64040AL is packed in 48-pin plastic TSOP (I).
Features
• Word organization
8,388,608 words by 8 bits (BYTE mode)
4,194,304 words by 16 bits (WORD mode)
• Page access mode
BYTE mode : 8 byte random page access
WORD mode : 4 word random page access
CC
• Operating supply voltage : V = 2.7 to 3.6 V
Operating supply voltage Access time / Page access time Power supply current (Active mode) Standby current (CMOS level input)
VCC
ns (MAX.)
90 / 25
mA (MAX.)
µA (MAX.)
3.3 V ± 0.3 V
3.0 V ± 0.3 V
65
55
30
30
100 / 30
Ordering Information
Part number
Package
µPD23C64040ALGY-xxx-MJH
µPD23C64040ALGY-xxx-MKH
48-pin plastic TSOP (I) (12 × 18) (Normal bent)
48-pin plastic TSOP (I) (12 × 18) (Reverse bent)
(xxx : ROM code suffix No.)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M13208EJ4V0DSJ1 (4th edition)
Date Published December 2000 NS CP (K)
Printed in Japan
The mark • shows major revised points.
1997
©
µ
PD23C64040AL
★
Pin Configurations (Marking Side)
/xxx indicates active low signal.
48-pin Plastic TSOP (I) (12 × 18) (Normal bent)
[ µPD23C64040ALGY-xxx-MJH ]
WORD, /BYTE
A16
A15
A14
A13
A12
A11
A10
A9
1
48
GND
GND
O15, A−1
O7
2
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
3
4
5
O14
O6
6
7
O13
O5
8
9
O12
O4
A8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A19
A21
A20
A18
A17
A7
V
CC
CC
V
NC
O11
O3
O10
O2
A6
A5
O9
A4
O1
A3
O8
A2
O0
A1
/OE, OE, DC
GND
GND
A0
/CE
A0 - A21
: Address inputs
O0 - O7, O8 - O14
: Data outputs
O15, A−1
: Data output 15 (WORD mode),
LSB Address input (BYTE mode)
: Mode select
WORD, /BYTE
/CE
: Chip Enable
/OE, OE
: Output Enable
: Supply voltage
: Ground
CC
V
GND
NC Note
DC
: No Connection
: Don’t Care
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the 1-pin index mark.
2
Data Sheet M13208EJ4V0DS
µ
PD23C64040AL
48-pin Plastic TSOP (I) (12 × 18) (Reverse bent)
[ µPD23C64040ALGY-xxx-MKH ]
GND
GND
O15, A−1
O7
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
WORD, /BYTE
A16
A15
A14
A13
A12
A11
A10
A9
3
4
O14
5
O6
6
O13
7
O5
8
O12
9
O4
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A8
V
V
CC
CC
A19
A21
A20
A18
A17
A7
NC
O11
O3
O10
O2
A6
O9
A5
O1
O8
A4
A3
O0
A2
/OE, OE, DC
GND
A1
A0
GND
/CE
A0 - A21
: Address inputs
O0 - O7, O8 - O14
O15, A−1
: Data outputs
: Data output 15 (WORD mode),
LSB Address input (BYTE mode)
: Mode select
WORD, /BYTE
/CE
: Chip Enable
/OE, OE
: Output Enable
: Supply voltage
: Ground
CC
V
GND
NC Note
DC
: No Connection
: Don’t Care
Note Some signals can be applied because this pin is not connected to the inside of the chip.
Remark Refer to Package Drawings for the 1-pin index mark.
3
Data Sheet M13208EJ4V0DS
µ
PD23C64040AL
Input / Output Pin Functions
Pin name
WORD, /BYTE
Input / Output
Function
Input
The pin for switching WORD mode and BYTE mode.
High level : WORD mode (4M-word by 16-bit)
Low level : BYTE mode (8M-word by 8-bit)
A0 to A21
Input
Address input pins.
(Address inputs)
A0 to A21 are used differently in the WORD mode and the BYTE mode.
WORD mode (4M-word by 16-bit)
A0 to A21 are used as 22 bits address signals.
BYTE mode (8M-word by 8-bit)
A0 to A21 are used as the upper 22 bits of total 23 bits of address signal.
(The least significant bit (A−1) is combined to O15.)
O0 to O7, O8 to O14
(Data outputs)
Output
Data output pins.
O0 to O7, O8 to O14 are used differently in the WORD mode and the BYTE
mode.
WORD mode (4M-word by 16-bit)
The lower 15 bits of 16 bits data outputs to O0 to O14.
(The most significant bit (O15) combined to A−1.)
BYTE mode (8M-word by 8-bit)
8 bits data outputs to O0 to O7 and also O8 to O14 are high impedance.
O15, A−1
(Data output 15,
LSB Address input)
Output, Input
O15, A−1 are used differently in the WORD mode and the BYTE mode.
WORD mode (4M-word by 16-bit)
The most significant output data bus (O15).
BYTE mode (8M-word by 8-bit)
The least significant address bus (A−1).
/CE
(Chip Enable)
Input
Input
Chip activating signal.
When the OE is active, output states are following.
High level: High impedance
Low level : Data out
/OE, OE, DC
(Output Enable, Don't Care)
Output enable signal. The active level of OE is mask option. The active level
of OE can be selected from high active, low active and Don’t care at order.
VCC
–
–
–
Supply voltage
GND
NC
Ground
Not internally connected (The signal can be connected).
4
Data Sheet M13208EJ4V0DS
µ
PD23C64040AL
Block Diagram
O8
O9
O10 O11 O12 O13 O14 O15, A–1
O2
O3 O4
O5 O6 O7
O0
O1
A0
A1
A2
A3
A4
A5
Output Buffer
Y-Selector
WORD, /BYTE
/OE, OE, DC
A6
A7
A8
A9
Memory Cell Matrix
A10
A11
A12
A13
A14
A15
A16
A17
4,194,304 words by 16 bits /
8,388,608 words by 8 bits
/CE
A18
A19
A20
A21
5
Data Sheet M13208EJ4V0DS
µ
PD23C64040AL
Mask Option
The active levels of output enable pin (/OE, OE, DC) are mask programmable and optional, and can be selected
from among "0" "1" "×" shown in the table below.
Option
/OE, OE, DC
OE active level
0
1
×
/OE
OE
DC
L
H
Don’t care
Operation modes for each option are shown in the tables below.
Operation mode (Option : 0)
/CE
L
/OE
L
Mode
Output state
Data out
Active
H
High impedance
High impedance
H
H or L
Standby
Operation mode (Option : 1)
/CE
L
OE
L
Mode
Output state
High impedance
Data out
Active
H
H
H or L
Standby
High impedance
Operation mode (Option : ×)
/CE
L
DC
Mode
Active
Output state
Data out
H or L
H or L
H
Standby
High impedance
Remark L : Low level input
H : High level input
6
Data Sheet M13208EJ4V0DS
µ
PD23C64040AL
Electrical Specifications
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
VCC
VI
Condition
Rating
Unit
–0.3 to +4.6
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
–10 to +70
V
V
Input voltage
Output voltage
VO
V
Operating ambient temperature
Storage temperature
TA
°C
°C
Tstg
–65 to +150
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Capacitance (TA = 25 °C)
Parameter
Symbol
CI
Test condition
f = 1 MHz
MIN.
TYP.
MAX.
10
Unit
pF
Input capacitance
Output capacitance
CO
12
pF
DC Characteristics (TA = −10 to +70 °C, VCC = 2.7 to 3.6 V)
Parameter
Symbol
VIH
Test condition
MIN.
2.0
TYP.
MAX.
VCC + 0.3
+0.5
Unit
V
High level input voltage
Low level input voltage
VIL
VCC = 3.0 V ± 0.3 V
–0.3
–0.3
2.4
V
VCC = 3.3 V ± 0.3 V
+0.8
High level output voltage
Low level output voltage
Input leakage current
Output leakage current
Power supply current
VOH
VOL
ILI
IOH = –100 µA
V
V
IOL = 2.1 mA
0.4
+10
+10
55
VI = 0 V to VCC
–10
–10
µA
µA
mA
ILO
VO = 0 V to VCC, Chip deselected
/CE = VIL (Active mode), VCC = 3.0 V ± 0.3 V
ICC1
IO = 0 mA
VCC = 3.3 V ± 0.3 V
65
Standby current
ICC3
/CE = VCC – 0.2 V (Standby mode)
30
µA
7
Data Sheet M13208EJ4V0DS
µ
PD23C64040AL
AC Characteristics (TA = −10 to +70 °C, VCC = 2.7 to 3.6 V)
Parameter
Symbol
Test condition
VCC = 3.0 V ± 0.3 V
VCC = 3.3 V ± 0.3 V
Unit
MIN.
TYP. MAX. MIN.
TYP. MAX.
Address access time
Page access time
tACC
tPAC
tCE
100
30
90
ns
ns
ns
ns
ns
ns
ns
25
Chip enable access time
Output enable access time
Output hold time
100
30
90
tOE
tOH
tDF
25
0
0
0
Output disable time
30
0
25
90
WORD, /BYTE access time
tWB
100
Remark tDF is the time from inactivation of /CE or /OE, OE to high-impedance state output.
AC Test Conditions
Input waveform (Rise / Fall Time ≤ 5 ns)
1.4 V
Test points
1.4 V
Output waveform
1.4 V
Test points
1.4 V
Output load
1 TTL + 100 pF
8
Data Sheet M13208EJ4V0DS
µ
PD23C64040AL
Read Cycle Timing Chart 1
A0 to A21,
(Input)
A–1Note 1
t
ACC
/CE (Input)
Note 2
DF
t
CE
t
/OE, OE (Input)
t
OE
t
OH
High impedance
O0 to O7,
(Output)
Data Out
O8 to O15Note 3
Notes 1. During WORD mode, A−1 is O15.
2. tDF is specified when one of /CE, /OE, OE is inactivated.
3. During BYTE mode, O8 to O14 are high impedance and O15 is A−1.
9
Data Sheet M13208EJ4V0DS
µ
PD23C64040AL
★
Read Cycle Timing Chart 2 (Page Access Mode)
A2 to A21 (Input)
tACC
/CE (Input)
t
CE
/OE, OE (Input)
t
OE
A–1,Note 1
(Input)
A0, A1
Note 4
tPAC
Note 4
PAC
Note 2
DF
t
t
t
OH
tOH
t
OH
High
impedance
High impedance
O0 to O7,
O8 to O15Note 3
Data Out
Data Out
Data Out
(Output)
Notes 1. During WORD mode, A−1 is O15.
2. tDF is specified when one of /CE, /OE, OE is inactivated.
3. During BYTE mode, O8 to O14 are high impedance and O15 is A−1.
4. The definitions of page access time is as follows.
Page access time
Upper address (A2 to A22)
inputs condition
/CE input condition
/OE, OE input condition
tPAC
Before tACC – tPAC
Before tCE – tPAC
Before stabilizing of page
address (A–1, A0, A1)
10
Data Sheet M13208EJ4V0DS
µ
PD23C64040AL
WORD, /BYTE Switch Timing Chart
High impedance
High impedance
A–1 (Input)
(Input)
WORD, /BYTE
t
OH
t
ACC
t
OH
t
WB
O0 to O7 (Output)
O8 to O15 (Output)
Data Out
Data Out
Data Out
Data Out
t
DF
High impedance
Data Out
Remark /OE, OE and /CE : Active.
11
Data Sheet M13208EJ4V0DS
µ
PD23C64040AL
★
Package Drawings
48-PIN PLASTIC TSOP(I) (12x18)
detail of lead end
1
48
F
G
R
Q
L
24
25
S
E
P
I
A
J
C
S
B
M
M
D
N
S
K
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
E
F
G
I
12.0±0.1
0.45 MAX.
0.5 (T.P.)
0.22±0.05
0.1±0.05
1.2 MAX.
1.0±0.05
16.4±0.1
0.8±0.2
0.145±0.05
0.5
2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
J
K
L
M
N
P
0.10
0.10
18.0±0.2
+5°
3°
Q
−3°
R
S
0.25
0.60±0.15
S48GY-50-MJH1-1
12
Data Sheet M13208EJ4V0DS
µ
PD23C64040AL
48-PIN PLASTIC TSOP(I) (12x18)
detail of lead end
1
48
E
S
L
Q
R
G
24
25
F
K
N
S
M
A
D
M
B
S
C
I
J
P
NOTES
1. Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
C
D
E
F
G
I
12.0±0.1
0.45 MAX.
0.5 (T.P.)
0.22±0.05
0.1±0.05
1.2 MAX.
1.0±0.05
16.4±0.1
0.8±0.2
0.145±0.05
0.5
2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.)
J
K
L
M
N
P
0.10
0.10
18.0±0.2
+5°
3°
Q
−3°
R
S
0.25
0.60±0.15
S48GY-50-MKH1-1
13
Data Sheet M13208EJ4V0DS
µ
PD23C64040AL
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the µPD23C64040AL.
Types of Surface Mount Device
µPD23C64040ALGY-MJH : 48-pin plastic TSOP (I) (12 × 18) (Normal bent)
µPD23C64040ALGY-MKH : 48-pin plastic TSOP (I) (12 × 18) (Reverse bent)
14
Data Sheet M13208EJ4V0DS
µ
PD23C64040AL
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
15
Data Sheet M13208EJ4V0DS
µ
PD23C64040AL
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
•
The information in this document is current as of December, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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