UPD16520GS-BGG_技术文档

DATA SHEET

MOS INTEGRATED CIRCUIT

µPD16520

VERTICAL DRIVER FOR CCD SENSORS

The µPD16520 is a vertical driver for CCD image sensors that has a level conversion circuit and a 3-level output

function. Since it incorporates a CCD vertical register driver equivalent to the µPD16510 (10 channels, consisting of

six 3-level channels and four 2-level channels) and a VOD shutter driver (1 channel), it is ideal as a vertical driver for

multiple-electrode high-pixel CCD transfer type area image sensors employed in digital still cameras.

The µPD16520 uses a CMOS process to achieve optimum transmission delay characteristics for vertical driving of

CCD image sensors, as well as output on-state resistance characteristics. The µPD16520 also supports low-voltage

logic (logic supply voltage: 2.0 to 5.5 V).

FEATURES

• CCD vertical register driver: 10 channels (3-level: 6 channels, 2-level: 4 channels)

• VOD shutter driver: 1 channel

• High withstand voltage: 33 V Max.

• Low-output on-state resistance: 30 Ω TYP.

• Low-voltage input supported (Logic supply voltage: 2.0 to 5.5 V)

• Latch-up free

• Same drive capacity as µPD16510

• Small package: 38-pin plastic shrink SOP (300 mil)

APPLICATIONS

Digital still cameras, digital video cameras, etc.

ORDERING INFORMATION

Part Number

Package

µPD16520GS-BGG

38-pin plastic shrink SOP (300 mil)

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No. S14201EJ1V0DS00 (1st edition)

Date Published May 1999 N CP(K)

Printed in Japan

1999

©

µPD16520

PIN CONFIGURATION (TOP VIEW)

•

38-pin plastic shrink SOP (300 mil)

µPD16520GS-BGG

1

2

3

4

5

GND

V^SS

38

37

VDD1

TO1

Vcc

TI1

36

35

TI2

VDD2a

TO2

TI3

34

33

6

7

TI4

TO3

VDD2a

32

31

TI5

TO4

TI6

8

PG1

PG2

PG3

PG4

PG5

PG6

BI1

9

30

29

TO5

VDD2a

10

11

12

13

28

27

26

25

TO6

BO1

BO2

VDD2b

BO3

BO4

14

15

16

17

24

23

22

21

20

BI2

BI3

SUBO

Vsb

BI4

18

19

Vss

SUBI

PIN NAMES

BI1 to BI4:

BO1 to BO4:

GND:

2 Level Driver Input

TO1 to TO6:

VDD1:

VDD2a:

VDD2b:

V^CC:

3 Level Pulse Output

Power Supply (V^H)

Power Supply (V^Ma)

Power Supply (V^Mb)

Power Supply (Logic)

Power Supply (V^HH)

Power Supply (V^L)

2 Level Pulse Output

Ground

PG1 to PG6:

SUBI:

3 Level Driver Input

VOD Shutter Drive Pulse Input

VOD Shutter Drive Pulse Output

3 Level Driver Input

SUBO:

Vsb:

TI1 to TI6:

V^SS:

2

Data Sheet S14201EJ1V0DS00

µPD16520

BLOCK DIAGRAM

Vss

38

37

1

GND

VDD1

Vcc

TI1

2

3

+

−

36

3 level

TO1

+

−

TI2

TI3

TI4

TI5

TI6

4

5

6

7

8

VDD2a

35

34

+

−

TO2

+

−

+

−

33

32

31

TO3

+

−

VDD2a

TO4

+

−

PG1

PG2

PG3

9

3 level

+

−

10

11

12

+

−

30

29

28

TO5

+

−

PG4

PG5

PG6

VDD2a

+

−

13

14

3 level

2 level

TO6

+

−

+

−

15

16

BI1

BI2

27

BO1

+

−

2 level

26

25

24

BO2

VDD2b

BI3

BI4

+

−

17

18

BO3

+

−

23

BO4

22

21

20

SUBO

+

−

19

SUBI

Vsb

Vss

Data Sheet S14201EJ1V0DS00

3

µPD16520

1. PIN FUNCTIONS

Pin No.

Pin Name

GND

I/O

−

I

Function

1

Ground

2

V^CC

Logic power supply

3

TI1

3-level driver input (for charge transfer) (See Function

Tables.)

4

TI2

I

5

TI3

I

6

TI4

I

7

TI5

I

8

TI6

I

9

PG1

PG2

PG3

PG4

PG5

PG6

BI1

I

3-level driver input (for charge read) (See Function

Tables.)

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

I

2-level driver input (for charge transfer) (See Function

Tables.)

BI2

I

BI3

I

BI4

I

SUBI

V^SS

I

VOD shutter drive pulse input

V^Lpower supply

−

O

−

O

−

O

−

O

−

O

−

Vsb

V^HHpower supply (for SUB drive)

VOD shutter drive pulse output

2-level pulse output

SUBO

BO4

BO3

VDD2b

BO2

BO1

TO6

VDD2a

TO5

TO4

VDD2a

TO3

TO2

VDD2a

TO1

VDD1

V^SS

V^Mbpower supply (for 2-level driver)

2-level pulse output

3-level pulse output

V^Mapower supply (for 3-level driver)

3-level pulse output

V^Mapower supply (for 3-level driver)

3-level pulse output

V^Mapower supply (for 3-level driver)

3-level pulse output

V^Hpower supply

V^Lpower supply

4

Data Sheet S14201EJ1V0DS00

µPD16520

Function Tables

V^L= V^SS, V^Ma= VDD2a, V^Mb= VDD2b, V^H= VDD1, V^HH= Vsb

Pins TO1 to TO6

Input

Output

Pin Name

Pin No.

TI1 TI2 TI3 TI4 TI5 TI6 PG1 PG2 PG3 PG4 PG5 PG6 TO1 TO2 TO3 TO4 TO5 TO6

3

4

5

6

7

8

9

10

11

12

13

14

36

34

33

31

30

28

L

H

L

V^H

V^Ma

V^L

H

V^L

Pins BO1 to BO4

Input

Output

BO2

26

Pin Name

Pin No.

BI1

15

BI2

16

BI3

17

BI4

18

BO1

27

BO3

24

BO4

23

L

V^Mb

V^L

H

Pin SUBO

Input

SUBI

19

Output

SUBO

22

Pin Name

Pin No.

L

V^HH

H

V^L

Data Sheet S14201EJ1V0DS00

5

µPD16520

2. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T

A

= 25°C, GND = 0 V)

Parameter

Symbol

V^SS

Conditions

Ratings

0.0 to −10

Unit

V

Supply voltage

V^CC

V^SS− 0.3 to V^SS+ 20.0

V^SS− 0.3 to V^SS+ 33.0

V^SS− 0.3 to V^CC+ 0.3

−25 to +85

V

VDD1

VDD2

Vsb

V^I

V

Input pin voltage

V

Operating ambient temperature

Storage temperature

Allowable dissipation

T^A

°C

mW

T^stg

−40 to +125

P^d

500

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on the

verge of suffering physical damage, and therefore the product must be used under conditions that

ensure that the absolute maximum ratings are not exceeded.

Recommended Operating Range (T = 25°C, GND = 0 V)

A

Parameter

Supply voltage

Symbol

V^CC

Conditions

MIN.

2.0

TYP.

15.0

MAX.

5.5

Unit

V

VDD1

VDD1-V^SS

VDD2a

VDD2b

V^SS

Note

10.5

16.5

−1.0

−10.0

21.0

31.0

+4.0

−6.0

31.0

V^CC

V

Vsb-V^SS

V^IH

Note

V

Input voltage, high

0.8V^CC

0

V

Input voltage, low

V^IL

0.3V^CC

+70

V

Operating ambient temperature

T^A

−20

°C

Note Set VDD1 and V^SSto values that satisfy VDD1-V^SSrating.

6

Data Sheet S14201EJ1V0DS00

µPD16520

Electrical Specifications

(Unless otherwise specified, VDD1 = +15 V, VDD2a = 0 V, VDD2b = +1.0 V, Vsb = +21.5 V, V^CC= +2.5 V, V^SS=

−7.0 V, T^A= 25°C, GND = 0 V)

Parameter

Output voltage, high

Output voltage, middle

Symbol

V^H

Conditions

I^O= −20 µA

MIN.

VDD1 −0.1

VDD2a −0.1

VDD2b

V^SS

TYP.

MAX.

VDD1

VDD2a

VDD2b + 0.1

V^SS+ 0.1

Vsb

Unit

V

V^Ma

V^Mb

V^L

I^O= −20 µA

I^O= 20 µA

I^O= −20 µA

I^O= 20 µA

I^O= 10 mA

I^O= ±10 mA

I^O= −10 mA

V

Output voltage, low

V

Output voltage, sub-high

Output voltage, sub-low

Output on-state resistance

V^subH

V^subL

R^L

Vsb − 0.1

V^SS

V

V^SS+ 0.1

30

V

20

30

Ω

R^M

45

Ω

R^H

40

Ω

R^sub

TD1

TD2

TD3

TP1

TP2

TP3

40

Ω

Transmission delay time 1

Transmission delay time 2

Transmission delay time 3

Rise/fall time 1

No load

200

ns

See Figure 2-2 Timing Charts.

200

See Figure 2-1 Output Load

Equivalence Circuit.

500

Rise/fall time 2

500

See Figure 2-2 Timing Charts.

Rise/fall time 3

200

Data Sheet S14201EJ1V0DS00

7

µPD16520

Figure 2-1. Output Load Equivalence Circuit

(a) Between output pins (b) Between output pin and GND

BO4

TO1

BO4

R10

R1

TO1'

BO3

R10

TO2

R1

TO2

BO3

BO4'

C10

TO1'

R2

TO2'

C1

R9

BO3'

R9

C2

C3

C4

BO3'

TO2'

C9

TO3'

R3

TO3

BO2

TO3

R3

TO3'

BO2'

BO2

R8 BO2'

C8

R8

TO4'

C7

C5

R4

BO1'

TO6

C6

BO1'

R7

R4

R7

TO5'

R5

TO6'

TO4'

BO1

TO4

R6

RGND

TO6'

TO5'

TO4

BO1

R5

R6

TO5

TO6

TO5

SUB0

C11

Output Load Capacitance Symbol

TO1'

−

TO2'

C_33

−

TO3'

C_33

−

TO4'

TO5'

TO6'

C_33

−

BO1'

C_32

C_23

C_32

C_23

C_32

C_23

−

BO2'

BO3'

BO4'

C_23

C_32

C_23

C_32

C_23

C_32

C_22

−

GND

C1

TO1'

TO2'

TO3'

TO4'

TO5'

TO6'

BO1'

BO2'

BO3'

BO4'

SUBO

C_33

−

C_33

−

C_23

C_32

C_23

C_32

C_23

C_32

C_22

−

C_32

C_23

C_32

C_23

C_32

C_23

C_22

−

C_33

C_32

C_23

C_32

C_23

−

C2

C_33

C_23

C_32

C_23

C_32

−

C3

C_33

C_32

C_23

C_32

C_23

−

C4

C_33

C_23

C_32

C_23

C_32

−

C5

C_33

C_32

C_23

C_32

C_23

−

C6

C_23

C_32

C_23

C_32

−

C7

C_22

−

C8

C_22

−

C9

C_22

−

C10

C11

−

8

Data Sheet S14201EJ1V0DS00

µPD16520

Output Load Equivalence Circuit Constants

Parameter

Symbol

R1 to R10

Constant

Vertical register serial resistor

0 Ω

Vertical register ground resistor

RGND

C_33

0 Ω

Capacitance 1 between vertical register clocks (3 level-3 level)

Capacitance 2 between vertical register clocks (2 level-2 level)

Capacitance 3 between vertical register clocks (3 level-2 level)

Capacitance 4 between vertical register clocks (2 level-3 level)

Vertical register ground capacitance 1 (3 level)

Vertical register ground capacitance 2 (2 level)

Substrate ground capacitance

0 pF

C_22

C_32

1000 pF

500 pF

C_23

C1 to C6

C7 to C10

C11

3000 pF

1500 pF

1600 pF

Figure 2-2. Timing Charts

BI1 to BI4

TI1 to TI6

TD1

VMb

VMa

BO1 to BO4

TO1 to TO6

VL

TP1

PG1 to PG6

TD2

VH

TO1 to TO6

VMa

TP2

SUBI

TD3

VHH

VL

SUBO

TP3

Data Sheet S14201EJ1V0DS00

9

µPD16520

3. CAUTIONS

3.1 Power ON/OFF Sequence

In the µPD16520, a PN junction (diode) exists between VDD2 → VDD1, input pin (TI1 to TI6, PG1 to PG6, BI1 to

BI4, SUBI) → VCC, so that in the case of voltage conditions: VDD2 > VDD1, input pin voltage (TI1 to TI6, PG1 to

PG6, BI1 to BI4, SUBI) > VCC, an abnormal current flows. Therefore, when turning the power ON/OFF, make sure

that the following voltage conditions are satisfied: VDD2 ≤ VDD1, input pin voltage (TI1 to TI6, PG1 to PG6, BI1 to

BI4, SUBI) ≤ VCC. Also, to minimize the negative potential applied to the SUB pin of the CCD image sensor, following

the power ON/OFF sequence described below.

(1) Power ON

<1> Powering ON VCC

Make sure that input pin voltage (TI1 to TI6, PG1 to PG6, BI1 to BI4, SUBI) ≤ VCC. Also, when Vsb = 2 V,

make sure that VCC reaches the rated voltage.

<2> Powering ON Vsb, VDD1, VDD2a, VDD2b, V^SS

At this time, make SUBI high level (0.8VCC or higher).

Vsb

VDD1

Vcc

2V

VDD2a, VDD2b

0V

<1> <2>

Vss

Time

10

Data Sheet S14201EJ1V0DS00

µPD16520

(2) Power OFF

<1> Powering OFF Vsb, VDD1, VDD2a, VDD2b, VSS

Until VCC power OFF, keep SUBI high level (0.8VCC or higher).

<2> Powering OFF VCC

Power OFF VCC when Vsb becomes 2 V or lower. At this time, make sure that the input pin voltage (TI1 to

TI6, PG1 to PG6, BI1 to BI4, SUBI) ≤ VCC.

<1>

Vsb

VDD1

<2>

Vcc

VDD2a, VDD2b

2V

0V

Vss

Time

3.2. Recommended Connection of Unused Pins

Handle input pins and output pins that are not used as follows.

Input pin:

High level (connect to VCC)

Output pin: Leave open

Data Sheet S14201EJ1V0DS00

11

µPD16520

4. APPLICATION CIRCUIT EXAMPLE

µ

12

Data Sheet S14201EJ1V0DS00

µPD16520

5. PACKAGE DRAWING

38-PIN PLASTIC SSOP (300 mil)

38

20

detail of lead end

G

F

P

L

1

19

A

E

H

I

J

S

B

C

N

S

K

M

D

M

NOTE

Each lead centerline is located within 0.10 mm of

its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS

A

B

C

12.7±0.3

0.65 MAX.

0.65 (T.P.)

+0.05

0.37

D

−0.1

E

F

G

H

I

0.125±0.075

1.675±0.125

1.55

7.7±0.2

5.6±0.2

J

1.05±0.2

+0.1

0.2

K

−0.05

L

M

N

0.6±0.2

0.10

+7°

3°

P

−3°

P38GS-65-BGG

Data Sheet S14201EJ1V0DS00

13

µPD16520

6. RECOMMENDED SOLDERING CONDITIONS

The µPD16520 should be soldered and mounted under the following recommended conditions.

For the details of the recommended soldering conditions, refer to the document Semiconductor Device

Mounting Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact your NEC sales

representative.

Table 6-1. Surface Mounting Type Soldering Conditions

• µPD16520GS-BGG: 38-pin plastic shrink SOP (300 mil)

Soldering Method

Infrared reflow

VPS

Soldering Conditions

Recommended

Condition Symbol

Package peak temperature: 235°C, Time: 30 sec. Max. (at 210°C or higher),

Count: Three times or less

IR35-00-3

Package peak temperature: 215°C, Time: 40 sec. Max. (at 200°C or higher),

Count: Three times or less

VP15-00-3

WS60-00-1

Wave soldering

Partial heating

Solder bath temperature: 260°C, Time: 10 sec. Max., Count: Once,

Preheating temperature: 120°C Max. (package surface temperature)

Pin temperature: 300°C Max., Time: 3 sec. Max. (per pin row)

−

Caution Do not use different soldering methods together (except for partial heating).

14

Data Sheet S14201EJ1V0DS00

µPD16520

NOTES FOR CMOS DEVICES

1

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V^DDor GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

Data Sheet S14201EJ1V0DS00

15

µPD16520

• The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

• No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in

this document.

• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property

rights of third parties by or arising from use of a device described herein or any other liability arising from use

of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other

intellectual property rights of NEC Corporation or others.

• Descriptions of circuits, software, and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these circuits,

software, and information in the design of the customer's equipment shall be done under the full responsibility

of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third

parties arising from the use of these circuits, software, and information.

• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,

the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or

property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety

measures in its design, such as redundancy, fire-containment, and anti-failure features.

• NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a

customer designated "quality assurance program" for a specific application. The recommended applications of

a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device

before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic

equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade,

they should contact an NEC sales representative in advance.

M7 98. 8


型号：	UPD16520GS-BGG
厂家：	NEC
描述：	VERTICAL DRIVER FOR CCD SENSORS 垂直驱动器，用于CCD传感器驱动器传感器 CD
文件：	总16页 (文件大小：102K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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