UPC1909GS-A [NEC]
Dual Switching Controller, 1.2A, 500kHz Switching Freq-Max, BIPolar, PDSO16, 0.300 INCH, PLASTIC, SOP-16;
| 型号： | UPC1909GS-A |
| 厂家： | 
NEC |
| 描述： | Dual Switching Controller, 1.2A, 500kHz Switching Freq-Max, BIPolar, PDSO16, 0.300 INCH, PLASTIC, SOP-16 开关 光电二极管 |
| 文件： | 总36页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µPC1909
SWITCHING REGULATOR CONTROL IC
DESCRIPTION
The µPC1909 is a switching regulator control IC ideal for primary side control of active-clamp typeNote DC/DC
converters. This IC has 2 outputs employing a totem-pole circuit with peak output current 1.2 A, and is capable of
directly driving a power MOS FET. As a result, it has been possible to realize primary side control of an active-clamp
type converter on a single chip.
Note It is necessary to obtain license from Vicor Corporation before using the µPC1909 in an active-clamp type circuit.
FEATURES
•
•
•
•
•
•
2 on-chip outputs; for Q and Q
Capable of directly driving a power MOS FET
Drive supply voltage range: 7 to 24 V
On-chip remote control circuit
On-chip pulse-by-pulse overcurrent protection circuit
On-chip overvoltage latch circuit
ORDERING INFORMATION
Part Number
µPC1909CX
µPC1909GS
Package
16-pin plastic DIP (7.62 mm (300))
16-pin plastic SOP (7.62 mm (300))
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
The mark ★ shows major revised points.
Document No. G14309EJ2V0DS00 (2nd edition)
Date Published November 2000 NS CP(K)
Printed in Japan
©
1999
µPC1909
★
BLOCK DIAGRAM
C
T
R
T
V
REF
DTC
1
FB
12
OUT
11
1
EMI
10
1
V
CC
16
15
14
13
9
PWM
comparator 1
Reference
power
supply
Oscillator
–
+
+
OLS
ON/OFF
control
Over-
Over-
PWM
comparator 2
voltage
current
protection
protection
1
2
3
4
5
6
7
8
OV
C
T2
GND
OC
DTC
2
OUT
2
ON/OFF EMI
2
2
Data Sheet G14309EJ2V0DS00
µPC1909
PIN CONFIGURATION (Top View)
16-pin plastic DIP (7.62 mm (300))
µPC1909CX
16-pin plastic SOP (7.62 mm (300))
µPC1909GS
OV
CT2
1
2
3
16
15
14
CT
RT
GND
OC
VREF
DTC1
4
5
6
7
8
13
12
11
10
9
DTC2
OUT2
FB
OUT1
EMI1
VCC
ON/OFF
EMI2
★
Pin Name
CT
: Timing Capacitance
CT2
: OLS Shift Control
: OUT1 Dead Time Control
: OUT2 Dead Time Control
: OUT1 Emitter
DTC1
DTC2
EMI1
EMI2
FB
: OUT2 Emitter
: Feedback Input
GND
OC
: Ground
: Over Current Protection
: ON/OFF Control
: OUT1 Output
ON/OFF
OUT1
OUT2
OV
: OUT2 Output
: Over Voltage Protection
: Timing Resistance
: Power Supply
RT
VCC
VREF
: Reference Voltage
3
Data Sheet G14309EJ2V0DS00
µPC1909
CONTENTS
1. PIN FUNCTION LIST........................................................................................................................................... 5
2. ELECTRICAL SPECIFICATIONS.........................................................................................................................6
★
3. OPERATION OVERVIEW...................................................................................................................................... 11
3.1 Startup............................................................................................................................................................. 11
3.2 Steady Operation............................................................................................................................................ 13
3.3 Overcurrent Limitation Operation................................................................................................................. 15
3.4 On/Off Operation.............................................................................................................................................16
3.5 Overvoltage Protection Operation................................................................................................................ 17
★
4. SETTINGS..............................................................................................................................................................18
4.1 Controller Settings......................................................................................................................................... 18
4.2 Startup Circuit, Low Voltage Malfunction Prevention Circuit Settings..................................................... 18
4.3 Oscillator Settings.......................................................................................................................................... 21
4.4 Dead Time Setting.......................................................................................................................................... 22
4.4.1 Level shift setting..................................................................................................................................... 22
4.4.2 Dead time adjustment.............................................................................................................................. 24
4.5 Duty Settings...................................................................................................................................................25
4.5.1 Maximum duty setting.............................................................................................................................. 25
4.5.2 Minimum duty limit................................................................................................................................... 25
4.5.3 Soft start...................................................................................................................................................25
4.6 Remote Control...............................................................................................................................................26
4.7 Overcurrent Limiter Settings......................................................................................................................... 27
4.8 Overvoltage Protection Circuit Setting.........................................................................................................28
4.9 Output Circuit..................................................................................................................................................29
5. PACKAGE DRAWINGS........................................................................................................................................30
6. RECOMMENDED SOLDERING CONDITIONS................................................................................................... 32
4
Data Sheet G14309EJ2V0DS00
µPC1909
★
1. PIN FUNCTION LIST
Pin No.
1
Symbol
OV
Function
Overvoltage protection
This is the input pin of the overvoltage detection comparator. Directly connect this pin to GND when not used.
2
CT2
OLS shift setting
The resistor that determines the amount of level shift for dCT (an internal triangle wave that is a level-shifted CT)
is connected between this pin and the VREF pin.
3
4
5
6
7
GND
Ground
This is the signal ground pin.
OC
Overcurrent protection
This is the input pin of the overcurrent detection comparator. Directly connect this pin to GND when not used.
DTC2
OUT2
ON/OFF
OUT2 dead time setting
This pins sets the dead time of the OUT2 output.
OUT2 output
This is the subswitch drive output pin.
ON/OFF control
The output circuit can be switched on or off by inputting an external signal.
Directly connect this pin to VREF when not used.
8
EMI2
OUT2 emitter
This is a power supply ground pin. This pin must be isolated from the signal ground pin (GND).
9
VCC
Power supply
10
EMI1
OUT1 emitter
This is a power supply ground pin. This pin must be isolated from the signal ground pin (GND).
11
12
13
14
15
16
OUT1
FB
OUT1 output
This is the main switch drive output pin.
Feedback input
This is the feedback input pin of PWM comparators 1 and 2.
DTC1
VREF
RT
OUT1 dead time setting
This pin sets the maximum duty of the OUT1 output and determines the minimum duty of the OUT2 output.
Reference voltage
This pin outputs a 4.9-V TYP. reference voltage.
Timing resistance
The resistor that determines the oscillation frequency is connected between this pin and GND.
CT
Timing capacitance
The capacitor that determines the oscillation frequency is connected between this pin and GND.
This pin outputs a triangle wave.
5
Data Sheet G14309EJ2V0DS00
µPC1909
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (Unless otherwise specified, TA = 25°C)
Parameter
Symbol
VCC
µPC1909CX
µPC1909GS
Unit
V
Power Supply Voltage
26
100
1.2
Output Current (DC, per output)
Output Current (peak, per output)
Total Power Dissipation
IC (DC)
IC (peak)
PT
mA
A
1000
694
mW
°C
°C
°C
Operating Ambient Temperature
Operating Junction Temperature
Storage Temperature
TA
−20 to +85
−20 to +150
−55 to +150
TJ
Tstg
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions
Parameter
Power Supply Voltage
Oscillation Frequency
Symbol
VCC
fOSC
CL
MIN.
7
TYP.
10
MAX.
24
Unit
V
50
200
2200
500
kHz
pF
Output Load Capacitance
Timing Resistance
3000
★
★
RT
10
kΩ
°C
Operating Junction Temperature
TJ
−20
+100
Caution The recommended operating range may be exceeded without causing any problems provided
that the absolute maximum ratings are not exceeded. However, if the device is operated in a
way that exceeds the recommended operating conditions, the margin between the actual
conditions of use and the absolute maximum ratings is small, and therefore thorough
evaluation is necessary. The recommended operating conditions do not imply that the device
can be used with all values at their maximum values.
6
Data Sheet G14309EJ2V0DS00
µPC1909
Electrical Characteristics (Unless otherwise specified, TA = 25°C, VCC = 10 V, RT = 10 kΩ, fosc = 200 kHz)
Block
Total
Parameter
Standby Current
Symbol
ICC (SB)
ICC
Conditions
MIN.
TYP.
0.1
12
9
MAX.
Unit
mA
mA
V
VCC = 7 V
Without load
Circuit Current
6
8
3
18
10
5
Under-
Voltage
Lockout
Circuit
Startup Threshold Voltage
VCC (L to H)
VH
Operating Voltage Hysteresis
Width
4
V
Reference
Voltage
Output Voltage
Line Regulation
VREF
IREF = 0 A
4.7
4.9
1
5.1
10
V
REGIN
8 V ≤ VCC ≤ 15 V,
mV
IREF = 0 A
Load Regulation
REGL
1 mA ≤ IREF ≤ 4 mA
6
12
mV
Output Voltage Temperature
Coefficient
∆VREF/∆T
−10°C ≤ TA ≤ +85°C,
400
(700)
µV/°C
IREF = 0 A
Short Circuit Current
IO short
fOSC
IREF = 0 A
15
200
1
mA
kHz
%
Oscillation
Oscillation Frequency
Frequency Line Regulation
180
220
(5)
∆f/∆V
∆f/∆T
8 V ≤ VCC ≤ 15 V
Frequency Temperature
Coefficient
−10°C ≤ TA ≤ +85°C
2
%
PWM
Input Bias Current
IB (COMP1)
IB (COMP2)
VTH (L)
VCOMP1 = VREF
VCOMP2 = VREF
10
10
µA
µA
V
Comparator
Low-level Threshold Voltage
High-level Threshold Voltage
1.5
3.5
3
VTH (H)
V
Dead time Temperature
Coeficient
∆DT/∆T
−10°C ≤ TA ≤ +85°C,
%
VD = 0.46 VREF
Output
Low-level Output Voltage
High-level Output Voltage
Rise Time
VOL
VOH
ISINK = 3 mA
0.5
V
V
V
CC
−
1.6
ISOURCE = 30 mA
tr
RL = 15 Ω, CL = 2200 pF
RL = 15 Ω, CL = 2200 pF
60
40
ns
ns
V
Fall Time
tf
Remote
Control
Input Voltage at Output ON
Input Voltage at Output OFF
Hysteresis Width
VIN (ON)
VIN (OFF)
VH
2.4
2.2
0.1
190
2.6
2.4
0.2
210
200
150
2.4
2.8
2.6
0.3
230
V
V
Overcurrent
Latch
Overcurrent Threshold Voltage
Input Bias Current
VTH (OC)
IB (OC)
td (OC)
VTH (OV)
IB (OV)
VR (OV)
td (OV)
mV
µA
ns
V
VCC = 0 V
Delay to Output
Overvoltage
Latch
Overvoltage Threshold Voltage
Input Bias Current
2
2.8
4
VOV = VREF
µA
V
OVL Reset Voltage
Delay to Output
2
750
ns
Remark Values in parentheses ( ) represent reference values.
7
Data Sheet G14309EJ2V0DS00
µPC1909
Typical Characteristics Curves (Unless otherwise specified, TA = 25°C, VCC = 10 V, Reference Values)
P
T
vs. T
A
Under-Voltage Lockout Circuit
1.2
1.0
0.8
0.6
0.4
0.2
15
12.5
10
µ
µ
PC1909CX
125 °C/W
PC1909GS
7.5
5
180 °C/W
2.5
V
H
V
CC (H to L)
V
CC (L to H)
0
25
50
75
100
125
150
0
2.5
5
7.5
10
12.5
15
T
A
- Ambient Temperature - °C
VCC - Supply Voltage - V
I
CC vs. VCC
ICC vs. VCC (During OVL Operation)
18
16
14
12
10
18
16
14
12
10
V
H
V
H
0.8
0.4
0.8
0.4
f
OSC = 200 kHz
CC (SB)
I
f
OSC = 200 kHz
CC (SB)
I
Without load
0
5
10
15
20
25
0
5
10
15
20
25
V
CC - Supply Voltage - V
VCC - Supply Voltage - V
I
CC(SB) vs. T
A
VOUT1 vs. VIN
250
200
150
100
50
20
15
10
5
µ
V
IN (OFF)
V
IN (ON)
0
−25
0
25
50
75
100
0
1
2
3
4
5
6
T
A
- Ambient Temperature - °C
VIN - Remote Control Voltage - V
8
Data Sheet G14309EJ2V0DS00
µPC1909
VREF vs. TA
∆
fosc vs. RT, CT
30
20
1000
500
10
CT = 220 pF
0
100
50
−10
−20
−30
CT = 1000 pF
CT = 470 pF
∆
−25
0
25
50
75
100
10
50
100
TA - Ambient Temperature - °C
RT - Timing Resistance - kΩ
fosc vs. TA
VOH, VOL vs. TA
VCC
225
220
215
210
205
200
195
190
185
180
175
− 1
VCC
− 1.5
VCC
− 2
1.53
1.49
1.45
−25
0
25
50
75
100
–25
0
25
50
75
100
TA - Ambient Temperature - °C
TA - Ambient Temperature - °C
tf, tr vs. TA (OUT1)
tf, tr vs. TA (OUT2)
100
80
60
40
20
0
100
80
60
40
20
0
fOSC = 555 kHz
fOSC = 555 kHz
tr
tf
tr
tf
−25
0
25
50
75
100
−25
0
25
50
75
100
TA - Ambient Temperature - °C
TA - Ambient Temperature - °C
9
Data Sheet G14309EJ2V0DS00
µPC1909
Duty vs. T
A
45
44
43
42
41
40
39
38
37
36
35
−25
0
25
50
75
100
TA
- Ambient Temperature - °C
10
Data Sheet G14309EJ2V0DS00
µPC1909
★
3. OPERATION OVERVIEW
3.1 Startup
The operating waveforms at startup are shown in Figure 3-1 below. The operations at startup are as follows.
<1> When the power supply voltage (VCC) rises and exceeds the starting voltage (VCC(L to H)), the reference voltage
(VREF) rises.
<2> The DTC1 voltage is boosted as the soft start capacitor is charged (refer to 4.5.3 Soft start).
<3> Because the DTC1 voltage is at a lower potential than other voltages, OUT1 and OUT2 become low and high
level respectively during the T1 period.
<4> If the DTC1 voltage is further boosted so that there is a period in which it is higher than the dCT voltage in the
T2 period, OUT2 becomes low level. In the period in which the DTC1 voltage exceeds CT, OUT1 and OUT2 are
high and low level respectively. The duty of OUT1 increases and that of OUT2 decreases as DTC1 is boosted.
Figure 3-1. Waveforms at Startup
VCC(LtoH)
V
CC
V
H
V
REF
FB
CT
dC
T
V
TH(H)
V
TH(L)
DTC
2
DTC
1
OUT
OUT
1
2
T
1
T
2
11
Data Sheet G14309EJ2V0DS00
µPC1909
Signal Name
OUT1
Function
Output for main switch
Signal Name
OUT2
Function
Output for subswitch
DTC1
Voltage for setting maximum duty limit of OUT1 DTC2
Voltage for setting maximum duty limit of OUT2
Triangle wave generated by oscillator
FB
Feedback voltage of converter output
CT
dCT
Triangle wave that is CT level-shifted via the
level shift circuit (OLS)
Remarks 1. The oscillation frequency of CT is determined by the external capacitor connected to the CT pin and the
external resistor connected to the RT pin (refer to 3.3 Overcurrent Limitation Operation). CT is a
symmetrical triangle wave with a trough voltage (low-level threshold voltage VTH(L)) of 1.5 V and a crest
voltage (high-level threshold voltage VTH(H)) of 3.5 V. Note that the dCT voltage cannot be viewed
externally.
2. In the T1 and T2 periods in Figure 3-1, the FB voltage level rises as the converter output voltage is boosted,
with the result that the converter voltage cannot be controlled by FB.
12
Data Sheet G14309EJ2V0DS00
µPC1909
3.2 Steady Operation
The operating waveforms during steady operation are shown in Figure 3-2 below. Steady operation as used here refers
to the state in which the overcurrent and overvoltage latches are not working. The operations that occur during steady
operation are as follows.
<1> When the converter is operating at the rated input and output, the FB voltage is between DTC1 and DTC2 (in
the T3 period in Figure 3-2).
•The FB voltage and CT triangle wave are compared by PWM comparator 1. OUT1 is high level when the FB
voltage is higher than the CT voltage.
•The FB voltage and level-shifted dCT triangle wave are compared by PWM comparator 2. OUT2 is high level
when the FB voltage is lower than the dCT voltage.
<2> Because the input voltage becomes lower as the load of the converter is increased, there is a period when the
FB voltage rises and the OUT1 duty increases (the T4 period in Figure 3-2).
When the FB voltage is greater than the DTC1 voltage, OUT1 operates at the maximum duty determined by
DTC1. At this time also, OUT2 operates at the minimum duty determined by DTC1.
<3> Because the input voltage becomes higher as the load of the converter is decreased, there is a period when
the FB voltage falls and the OUT1 duty decreases (the T5 period in Figure 3-2).
When the FB voltage is less than the DTC2 voltage, OUT2 operates at the maximum duty determined by DTC2.
Figure 3-2. Waveforms During Steady Operation
CT
dCT
Vd
DTC
FB
DTC
1
2
OUT
1
2
OUT
T
3
T
4
T
5
13
Data Sheet G14309EJ2V0DS00
µPC1909
For the dCT level shift amount and the OUT1 and OUT2 dead time settings, refer to 4.4 Dead Time Setting.
The relationship between the FB, DTC1, and DTC2 voltages in each operating state and the pins that determine the duty
of OUT1 and OUT2 are shown in Table 3-1 below. For the duty settings, refer to 4.5 Duty Settings.
Table 3-1. Relationship Between Pins That Determine Duty During Steady Operation
Operating Status
Voltage Relationship
DTC2 < FB < DTC1
DTC2 < DTC1 < FB
FB < DTC2 < DTC1
Pin That Determines
OUT1 Duty
Pin That Determines
OUT2 Duty
Steady operation 1
T3
T4
T5
FB
DTC1
FB
FB
(rated status)
Steady operation 2
DTC1
DTC2
(heavy load, low input)
Steady operation 3
(light load, high input)
14
Data Sheet G14309EJ2V0DS00
µPC1909
3.3 Overcurrent Limitation Operation
The internal configuration of the overcurrent latch circuit is shown in Figure 3-3 below.
Figure 3-3. µPC1909 Overcurrent Latch Circuit
Overcurrent detection comparator
Flip-flop
OC
4
S
R
Q
To output circuit of OUT
To PWM comparator 2
1
V
TH(OC)
CT
16
3 V
If a voltage that exceeds the overcurrent detection voltage (VTH(OC) = 210 mV TYP.) is input to the OC pin, OUT1 is
latched to low level, and then OUT2 is latched to high level. The time between the detection of overcurrent and when
OUT1 becomes low level is the overcurrent detection delay time. Moreover, if the voltage of the CT pin exceeds 3.0 V, the
reset signal will be input to the flip-flop, and the latch status of OUT1 and OUT2 will be reset. When the OC pin voltage
reaches the overcurrent detection voltage, even in the cycle in which the latch status was reset, the latch and reset
operations will be repeated. In other words, the pulse width is limited every cycle (pulse-by-pulse current limitation).
The waveforms when overcurrent limitation is operating are shown in Figure 3-4 below.
Figure 3-4. Waveforms When Overcurrent Limitation Is Operating
Reset voltage (3 V)
dCT
CT
DTC
1
FB
DTC
2
V
TH(OC)
OC
t
d(OC)
OUT
OUT
1
2
T
6
15
Data Sheet G14309EJ2V0DS00
µPC1909
3.4 On/Off Operation
The output of OUT1 and OUT2 can be made low level (off) by making the voltage of the ON/OFF pin low level. This
also causes discharge of the soft start capacitor externally connected to the DTC1 pin and the timing capacitor externally
connected to the CT pin.
To prevent chattering when turning on and off slowly, the threshold voltage of the ON/OFF pin has a 0.2-V hysteresis.
The waveforms during the on/off operation are shown in Figure 3-5 below.
Figure 3-5. Waveforms During On/Off Operation
Discharge of C
T
, DTC
1
CT
dCT
DTC
1
FB
DTC
2
DTC
1
V
IN(ON)
ON/OFF
V
IN(OFF)
OUT
OUT
1
2
T
7
T
8
16
Data Sheet G14309EJ2V0DS00
µPC1909
3.5 Overvoltage Protection Operation
The overvoltage latch circuit is a protection circuit that stops the power supply to prevent damage to the load after
detection of overvoltage caused by abnormal boosting of the output of the converter.
The internal configuration of the overvoltage latch circuit is shown in Figure 3-6 below.
Figure 3-6. µPC1909 Overvoltage Latch Circuit
Overvoltage detection comparator
Flip-flop
OV
1
S
R
Q
To output circuit of OUT
1, OUT
2
V
TH(OV)
VREF 14
The threshold voltage (VTH(OV)) connected to the overvoltage detection comparator is 2.0 to 2.8 V (2.4 V TYP.). If the
voltage of the OV pin exceeds VTH(OV), OUT1 and OUT2 are latched to low level. The waveforms when OV (overvoltage)
occurs are shown in Figure 3-7 below.
To reset the status of the overvoltage latch, drop the voltage of the VCC pin to below the OVL release voltage (VR(OV) =
2 V TYP.), and drop the voltage of the VREF pin to a sufficiently low level.
Figure 3-7. Waveforms When Overvoltage Latch Is Operating
dCT
CT
DTC
1
FB
DTC
2
VTH(OV)
OV
t
d(OV)
OUT
1
2
OUT
T9
17
Data Sheet G14309EJ2V0DS00
µPC1909
★
4. SETTINGS
4.1 Controller Settings
The feedback circuit for when the converter output voltage is detected on the secondary side is configured as shown in
Figure 4-1 below. The feedback gain is primarily determined by the R1 resistor.
Figure 4-1. Feedback Circuit Configuration
V
REF
14
12
R1
PWM comparator 1
To output circuit of OUT
FB
1
I
K
Photo-
coupler
From comparator output
To output circuit of OUT
PWM comparator 2
2
GND
3
Shunt regulator
The voltage of the FB pin is input to PWM comparators 1 and 2.
During steady operation (DTC2 < FB < DTC1), the duty of OUT1 and OUT2 is determined by the slice level of the
triangle wave based on the FB pin voltage.
Caution When using a shunt regulator such as the µPC1093 for the secondary-side detector, Ik must be
set bearing in mind the variation of the CTR in the photocoupler. Also, be sure to use the
photocoupler grounded at the emitter ground.
4.2 Startup Circuit, Low Voltage Malfunction Prevention Circuit Settings
The startup circuit is configured as shown in Figure 4-2 below.
Figure 4-2. Startup Circuit
VCC IN
R2
D1
9
V
CC
N
P
NZ
14 VREF
13 DTC
Primary coil
C1
C
2
R
3
4
1
C3
R
3
GND
18
Data Sheet G14309EJ2V0DS00
µPC1909
In the µPC1909, when the power supply voltage (VCC) rises but is less than the operation start voltage (VCC(L to H)),
a current of about 100 µA flows as a standby current.
When VCC reaches or exceeds VCC(L to H), the internal reference voltage (VREF) rises and operating current is supplied to
the internal circuits, increasing the circuit current (ICC) to a level of about 12 mA.
In the startup circuit in Figure 4-2, ICC(SB) is supplied via a startup resistor (R2), and when the power MOS FET is turned
on after the µPC1909 is started up, ICC is supplied from a capacitor (C1) until voltage reaches the auxiliary coil. R2 is
determined using ICC(SB) as follows.
VIN(MIN.) − VCC(LtoH)(MAX.)
R2
ICC(SB)(MAX.) + IREF
If R2 is too small, the loss via R2 during steady operation will be large. The loss via R2 during steady operation (PL(MAX.))
is shown below. In this equation, NZ is the number of turns in the power supply auxiliary coil, NP is the number of turns in
the primary coil, and VF(D1) is the forward direction voltage drop in the diode (D1).
2
{(1 − N
Z
/N )·VIN(MAX.) + VF(D1)}
P
P
L(MAX.)
=
R2
Note that a film or other capacitor (C2) with good high-frequency characteristics should be connected to prevent a high-
frequency current flowing through the VCC line when the power MOS FET is driven.
To apply a soft start, connect a soft start capacitor (C3) between the DTC1 pin and GND. Using the overcurrent limitation
function of the OC pin allows the duty to be limited on a pulse-by-pulse basis, enabling a more secure soft start.
The time between the startup of the µPC1909 and the first output of OUT1 (t1) is expressed as follows.
C3 · R3
1 + R3 / R4
t1 = −
ln {1 − (1 + R3 / R4)·(VTH(L) / VREF)}
Although VCC drops in the t1 period, C1 is determined so that OUT1 is output while the drop voltage has not fallen to the
operating voltage hysteresis width VH. At this time, because OUT2 is output before OUT1 (refer to 3.1 Startup), C1 must
be set to compensate for the increase in current caused by the output of OUT2. Refer to Figure 3-1. Waveforms at Startup
for the operating waveforms.
I
CC + IREF + IOUT − I
C1
>
CC(R) · t
1
V
H
Here, IREF is the current that flows through the resistor with the maximum duty setting connected to the VREF pin, IOUT is
the power MOS FET drive current, and ICC(R) is the current that is supplied from the startup resistor (R2).
19
Data Sheet G14309EJ2V0DS00
µPC1909
Note that when the rising of VREF is later than the rising of VCC at startup, OUT1 and OUT2 become high level
simultaneously when VREF is in a range of about 0.45 to 0.5 V, which may result in the external power MOS FET being
inadvertently turned on. To prevent this, speed up the rising of VREF by pulling it up to VCC with a resistor. Note, however,
that the standby current (ICC(SB)) will increase by only the current that flows through the connected resistor.
The pull-up resistance value (R) can be calculated from the following equation.
V
CC(MAX.) [V] − 0.5
R [kΩ] =
0.1 [mA]
Remark VCC(MAX.): The highest power supply voltage that can be applied at startup without causing malfunction.
For the same reason, if VCC drops below the operation stopped voltage (VCC(L to H) – VH), VREF and the constant current
circuit will be cut-off, which weakens the drive capacity of the OUT1 and OUT2 outputs when the power supply is cut-off.
If this drive capacity is weakened, the charge that has accumulated at the power MOS FET gates may not be sufficiently
discharged, blunting the falling section of the power MOS FET gate drive waveform. In this case, connecting a capacitor
of at least 0.47 µF between the VREF pin and GND allows sufficient time and output block drive capacity to discharge the
charge accumulated at the gates of the power MOS FET.
Because the operation start and stop voltages in the µPC1909 are 9 V TYP. and 5 V TYP. respectively, VREF is output
while operation is stopped until VCC is 5 V or lower. However, when VCC reaches about 6.5 V, VREF falls together with
VCC, as can be seen in Figure 4-3. When VREF falls, the constant current value of the triangle wave oscillator decreases,
causing the oscillation frequency to drop.
Figure 4-3. VREF vs. VCC Characteristics
6
TA = 25°C
5
4
3
2
1
I
REF = 0 A
I
REF = 10 mA
V
CC(L to H)
V
H
0
1
2
3
4
5
6
7
8
9
10
V
CC - Supply Voltage - V
In standard applications, VREF is resistance-divided to create the DTC1, DTC2, and FB voltages. In addition, because
the levels of the triangle wave (CT) and internally level-shifted triangle wave (dCT) are also generated internally by
dividing the resistance of VREF, if VREF drops, each of the above will drop in proportion to VREF. As a result, even if the
oscillation frequency drops, standard applications are not affected. Further study will be required, however, including for
transient states.
20
Data Sheet G14309EJ2V0DS00
µPC1909
4.3 Oscillator Settings
The oscillator circuit is shown in Figure 4-4 below.
Figure 4-4. µPC1909 Oscillator Circuit
V
REF
14
Comparator H
Flip-flop
Tr
1
S
R
Q
I
CT
R
T
T
15
16
V
TH(H)
C
Tr
3
Tr
2
2·ICT
Comparator L
TH(L)
RT
CT
V
GND
3
A timing resistor (RT) is connected between the RT pin and GND, and a timing capacitor (CT) is connected between the
CT pin and GND. The charge/discharge current of CT is determined by RT. The oscillator operates as follows.
<1> If ICT is taken as the current that flows through Tr1, the current the flows through Tr3 is set as 2 x ICT. Because
the flip-flop (Q) outputs a high level at startup, Tr2 is off, and CT is charged with ICT.
<2> When the CT voltage reaches VTH(H) = 3.5 V TYP., the output of comparator H is inverted, and Tr2 is turned on.
Due to the discharging of the current set by 2 x ICT, the current flowing through CT is (ICT – 2 x ICT) = – ICT, so
CT is discharged by ICT.
<3> If the CT voltage drops to VTH(L) = 1.5 V TYP., the output of comparator L is inverted, the flip-flop is reset, and
CT is recharged because Tr2 is off.
<4> <2> and <3> are repeated, generating a triangle wave with an amplitude of 1.5 to 3.5 V.
The oscillation frequency can be approximated from the following equation.
1 × 106
f
OSC
[kHz]
0.8251 × C
T
[pF] × (R [kΩ] + 0.8) + 320
T
21
Data Sheet G14309EJ2V0DS00
µPC1909
The results of measuring fOSC vs. RT are shown in Figure 4-5 below, with CT as the parameter.
Figure 4-5. Relationship Between Oscillation Frequency (fOSC), Timing Capacitor (CT) and Timing Resistor (RT)
1000
500
CT = 220 pF
100
50
CT
= 1000 pF
CT = 470 pF
10
50
- Timing Resistance - kΩ
100
RT
4.4 Dead Time Setting
The period in which OUT1 and OUT2 are simultaneously off is called dead time. This is an important parameter to
realize a zero-cross switch when active-clamping. To set the dead time, it is necessary to adjust both the oscillation
frequency and level shift parameters (for details of the oscillation frequency setting, refer to 4.3 Oscillator Settings).
4.4.1 Level shift setting
Whichever is higher of the DTC2 pin and FB pin voltages is compared with the triangle wave that is the internally level-
shifted wave of the CT pin (dCT). OUT2 is high level while dCT is higher than the DTC2 and FB voltages.
The triangle wave dCT, which controls OUT2, is generated by internally level-shifting the CT wave on the low potential
side. The amount of shift (Vd) is determined using the resistor (RCT2) connected between the CT2 and VREF pins.
Vd can be calculated from the following equation.
2 × 4.2
RCT2 [kΩ] + 10
Vd
[V]
A general diagram of the level shift circuit (OLS) is shown in Figure 4-6, and the relationship between the oscillation
frequency (fOSC), the dead time (tqd), and resistor RCT2 is shown in Figure 4-7.
22
Data Sheet G14309EJ2V0DS00
µPC1909
Figure 4-6. µPC1909 Level Shift Circuit (OLS)
V
REF
14
16
PWM comparator 1
To output circuit of OUT
1
CT
RCT2
PWM comparator 2
To output circuit of OUT
C
T2
2
3
2
GND
Figure 4-7. Relationship Between fOSC, tqd and RCT2
100
10
1
V
CC = 10 V
FB = 2.5 V
R
CT2 = 5 kΩ
CT2 = 10 kΩ
CT2 = 20 kΩ
R
R
µ
R
CT2 = 50 kΩ
OUT
1
2
50%
t
qd
0.1
RCT2 = 100 kΩ
OUT
50%
RCT2 = 200 kΩ
R
CT2 = 300 kΩ
0.01
10
100
1000
f
osc - Oscillation Frequency - kHz
23
Data Sheet G14309EJ2V0DS00
µPC1909
4.4.2 Dead time adjustment
The dead time between the fall of OUT1 and the rise of OUT2 (tqc) and the dead time between the fall of OUT2 and the
rise of OUT1 (tqd) is determined by the oscillation frequency and the amount of level shift of the triangle wave.
Although usually tqc = tqd, if these values differ, connect a suitable resistor between the CT pin and the VREF pin, as well
as between the CT pin and GND, and adjust the dead time by making the oscillation waveform asymmetrical, as shown
in Figure 4-8.
Figure 4-8. Dead Time Adjustment
(a) tqc < tqd
dC
(b) tqc > tqd
CT
T
dCT
CT
14 VREF
14 VREF
FB
FB
R1
16 C
T
16 C
T
CT
R2
CT
OUT
1
2
OUT
OUT
1
2
3
GND
3 GND
RT
RT
OUT
15 R
T
15 R
T
t
qc
t
qd
t
qc
t
qd
The charge current (ICT) of the timing capacitor (CT) is expressed as follows.
4.2
800 + R
I
CT [A] =
T
[Ω]
If RT is taken as 20 kΩ, ICT will be approximately 200 µA.
To reduce tqc, connect a resistor (R1) between the VREF and CT pins. If the value of the resistor is set so that the current
charged in CT is about 10% more than ICT, tqc can be reduced and tqd increased by about 10% compared to when R1 is
not connected.
R1 here can be calculated from the following equation.
VREF [V] − VOSC [V]
R1 [Ω] =
∆
ICT [A]
Remark VOSC : Central voltage value of triangle wave
∆ICT : Value of ICT current increased (decreased) by R1 (R2)
Note also that connecting a resistor (R2) between CT and GND makes it possible to reduce the current charged to CT.
If a resistor is selected that allows about 10% current to flow, tqc can be increased and tqd reduced by about 10%
compared to when R2 is not connected.
R2 here can be calculated from the following equation.
V
∆
OSC [V]
R2 [Ω] =
I
CT [A]
24
Data Sheet G14309EJ2V0DS00
µPC1909
4.5 Duty Settings
4.5.1 Maximum duty setting
In the steady operation state (DTC2 < FB < DTC1), the duty during operation at the FB voltage is determined by OUT1
and OUT2. To set the duty as an independent FB input at times such as at startup, during low voltage input, and when the
current is limited, the OUT1 and OUT2 outputs must be set to their maximum duty values. Set the maximum duty for OUT1
and OUT2 via the DTC1 and DTC2 pins, respectively, as shown in Figure 4-9.
Figure 4-9. Maximum Duty Settings in µPC1909
14 VREF
13 DTC
1
5
3
DTC
2
GND
Note that when pulse-by-pulse current limitation is being applied using the OC pin, the maximum duty of OUT1 should be
set to between 60 and 65%. This is because the duty conversion of OUT1 sets the reset level of the internal OC circuit to
about 75%. For details, refer to 4.7 Overcurrent Limiter Settings.
There is no limit to the maximum duty of OUT2.
4.5.2 Minimum duty limit
When OUT1 is operating at maximum duty, if OUT2 is not output, it may inadvertently be set to a duty of 0%, depending
on the value of “OUT1 ON time + tqc + tqd”. If OUT2 has 0% duty when active clamping, the transformer will not be able to
be reset, and a minimum duty limit will have to be set for OUT2 at the same time the maximum duty of OUT1 is
determined. Because the DTC1 pin is also the input of PWM comparator 2 on the OUT2 side, if the FB voltage is higher
than the DTC1 voltage, the DTC1 voltage is compared with dCT and the minimum duty of OUT2 is limited.
4.5.3 Soft start
This IC incorporates a transistor for discharging the soft start capacitor connected between the DCT1 pin and GND. If
VCC falls below the operation stopped voltage (5 V TYP.) or if the ON/OFF pin becomes low level (off), the DTC1 pin
becomes low level and the soft start capacitor is initialized.
There is no such transistor incorporated on the DTC2 side.
25
Data Sheet G14309EJ2V0DS00
µPC1909
4.6 Remote Control
In the µPC1909, starting up and stopping a converter can be controlled by turning on and off the output circuit using an
external signal. When the ON/OFF pin is made low level, the low voltage malfunction protection circuit operates and
cuts off OUT1 and OUT2, causing the timing capacitor connected between the CT pin and GND (CT) and the soft start
capacitor connected between the DTC1 pin and GND to discharge. Because the on/off threshold voltage has 0.2-V
hysteresis, the occurrence of chattering can be suppressed, even in slow on/off operations.
The ON/OFF pin is internally pulled up to VREF via a 100 kΩ resistor. When the on/off function is not used, however, be
sure to connect the ON/OFF pin directly to the VREF pin in order to prevent the occurrence of noise.
A configuration whereby on/off control is controlled from the primary side by a photocoupler is shown in Figure 4-10
below. Be sure to set the pull-down resistor connected to the ON/OFF pin so that the leakage current between C and E
when the photocoupler is off does not cause the ON/OFF pin voltage to be boosted to a level whereby the µPC1909 is
turned on.
Figure 4-10. ON/OFF Pin Connection
V
REF
14
7
100 kΩ
ON/OFF
GND
Photo-
coupler
2.6 V/2.4 V
3
26
Data Sheet G14309EJ2V0DS00
µPC1909
4.7 Overcurrent Limiter Settings
The OC pin in the µPC1909 allows the realization of a pulse-by-pulse overcurrent limiter, whose configuration is shown
in Figure 4-11 below.
Figure 4-11. µPC1909 Overcurrent Limiter
PWM comparator 1
Main switch
Output circuit of OUT
1
1 11
OUT
Overcurrent detection comparator
OC
4
S
Q
I
B(OC)
R
V
TH(OC)
C
T 16
Flip-flop
Threshold voltage (3 V TYP.)
GND
3
If overcurrent is detected by the overcurrent detection comparator, OUT1 is latched to low level by the flip-flop.
Moreover, if the triangle wave generated by the oscillator and a voltage with a threshold value that causes the output
latch to be reset are input to the other comparator the flip-flop will be reset at each cycle.
Because the reset threshold voltage is internally set to 3 V TYP. (about 75% VREF), if a maximum duty of 75% or over is
set by the DTC1 pin thus activating overcurrent limitation by the OC pin, two pulses will be inadvertently output in one
cycle. To allow for differences in ICs, do not set the maximum duty of DTC1 (60% or over) to more than 65% when
applying overcurrent limitation using the OC pin. Alternatively, do not use OC pin overcurrent limitation if setting the
maximum duty (60% or over) to more than 65%. In this case (overcurrent limitation current not used), connect the OC pin
directly to GND.
Discharge current flows through the OC pin. This discharge current is expressed as the input bias current of the
overcurrent latch block (IB(OC)). Although a filter is attached to the OC pin to prevent the overcurrent latch circuit from
malfunctioning due to the surge current that flows when the power MOS FET is turned on, be sure to set the resistor to
no more than 100 Ω to stop IB(OC) causing a shift in the overcurrent detection point.
When overcurrent is being limited by the OC pin, OUT1 operates at the minimum pulse width limitable by the
overcurrent latch circuit. The minimum pulse width is the sum of the µPC1909’s overcurrent detection delay time (td(OC)),
the delay of the filter attached to the OC pin, and the turn-on time of the power MOS FET.
During steady operation (DTC2 < FB < DTC1), OUT2 operates at the duty determined by the FB voltage. Because the
FB voltage rises when the output of the converter drops, the duty of the OUT2 output drops in line with the converter
output, until it reaches the minimum duty set by the DTC1 voltage.
27
Data Sheet G14309EJ2V0DS00
µPC1909
4.8 Overvoltage Protection Circuit Setting
The overvoltage protection circuit based on the overvoltage latch in the µPC1909 is configured as shown in Figure 4-
12 below. The threshold voltage connected to the overvoltage detection comparator (VTH(OV)) is 2.0 to 2.8 V (2.4 V
TYP.). If the input at the OV pin exceeds VTH(OV), the flip-flop in the IC latches OUT1 and OUT2 to low level. Once the
overvoltage latch circuit is latched, it is not released until the power supply voltage of the IC (VCC) falls below the OVL
release voltage (2 V TYP.) (because ICC is higher than ICC(SB) when the circuit is latched, the operation status will not be
restored in the steady input state).
Figure 4-12. µPC1909 Overvoltage Protection Circuit
V
CC
Reference
voltage
9
Photo-
coupler
V
REF 14
From converter output
Overvoltage detection comparator
Flip-flop
OV
1
To output circuit
of OUT , OUT
S
R
Q
I
B(OV)
1
2
V
TH(OV)
GND
3
Zener diode
Discharge current flows through the OV pin. This is the input bias current of the overvoltage latch block in the electrical
specifications (IB(OV) = 4 µA MAX.). To prevent the detection level fluctuating due to IB(OV), and to allow for the effect of
the leakage current between C and E in the photocoupler, be sure to set the overvoltage detection resistor connected to
the OV pin to no more than 100 kΩ.
Because the OVL (overvoltage latch) detection delay time is about 750 ns, a capacitor with good frequency
characteristics should be connected between the OV pin and GND to prevent malfunction due to noise. However, if the
overvoltage latch circuit does malfunction due to electrostatic discharge or other such external noise, an effective
countermeasure is to connect a capacitor with good frequency characteristics such as a film capacitor between VCC and
GND.
Caution If the power is reapplied immediately after being stopped (VREF drop) while there is charge remaining
in the filter’s capacitor (such as when VCC (auxiliary coil voltage) is being monitored from VREF without
configuring an overvoltage protection circuit such as is shown in Figure 4-12), the overvoltage latch
threshold value will be boosted in proportion with the boosting of VREF, possibly causing the over-
voltage latch to latch too easily.
28
Data Sheet G14309EJ2V0DS00
µPC1909
4.9 Output Circuit
The output circuit is a totem-pole output with a peak output current rating (IC(peak)) of 1.2 A. Although a power MOS FET
can be driven directly, be careful not to exceed the allowable loss of the µPC1909 when the input capacitance of the
power MOS FET is large or the operating frequency is high. The switching speed of the power MOS FET is determined by
the charge/discharge current of the gates and the charge of the power MOS FET’s gates. Be sure, however, to insert a
series resistor at the gates of the power MOS FET to avoid exceeding the peak output current rating of the µPC1909.
Note that the heat generated in the µPC1909 by the output current is determined by the charge at the gates of the power
MOS FET, and is not related to the switching speed.
Figure 4-13. 2SK1954 Gate Change Characteristics
When the 2SK1954 is used, for example, the loss of the
160
140
120
100
80
16
14
12
10
8
µPC1909 (Pd) can be determined as follows,
when the gate drive voltage VGS VOUT1 = 10 V and
the oscillation frequency fOSC = 200 kHz,
V
GS
V
DD = 140 V
90 V
36 V
as shown in the gate charge graph on the right (Figure 4-13):
Pd = QG · VGS · fOSC
=10 [nC] x 10 [V] x 200 [kHz]
=0.02 [W]
60
6
40
4
V
DS
Moreover, when the µPC1909 and the power MOS FET are
separated, the wiring from the OUT1 and OUT2 output pins is
lengthened, which combined with the parasitic inductance and
floating capacitance elements of the power MOS FET causes
20
2
0
I
D
= 4 A
14
0
2
4
6
8
10
12
16
Q
G
- Gate Charge - nC
the voltage of the OUT1 and OUT2 pins to fall below that of the GND pin (undershoot). In this case, clamp the undershoot
by connecting a Schottky barrier diode as shown in Figure 4-14 to prevent the possibility of malfunction in the µPC1909.
Figure 4-14. Power MOS FET Drive Circuit Block
Schottky barrier diode
µPC1909
OUT
1
(Pin No.11),
OUT
2
(Pin No.6)
GND
3
Shunt resistor
EMI
EMI
1
(Pin No.10),
(Pin No.8)
2
Note that when active clamping, if the C-cut drive transistor is driven by OUT2, the voltage of the OUT2 pin may become
higher than VCC. It is therefore vital to observe VOUT2 ≤ VCC + 5 V by taking action such as connecting a diode between
OUT2 and VCC.
29
Data Sheet G14309EJ2V0DS00
µPC1909
★
5. PACKAGE DRAWINGS
16-PIN PLASTIC DIP (7.62mm(300))
16
9
1
8
A
J
K
L
P
I
F
C
B
H
R
M
M
N
D
G
NOTES
ITEM MILLIMETERS
1. Each lead centerline is located within 0.25 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
G
H
I
20.32 MAX.
1.27 MAX.
2.54 (T.P.)
0.50±0.10
1.1 MIN.
2. Item "K" to center of leads when formed parallel.
3.5±0.3
0.51 MIN.
4.31 MAX.
5.08 MAX.
7.62 (T.P.)
6.5
J
K
L
+0.10
0.25
M
−0.05
N
P
R
0.25
1.1 MIN.
0
15°
P16C-100-300B-2
30
Data Sheet G14309EJ2V0DS00
µPC1909
16-PIN PLASTIC SOP (7.62 mm (300))
16
9
detail of lead end
P
1
8
A
H
I
F
G
J
S
B
L
N
S
K
C
D
M
M
E
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
A
B
C
10.2±0.2
0.78 MAX.
1.27 (T.P.)
+0.08
0.42
D
−0.07
E
F
G
H
I
0.1±0.1
1.65±0.15
1.55
7.7±0.3
5.6±0.2
1.1±0.2
J
+0.08
0.22
K
−0.07
L
M
N
0.6±0.2
0.12
0.10
+7°
3°
P
−3°
P16GM-50-300B-6
31
Data Sheet G14309EJ2V0DS00
µPC1909
6. RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering
processes are used, or if the soldering is performed under different conditions, please make sure to consult with our
sales offices.
For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL"(C10535E).
Type of Through-hole Device
µPC1909CX: 16-pin plastic DIP (7.62 mm (300))
Soldering Method
Wave soldering (pins only)
Partial heating
Soldering Conditions
Solder bath temperature : 260°C MAX., Time : 10 seconds MAX.
Pin temperature : 300°C MAX., Time : 3 seconds MAX. (per pin)
Caution For through-hole device, the wave soldering process must be applied only to leads, and make
sure that the package body does not get jet soldered.
Type of Surface Mount Device
µPC1909GS: 16-pin plastic SOP (7.62 mm (300))
Recommended
Soldering Method
Soldering Conditions
Condition symbol
Infrared reflow
Package peak temperature : 235°C, Time : 30 seconds MAX.
(at 210°C or higher), Count : Twice or less
IR35-00-2
VPS
Package peak temperature : 215°C, Time : 40 seconds MAX.
(at 200°C or higher), Count : Twice or less
VP15-00-2
WS60-00-1
Wave soldering
Soldering bath temperature : 260°C or less, Time : 10 seconds
MAX., Count : Once, Preheating temperature : 120°C MAX.
(package surface temperature)
Caution Do not use different soldering methods together.
32
Data Sheet G14309EJ2V0DS00
µPC1909
[MEMO]
33
Data Sheet G14309EJ2V0DS00
µPC1909
[MEMO]
34
Data Sheet G14309EJ2V0DS00
µPC1909
[MEMO]
35
Data Sheet G14309EJ2V0DS00
µPC1909
•
The information in this document is current as of November, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
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NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
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patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
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While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
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Customers must check the quality grade of each semiconductor product before using it in a particular
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"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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