MX26L6411TC-10 [Macronix]
EEPROM;
| 型号： | MX26L6411TC-10 |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总44页 (文件大小：320K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCED INFORMATION
MX26L6411
64M[x16] SINGLE3VPAGEMODEMTPMEMORY
FEATURES
• 2.7V to 3.6V operation voltage
• Block Structure
• High Performance
- Block erase time: 2s typ.
- 64 x 64Kword Erase Blocks
- Byte programming time: 210us typ.
- Block programming time: 0.8s typ. (using Write to
Buffer Command)
• Fast random / page mode access time
- 100/30 ns Read AccessTime (page depth:8-word)
• 128-bit Protection Register
• Program/Erase Endurance cycles: 100 cycles
- 64-bit Unique Device Identifier
- 64-bit User Programmable OTP Cells
• 16-WordWrite Buffer
Software Feature
• Support Common Flash Interface (CFI)
- MTP device parameters stored on the device and
- 14 us/word Effective Programming Time
• Enhanced Data Protection Features Absolute Protec-
tion with VPEN = GND
provide the host system to access.
• Automation Suspend Options
- Block Erase Suspend to Read
- Block Erase Suspend to Program
- Program Suspend to Read
- Flexible Block Locking
- Block Erase/Program Lockout during PowerTransi-
tions
Performance
Packaging
• Low power dissipation
- 48-LeadTSOP
- typical 15mA active current for page mode read
- 80uA/(max.) standby current
- Deep power-down current: 5uA
Technology
- Two bits per cell Nbit (0.25u) MTPTechnology
electrical erasure and programming.The device uses a
command register to manage this functionality.
GENERAL DESCRIPTION
The MXIC's MX26L6411 series MTP use the most ad-
vance 2 bits/cell Nbit technology, double the storage ca-
pacity of memory cell.The device provide the high den-
sity MTP memory solution with reliable performance and
most cost-effective.
The MXIC's Nbit technology reliably stores memory con-
tents even after the specific erase and program cycles.
The MXIC cell is designed to optimize the erase and
program mechanisms by utilizing the dielectric's charac-
ter to trap or release charges from ONO layer.
The device organized as by 16 bits of output bus. The
device is packaged in 48-Lead TSOP. It is designed to
be reprogrammed and erased in system or in standard
EPROM programmers.
The device uses a 2.7V to 3.6V VCC supply to perform
the High Reliability Erase and auto Program/Erase algo-
rithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
The device offers fast access time and allowing opera-
tion of high-speed microprocessors without wait states.
The device augment EPROM functionality with in-circuit
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MX26L6411
PIN CONFIGURATION
48-TSOP (12mm x 20mm)
WE
A16
A15
A14
A13
A12
A11
A10
A9
1
48
GND
GND
Q15
Q7
2
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
3
4
5
Q14
Q6
6
7
Q13
Q5
8
9
Q12
Q4
A8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A19
A21
A20
A18
A17
A7
VCC
VCC
NC
MX26L6411 (x16 only)
Normal Type
Q11
Q3
Q10
Q2
A6
A5
Q9
A4
Q1
A3
Q8
A2
Q0
A1
OE
A0
GND
GND
CE
PIN DESCRIPTION
SYMBOL
A0~A21
Q0~Q15
CE
PIN NAME
Address Input
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Device Power Supply
Device Ground
WE
OE
VCC
GND
NC
Pin Not Connected Internally
Don't Use
DU
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MX26L6411
BLOCK DIAGRAM
WRITE
STATE
CONTROL
INPUT
PROGRAM/ERASE
HIGH VOLTAGE
CE
OE
WE
MACHINE
(WSM)
LOGIC
STATE
REGISTER
ADDRESS
LATCH
MTP
ARRAY
ARRAY
A0-A21
SOURCE
HV
AND
COMMAND
DATA
BUFFER
Y-PASS GATE
DECODER
PGM
DATA
HV
SENSE
AMPLIFIER
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
I/O BUFFER
Q0-Q15
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MX26L6411
Figure 1. Block Architecture
MTP memory reads erases and writes in-system via the local CPU. All bus cycles to or from the MTP memory
conform to standard microprocessor bus cycles.
3FFFFF
63
64-Kword Block
3F0000
.
.
.
1FFFFF
1F0000
31
64-Kword Block
.
.
.
01FFFF
1
0
64-Kword Block
64-Kword Block
010000
00FFFF
000000
Word Mode (x16)
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MX26L6411
Table 1. Bus Operations
Command
Sequence
Read
Array
Output
Disable
Standby Read ID Read
Query
Read
Read
Write
Status
Status
(WSM off)
(WSM on)
Notes
CE
3,4
8,9
Enabled Enabled Disabled Enabled Enabled
Enabled
VIL
Enabled
VIL
Enabled
VIH
VIL
OE (1)
WE (1)
Address
VIL
VIH
X
VIH
VIH
X
X
X
X
VIL
VIH
See
VIL
VIH
See
VIH
VIH
X
X
X
Figure 2 Table 5
Note 6 Note 7
Q (2)
Data out High Z
High Z
Data out
Q7=Data out
Q15-8=High Z
Q6-0=High Z
Data in
NOTES:
1. OE and WE should never be enabled simultaneously.
2. Q refers to Q0~Q15.
3. Refer to DC Characteristics.
4. X can be VIL or VIH for control and address pins, and VPENLK or VPENH for VPEN . See DC Characteristics for
VPENLK and VPENH voltages.
5. High Z will be VOH with an external pull-up resistor.
6. See Section , "Read Identifier Codes" for read identifier code data.
7. See Section , "Read Query Mode Command" for read query data.
8. Command writes involving block erase, program, or lock-bit configuration are reliably executed whenVCC is within
specification.
9. Refer toTable 2 on page 7 for valid DIN during a write operation.
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MX26L6411
FUNCTION
STANDBY
The device includes on-chip program/erase control cir-
cuitry. The Write State Machine (WSM) controls block
erase and byte/word/page program operations. Opera-
tional modes are selected by the commands written to
the Command User Interface (CUI).The Status Register
indicates the status of the WSM and when the WSM
successfully completes the desired program or block
erase operation.
When CE disable the device (see table1) and place it in
standby mode.The power consumption of this device is
reduced. Data input/output are in a high-impedance(High-
Z) state. If the memory is deselected during block erase,
program or lock-bit configuration, the internal control cir-
cuits remain active and the device consume normal ac-
tive power until the operation completes.
READ QUERY
READ
The read query operation outputs block status informa-
tion, CFI (Common Flash Interface) ID string, system
interface information, device geometry information and
MXIC extended query information.
The appropriate read command are required to be writ-
ten to the CUI. Upon initial device powerup or after exit
from deep powerdown, the device automatically resets
to read array mode. In the read array mode, low level
input to CE and OE, high level input to WE, and address
signals to the address inputs (A21-A0) output the data
of the addressed location to the data input/output
(Q15~Q0).
When reading information in read array mode, the de-
vice defaults to asynchronous page mode. In this state,
data is internally read and stored in a high-speed page
buffer.A2:0 addresses data in the page buffer.The page
size is 8 words. Asynchronous word mode is supported
with no additional commands required.
WRITE
To write commands to the CUI enables reading of memory
array data, device identifiers, reading and clearing of the
Status Register, block erasure, program, and lock-bit con-
figuration.The CUI is written when the device is enable,
WE is active and OE is at high level. Address and data
are latched on the earlier rising edge of WE and CE.
Standard micro-processor write timings are used.
OUTPUT DISABLE
When OE is at VIH, output from the devices is disabled.
Data input/output are in a high-impedance(High-Z) state.
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MX26L6411
COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the CUI.Table 3 defines the valid
register command sequences.
Table 2. Command Definitions
Command
Sequence
Read
Array
Read Read
Read
Clear
Write to Word
Sector
ID
Query Status
Status
Buffer
Program Erase
Register Register
Notes
5
6
7,8,9
10,11
9,10
Bus Write Cycles Req'd
1
> 2
> 2
2
1
> 2
2
2
First Bus
Operation(2)
Write
X
Write Write
Write
X
Write
X
Write
BA
Write
X
Write
BA
Write Cycles Address(3)
Data(4,5)
X
X
FFH
90H
98H
70H
Read
X
50H
E8H
Write
BA
40H/10H
Write
PA
20H
Write
BA
Second Bus Operation(2)
Read Query Address(3)
Data(4,5)
Read Read
IA
ID
QA
QD
SRD
N
PD
D0H
Command
Sequence
Sector
Erase,
Program
Suspend
10,12
Sector
Configur-
ation
Set Sector Clear
Protection
Program
Erase,
Program
Resume
10
Lock-Bit
Sector
Lock-Bit
Notes
13
Bus Write Cycles Req'd
1
1
2
2
2
2
First Bus
Operation(2) Write
Write
X
Write
X
Write
X
Write
X
Write
X
Write Cycle Address(3)
Data(4,5)
X
B0H
D0H
B8H
Write
X
60H
Write
BA
60H
Write
X
C0H
Write
PA
Second Bus Operation(2)
Write Cycle Address(3)
Data(4,5)
CC
01H
D0H
PD
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MX26L6411
NOTES:
1. Bus operations are defined inTable 1.
2. X = Any valid address within the device.
BA = Address within the block.
IA = Identifier Code Address: see Figure 2 and Table 13.
QA = Query database Address.
PA = Address of memory location to be programmed.
RCD = Data to be written to the read configuration register.This data is presented to the device on A 16-1 ;all other
address inputs are ignored.
3. ID = Data read from Identifier Codes.
QD = Data read from Query database.
SRD = Data read from status register. See Table 14 for a description of the status register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
CC = Configuration Code.
4. The upper byte of the data bus (Q8-Q15) during command writes is a "Don't Care" in x16 operation.
5. Following the Read Identifier Codes command, read operations access manufacturer, device and block lock
codes. See Section 4.3 for read identifier code data.
6. If the WSM is running, only Q7 is valid; Q15-Q8 and Q6-Q0 float, which places them in a high impedance state.
7. After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing.
8. The number of words to be written to the Write Buffer = N + 1, where N = word count argument.
Count ranges on this device for word mode are N = 0000H to N =000FH.The third and consecutive bus cycles, as
determined by N, are for writing data into the Write Buffer.
The Confirm command (D0H) is expected after exactly N + 1 write cycles; any other command at that point in the
sequence aborts the write to buffer operation. Please see Figure 4. "Write to Buffer Flowchart" for additional
information.
9. The write to buffer or erase operation does not begin until a Confirm command (D0h) is issued.
10.Attempts to issue a block erase or program to a locked block.
11.Either 40H or 10H are recognized by the WSM as the word program setup.
12.Program suspends can be issued after either theWrite-to-Buffer or Word-Program operation is initiated.
13.The clear block lock-bits operation simultaneously clears all block lock-bits.
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MX26L6411
Figure 2. Device Identifier Code Memory Map
3FFFFF
Block 63
Reserved for Future
Implementation
3F0003
3F0002
Block 63 Lock Configuration
Reserved for Future
Implementation
3F0000
3EFFFF
(Block 32 through 62)
Block 31
Reserved for Future
Implementation
1F0003
1F0002
Block 31 Lock Configuration
Reserved for Future
Implementation
1F0000
1EFFFF
(Block 2 through 30)
01FFFF
Block 1
Reserved for Future
Implementation
010003
010002
Block 1 Lock Configuration
Reserved for Future
Implementation
010000
00FFFF
Block 0
Reserved for Future
Implementation
000004
000003
000002
000001
Block 0 Lock Configuration
Device Code
Manufacturer Code
000000
NOTE:A0 is not used when obtaining these identifier codes.Data is always given on the low byte in x16 mode (upper
byte contains 00h).
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MX26L6411
Read Array Command
The device is in Read Array mode on initial device power
up and after exit from deep power down, or by writing
FFH to the Command User Interface.The read configu-
ration register defaults to asynchronous read page mode.
The device remains enabled for reads until another com-
mand is written.
Read Query Mode Command
This section defines the data structure or "Database"
returned by the Common Flash Interface (CFI) Query
command. System software should parse this structure
to gain critical information such as block size, density,
x8/x16, and electrical specifications. Once this informa-
tion has been obtained, the software will know which
command sets to use to enable MTP writes, block
erases, and otherwise control the MTP component.
Query Structure Output
The Query Database allows system software to gain in-
formation for controlling the MTP component.This sec-
tion describes the device CFI-compliant interface that
allows the host system to access Query data.
Query data are always presented on the lowest-order
data outputs (DQ 0-7) only.The numerical offset value is
the address relative to the maximum bus width supported
by the device. On this family of devices, the Query table
device starting address is a 10h, which is a word ad-
dress for x16 devices.
For a word-wide (x16) device, the first two bytes of the
Query structure, "Q" and "R" in ASCII, appear on the
low byte at word addresses 10h and 11h.This CFI-com-
pliant device outputs 00H data on upper bytes.Thus, the
device outputs ASCII "Q" in the low byte (DQ 0-7 ) and
00h in the high byte (DQ 8-15 ).
At Query addresses containing two or more bytes of in-
formation, the least significant data byte is presented at
the lower address, and the most significant data byte is
presented at the higher address.
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MX26L6411
In all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been
dropped.In addition, since the upper byte of word-wide devices is always "00h",” the leading "00" has been dropped
from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h
on the upper byte in this mode.
Table 3. Summary of Query Structure Output as a Function of Device and Mode
Device
Query start location in
maximum device bus
width addresses
Query data with maximum
device bus width addressing
Query data with byte
addressing
Type/Mode
Hex
Offset
10:
Hex
Code
0051
0052
0059
ASCII
Value
"Q"
Hex
Hex
Code
51
ASCII
Offset
20:
Value
"Q"
x16 device
x16 mode
10h
11:
"R"
21:
00
"Null"
"R"
12:
"Y"
22:
52
x16 device
x8 mode
20:
51
"Q"
N/A (1)
N/A (1)
21:
51
"Q"
22:
52
"R"
NOTE:
1. The system must drive the lowest order addresses to access all the device's array data when the device is
configured in x8 mode.Therefore, word addressing, where these lower addresses are not toggled by the system, is
"Not Applicable" for x8-configured devices.
Table 4. Example of Query Structure Output of a x16- and x8-Capable Device
Word Addressing
Hex Code
Byte Addressing
Hex Code
Offset
A15-A0
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
...
Value
Offset
A7-A0
20h
21h
22h
23h
24h
25h
26h
27h
28h
...
Value
D15 - D0
D7 - D0
0051
0052
0059
P_IDLO
P_IDHI
PLO
"Q"
"R"
51
51
"Q"
"Q"
"Y"
52
"R"
PrVendor
ID#
52
"R"
59
"Y"
PrVendor
TblAdr
AltVendor
ID#
59
"Y"
PHI
P_IDLO
P_IDLO
P_IDHI
...
PrVendor
ID#
A_IDLO
A_IDHI
...
ID#
...
...
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MX26L6411
Query Structure Overview
The Query command causes the MTP component to display the Common Flash Interface (CFI) Query structure or
"database". The structure sub-sections and address locations are summarized below.
Table 5. Query Structure (1)
Offset
00h
Sub-Section
Name Description
Manufacturer Code
01h
Device Code
(BA+2)h (2)
04-0Fh
10h
Block Status Register
Reserved
Block-Specific Information
Reserved forVendor-Specific Information
Reserved forVendor-Specific Information
Command Set ID andVendor Data Offset
MTP Device Layout
CFI Query Identification String
System Interface Information
Device Geometry Definition
Primary MXIC-Specific Extended
QueryTable
1Bh
27h
P (3)
Vendor-Defined Additional Information Specific to the
PrimaryVendor Algorithm
NOTES:
1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a
function of device bus width and mode.
2. BA = Block Address beginning location (i.e., 02000h is block 2s beginning location when the block size is 128
Kbyte).
3. Offset 15 defines "P" which points to the Primary Intel-Specific Extended Query Table.
Block Status Register
The block status register indicates whether an erase operation completed successfully or whether a given block is
locked or can be accessed for MTP program/erase operations.
Table 6. Block Status Register
Offset
Length
Description
Address
Value
(BA+2)h (1)
1
Block Lock Status Register
BSR.0 Block Lock Status
0 = Unlocked
BA+2:
--00 or --01
BA+2:
BA+2:
(bit 0): 0 or 1
(bit 1-7): 0
1 = Locked
BSR 1-7: Reserved for Future Use
NOTE:
1. BA =The beginning location of a Block Address (i.e., 008000h is block 1s (64-KB block) beginning location in word
mode).
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MX26L6411
CFI Query Identification String
The CFI Query Identification String provides verification that the component supports the Common Flash Interface
specification. It also indicates the specification version and supported vendor-specified command set(s).
Table 7. CFI Identification
Offset
Length
Description
Add.
Hex
Code
--51
--52
--59
--01
--00
--31
--00
--00
--00
--00
--00
Value
10h
3
Query-unique ASCII string "QRY"
10
11:
12:
13:
14:
15:
16:
17:
18:
19:
1A:
"Q"
"R"
"Y"
13h
15h
17h
19h
2
2
2
2
Primary vendor command set and control interface ID code.
16-bit ID code for vendor-specified algorithms
Extended QueryTable primary algorithm address
Alternate vendor command set and control interface ID code.
0000h means no second vendor-specified algorithm exists
Secondary algorithm Extended QueryTable address.
0000h means none exists
System Interface Information
The following device information can optimize system interface software.
Table 8. System Interface Information
Offset
Length
Description
Add.
1B:
1C:
1D:
1E:
Hex
Value
2.7 V
3.6 V
0.0V
0.0V
Code
1Bh
1
VCC logic supply minimum program/erase voltage
bits 0-3 BCD 100 mV
--27
--36
--00
--00
bits 4-7 BCD volts
1Ch
1Dh
1Eh
1
1
1
VCC logic supply maximum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 BCD volts
VPP [programming] supply minimum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 HEX volts
VPP [programming] supply maximum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 HEX volts
1Fh
20h
21h
22h
23h
24h
25h
26h
1
1
1
1
1
1
1
1
"n" such that typical single word program time-out = 2us
"n" such that typical max. buffer write time-out = 2us
"n" such that typical block erase time-out = 2ms
"n" such that typical full chip erase time-out = 2ms
1F:
20:
21:
22:
--07
--07
--0A
--00
--04
--04
--04
--00
128us
128us
1s
NA
"n" such that maximum word program time-out = 2 times typical 23:
2ms
2ms
16s
"n" such that maximum buffer write time-out = 2 times typical
"n" such that maximum block erase time-out = 2 times typical
"n" such that maximum chip erase time-out = 2 times typical
24:
25:
26:
NA
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MX26L6411
Device Geometry Definition
This field provides critical details of the MTP device geometry.
Table 9. Device Geometry Definition
Offset Length
Description
Code See Table
Below
27h
28h
1
2
"n" such that device size = 2n in number of bytes
MTP device interface: x8 async(28:00,29:00),
27:
28:
29:
2A:
2B:
--17
--01
--00
--05
--00
x16
32
x16 async(28:01,29:00), x8/x16 async(28:02,29:00)
"n" such that maximum number of bytes in write buffer = 2n
2Ah
2
Number of erase block regions within device:
1. x = 0 means no erase blocking; the device erases in "bulk"
2. x specifies the number of device or partition regions with one or
more contiguous same-size erase blocks
2Ch
2Dh
1
4
2C:
--01
1
3. Symmetrically blocked partitions have one blocking region
4. Partition size = (total blocks) x (individual block size)
Erase Block Region 1 Information
2D:
2E:
2F:
30:
--3F
--00
--00
--02
bits 0-15 = y, y+1 = number of identical-size erase blocks
bits 16-31 = z, region erase block(s) size are z x 256 bytes
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MX26L6411
Primary-Vendor Specific Extended Query Table
Certain MTP features and commands are optional.The PrimaryVendor-Specific Extended Query table specifies this
and other similar information.
Table 10. Primary Vendor-Specific Extended Query
Offset(1) Length Description
Add.
Hex
Code
--50
--52
--49
--31
--31
--0A
--00
--00
--00
Value
P=31h
(P+0)h
(P+1)h
(P+2)h
(P+3)h
(P+4)h
(P+5)h
(P+6)h
(P+7)h
(P+8)h
(Optional MTP Features and Commands)
3
Primary extended query table
Unique ASCII string "PRI"
31:
32:
33:
34:
35:
36:
37:
38:
39:
"P"
"R"
"I"
1
1
Major version number, ASCII
"1"
"1"
Minor version number, ASCII
Optional feature and command support (1=yes, 0=no)
bits 9-31 are reserved; undefined bits are "0". If bit 31 is
"1" then another 31 bit field of optional features follows at
the end of the bit-30 field.
bit 0 Chip erase supported
bit 0 = 0
No
Yes
Yes
Yes(1)
No
4
bit 1 Suspend erase supported
bit 1 = 1
bit 2 = 1
bit 2 Suspend program supported
bit 3 Legacy lock/unlock supported
bit 4 Queued erase supported
bit 3 = 1(1)
bit 4 = 0
bit 5 = 0
bit 6 = 1
bit 7 = 1
bit 8 = 0
bit 5 Instant Individual block locking supported
bit 6 Protection bits supported
No
Yes
Yes
No
bit 7 Page-mode read supported
bit 8 Synchronous read supported
(P+9)h
1
Supported functions after suspend:read Array, Status,Query
Other supported operations are:
3A:
--01
bit 0 = 1
bits 1-7 reserved; undefined bits are "0"
bit 0 Program supported after erase suspend
Block status register mask
Yes
(P+A)h
(P+B)h
3B:
3C:
--01
--00
2
1
1
bits 2-15 are Reserved; undefined bits are "0"
bit 0 Block Lock-Bit Status register active
bit 1 Block Lock-Down Bit Status active
VCC logic supply highest performance program/erase voltage
bits 0-3 BCD value in 100 mV
bit 0 = 1
bit 1 = 0
Yes
No
(P+C)h
(P+D)h
3D:
3E:
--33
--00
3.3V
0.0V
bits 4-7 BCD value in volts
VPP optimum program/erase supply voltage
bits 0-3 BCD value in 100 mV
bits 4-7 HEX value in volts
NOTE:
1.Future devices may not support the described "Legacy Lock/Unlock" function.Thus bit 3 would have a value of "0".
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MX26L6411
Table 11. Protection Register Information
Offset(1) Length Description
Add. Hex
Code
Value
P=31h
(Optional MTP Features and Commands)
(P+E)h
1
Number of Protection register fields in JEDEC ID space.
"00h," indicates that 256 protection bytes are available
Protection Field 1: Protection Description
3F:
--01
01
This field describes user-available OneTime Programmable
(OTP) protection register bytes.Some are pre-programmed
with device-unique serial numbers. Others are user-programmable.
Bits 0-15 point to the protection register lock
(P+F)h
(P+10)h
(P+11)h
(P+12)h
40:
--00
00h
byte, the section's first byte. The following bytes are factory
pre-programmed and user-programmable.
bits 0-7 = Lock/bytes JEDEC-plane physical low address
bits 8-15 = Lock/bytes JEDEC-plane physical high address
bits 16-23 = "n" such that 2 n = factory pre-programmed bytes
bits 24-31 = "n" such that 2 n = user-programmable bytes
NOTE:
1.The variable P is a pointer which is defined at CFI offset 15h.
Table 12. Page Read Information
Offset(1) Length Description
Add.
Hex
Value
P=31h
(Optional MTP Features and Commands)
Code
Page Mode Read capability
bits 0-7 = "n" such that 2n HEX value represents the number
of read-page bytes. See offset 28h for device word width to
determine page-mode data output width. 00h indicates no
read page buffer.
(P+13)h
1
1
44:
--04
16 byte
0
(P+14)h
(P+15)h
Number of synchronous mode read configuration fields that
follow. 00h indicates no burst capability.
Reserved for future use
45:
46:
--00
NOTE:
1.The variable P is a pointer which is defined at CFI offset 15h.
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MX26L6411
DEVICE OPERATION
SILICON ID READ
The Silicon ID Read mode allows the reading out of a
binary code from the device and will identify its manu-
facturer and type. This mode is intended for use by
programming equipment for the purpose of automatically
matching the device to be programmed with its corre-
sponding programming algorithm. This mode is func-
tional over the entire temperature range of the device.
inTable 13.)
During the "Silicon ID Read" Mode, manufacturer's code
(MXIC=C2H) can be read out by setting A0=VIL and
device identifier can be read out by setting A0=VIH.
To terminate the operation, it is necessary to write the
read command. This command is valid only when the
WSM is off or the device is suspended.
To activate this mode, the two cycle "Silicon ID Read"
command is requested. (The ID code value is illustrated
Table 13. MX26L6411 Silicon ID Codes
Type
Address (1) Code (HEX) Q7 Q6
Q5 Q4 Q3 Q2 Q1 Q0
Manufacture Code
Device Code
00000
C2H
1
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
00001
00BEH
Block Lock Configuration
- Block is Unlocked
- Block is Locked
- Reserved for Future Use
X0002 (2)
DQ0=0
DQ0=1
DQ1-7
Notes:
1. A0 is not used when obtaining the identifier codes.The lowest order address line is A1.
2. X selects the specific blocks lock configuration code.
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MX26L6411
Table 14. Status Register Definitions
High Z
Symbol When Status
Busy?
Definition
Notes
"1"
"0"
Busy
Block Erase Suspended Block Erase in
Progress/Completed
ERASE AND CLEAR LOCK-BITS Error in Block Erasure or Successful Block
SR.7
SR.6
No
WRITE STATE MACHINE STATUS Ready
ERASE SUSPEND STATUS
1
Yes
SR.5
Yes
2
3
STATUS
Clear Lock-Bits
Erase or Clear
Lock-Bits
SR.4
SR.3
Yes
Yes
PROGRAM AND SET LOCK-BIT
STATUS
Error in Setting Lock-Bit Successful Set Block
Lock Bit
PROGRAMMINGVOLTAGE
STATUS
Low ProgrammingVoltage ProgrammingVoltage
Detected, Operation
Aborted
OK
SR.2
SR.1
Yes
Yes
Yes
PROGRAM SUSPEND STATUS
DEVICE PROTECT STATUS
RESERVED
Program suspended
Program in progress/
completed
Block Lock-Bit Detected, Unlock
Operation Abort
4
5
SR.0
Notes
1. Check STS or SR.7 to determine block erase, program, or lock-bit configuration completion. SR.6-SR.0 are not
driven while SR.7 = 0
2. If both SR.5 and SR.4 are "1" after a block erase or lock-bit configuration attempt, an improper command se-
quence was entered.
3. SR.3 does not provide a continuous programming voltage level indication.TheWSM interrogates and indicates the
programming voltage level only after Block Erase, Program, Set Block Lock-Bit, or Clear Block Lock-Bits com-
mand sequences.
4. SR.1 does not provide a continuous indication of block lock-bit values.The WSM interrogates the block lock-bits
only after Block Erase, Program, or Lock-Bit configuration command sequences. It informs the system, depend-
ing on the attempted operation, if the block lock-bit is set. Read the block lock configuration codes using the Read
Identifier Codes command to determine block lock-bit status.
5. SR.0 is reserved for future use and should be masked when polling the status register.
Table 15. Extended Status Register Definitions
High Z
Symbol When Status
Busy?
Definition
Notes
"1"
Write buffer available
"0"
XSR.7 No
XSR.6- Yes
XSR.0
WRITE BUFFER STATUS
RESERVED
Write buffer not available
1
2
Notes:
1. After a Buffer-Write command, XSR.7 = 1 indicates that a Write Buffer is available.
2. XSR.6-XSR.0 are reserved for future use and should be masked when polling the status register.
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MX26L6411
READ STATUS REGISTER COMMAND
At this time, A read array/program command sequence
can also be issued during erase suspend to read or pro-
gram data in other blocks. During a program operation
with block erase suspended, status register bit SR.7 will
return to "0".The WSM will continue to run, idling in the
SUSPEND state, regardless of the state of all input con-
trol pins.
The Status Register is read after writing the Read Status
Register command of 70H to the Command User Inter-
face. Also, after starting the internal operation the de-
vice is set to the Read Status Register mode automati-
cally.
The only other valid commands while block erase is sus-
pended are Read Query, Read Status Register, Clear
Status Register, Configure, and Block Erase Resume.
After a Block Erase Resume command is written to the
MTP memory, the WSM will continue the block erase
process. Status register bits SR.6 and SR.7 will auto-
matically clear. Block erase cannot resume until pro-
gram operations initiated during block erase suspend
have completed.
The contents of Status Register are latched on the later
falling edge of OE or the first edge of CE that enables
the device OE must be toggle toVIH or the device must
be disable before further reads to update the status reg-
ister latch.
CLEAR STATUS REGISTER COMMAND
The Erase Status, Program Status, Block Status bits
and protect status are set to "1" by the Write State Ma-
chine and can only be reset by the Clear Status Register
command of 50H. These bits indicates various failure
conditions.
WRITE TO BUFFER COMMAND
To program the device, a Write to Buffer command is
issue first. A variable number of bytes, up to the buffer
size, can be loaded into the buffer and written to the
MTP device. First, the Write to Buffer Setup command
is issued along with the Block Address (see Figure ,
Write to Buffer Flowchart ” on page ). After the com-
mand is issued, the extended Status Register (XSR) can
be read when CE is VIL. XSR.7 indicates if the Write
Buffer is available.
BLOCK ERASE COMMAND
Automated block erase is initiated by writing the Block
Erase command of 20H followed by the Confirm com-
mand of D0H. An address within the block to be erased
is required (erase changes all block data to FFH).
Block preconditioning, erase, and verify are handled in-
ternally by the WSM (invisible to the system).The CPU
can detect block erase completion by analyzing the sta-
tus register bit SR.7.Toggle OE, CE to update the status
register. The CUI remains in read status register mode
until a new command is issued. Also, reliable block era-
sure can only occur when VCC is valid.
If the buffer is available, the number of words/bytes to
be program is written to the device. Next, the start ad-
dress is given along with the write buffer data. Subse-
quent writes provide additional device addresses and
data, depending on the count. After the last buffer data
is given, a Write Confirm command must be issued.The
WSM beginning copy the buffer data to the MTP array.
If an error occurs while writing, the device will stop writ-
ing, and status register bit SR.4 will be set to a "1" to
indicate a program failure.The internal WSM verify only
detects errors for "1" that do not successfully program
to "0" . If a program error is detected, the status register
should be cleared. Any time SR.4 and/or SR.5 is set, the
device will not accept any more Write to Buffer com-
mands.Reliable buffered writes can only occur whenVCC
is valid. Also, successful programming requires that the
corresponding block lock-bit be reset.
BLOCK ERASE SUSPEND COMMAND
This command only has meaning while the WSM is ex-
ecuting Block erase operation, and therefore will only be
responded to during Block erase operation. After this com-
mand has been executed, the WSM suspend the erase
operations, and then return to Read Status Register
mode.The WSM will set the SR.6 bit to a "1". Once the
WSM has reached the Suspend state, the WSM will set
the Q7 bit to a "1".
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MX26L6411
WORD PROGRAM COMMANDS
Word program is executed by a two-command sequence.
TheWord Program Setup command of 40H is written to
the Command Interface, followed by a second write speci-
fying the address and data to be written.TheWSM con-
trols the program pulse application and verify operation.
The CPU can detect the completion of the program event
by analyzing the status register bit SR.7.
Successful word programs require that the correspond-
ing block lock-bit be cleared. If a word program is at-
tempted when the corresponding block lock-bit is set,
SR.1 and SR.4 will be set to "1".
SUSPEND/RESUME COMMAND
Writing the Suspend command of B0H during block erase
operation interrupts the block erase operation and allows
read out from another block of memory.Writing the Sus-
pend command of B0H during program operation inter-
rupts the program operation and allows read out from
another block of memory.The Block address is required
when writing the Suspend/Resume Command.The de-
vice continues to output Status Register data when read,
after the Suspend command is written to it. Polling the
WSM Status and Suspend Status bits will determine when
the erase operation or program operation has been sus-
pended.When SR.7 = 1, SR.2 should also be set to "1",
indicating that the device is in the program suspend mode.
At this time, writing of the Read Array command to the
CUI enables reading data from blocks other than that
which is suspended.The only other valid commands while
programming is suspended are Read Query, Read Sta-
tus Register, Clear Status Register, Configure, and Pro-
gram Resume. When the Resume command of D0H is
written to the CUI, theWSM will continue with the erase
or program processes. Status register bits SR.2 and SR.7
will automatically clear.
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MX26L6411
Read Configuration
The device will support both asynchronous page mode and standard word reads.No configuration is required.
Status register and identifier only support standard word single read operations.
Table 16. Read Configuration Register Definition
RM
R
15
R
7
R
14
R
6
R
13
R
5
R
R
11
R
3
R
10
R
2
R
9
16(A16)
12
R
8
R
R
1
4
Notes
RCR.16 = READ MODE (RM)
Read mode configuration effects reads from the MTP
array.
0 = Standard Word Reads Enabled (Default)
1 = Page-Mode Reads Enabled
Status register, query, and identifier reads support
standard word read cycles.
RCR.15-1= RESERVED FOR FUTURE
ENHANCEMENTS (R)
These bits are reserved for future use. Set these
bits to "0".
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MX26L6411
Set Block Lock-Bit Commands
Programming the Protection Register
The protection register bits are programmed using the
two-cycle Protection Program command.The 64-bit num-
ber is programmed 16 bits at a time for word-wide parts
and eight bits at a time for byte-wide parts. First write
the Protection Program Setup command, C0H.The next
write to the device will latch in address and data and
program the specified location.
This device provided the block lock-bits, to lock and
unlock the individual block.To set the block lock-bit, the
two cycle Set Block Lock-Bit command is requested.
This command is invalid while theWSM is running or the
device is suspended.Writing the set block lock-bit com-
mand of 60H followed by confirm command and an ap-
propriate block address. After the command is written,
the device automatically outputs status register data when
read.The CPU can detect the completion of the set lock-
bit event by analyzing the status register bit SR.7. Also,
reliable operations occur only when VCC is valid.
Any attempt to address Protection Program commands
outside the defined protection register address space will
result in a status register error. Attempting to program a
locked protection register segment will result in a status
register error.
Clear Block Lock-Bits Command
Locking the Protection Register
All set block lock-bits can clear by the Clear Block Lock-
Bits command.This command is invalid while the WSM
is running or the device is suspended.To Clear the block
lock-bits, two cycle command is requested .The device
automatically outputs status register data when read.The
CPU can detect completion of the clear block lock-bits
event by analyzing the status register bit SR.7. If a clear
block lock-bits operation is aborted due to VCC
transitioning out of valid range, block lock-bit values are
left in an undetermined state. A repeat of clear block
lock-bits is required to initialize block lock-bit contents
to known values.
The user-programmable segment of the protection regis-
ter is lockable by programming Bit 1 of the PR-LOCK
location to 0. Bit 0 of this location is programmed to 0 at
the Intel factory to protect the unique device number. Bit
1 is set using the Protection Program command to pro-
gram "FFFD" to the PR-LOCK location. After these bits
have been programmed, no further changes can be made
to the values stored in the protection register. Protection
Program commands to a locked section will result in a
status register error. Protection register lockout state is
not reversible.
Protection Register Program Command
VCC--TRANSITIONS
The device offer a 128-bit protection register to increase
the security of a system design.The 128-bits protection
register are divided into two 64-bit segments. One is pro-
grammed in the factory with a unique 64-bit number,
which is unchangeable. The other one is left blank for
customer designers to program as desired. Once the
customer segment is programmed, it can be locked to
prevent reprogramming.
Block erase, program, and lock-bit configuration are not
guaranteed if VCC falls outside of the specified operat-
ing ranges.Therefore, block erase and lock-bit configu-
ration commands must be repeated after normal opera-
tion is restored. Device power-off clears the Status Reg-
ister.
The CUI latches commands issued by system software
and is not altered by CE transitions, or WSM actions. Its
state is read array mode upon power-up, or after VCC
transitions belowVLKO.
Reading the Protection Register
The protection register is read in the identification read
mode.The device is switched to this mode by writing the
Read Identifier command 90H. Once in this mode, read
cycles from addresses retrieve the specified informa-
tion.To return to read array mode, write the Read Array
command (FFH).
After block erase, program, or lock-bit configuration, the
CUI must be placed in read array mode via the Read
Array command if subsequent access to the memory
array is desired.
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MX26L6411
Figure 3. Protection Register Memory Map
Word
Address
A[22 -1]: 64 Mbit
88H
4 Words
User Programmed
85H
84H
4 Words
Factory Programmed
81H
80H
1 Word Lock
NOTE: A 0 is not used in x16 mode when accessing the protection register map (See Table 20 for x16 addressing).
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MX26L6411
Table 17. Word-Wide Protection Register Addressing
Word
Use
A8
1
A7
0
A6
0
A5
0
A4
0
A3
0
A2
0
A1
LOCK
Both
0
0
1
2
3
4
5
6
7
Factory
Factory
Factory
Factory
User
1
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
0
1
0
User
1
0
0
0
0
1
1
User
1
0
0
0
0
1
1
User
1
0
0
0
1
0
0
NOTE: 1. All address lines not specified in the above table must be 0 when accessing the Protection Register,
i.e., A23-A9 = 0.
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MX26L6411
Figure 4. Write to Buffer Flowchart
Start
Set Time-Out
NO
Write E8H to Block Address
Read Extended Status Register
YES
NO
Write to Buffer
Time-Out ?
XSR.7=1 ?
YES
Write Word or Byte
Count to Block Address
Write Buffer Data,
Start Address
YES
X = 0
Check
X=N ?
Abort Write to
Buffer Command?
YES
Write to Another
Block Address
NO
Write to Buffer
Failed
YES
Write Next Buffer Data,
Device Address
X = X+1
Program Buffer to MTP
Confirm D0H
Another Write
to Buffer ?
Issue Read
Status Command
NO
Read Status Register
NO
SR.7=1?
YES
Full Status Check if Desired
Programming Complete
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MX26L6411
Figure 5. Program Suspend/Resume Flowchart
Start
Write B0H
Read Status Register
NO
SR.7=1 ?
YES
NO
SR.2=1 ?
YES
Programming Completed
Write FFH
Read Array Data
NO
Done Reading
YES
Write D0H
Write FFH
Programming Resumed
Read Array Data
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MX26L6411
Figure 6. Word Programming Flowchart
Bus
Command
Comments
Operation
Write
Start
Setup
Data=40H
Word Program Addr=Location to Be
Programmed
Write 40H,
Address
Write
Word
Program
Data=Data to Be
Programmed
Write Data
and Address
Addr=Location to Be
Programmed
Read
Status Register Data
Read
(Note 1)
Standby
Status Register
Check SR.7
1=WSM Ready
0=WSM Busy
0
SR.7=
1.Toggling OE (low to high to low) updates the status
register.This can be done in place of issuing the Read
Status Register command. Repeat for subsequent pro-
gramming operations.
1
Full Status Check if Desired
SR full status check can be done after each program
operation, or after a sequence of programming opera-
tions.
Word Program Complete
Write FFH after the last program operation to place
device in read array mode.
FULL STATUS CHECK PROCEDURE
Bus
Command Comments
Read Status Register
Data (See Above)
Operation
Standby
Check SR.3
1=Programming toVoltage
Error Detect
1
VPP Range Error
SR.3=
Standby
Check SR.1
1=Device Protect Detect
RP=VIH, Block Lock-Bit is
Set Only required for
systems
0
1
1
SR.1=
0
Device Protect Error
Programming Error
Standby
Check SR.4
1=Programming Error
Toggling OE (low to high to low) updates the status
register.This can be done in place of issuing the Read
Status Register command. Repeat for subsequent pro-
gramming operations.
SR.4=
0
SR.4, SR.3, and SR.1 are only cleared by the Clear
Status Register Command in cases where multiple lo-
cation are programmed before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery.
Word Program Successful
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MX26L6411
Figure 7. Block Erase Flowchart
Start
Write 20H to Block Address
Write Confirm D0H to Block Address
Read
Status Register
NO
NO
SR.7=1 ?
YES
Write B0H?
YES
Full Status Check
If Desired
Suspend Loop
Write D0H
YES
Erase MTP
Block(s) Completed
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MX26L6411
Figure 8. Block Erase Suspend/Resume Flowchart
Bus
Command
Comments
Start
Operation
Write
Erase
Data=B0H
Suspend
Addr=X
Write B0H
Read
Status Register Data
Addr=X
Read
Status Register
Standby
Check SR.7
1=WSM Ready
0=WSM Busy
Check SR.6
0
SR.7=
Standby
Write
1=Block Erase Suspend
0=Block Erase Completed
Data=D0H
1
0
Erase
SR.6=
1
Erase Completed
Resume
Addr=X
Read
Program
Read or Program?
No
Read Array
Program
Loop
Data
Done ?
Yes
Write D0H
Write FFH
Block Erase Resumed
Read Array Data
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MX26L6411
Figure 9. Set Block Lock-Bit Flowchart
Start
Write 60H, Block Address
Write 01H, Block Address
Read
Status Register
NO
SR.7=1 ?
YES
Full Status Check
If Desired
Set Lock-Bit Completed
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
NO
Voltage Range Error
SR.3=0 ?
YES
YES
SR.4,5=1 ?
Command Sequence Error
NO
NO
Set Lock-Bit Error
SR.4=0 ?
YES
Set Lock-Bit Successful
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MX26L6411
Figure 10. Clear Lock-Bit Flowchart
Start
Write 60H
Write D0H
Read
Status Register
NO
SR.7=1 ?
YES
Full Status Check
If Desired
Set Lock-Bit Completed
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
NO
Voltage Range Error
SR.3=0 ?
YES
YES
SR.4,5=1 ?
Command Sequence Error
Clear Block Lock-Bits Error
NO
NO
SR.5=0 ?
YES
Clear Block Lock-Bit Successful
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MX26L6411
Figure 11. Protection Register Programming Flowchart
Start
Write C0H (Protection Reg.
Program Setup)
Write Protect. Register
Address/Data
Read
Status Register
NO
SR.7=1 ?
YES
Full Status Check
If Desired
Program Completed
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
1,1
VPEN Range Error
SR.3, SR.4=
0,1
Protection Register
Programming Error
SR.1, SR.4=
1,1
Attempted Program to Locked
Register-Aborted
SR.1, SR.4=
YES
Program Successful
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MX26L6411
OPERATING RATINGS
ABSOLUTE MAXIMUM RATINGS
StorageTemperature
Commercial (C) Devices
Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC
Ambient Temperature (TA ). . . . . . . . . . . . 0°C to +70°C
VCC Supply Voltages
AmbientTemperature
with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC
Voltage with Respect to Ground
VCC for full voltage range. . . . . . . . . . . +2.7 V to 3.6 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V
A9, OE, and
All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5 V.
During voltage transitions, input or I/O pins may over-
shoot VSS to -2.0 V for periods of up to 20 ns. See
Figure 6. Maximum DC voltage on input or I/O pins is
VCC +0.5 V. During voltage transitions, input or I/O
pins may overshoot to VCC +2.0 V for periods up to
20 ns. See Figure 7.
2. Minimum DC input voltage on pins A9 and OE is
-0.5V.During voltage transitions, A9 and OE may over-
shoot VSS to -2.0 V for periods of up to 20 ns. See
Figure 6. Maximum DC input voltage on pin A9 is +12.5
V which may overshoot to 14.0 V for periods up to 20
ns.
3.No more than one output may be shorted to ground at
a time. Duration of the short circuit should not be
greater than one second.
Stresses above those listed under "Absolute Maximum
Rat-ings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those in-
dicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maxi-
mum rating conditions for extended periods may affect
device reliability.
P/N:PM0947
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33
MX26L6411
DC Characteristics
Symbol Parameter
Notes Typ
Max
±1
Unit Test Conditions
ILI
Input Load Current
1
1
uA
uA
uA
VCC = VCC Max, VIN = VCC or GND
VCC = VCC Max, VIN = VCC or GND
CMOS Inputs, VCC = VCC Max,
Device is disabled (see table 1)
TTL Inputs, VCC=VCC max,
Device is disable (see table 1)
IOUT(STS)=0mA
ILO
ICC1
Output Leakage Current
VCC Standby Current
±10
80
1,2,3
25
0.71
2
2
5
mA
uA
ICC2
ICC3
VCC Power-Down Current
CMOS Inputs, VCC=VCC Max,
Device is enabled (see Table 1)
f=5MHz, IOUT=0mA
15
20
mA
VCC Page Mode Read Current 1,3
VCCWord Mode Read Current 1,3
CMOS Inputs, VCC=VCC Max,
Device is enabled (see Table 1)
f=33MHz, IOUT=0mA
24
60
29
70
mA
mA
CMOS Inputs, VCC=VCC Max,
Device is enabled (see Table 1)
f=5MHz, IOUT=0MA
ICC4
ICC5
ICC6
ICC7
VCC Program or Set Lock-Bit 1,4
Current
35
40
35
40
60
70
70
80
10
mA
mA
mA
mA
mA
CMOS Inputs
TTL Inputs
VCC Block Erase or Clear
Block Lock-Bits Current
VCC Program Suspend or
Block Erase Suspend Current
Input LowVoltage
1,4
CMOS Inputs
TTL Inputs
1,5
Device is disabled (see Table 1)
VIL
3
3
3
-0.5
2.0
0.8
VCC+0.5
0.4
V
V
V
V
V
VIH
VOL
Input HighVoltage
Output LowVoltage
VCC=VCC Min, IOL=2mA
VCC=VCC Min, IOL=100uA
VCC=VCC Min
0.2
0.85 x
VCC
IOH=-2.5mA
VOH
Output HighVoltage
VCC LockoutVoltage
3
5
VCC-0.2
V
V
VCC=VCC Min
IOH=-100uA
VLKO
2.2
NOTES:
1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and
speeds).
2. CMOS inputs are either VCC ±0.2 V or GND ±0.2 V.TTL inputs are either VIL or VIH .
3. Sampled, not 100% tested.
4. ICCWS and ICCES are specified with the device de-selected. If the device is read or written while in erase suspend
mode, the device's current draw is ICCR or ICCW .
5.Block erases, programming, and lock-bit configurations are inhibited whenVCC <VLKO , and not guaranteed in the
range betweenVLKO (min) andVCC (min), and aboveVCC (max).
P/N:PM0947
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34
MX26L6411
Figure 12. Transient Input/Output Reference Waveform
3.0
1.5V
1.5V
TEST POINTS
0.0
Input
Output
Note : AC test inputs are driven for a Logic "1" and 0.0V for a Logic "0".
Input rise and fall times (10% tp 90%) < 5ns.
Figure 13. Transient Equivalent Testing Load Circuit
1.3V
1N914
RL=3.3K ohm
Device
Out
Under Test
CL
NOTE: CL Includes Jig Capacitance
P/N:PM0947
REV. 0.1,NOV. 20, 2002
35
MX26L6411
AC Characteristics --Read-Only Operations (1,2)
Versions
VCC
3.0V-3.6V(3)
2.7V-3.6V(3)
(All units in ns unless otherwise noted)
Sym
Parameter
Notes
Min
Max
Min
Max
tAVAV
tAVQV
tELQV
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
tOH
Read/Write CycleTime
100
100
Address to Output Delay
CEX to Output Delay
100
100
50
100
100
50
2
OE to Non-Array Output Delay
RESET High to Output Delay
CEX to Output in Low Z
2, 4
180
180
5
5
5
5
5
0
0
0
0
OE to Output in Low Z
CEX High to Output in High Z
OE High to Output in High Z
Output Hold from Address, CEX, or OE
Change, Whichever Occurs First
35
15
35
15
0
0
0
0
tELFL/tELFH CEX Low to BYTE High or Low
tFLQV/tFHQV BYTE to Output Delay
5
10
10
1000
1000
1000
1000
tFLQZ
tEHEL
tAPA
BYTE to Output in High Z
CEx High to CEx Low
5
5
Page Address Access Time
OE to Array Output Delay
5, 6
4
25
25
30
30
tGLQV
NOTES:
CEX low is defined as the first edge of CE that enables the device. CEX high is defined at the first edge of CE that
disables the device (see Table 1).
1. See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.
2. OE may be delayed up to t ELQV -t GLQV after the first edge of CE that enables the device (see Table 1) without
impact on t ELQV .
3. See Figures 12-13, Transient Input/Output Reference Waveform for VCC= 2.7V-3.6V, and Transient Equivalent
Testing Load Circuit for testing characteristics.
4.When reading the MTP array a faster tGLQV (R16) applies. Non-array reads refer to status register reads, query
reads, or device identifier reads.
5. Sampled, not 100% tested.
6.For devices configured to standard word read mode, R15 (tAPA) will equal R2 (tAVQV).
P/N:PM0947
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36
MX26L6411
Figure 14. AC Waveform for Both Page-Mode and Standard Word Read Operations
VIH
VIL
Address
(A23-A3)
tAVAV
VIH
VIL
Address
(A2-A0)
Valid Address
Valid Address Valid Address
Valid Address
tEHEL
Disable
VIH
VIL
CEx[E]
Enable
tEHQZ
tAVQV
VIH
VIL
OE [G]
tGHQZ
tELQV
VIH
VIL
WE [W]
tGLQV
tOH
tAPA
tPHQV
tELQX
VOH
VOL
DATA[D/Q]
Q0- Q15
High Z
High Z
Valid
Valid
Valid
Valid
Output
Output Output Output
tGLQX
VIH
VIL
VCC
NOTE:
1. CEX low is defined as the first edge of CE that enables the device. CEX high is defined at the first edge of CE that
disables the device (see Table 1).
2. For standard word read operations, tAPA will equal tAVQV.
3. When reading the MTP array a faster tGLQV applies. Non-array reads refer to status register reads, query reads,
or device identifier reads.
P/N:PM0947
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MX26L6411
AC Characteristics--Write Operations (1,2)
Versions
Valid for All
Speeds
Unit
Symbol
Parameter
Notes
Min
Max
tPHWL (tPHEL )
tELWL (tWLEL )
tWP
RESET High Recovery to WE(CEX) Going Low
CEX (WE) Low toWE(CEX) Going Low
Write PulseWidth
3
4
4
5
5
2
0
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
sec
us
us
70
50
55
0
tDVWH (tDVEH )
tAVWH (tAVEH )
tWHEH (tEHWH)
tWHDX (tEHDX)
tWHAX (tEHAX)
tWPH
Data Setup to WE(CEX) Going High
Address Setup to WE(CEX) Going High
CEX (WE) Hold fromWE(CEX) High
Data Hold fromWE(CEX) High
Address Hold fromWE(CEX) High
Write PulseWidth High
0
0
6
3
30
0
tVPWH (tVPEH)
tWHGL (tEHGL)
tQVVL
VPEN Setup to WE(CEX) Going High
Write Recovery before Read
7
35
0
VPEN Hold from Valid SRD, STS Going High
3,8
4,8
4
tWHQV5 (tEHQV5) Set Lock-Bit Time
64
0.5
25
26
75/85
0.70
tWHQV6 (tEHQV6) Clear Block Lock-Bits Time
tWHRH1 (tEHRH1) Program Suspend LatencyTime to Read
8
75/90
35/40
tWHRH (tEHRH)
Erase Suspend LatencyTime to Read
8
NOTES:
CEX low is defined as the first edge of CE that enables the device. CEX high is defined at the first edge of CE that
disables the device (see Table 1).
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as
during read-only operations. Refer to AC Characteristics-Read-Only Operations.
2. A write operation can be initiated and terminated with either CE X or WE.
3. Sampled, not 100% tested.
4. Write pulse width (tWP) is defined from CEX orWE going low (whichever goes low last) to CEX orWE going high
(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH.
5. Refer to Table 3 for valid A IN and D IN for block erase, program, or lock-bit configuration.
6. Write pulse width high (t WPH) is defined from CEX or WE going high (whichever goes high first) to CEX or WE
going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL .
7. For array access, tAVQV is required in addition to tWHGL for any accesses after a write.
8. VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success
(SR.1/3/4/5=0).
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38
MX26L6411
Figure 15. AC Waveform for Write Operations
A
B
C
D
E
F
VIH
VIL
Address
(A)
AIN
AIN
tAVWH
(tAVEH)
tWHAX
(tEHAX)
Disable
VIH
VIL
CEx,(WE)[E(W)]
Enable
tWHGL
(tEHGL)
tWHEH
(tEHWH)
tPHWL
(tPHEL)
VIH
VIL
OE
tELWL
(tWLEL)
tWPH
tWHQZ/tWHRH
Disable
VIH
VIL
WE,(CEx)[W(E)]
Enable
tWP
tOVWH
(tDVEH)
tWHDX
(tEHDX)
VIH
VIL
Valid
DIN
DATA[D/Q]
STS[R]
DIN
DIN
SRD
tWHRL
(tEHRL)
VOH
VOL
NOTES:
1. CEX low is defined as the first edge of CE that enables the device. CEX high is defined at the first edge of CE that
disables the device (see Table 1).
a.VCC power-up and standby.
b.Write block erase, write buffer, or program setup.
c.Write block erase or write buffer confirm, or valid address and data.
d. Automated erase delay.
e. Read status register or query data.
f. Write Read Array command.
P/N:PM0947
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MX26L6411
ERASE AND PROGRAMMING PERFORMANCE(1)
LIMITS
PARAMETER
MIN.
TYP.(2)
2.0
MAX.
15.0
654
UNITS
sec
Block Erase Time
Write Buffer Byte Program Time
(Time to Program 16 words)
218
us
Byte Program Time (Using Word Program Command)
Block Program Time (Using Write to Buffer Command)
Block Erase/Program Cycles
210
0.8
630
2.4
us
sec
100
Cycles
Note: 1.Not 100% Tested, Excludes external system level over head.
2.Typical values measured at 25°C,3.3V. Additionally programming typically assume checkerboard pattern.
LATCH-UP CHARACTERISTICS
MIN.
-1.0V
MAX.
13.5V
Input Voltage with respect to GND on all pins except I/O pins
Input Voltage with respect to GND on all I/O pins
Current
-1.0V
Vcc + 1.0V
+100mA
-100mA
Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.
CAPACITANCE TA=0°C to 70°C, VCC=2.7V~3.6V
Parameter Symbol
Parameter Description
Input Capacitance
Test Set
VIN=0
TYP
MAX
8
UNIT
pF
CIN
6
8
COUT
Output Capacitance
VOUT=0
12
pF
Notes:
1. Sampled, not 100% tested.
2.Test conditions TA=25°C, f=1.0MHz
DATA RETENTION
Parameter
Test Conditions
Min
10
Unit
Minimum Pattern Data Retention Time
150
125
Years
Years
20
P/N:PM0947
REV. 0.1,NOV. 20, 2002
40
MX26L6411
ORDERING INFORMATION
PLASTIC PACKAGE
Part NO.
Access Time
(ns)
Packagetype
Cycles
MX26L6411TC-10
100/30
48-TSOP
100
P/N:PM0947
REV. 0.1,NOV. 20, 2002
41
MX26L6411
PACKAGE INFORMATION
P/N:PM0947
REV. 0.1,NOV. 20, 2002
42
MX26L6411
REVISION HISTORY
Revision No. Description
Page
Date
0.1
1. To modify Package Information
P42
NOV/20/2002
P/N:PM0947
REV. 0.1,NOV. 20, 2002
43
MX26L6411
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