MX26L6419TC-10 [Macronix]
64M [x16] SINGLE 3V PAGE MODE MTP MEMORY; 64M 【 X16 】 3V单页模式MTP存储器
| 型号： | MX26L6419TC-10 |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | 64M [x16] SINGLE 3V PAGE MODE MTP MEMORY |
| 文件： | 总45页 (文件大小：436K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCED INFORMATION
MX26L6419
64M[x16] SINGLE3VPAGEMODEMTPMEMORY
FEATURES
• 3.0V to 3.6V operation voltage
• Block Structure
Software Feature
• Support Common Flash Interface (CFI)
- MTP device parameters stored on the device and
provide the host system to access.
- 64 x 64Kword Erase Blocks
• Fast random / page mode access time
- 100/25 ns Read AccessTime (page depth:8-word)
• 128-bit Protection Register
Hardware Feature
- 64-bit Unique Device Identifier
- 64-bit User Programmable OTP Cells
• 16-WordWrite Buffer
• ACC pin
- 12V VPP for fast program/erase mode.
• VPEN pin
- 14 us/word Effective Programming Time
- For Erase /Program/ Block Lock enable.
• Enhanced Data Protection Features Absolute Protec-
tion with VPEN = GND
• VCCQ Pin
-The output buffer power supply, control the device 's
- Flexible Block Locking
- Block Erase/Program Lockout during PowerTransi-
tions
output voltage.
• RESET pin
- Hardware reset
Performance
• Low power dissipation
Packaging
- 48-LeadTSOP
- typical 15mA active current for page mode read
- 80uA/(max.) standby current
• High Performance
Technology
- Two bits per cell Nbit (0.25u) MTPTechnology
- Block erase time: 2s typ.
- Word programming time:210us typ.
- Block programming time: 0.8s typ. (using Write to
Buffer Command)
• Program/Erase Endurance cycles: 100 cycles
electrical erasure and programming.The device uses a
command register to manage this functionality.
GENERAL DESCRIPTION
The MXIC's MX26L6419 series MTP use the most ad-
vance 2 bits/cell Nbit technology, double the storage ca-
pacity of memory cell.The device provide the high den-
sity MTP memory solution with reliable performance and
most cost-effective.
The MXIC's Nbit technology reliably stores memory con-
tents even after the specific erase and program cycles.
The MXIC cell is designed to optimize the erase and
program mechanisms by utilizing the dielectric's charac-
ter to trap or release charges from ONO layer.
The device organized as by 16 bits of output bus. The
device is packaged in 48-Lead TSOP. It is designed to
be reprogrammed and erased in system or in standard
EPROM programmers.
The device uses a 3.0V to 3.6V VCC supply to perform
the High Reliability Erase and auto Program/Erase algo-
rithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
The device offers fast access time and allowing opera-
tion of high-speed microprocessors without wait states.
The device augment EPROM functionality with in-circuit
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MX26L6419
PIN CONFIGURATION
48-TSOP (12mm x 20mm)
A15
A14
A13
A12
A11
A10
A9
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
VCCQ
GND
Q15
Q7
2
3
4
5
6
Q14
Q6
7
A8
8
Q13
Q5
A21
A20
WE
RESET
ACC
VPEN
A19
A18
A17
A7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Q12
Q4
VCC
Q11
Q3
MX26L6419 (x16 only)
Normal Type
Q10
Q2
Q9
Q1
A6
Q8
A5
Q0
A4
OE
A3
GND
CE
A2
A1
A0
PIN DESCRIPTION
SYMBOL
A0~A21
Q0~Q15
CE
PIN NAME
Address Input
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Reset Power Down mode
WE
OE
RESET
VPEN
ERASE/PROGRAM/BLOCK Lock
Enable
ACC
Program/erase acceleration pin
Output Buffer Power Supply
Device Power Supply
Device Ground
VCCQ
VCC
GND
Note: ACC pin and VPEN pin are not allowed to be op-
eration at the same time.
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MX26L6419
BLOCK DIAGRAM
WRITE
STATE
CE
OE
WE
CONTROL
INPUT
PROGRAM/ERASE
HIGH VOLTAGE
MACHINE
(WSM)
LOGIC
RESET
STATE
REGISTER
ADDRESS
LATCH
MTP
ARRAY
ARRAY
A0-A21
SOURCE
HV
AND
COMMAND
DATA
BUFFER
Y-PASS GATE
DECODER
PGM
DATA
HV
SENSE
AMPLIFIER
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
I/O BUFFER
Q0-Q15
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MX26L6419
Figure 1. Block Architecture
MTP memory reads erases and writes in-system via the local CPU. All bus cycles to or from the MTP memory
conform to standard microprocessor bus cycles.
A21~A0
3FFFFF
63
31
64-Kword Block
3F0000
.
.
.
1FFFFF
1F0000
64-Kword Block
.
.
.
01FFFF
1
0
64-Kword Block
64-Kword Block
010000
00FFFF
000000
Word Mode (x16)
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MX26L6419
Table 1. Bus Operations
Command
Sequence
Read
Array
Output Standby RESET Read ID Read
Read
Read
Write
Disable
Mode/
Power
Down
Mode
Query Status
Status
(WSM off) (WSM on)
Notes
RESET
CE
3,4
8,9
VIH
VIH
VIH
VIL
VIH
VIH
VIH
VIH
Enabled
VIL
VIH
X
VIH
Enabled Enabled Disabled X
Enabled Enabled Enabled
Enabled
VIH
OE (1)
WE (1)
Address
VPEN
Q (2)
VIL
VIH
X
VIH
VIH
X
X
X
X
X
X
X
X
X
VIL
VIH
See
VIL
VIH
See
VIL
VIH
X
VIL
X
Figure 2 Table 5
X
X
X
X
X
X
VPENH
Data out High Z High Z
High Z Note 6
Note 7 Data out Q7=Data out Data in
Q15-8=High Z
Q6-0=High Z
NOTES:
1. OE and WE should never be enabled simultaneously.
2. Q refers to Q0~Q15.
3. Refer to DC Characteristics.When VPEN < VPENLK , memory contents can be read, but not altered.
4. X can be VIL or VIH for control and address pins, and VPENLK or VPENH for VPEN . See DC Characteristics for
VPENLK and VPENH voltages.
5. High Z will beVOH with an external pull-up resistor.
6. See Section , "Read Identifier Codes" for read identifier code data.
7. See Section , "Read Query Mode Command" for read query data.
8. Command writes involving block erase, program, or lock-bit configuration are reliably executed when VPEN=
VPENH and VCC is within specification.
9. Refer to Table 2 on page 7 for valid DIN during a write operation.
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MX26L6419
FUNCTION
OUTPUT DISABLE
The device includes on-chip program/erase control cir-
cuitry. The Write State Machine (WSM) controls block
erase and word/page program operations. Operational
modes are selected by the commands written to the
Command User Interface (CUI).The Status Register in-
dicates the status of the WSM and when the WSM suc-
cessfully completes the desired program or block erase
operation.
When OE is atVIH, output from the devices is disabled.
Data input/output are in a high-impedance(High-Z) state.
STANDBY
When CE disable the device (see table1) and place it in
standby mode.The power consumption of this device is
reduced. Data input/output are in a high-impedance(High-
Z) state. If the memory is deselected during block erase,
program or lock-bit configuration, the internal control cir-
cuits remain active and the device consume normal ac-
tive power until the operation completes.
A Powerdown mode is enabled when the RESET pin is
at GND minimizing power consumption.
READ
The device has three read modes, which accesses to
the memory array, the Device Identifier or the Status
Register independent of the VPEN voltage. The appro-
priate read command are required to be written to the
CUI. Upon initial device powerup or after exit from
powerdown, the device automatically resets to read ar-
ray mode. In the read array mode, low level input to CE
and OE, high level input to WE and RESET or low level
input to RESET, and address signals to the address in-
puts (A21-A0) output the data of the addressed location
to the data input/output (Q15~Q0).
POWER-DOWN
When RESET pin is at VIL, the device is in the power-
down mode and its power consumption is substantially
low around 25uA. During read modes, the memory is
deselected and the data input/output are in a high-
impedance(High-Z) state. To return from power down
mode requires RESET pin at VIH. After return from
powerdown, the CUI is reset to Read Array , and the
Status Register is set to value 80H.
During block erase program or lock-bit configuration
modes, RESET pin at VIL will abort either operation.
Memory array data of the block being altered become
invalid.
When reading information in read array mode, the de-
vice defaults to asynchronous page mode. In this state,
data is internally read and stored in a high-speed page
buffer.A2:0 addresses data in the page buffer.The page
size is 8 words. Asynchronous word mode is supported
with no additional commands required.
Time tPHWL is required after RESET goes to logic-high
(VIH) before another command can be written.
WRITE
READ QUERY
Writes to the CUI enables reading of memory array data,
device identifiers and reading and clearing of the Status
Register and when VPEN=VPENH block erasure pro-
gram and lock-bit configuration.The CUI is written when
the device is enable, WE is active and OE is at high
level. Address and data are latched on the earlier rising
edge ofWE and CE.Standard micro-processor write tim-
ings are used.
The read query operation outputs block status informa-
tion, CFI (Common Flash Interface) ID string, system
interface information, device geometry information and
MXIC extended query information.
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MX26L6419
COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the CUI.Table 3 defines the valid
register command sequences.
When VPEN<VPENLK only read operations from the status register, query, indentifier code or blocks are enabled.
WhenVPEN=VPENH enables block erase program and lock-bit configuration operations.
Table 2. Command Definitions
Command
Sequence
Read
Array
Read Read
Read
Clear
Write to Word
Sector
ID
Query Status
Status
Buffer
Program Erase
Register Register
Notes
5
6
7,8,9
10,11
9,10
Bus Write Cycles Req'd
1
> 2
> 2
2
1
> 2
2
2
First Bus
Operation(2)
Write
X
Write Write
Write
X
Write
X
Write
BA
Write
X
Write
BA
Write Cycles Address(3)
Data(4,5)
X
X
FFH
90H
98H
70H
Read
X
50H
E8H
Write
BA
40H/10H
Write
PA
20H
Write
BA
Second Bus Operation(2)
Read Query Address(3)
Data(4,5)
Read Read
IA
ID
QA
QD
SRD
N
PD
D0H
Command
Sequence
Configur-
ation
Set Sector Clear
Protection
Lock-Bit
Sector
Program
Lock-Bit
Notes
12
Bus Write Cycles Req'd
2
2
2
2
First Bus
Operation(2) Write
Write
X
Write
X
Write
X
Write Cycle Address(3)
Data(4,5)
X
B8H
60H
Write
BA
60H
Write
X
C0H
Write
PA
Second Bus Operation(2) Write
Write Cycle Address(3)
Data(4,5)
X
CC
01H
D0H
PD
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MX26L6419
NOTES:
1. Bus operations are defined inTable 1.
2. X = Any valid address within the device.
BA = Address within the block.
IA = Identifier Code Address: see Figure 2 and Table 13.
QA = Query database Address.
PA = Address of memory location to be programmed.
RCD = Data to be written to the read configuration register.This data is presented to the device on A15~A0 ; all
other address inputs are ignored.
3. ID = Data read from Identifier Codes.
QD = Data read from Query database.
SRD = Data read from status register. See Table 14 for a description of the status register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE.
CC = Configuration Code.
4. The upper byte of the data bus (Q8-Q15) during command writes is a "Don't Care" in x16 operation.
5. Following the Read Identifier Codes command, read operations access manufacturer, device and block lock
codes. See Section 4.3 for read identifier code data.
6. If the WSM is running, only Q7 is valid; Q15-Q8 and Q6-Q0 float, which places them in a high impedance state.
7. After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing.
8. The number of words to be written to the Write Buffer = N + 1, where N = word count argument.
Count ranges on this device for word mode are N = 0000H to N =000FH.The third and consecutive bus cycles, as
determined by N, are for writing data into the Write Buffer.
The Confirm command (D0H) is expected after exactly N + 1 write cycles; any other command at that point in the
sequence aborts the write to buffer operation. Please see Figure 4. "Write to Buffer Flowchart" for additional
information.
9. The write to buffer or erase operation does not begin until a Confirm command (D0h) is issued.
10.Attempts to issue a block erase or program to a locked block.
11.Either 40H or 10H are recognized by the WSM as the word program setup.
12.The clear block lock-bits operation simultaneously clears all block lock-bits.
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MX26L6419
Figure 2. Device Identifier Code Memory Map
3FFFFF
Block 63
Reserved for Future
Implementation
3F0003
3F0002
Block 63 Lock Configuration
Reserved for Future
Implementation
3F0000
3EFFFF
(Block 32 through 62)
Block 31
Reserved for Future
Implementation
1F0003
1F0002
Block 31 Lock Configuration
Reserved for Future
Implementation
1F0000
1EFFFF
(Block 2 through 30)
01FFFF
Block 1
Reserved for Future
Implementation
010003
010002
Block 1 Lock Configuration
Reserved for Future
Implementation
010000
00FFFF
Block 0
Reserved for Future
Implementation
000004
000003
000002
000001
Block 0 Lock Configuration
Device Code
Manufacturer Code
000000
NOTE: Data is always given on the low byte in x16 mode (upper byte contains 00h).
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MX26L6419
Read Array Command
The device is in Read Array mode on initial device power
up and after exit from power down, or by writing FFH to
the Command User Interface.The read configuration reg-
ister defaults to asynchronous read page mode.The de-
vice remains enabled for reads until another command
is written.The Read Array command functions indepen-
dently of the VPEN voltage.
Read Query Mode Command
This section defines the data structure or "Database"
returned by the Common Flash Interface (CFI) Query
command. System software should parse this structure
to gain critical information such as block size, density,
x8/x16, and electrical specifications. Once this informa-
tion has been obtained, the software will know which
command sets to use to enable MTP writes, block
erases, and otherwise control the MTP component.
Query Structure Output
The Query Database allows system software to gain in-
formation for controlling the MTP component.This sec-
tion describes the device CFI-compliant interface that
allows the host system to access Query data.
Query data are always presented on the lowest-order
data outputs (DQ 0-7) only.The numerical offset value is
the address relative to the maximum bus width supported
by the device. On this family of devices, the Query table
device starting address is a 10h, which is a word ad-
dress for x16 devices.
For a word-wide (x16) device, the first two bytes of the
Query structure, "Q" and "R" in ASCII, appear on the
low byte at word addresses 10h and 11h.This CFI-com-
pliant device outputs 00H data on upper bytes.Thus, the
device outputs ASCII "Q" in the low byte (DQ 0-7 ) and
00h in the high byte (DQ 8-15 ).
At Query addresses containing two or more bytes of in-
formation, the least significant data byte is presented at
the lower address, and the most significant data byte is
presented at the higher address.
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MX26L6419
In all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been
dropped.In addition, since the upper byte of word-wide devices is always "00h",” the leading "00" has been dropped
from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h
on the upper byte in this mode.
Table 3. Summary of Query Structure Output as a Function of Device and Mode
Device
Query start location in
maximum device bus
width addresses
Query data with maximum
device bus width addressing
Query data with byte
addressing
Type/Mode
Hex
Offset
10:
Hex
Code
0051
0052
0059
ASCII
Value
"Q"
Hex
Hex
Code
51
ASCII
Offset
20:
Value
"Q"
x16 device
x16 mode
10h
11:
"R"
21:
00
"Null"
"R"
12:
"Y"
22:
52
x16 device
x8 mode
20:
51
"Q"
N/A (1)
N/A (1)
21:
51
"Q"
22:
52
"R"
NOTE:
1. The system must drive the lowest order addresses to access all the device's array data when the device is
configured in x8 mode.Therefore, word addressing, where these lower addresses are not toggled by the system, is
"Not Applicable" for x8-configured devices.
Table 4. Example of Query Structure Output of a x16- and x8-Capable Device
Word Addressing
Hex Code
Byte Addressing
Hex Code
Offset
A15-A0
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
...
Value
Offset
A7-A0
20h
21h
22h
23h
24h
25h
26h
27h
28h
...
Value
D15 - D0
D7 - D0
0051
0052
0059
P_IDLO
P_IDHI
PLO
"Q"
"R"
51
51
"Q"
"Q"
"Y"
52
"R"
PrVendor
ID#
52
"R"
59
"Y"
PrVendor
TblAdr
AltVendor
ID#
59
"Y"
PHI
P_IDLO
P_IDLO
P_IDHI
...
PrVendor
ID#
A_IDLO
A_IDHI
...
ID#
...
...
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MX26L6419
Query Structure Overview
The Query command causes the MTP component to display the Common Flash Interface (CFI) Query structure or
"database". The structure sub-sections and address locations are summarized below.
Table 5. Query Structure (1)
Offset
00h
Sub-Section
Name Description
Manufacturer Code
01h
Device Code
(BA+2)h (2)
04-0Fh
10h
Block Status Register
Reserved
Block-Specific Information
Reserved forVendor-Specific Information
Reserved forVendor-Specific Information
Command Set ID andVendor Data Offset
MTP Device Layout
CFI Query Identification String
System Interface Information
Device Geometry Definition
Primary MXIC-Specific Extended
QueryTable
1Bh
27h
P (3)
Vendor-Defined Additional Information Specific to the
PrimaryVendor Algorithm
NOTES:
1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a
function of device bus width and mode.
2. BA = Block Address beginning location (i.e., 02000h is block 2s beginning location when the block size is 128
Kbyte).
3. Offset 15 defines "P" which points to the Primary MXIC-Specific Extended Query Table.
Block Status Register
The block status register indicates whether an erase operation completed successfully or whether a given block is
locked or can be accessed for MTP program/erase operations.
Table 6. Block Status Register
Offset
Length
Description
Address
Value
(BA+2)h (1)
1
Block Lock Status Register
BSR.0 Block Lock Status
0 = Unlocked
BA+2:
--00 or --01
BA+2:
BA+2:
(bit 0): 0 or 1
(bit 1-7): 0
1 = Locked
BSR 1-7: Reserved for Future Use
NOTE:
1. BA =The beginning location of a Block Address (i.e., 008000h is block 1s (64-KB block) beginning location in word
mode).
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MX26L6419
CFI Query Identification String
The CFI Query Identification String provides verification that the component supports the Common Flash Interface
specification. It also indicates the specification version and supported vendor-specified command set(s).
Table 7. CFI Identification
Offset
Length
Description
Add.
Hex
Code
--51
--52
--59
--01
--00
--31
--00
--00
--00
--00
--00
Value
10h
3
Query-unique ASCII string "QRY"
10
11:
12:
13:
14:
15:
16:
17:
18:
19:
1A:
"Q"
"R"
"Y"
13h
15h
17h
19h
2
2
2
2
Primary vendor command set and control interface ID code.
16-bit ID code for vendor-specified algorithms
Extended QueryTable primary algorithm address
Alternate vendor command set and control interface ID code.
0000h means no second vendor-specified algorithm exists
Secondary algorithm Extended QueryTable address.
0000h means none exists
System Interface Information
The following device information can optimize system interface software.
Table 8. System Interface Information
Offset
Length
Description
Add.
1B:
1C:
1D:
1E:
Hex
Value
3.0V
3.6 V
0.0V
0.0V
Code
1Bh
1
VCC logic supply minimum program/erase voltage
bits 0-3 BCD 100 mV
--30
--36
--00
--00
bits 4-7 BCD volts
1Ch
1Dh
1Eh
1
1
1
VCC logic supply maximum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 BCD volts
VPP [programming] supply minimum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 HEX volts
VPP [programming] supply maximum program/erase voltage
bits 0-3 BCD 100 mV
bits 4-7 HEX volts
1Fh
20h
21h
22h
23h
24h
25h
26h
1
1
1
1
1
1
1
1
"n" such that typical single word program time-out = 2nus
"n" such that typical max. buffer write time-out = 2nus
"n" such that typical block erase time-out = 2nms
"n" such that typical full chip erase time-out = 2nms
1F:
20:
21:
22:
--07
--07
--0A
--00
--04
--04
--04
--00
128us
128us
1s
NA
"n" such that maximum word program time-out = 2n times typical 23:
2ms
2ms
16s
"n" such that maximum buffer write time-out = 2n times typical
"n" such that maximum block erase time-out = 2n times typical
"n" such that maximum chip erase time-out = 2n times typical
24:
25:
26:
NA
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MX26L6419
Device Geometry Definition
This field provides critical details of the MTP device geometry.
Table 9. Device Geometry Definition
Offset Length
Description
Code See Table
Below
27h
28h
1
2
"n" such that device size = 2n in number of bytes
MTP device interface: x8 async(28:00,29:00),
27:
28:
29:
2A:
2B:
--17
--01
--00
--05
--00
x16
32
x16 async(28:01,29:00), x8/x16 async(28:02,29:00)
"n" such that maximum number of bytes in write buffer = 2n
2Ah
2
Number of erase block regions within device:
1. x = 0 means no erase blocking; the device erases in "bulk"
2. x specifies the number of device or partition regions with one or
more contiguous same-size erase blocks
2Ch
2Dh
1
4
2C:
--01
1
3. Symmetrically blocked partitions have one blocking region
4. Partition size = (total blocks) x (individual block size)
Erase Block Region 1 Information
2D:
2E:
2F:
30:
--3F
--00
--00
--02
bits 0-15 = y, y+1 = number of identical-size erase blocks
bits 16-31 = z, region erase block(s) size are z x 256 bytes
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MX26L6419
Primary-Vendor Specific Extended Query Table
Certain MTP features and commands are optional.The PrimaryVendor-Specific Extended Query table specifies this
and other similar information.
Table 10. Primary Vendor-Specific Extended Query
Offset(1) Length Description
Add.
Hex
Code
--50
--52
--49
--31
--31
--C8
--00
--00
--00
Value
P=31h
(P+0)h
(P+1)h
(P+2)h
(P+3)h
(P+4)h
(P+5)h
(P+6)h
(P+7)h
(P+8)h
(Optional MTP Features and Commands)
3
Primary extended query table
Unique ASCII string "PRI"
31:
32:
33:
34:
35:
36:
37:
38:
39:
"P"
"R"
"I"
1
1
Major version number, ASCII
"1"
"1"
Minor version number, ASCII
Optional feature and command support (1=yes, 0=no)
bits 9-31 are reserved; undefined bits are "0". If bit 31 is
"1" then another 31 bit field of optional features follows at
the end of the bit-30 field.
bit 0 Chip erase supported
bit 0 = 0
No
No
4
bit 1 Suspend erase not supported
bit 2 Suspend program not supported
bit 3 Legacy lock/unlock supported
bit 4 Queued erase supported
bit 1 = 0
bit 2 = 0
No
bit 3 = 1(1)
bit 4 = 0
bit 5 = 0
bit 6 = 1
bit 7 = 1
bit 8 = 0
Yes(1)
No
bit 5 Instant Individual block locking supported
bit 6 Protection bits supported
No
Yes
Yes
No
bit 7 Page-mode read supported
bit 8 Synchronous read supported
(P+9)h
1
Reserved for future use
3A:
--00
(P+A)h
(P+B)h
Block status register mask
3B:
3C:
--01
--00
2
1
1
bits 2-15 are Reserved; undefined bits are "0"
bit 0 Block Lock-Bit Status register active
bit 1 Block Lock-Down Bit Status active
VCC logic supply highest performance program/erase voltage
bits 0-3 BCD value in 100 mV
bit 0 = 1
bit 1 = 0
Yes
No
(P+C)h
(P+D)h
3D:
3E:
--33
--00
3.3V
0.0V
bits 4-7 BCD value in volts
VPP optimum program/erase supply voltage
bits 0-3 BCD value in 100 mV
bits 4-7 HEX value in volts
NOTE:
1.Future devices may not support the described "Legacy Lock/Unlock" function.Thus bit 3 would have a value of "0".
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MX26L6419
Table 11. Protection Register Information
Offset(1) Length Description
Add. Hex
Code
Value
P=31h
(Optional MTP Features and Commands)
(P+E)h
1
Number of Protection register fields in JEDEC ID space.
"00h," indicates that 256 protection bytes are available
Protection Field 1: Protection Description
3F:
--01
01
This field describes user-available OneTime Programmable
(OTP) protection register bytes.Some are pre-programmed
with device-unique serial numbers. Others are user-programmable.
Bits 0-15 point to the protection register lock
(P+F)h
(P+10)h
(P+11)h
(P+12)h
40:
--00
00h
byte, the section's first byte. The following bytes are factory
pre-programmed and user-programmable.
bits 0-7 = Lock/bytes JEDEC-plane physical low address
bits 8-15 = Lock/bytes JEDEC-plane physical high address
bits 16-23 = "n" such that 2 n = factory pre-programmed bytes
bits 24-31 = "n" such that 2 n = user-programmable bytes
NOTE:
1.The variable P is a pointer which is defined at CFI offset 15h.
Table 12. Page Read Information
Offset(1) Length Description
Add.
Hex
Value
P=31h
(Optional MTP Features and Commands)
Code
Page Mode Read capability
bits 0-7 = "n" such that 2n HEX value represents the number
of read-page bytes. See offset 28h for device word width to
determine page-mode data output width. 00h indicates no
read page buffer.
(P+13)h
1
1
44:
--04
16 byte
0
(P+14)h
(P+15)h
Number of synchronous mode read configuration fields that
follow. 00h indicates no burst capability.
Reserved for future use
45:
46:
--00
NOTE:
1.The variable P is a pointer which is defined at CFI offset 15h.
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MX26L6419
DEVICE OPERATION
SILICON ID READ
The Silicon ID Read mode allows the reading out of a
binary code from the device and will identify its manu-
facturer and type. This mode is intended for use by
programming equipment for the purpose of automatically
matching the device to be programmed with its corre-
sponding programming algorithm. This mode is func-
tional over the entire temperature range of the device.
During the "Silicon ID Read" Mode, manufacturer's code
(MXIC=C2H) can be read out by setting A0=VIL and
device identifier can be read out by setting A0=VIH.
To terminate the operation, it is necessary to write the
read command. The "Silicon ID Read" command func-
tions independently of theVPEN voltage.This command
is valid only when the WSM is off.
To activate this mode, the two cycle "Silicon ID Read"
command is requested. (The ID code value is illustrated
inTable 13.)
Table 13. MX26L6419 Silicon ID Codes
Type
Address (1) Code (HEX) Q7 Q6
Q5 Q4 Q3 Q2 Q1 Q0
Manufacture Code
Device Code
00000
C2H
1
1
1
0
0
1
0
0
0
1
0
1
1
1
0
0
00001
00AEH
Block Lock Configuration
- Block is Unlocked
- Block is Locked
X0002 (2)
DQ0=0
DQ0=1
DQ1-7
- Reserved for Future Use
Notes:
1.The lowest order address line is A0.
2. X selects the specific blocks lock configuration code.
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MX26L6419
Table 14. Status Register Definitions
High Z
Symbol When Status
Busy?
Definition
Notes
"1"
"0"
Busy
SR.7
SR.6
No
WRITE STATE MACHINE STATUS Ready
RESERVED
1
Yes
SR.5
Yes
ERASE AND CLEAR LOCK-BITS Error in Block Erasure or Successful Block
2
3
STATUS
Clear Lock-Bits
Erase or Clear
Lock-Bits
SR.4
SR.3
Yes
Yes
PROGRAM AND SET LOCK-BIT
STATUS
Error in Setting Lock-Bit Successful Set Block
Lock Bit
PROGRAMMINGVOLTAGE
STATUS
Low ProgrammingVoltage ProgrammingVoltage
Detected, Operation
Aborted
OK
SR.2
SR.1
Yes
Yes
Yes
RESERVED
DEVICE PROTECT STATUS
RESERVED
Block Lock-Bit Detected, Unlock
Operation Abort
4
5
SR.0
Notes
1. Check SR.7 to determine block erase, program, or lock-bit configuration completion. SR.6-SR.0 are not driven
while SR.7 = 0
2. If both SR.5 and SR.4 are "1" after a block erase or lock-bit configuration attempt, an improper command se-
quence was entered.
3. SR.3 does not provide a continuous programming voltage level indication.TheWSM interrogates and indicates the
programming voltage level only after Block Erase, Program, Set Block Lock-Bit, or Clear Block Lock-Bits com-
mand sequences.
4. SR.1 does not provide a continuous indication of block lock-bit values.The WSM interrogates the block lock-bits
only after Block Erase, Program, or Lock-Bit configuration command sequences. It informs the system, depend-
ing on the attempted operation, if the block lock-bit is set. Read the block lock configuration codes using the Read
Identifier Codes command to determine block lock-bit status.
5. SR.0 is reserved for future use and should be masked when polling the status register.
Table 15. Extended Status Register Definitions
High Z
Symbol When Status
Busy?
Definition
Notes
"1"
Write buffer available
"0"
XSR.7 No
XSR.6- Yes
XSR.0
WRITE BUFFER STATUS
RESERVED
Write buffer not available
1
2
Notes:
1. After a Buffer-Write command, XSR.7 = 1 indicates that a Write Buffer is available.
2. XSR.6-XSR.0 are reserved for future use and should be masked when polling the status register.
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MX26L6419
be read when CE is VIL. XSR.7 indicates if the Write
Buffer is available.
READ STATUS REGISTER COMMAND
The Status Register is read after writing the Read Status
Register command of 70H to the Command User Inter-
face. Also, after starting the internal operation the de-
vice is set to the Read Status Register mode automati-
cally.
If the buffer is available, the number of words to be pro-
gram is written to the device. Next, the start address is
given along with the write buffer data. Subsequent writes
provide additional device addresses and data, depend-
ing on the count. After the last buffer data is given, a
Write Confirm command must be issued.The WSM be-
ginning copy the buffer data to the MTP array.
The contents of Status Register are latched on the later
falling edge of OE or the first edge of CE that enables
the device OE must be toggle toVIH or the device must
be disable before further reads to update the status reg-
ister latch. The Read Status Register command func-
tions independently of the VPEN voltage.
If an error occurs while writing, the device will stop writ-
ing, and status register bit SR.4 will be set to a "1" to
indicate a program failure.The internal WSM verify only
detects errors for "1" that do not successfully program
to "0" . If a program error is detected, the status register
should be cleared. Any time SR.4 and/or SR.5 is set, the
device will not accept any more Write to Buffer com-
mands.Reliable buffered writes can only occur whenVCC
is valid and VPEN = VPENH. Also, successful program-
ming requires that the corresponding block lock-bit be
reset.
CLEAR STATUS REGISTER COMMAND
The Erase Status, Program Status, Block Status bits
and protect status are set to "1" by the Write State Ma-
chine and can only be reset by the Clear Status Register
command of 50H. These bits indicates various failure
conditions.
WORD PROGRAM COMMANDS
BLOCK ERASE COMMAND
Word program is executed by a two-command sequence.
The Word Program Setup command of 40H is written to
the Command Interface, followed by a second write speci-
fying the address and data to be written.The WSM con-
trols the program pulse application and verify operation.
The CPU can detect the completion of the program event
by analyzing the status register bit SR.7.
Automated block erase is initiated by writing the Block
Erase command of 20H followed by the Confirm com-
mand of D0H. An address within the block to be erased
is required (erase changes all block data to FFH).
Block preconditioning, erase, and verify are handled in-
ternally by the WSM (invisible to the system). The CPU
can detect block erase completion by analyzing the sta-
tus register bit SR.7.Toggle OE, CE to update the status
register. The CUI remains in read status register mode
until a new command is issued. Also, reliable block era-
sure can only occur when VCC is valid and VPEN =
VPENH .
If a word program is attempted while VPEN_V PENLK,
status register bits SR.4 and SR.3 will be set to "1".
Successful word programs require that the correspond-
ing block lock-bit be cleared. If a word program is at-
tempted when the corresponding block lock-bit is set,
SR.1 and SR.4 will be set to "1".
ACC FAST PROGRAM/ERASE FUNCTIONS
WRITE TO BUFFER COMMAND
When VPP is between 3.0V and 3.6V, all program and
erase current is drawn through theVCC pin.When ACC
pin is connected to a 12V power supply, the device draws
program and erase current directly from the ACC pin.
This eliminates the need for an external switching tran-
sistor control the voltage VPP.
To program the device, a Write to Buffer command is
issue first. A variable number of bytes, up to the buffer
size, can be loaded into the buffer and written to the
MTP device. First, the Write to Buffer Setup command
is issued along with the Block Address (see Figure 4,
Write to Buffer Flowchart on page 25). After the com-
mand is issued, the extended Status Register (XSR) can
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MX26L6419
The 12V ACC mode enhances programming performance
during the short period of time typically found in manu-
facturing processes; however, it is not intended for ex-
tended use. ACC pin may be connected to 12V for a
total of 80 hours maximum. Stressing the device beyond
these limits may cause permanent damage.
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MX26L6419
Read Configuration
The device will support both asynchronous page mode and standard word reads.No configuration is required.
Status register and identifier only support standard word single read operations.
Table 16. Read Configuration Register Definition
RM
R
14
R
6
R
13
R
5
R
12
R
4
R
R
10
R
2
R
9
R
8
15(A15)
11
R
7
R
R
1
R
0
3
Notes
RCR.15 = READ MODE (RM)
Read mode configuration effects reads from the MTP
array.
0 = Standard Word Reads Enabled (Default)
1 = Page-Mode Reads Enabled
Status register, query, and identifier reads support
standard word read cycles.
RCR.14-0= RESERVED FOR FUTURE
ENHANCEMENTS (R)
These bits are reserved for future use. Set these
bits to "0".
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MX26L6419
tion.To return to read array mode, write the Read Array
command (FFH).
Set Block Lock-Bit Commands
This device provided the block lock-bits, to lock and
unlock the individual block.To set the block lock-bit, the
two cycle Set Block Lock-Bit command is requested.
This command is invalid while the WSM is running. Writ-
ing the set block lock-bit command of 60H followed by
confirm command and an appropriate block address.
After the command is written, the device automatically
outputs status register data when read. The CPU can
detect the completion of the set lock-bit event by ana-
lyzing the status register bit SR.7. Also, reliable opera-
tions occur only when VCC and VPEN are valid. With
VPEN _VPENLK , lock-bit contents are protected against
alteration.
Programming the Protection Register
The protection register bits are programmed using the
two-cycle Protection Program command.The 64-bit num-
ber is programmed 16 bits at a time for word-wide parts.
First write the Protection Program Setup command, C0H.
The next write to the device will latch in address and
data and program the specified location.
Any attempt to address Protection Program commands
outside the defined protection register address space will
result in a status register error. Attempting to program a
locked protection register segment will result in a status
register error.
Clear Block Lock-Bits Command
All set block lock-bits can clear by the Clear Block Lock-
Bits command.This command is invalid while the WSM
is running. To Clear the block lock-bits, two cycle com-
mand is requested . The device automatically outputs
status register data when read. The CPU can detect
completion of the clear block lock-bits event by analyz-
ing the status register bit SR.7. If a clear block lock-bits
operation is aborted due toV PEN orV CC transitioning
out of valid range, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-bits is
required to initialize block lock-bit contents to known
values.
Locking the Protection Register
The user-programmable segment of the protection regis-
ter is lockable by programming Bit 1 of the PR-LOCK
location to 0. Bit 0 of this location is programmed to 0 at
the MXIC factory to protect the unique device number.
Bit 1 is set using the Protection Program command to
program "FFFD" to the PR-LOCK location. After these
bits have been programmed, no further changes can be
made to the values stored in the protection register.Pro-
tection Program commands to a locked section will re-
sult in a status register error. Protection register lockout
state is not reversible.
Protection Register Program Command
VCC, VPEN, RESET--TRANSITIONS
The device offer a 128-bit protection register to increase
the security of a system design.The 128-bits protection
register are divided into two 64-bit segments. One is pro-
grammed in the factory with a unique 64-bit number,
which is unchangeable. The other one is left blank for
customer designers to program as desired. Once the
customer segment is programmed, it can be locked to
prevent reprogramming.
Block erase, program, and lock-bit configuration are not
guaranteed ifVPEN orVCC falls outside of the specified
operating ranges, or RESET =VIH.If RESET transitions
toVIL during block erase, program, or lock-bit configura-
tion will remain low for a maximum time of tPLPH+tPHRH
until the reset operation is complete.Then, the operation
will abort and the device will enter reset/power-down mode.
The aborted operation may leave data partially corrupted
after programming, or partially altered after an erase or
lock-bit configuration. Therefore, block erase and lock-
bit configuration commands must be repeated after nor-
mal operation is restored. Device power-off or RESET=VIL
clears the Status Register.
Reading the Protection Register
The protection register is read in the identification read
mode.The device is switched to this mode by writing the
Read Identifier command 90H. Once in this mode, read
cycles from addresses retrieve the specified informa-
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MX26L6419
The CUI latches commands issued by system software
and is not altered by VPEN, CE transitions, or WSM ac-
tions. Its state is read array mode upon power-up, after
exit from reset/power-down mode, or after VCC transi-
tions below VLKO.VCC must be kept at or aboveVPEN
duringVCC transitions.
After block erase, program, or lock-bit configuration, even
after VPEN transitions down to VPENLK, the CUI must
be placed in read array mode via the Read Array com-
mand if subsequent access to the memory array is de-
sired.VPEN must be kept at or belowVCC duringVPEN
transitions.
Figure 3. Protection Register Memory Map
Word
Address
A[21 - 0]: 64 Mbit
88H
4 Words
User Programmed
85H
84H
4 Words
Factory Programmed
81H
80H
1 Word Lock
NOTE: The lowest order address line is A0.
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MX26L6419
Table 17. Word-Wide Protection Register Addressing
Word
Use
A7
1
A6
0
A5
0
A4
0
A3
0
A2
0
A1
A0
0
LOCK
Both
0
0
1
2
3
4
5
6
7
Factory
Factory
Factory
Factory
User
1
0
0
0
0
0
0
1
1
0
0
1
1
0
1
1
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
0
0
0
1
1
User
1
0
0
0
0
1
0
User
1
0
0
0
0
1
1
User
1
0
0
0
1
0
0
NOTE: 1. All address lines not specified in the above table must be 0 when accessing the Protection Register,
i.e., A21-A8 = 0.
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MX26L6419
Figure 4. Write to Buffer Flowchart
Start
Command Cycle
- Issue Write-to-Buffer Command
- Address=Any address in block
- Data=0xE8
Check Ready Status
- Read Status Register Command not required
- Perform read operation
- Read Ready Status on signal D7
NO
NO
Write to Buffer
Time-Out ?
D7=1?
YES
YES
Write Word Count
- Address=Any address in block
- Data=word count
- Valid range=0x0 thru 0x1F
Write Buffer Data
- Fill write buffer up to word count
- Address=Address(es) within buffer range
- Data=Data to be written
Confirm Cycle
- Issue Confirm Command
- Address=Any address in block
- Data=0xD0
Read Status Register
See Status Register Flowchart
YES
Error-Handler
User-defined routine
Any Errors?
NO
End
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MX26L6419
Figure 5. Status Register Flowchart
Start
Command Cycle
- Issue Status Register Command
- Address = any device address
- Data = 0x70
Data Cycle
- Read Status Register SR[7:0]
No
SR7 = '1'
Yes
Yes
- Set/Reset
by WSM
Erase Suspend
See Suspend/Resume Flowchart
SR6 = '1'
No
Yes
Program Suspend
See Suspend/Resume Flowchart
SR2 = '1'
No
Yes
Yes
Error
SR5 = '1'
SR4 = '1'
Command Sequence
No
No
Error
Erase Failure
Yes
Error
Program Failure
SR4 = '1'
No
- Set by WSM
- Reset by user
- See Clear Status
Register
Yes
Error
VPEN < VPENLK
SR3 = '1'
Command
No
Yes
Error
Block Locked
SR1 = '1'
No
End
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MX26L6419
Figure 6. Word Programming Flowchart
Bus
Command
Comments
Operation
Write
Start
Setup
Data=40H
Word Program Addr=Location to Be
Programmed
Write 40H,
Address
Write
Word
Program
Data=Data to Be
Programmed
Write Data
and Address
Addr=Location to Be
Programmed
Read
Status Register Data
Read
(Note 1)
Standby
Status Register
Check SR.7
1=WSM Ready
0=WSM Busy
0
SR.7=
1.Toggling OE (low to high to low) updates the status
register.This can be done in place of issuing the Read
Status Register command. Repeat for subsequent pro-
gramming operations.
1
Full Status Check if Desired
SR full status check can be done after each program
operation, or after a sequence of programming opera-
tions.
Word Program Complete
Write FFH after the last program operation to place
device in read array mode.
FULL STATUS CHECK PROCEDURE
Bus
Command Comments
Read Status Register
Data (See Above)
Operation
Standby
Check SR.3
1=Programming toVoltage
Error Detect
1
VPP Range Error
SR.3=
Standby
Check SR.1
1=Device Protect Detect
RP=VIH, Block Lock-Bit is
Set Only required for
systems
0
1
1
SR.1=
0
Device Protect Error
Programming Error
Standby
Check SR.4
1=Programming Error
Toggling OE (low to high to low) updates the status
register.This can be done in place of issuing the Read
Status Register command. Repeat for subsequent pro-
gramming operations.
SR.4=
0
SR.4, SR.3, and SR.1 are only cleared by the Clear
Status Register Command in cases where multiple lo-
cation are programmed before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery.
Word Program Successful
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MX26L6419
Figure 7. Block Erase Flowchart
Start
Write 20H to Block Address
Write Confirm D0H to Block Address
Read
Status Register
NO
SR.7=1 ?
YES
Full Status Check
If Desired
Erase MTP
Block(s) Completed
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MX26L6419
Figure 8. Set Block Lock-Bit Flowchart
Start
Write 60H, Block Address
Write 01H, Block Address
Read
Status Register
NO
SR.7=1 ?
YES
Full Status Check
If Desired
Set Lock-Bit Completed
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
NO
Voltage Range Error
SR.3=0 ?
YES
YES
SR.4,5=1 ?
Command Sequence Error
NO
NO
Set Lock-Bit Error
SR.4=0 ?
YES
Set Lock-Bit Successful
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MX26L6419
Figure 9. Clear Lock-Bit Flowchart
Start
Write 60H
Write D0H
Read
Status Register
NO
SR.7=1 ?
YES
Full Status Check
If Desired
Set Lock-Bit Completed
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
NO
Voltage Range Error
SR.3=0 ?
YES
YES
SR.4,5=1 ?
Command Sequence Error
Clear Block Lock-Bits Error
NO
NO
SR.5=0 ?
YES
Clear Block Lock-Bit Successful
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MX26L6419
Figure 10. Protection Register Programming Flowchart
Start
Write C0H (Protection Reg.
Program Setup)
Write Protect. Register
Address/Data
Read
Status Register
NO
SR.7=1 ?
YES
Full Status Check
If Desired
Program Completed
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (See Above)
1,1
VPEN Range Error
SR.3, SR.4=
0,1
Protection Register
Programming Error
SR.1, SR.4=
1,1
Attempted Program to Locked
Register-Aborted
SR.1, SR.4=
YES
Program Successful
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MX26L6419
OPERATING RATINGS
ABSOLUTE MAXIMUM RATINGS
StorageTemperature
Commercial (C) Devices
Plastic Packages . . . . . . . . . . . . . ..... -65oC to +150oC
Ambient Temperature (TA ). . . . . . . . . . . . 0°C to +70°C
VCC Supply Voltages
AmbientTemperature
with Power Applied. . . . . . . . . . . . . .... -65oC to +125oC
Voltage with Respect to Ground
VCC for full voltage range. . . . . . . . . . . +3.0 V to 3.6 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V
RESET (Note 2) . . . . . . . . . . . . . . -0.5 V to +12.5 V
All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V
ACC pin (Note 1, Note 4) . . . . . . . -0.5 V to +13.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5 V.
During voltage transitions, input or I/O pins may over-
shoot VSS to -2.0 V for periods of up to 20 ns. See
Figure 6. Maximum DC voltage on input or I/O pins is
VCC +0.5 V. During voltage transitions, input or I/O
pins may overshoot to VCC +2.0 V for periods up to
20 ns. See Figure 7.
2. Minimum DC input voltage on pins RESET is -0.5 V.
During voltage transitions, RESET may overshoot
VSS to -2.0V for periods of up to 20 ns.See Figure 6.
3.No more than one output may be shorted to ground at
a time. Duration of the short circuit should not be
greater than one second.
4. ACC pin may be connected to 12V for a total of 80
hours maximum.
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device at these or any other conditions above those in-
dicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maxi-
mum rating conditions for extended periods may affect
device reliability.
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MX26L6419
DC Characteristics
Symbol Parameter
Notes
Typ
Max
Unit
Test Conditions
ILI
Input andVPEN Load Current
±1
uA
VCC =VCC Max;VCCQ =VCCQ Max
VIN = VCCQ or GND
ILO
Output Leakage Current
VCC Standby Current
±10
uA
VCC =VCC Max;VCCQ =VCCQ Max
VIN = VCCQ or GND
CMOS Inputs, VCC = VCC Max,
Device is disabled (see table 1)
RESET=VCCQ±0.2V
ICC1
ICC2
ICC3
1,2
25
80
2
uA
0.71
mA
TTL Inputs, VCC=VCC max,
Device is disable (see table 1),
RESET=VIH
VCC Power-Down Current
25
15
24
80
20
29
uA
mA
mA
RESET=GND±0.2V,
CMOS Inputs, VCC=VCC Max,
VCCQ=VCCQ Max
Device is enabled (see Table 1)
f=5MHz, IOUT=0mA
VCC Page Mode Read Current
2
CMOS Inputs, VCC=VCC Max,
VCCQ=VCCQ Max
Device is enabled (see Table 1)
f=33MHz, IOUT=0mA
ICC5
ICC6
VCC Program or Set Lock-Bit
Current
35
40
35
40
60
70
70
80
mA
mA
mA
mA
CMOS Inputs, VPEN=VCC
TTL Inputs, VPEN=VCC
CMOS Inputs, VPEN=VCC
TTL Inputs, VPEN=VCC
VCC Block Erase or Clear
Block Lock-Bits Current
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MX26L6419
DC Characteristics, Continued
Symbol Parameter
Notes
Min
-0.5
2.0
Max
0.8
Unit
Test Conditions
VIL
Input LowVoltage
Input HighVoltage
2
2
V
V
V
VIH
VCCQ+0.5
0.4
VCCQ=VCCQ2/3 Min
IOL=2mA
VOL
Output LowVoltage
2
0.2
V
V
V
V
V
V
VCCQ=VCCQ2/3 Min
IOL=100uA
0.85 x
VCCQ
VCCQ=VCCQ Min
IOH=-2.5mA
VOH
Output HighVoltage
2
VCCQ-0.2
VCCQ=VCCQ Min
IOH=-100uA
VPENLK VPEN Lockout during Program, 2,3,4
Erase and Lock-Bit Operations
0.5xVCC
3.6
VPENH VPEN during Block Erase,
Program, or Lock-Bit Operations
3,4
3.0
2.2
VLKO
VCC LockoutVoltage
5
NOTES:
1. CMOS inputs are either VCC ±0.2 V or GND ±0.2 V.TTL inputs are either VIL or VIH .
2. Sampled, not 100% tested.
3.Block erases, programming, and lock-bit configurations are inhibited whenVPEN ˆVPENLK , and not guaranteed
in the range betweenVPENLK (max) andVPENH (min), and aboveVPENH (max).
4.Typically, VPEN is connected to VCC (3.0V - 3.6 V).
5.Block erases, programming, and lock-bit configurations are inhibited whenVCC <VLKO , and not guaranteed in the
range betweenVLKO (min) andVCC (min), and aboveVCC (max).
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34
MX26L6419
Figure 11. Transient Input/Output Reference Waveform for VCCQ=3.0V-3.6V
VCCQ
Input VCCQ/2
0.0
VCCQ/2 Output
TEST POINTS
Note:AC test inputs are driven at VCCQ for a Logic "1" and 0.0V for a Logic "0".
Input timing being, and output timing ends, at VCCQ/2V (50% of VCCQ).
Input rise and fall times (10% tp 90%)<5ns.
Figure 12. Transient Equivalent Testing Load Circuit
1.3V
1N914
RL=3.3K ohm
Device
Out
Under Test
CL
NOTE: CL Includes Jig Capacitance
Test Configuration
C L (pF)
VCCQ = VCC = 3.0 V-3.6 V
30
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35
MX26L6419
AC Characteristics --Read-Only Operations (1,2)
Versions
VCC
VCCQ
Notes
3.0V-3.6V(3)
3.0V-3.6V(3)
(All units in ns unless otherwise noted)
Sym
Parameter
Min
Max
tAVAV
tAVQV
tELQV
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
tOH
Read/Write CycleTime
100
Address to Output Delay
CEX to Output Delay
100
100
50
2
OE to Non-Array Output Delay
RESET High to Output Delay
CEX to Output in Low Z
2, 4
180
5
5
5
5
5
0
0
OE to Output in Low Z
CEX High to Output in High Z
OE High to Output in High Z
Output Hold from Address, CEX, or OE
Change, Whichever Occurs First
CEx High to CEx Low
35
15
0
0
tEHEL
tAPA
5
5, 6
4
Page Address Access Time
OE to Array Output Delay
25
25
tGLQV
NOTES:
CEX low is defined as the first edge of CE that enables the device. CEX high is defined at the first edge of CE that
disables the device (see Table 1).
1. See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.
2. OE may be delayed up to tELQV - tGLQV after the first edge of CE that enables the device (see Table 1) without
impact on tELQV .
3. See Figures 12-13, Transient Input/Output Reference Waveform forVCCQ = 3.0V - 3.6V andTransient Equivalent
Testing Load Circuit for testing characteristics.
4.When reading the MTP array a faster tGLQV (R15) applies. Non-array reads refer to status register reads, query
reads, or device identifier reads.
5. Sampled, not 100% tested.
6.For devices configured to standard word read mode, R14 (tAPA) will equal R1 (tAVQV).
P/N:PM0946
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36
MX26L6419
Figure 13. AC Waveform for Both Page-Mode and Standard Word Read Operations
VIH
VIL
Address
(A21-A2)
tAVAV
VIH
VIL
Address
(A1-A0)
Valid Address
Valid Address Valid Address
Valid Address
tEHEL
Disable
VIH
VIL
CEx[E]
Enable
tEHQZ
tAVQV
VIH
VIL
OE [G]
tGHQZ
tELQV
VIH
VIL
WE [W]
tGLQV
tOH
tAPA
tPHQV
tELQX
VOH
VOL
DATA[D/Q]
Q0- Q15
High Z
High Z
Valid
Valid
Valid
Valid
Output
Output Output Output
tGLQX
VIH
VIL
VCC
VIH
VIL
RESET[P]
NOTE:
1. CEX low is defined as the first edge of CE that enables the device. CEX high is defined at the first edge of CE that
disables the device (see Table 1).
2. For standard word read operations, tAPA will equal tAVQV.
3. When reading the MTP array a faster tGLQV applies. Non-array reads refer to status register reads, query reads,
or device identifier reads.
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MX26L6419
AC Characteristics--Write Operations (1,2)
Versions
Valid for All
Speeds
Unit
Symbol
Parameter
Notes
Min
Max
tPHWL (tPHEL )
tELWL (tWLEL )
tWP
RESET High Recovery to WE(CEX) Going Low
CEX (WE) Low toWE(CEX) Going Low
Write PulseWidth
3
4
4
5
5
210
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
sec
70
50
55
0
tDVWH (tDVEH )
tAVWH (tAVEH )
tWHEH (tEHWH)
tWHDX (tEHDX)
tWHAX (tEHAX)
tWPH
Data Setup to WE(CEX) Going High
Address Setup to WE(CEX) Going High
CEX (WE) Hold fromWE(CEX) High
Data Hold fromWE(CEX) High
Address Hold fromWE(CEX) High
Write PulseWidth High
0
0
6
3
30
0
tVPWH (tVPEH)
tWHGL (tEHGL)
tQVVL
VPEN Setup to WE(CEX) Going High
Write Recovery before Read
7
35
0
VPEN Hold from Valid SRD
3,8
4,8
4
tWHQV5 (tEHQV5) Set Lock-Bit Time
64
0.5
75/85
2
tWHQV6 (tEHQV6) Clear Block Lock-Bits Time
NOTES:
CEX low is defined as the first edge of CE that enables the device. CEX high is defined at the first edge of CE that
disables the device (see Table 1).
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as
during read-only operations. Refer to AC Characteristics-Read-Only Operations.
2. A write operation can be initiated and terminated with either CE X or WE.
3. Sampled, not 100% tested.
4. Write pulse width (tWP) is defined from CEX orWE going low (whichever goes low last) to CEX orWE going high
(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH.
5. Refer to Table 3 for valid A IN and D IN for block erase, program, or lock-bit configuration.
6. Write pulse width high (t WPH) is defined from CEX or WE going high (whichever goes high first) to CEX or WE
going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL .
7. For array access, tAVQV is required in addition to tWHGL for any accesses after a write.
8. VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success
(SR.1/3/4/5=0).
P/N:PM0946
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MX26L6419
Figure 14. AC Waveform for Write Operations
A
B
C
D
E
F
VIH
VIL
Address
(A)
AIN
AIN
tAVWH
(tAVEH)
tWHAX
(tEHAX)
Disable
VIH
VIL
CEx,(WE)[E(W)]
Enable
tWHGL
(tEHGL)
tWHEH
(tEHWH)
tPHWL
(tPHEL)
VIH
VIL
OE
tELWL
(tWLEL)
tWPH
Disable
VIH
VIL
WE,(CEx)[W(E)]
Enable
tWP
tOVWH
(tDVEH)
tWHDX
(tEHDX)
VIH
VIL
Valid
SRD
DATA[D/Q]
RESET [P]
DIN
DIN
DIN
VIH
VIL
tVPWH
(tVPEH)
tQVVL
VPENH
VPENLK
VIL
VPEN[V]
NOTES:
1. CEX low is defined as the first edge of CE that enables the device. CEX high is defined at the first edge of CE that
disables the device (see Table 1).
a.VCC power-up and standby.
b.Write block erase, write buffer, or program setup.
c.Write block erase or write buffer confirm, or valid address and data.
d. Automated erase delay.
e. Read status register or query data.
f. Write Read Array command.
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MX26L6419
Figure 15. AC Waveform for Reset Operation
VIH
RESET (P)
VIL
tPLPH
Reset Specifications (1)
Sym
Parameter
Notes
Min
Max Unit
tPLPH
RESET Pulse Low Time
2
35
us
(If RESET is tied to VCC , this specification is not applicable)
NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. If RESET is asserted while a block erase, program, or lock-bit configuration operation is not executing then the
minimum required RESET Pulse LowTime is 100ns.
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MX26L6419
ERASE AND PROGRAMMING PERFORMANCE(1)
LIMITS
PARAMETER
MIN.
TYP.(2)
2.0
MAX.
15.0
900
UNITS
sec
Block Erase Time
Write Buffer Byte Program Time
(Time to Program 16 words)
218
us
Word Program Time (Using Word Program Command)
Block Program Time (Using Write to Buffer Command)
Block Erase/Program Cycles
210
0.8
900
2.4
us
sec
100
Cycles
Note: 1.Not 100% Tested, Excludes external system level over head.
2.Typical values measured at 25°C,3.3V. Additionally programming typically assume checkerboard pattern.
LATCH-UP CHARACTERISTICS
MIN.
-1.0V
MAX.
12.5V
Input Voltage with respect to GND on OE
Input Voltage with respect to GND on all power pins, Address pins, CE and WE
Input Voltage with respect to GND on all I/O pins
Current
-1.0V
2 VCCmax
VCC + 1.0V
+100mA
-1.0V
-100mA
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
CAPACITANCE TA=0°C to 70°C, VCC=3.0V~3.6V
Parameter Symbol
Parameter Description
Input Capacitance
Test Set
VIN=0
TYP
MAX
7.5
12
UNIT
pF
CIN
6
COUT
CIN2
Output Capacitance
Control Pin Capacitance
VOUT=0
VIN=0
8.5
7.5
pF
9
pF
Notes:
1. Sampled, not 100% tested.
2.Test conditions TA=25°C, f=1.0MHz
DATA RETENTION
Parameter
Test Conditions
Min
10
Unit
Minimum Pattern Data Retention Time
150
125
Years
Years
20
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MX26L6419
ORDERING INFORMATION
PLASTIC PACKAGE
Part NO.
Access Time
(ns)
Packagetype
Cycles
MX26L6419TC-10
100/25
48-TSOP
100
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MX26L6419
PACKAGE INFORMATION
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MX26L6419
REVISION HISTORY
Revision No. Description
Page
Date
0.1
0.2
1. To modify Package Information
1. To remove deep power down mode:
1-1 power down mode:25uA(typ.)
P44
P1,2,5,6,10
P34,6
NOV/20/2002
JUN/03/2003
1-2 tPHWL: 2us --> 210ns(min.)
P39
2. To change VCC range: 2.7V to 3.6V --> 3.0 to 3.6V
P1,13,20,33,
35,36,37,42
P34
3. To remove word mode read current
4. Revise the VPENLK spec from 2.2V(max.) to 0.5 x VCC(max.) P35
5. tWHQV6: 0.7s(max.)-->2s(max.) P39
6. To remove the DC Characteristics note "All currents are in RMS P35
unless otherwise noted"
7. To remove program/erase suspend/resume function
P1,7,8,18,19,20,22
26,28,29,34,35,39,40
- CFI code of Address 36: 0A-->C8
- CFI code of Address 3A: 01-->00
8. Typing error
P15
P15
P1,4,9,12,13,17,21,22
23~25, 37,38
0.3
1. Change write to buffer flowchart to align industry spec
2. Added Figure 5. status register flowchart
3. To relax the maximum program time spec from 654us (write
buffer program) to 900us and from 630us(byte program time) to
900us
P25
P26
P41
OCT/08/2003
4. Latch-up:
P41
a. Input max. voltage with respect to GND on OE from 13.5V to 12.5V
b. Input max. voltage with respect to GND on power, address, CE,
WE from 13.5V to 2xVCC max.
c. test condition from VCC=5.0V to VCC=3V
Capacitance:
a. CIN from 8pF(max.) to 7.5pF(max.)
b. COUT from 8pF(typ) to 8.5pF(typ)
c. Add CIN2
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MX26L6419
MACRONIX INTERNATIONAL CO., LTD.
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