MX26C4000BQI-12_技术文档

ADVANCE INFORMATION

MX26C4000B

4M-BIT[512Kx8]CMOS

MULTIPLE-TIME-PROGRAMMABLE-EPROM

FEATURES

• 512Kx 8 organization

• Chip erase time: 2s (typ.)

• Single +5V power supply

• +12Vprogrammingvoltage

• Fast access time:70/90/100/120/150 ns

• Totally static operation

• Completely TTL compatible

• Operatingcurrent:30mA

• Standby current: 100uA

• Chip program time: 25s (typ.)

• 100 minimum erase/program cycles

• Typical fast programming cycle duration 100us/byte

• Package type:

- 32 pin plastic DIP

- 32 pin PLCC

- 32 pin TSOP

- 32 pin SOP

GENERAL DESCRIPTION

The MX26C4000B is a 5V only, 4M-bit, MTP EPROM^TM

(Multiple Time Programmable Read Only Memory). It is

organized as 512K words by 8 bits per word, operates

fromasingle+5volt supply,hasastaticstandby mode,

and features fast single address location programming.

All programming signals are TTL levels, requiring a

single pulse. It is design to be programmed and erased

by an EPROM programmer or on-board. The

MX26C4000B supports a intelligent fast programming

algorithm which can result in programming time of less

than one minute.

ThisMTPEPROM^TMispackagedinindustrystandard32

pin dual-in-line packages, 32 lead PLCC, 32 lead SOP

and 32 lead TSOP packages.

PIN CONFIGURATIONS

32 PDIP/SOP

32 PLCC

VCC

A18

A17

A14

A13

A8

VPP

A16

A15

A12

A7

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

1

2

4

1

32

30

29

A14

A13

A8

5

3

A7

A6

A5

A4

A3

A2

A1

A0

Q0

4

5

A6

6

A9

A5

7

A11

OE

A10

CE

A4

8

A11

OE

A10

CE

Q7

9

25

MX26C4000B

A3

9

A2

10

11

12

13

14

15

16

A1

Q7

A0

Q6

Q0

13

21

Q5

Q1

14

17

20

Q4

Q2

Q3

GND

32 TSOP

PIN DESCRIPTION

SYMBOL

A0~A18

Q0~Q7

CE

PIN NAME

A11

A9

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

OE

A10

CE

Q7

Q6

Q5

Q4

Q3

GND

Q2

Q1

Q0

A0

2

Address Input

A8

3

A13

A14

A17

A18

VCC

VPP

A16

A15

A12

A7

4

DataInput/Output

Chip Enable Input

Output Enable Input

5

6

7

8

OE

MX26C4000B

9

10

11

12

13

14

15

16

VPP

ProgramSupplyVoltage

NoInternalConnection

Power Supply Pin (+5V)

GroundPin

NC

A6

A1

VCC

A5

A2

A4

A3

GND

P/N: PM0768

REV. 0.6, JAN. 14, 2002

1

MX26C4000B

BLOCK DIAGRAM

WRITE

STATE

CONTROL

INPUT

PROGRAM/ERASE

HIGH VOLTAGE

CE

OE

MACHINE

(WSM)

LOGIC

STATE

MX26C4000B

FLASH

ADDRESS

LATCH

REGISTER

ARRAY

A0-A18

AND

SOURCE

HV

BUFFER

Y-PASS GATE

COMMAND

DATA

DECODER

PGM

SENSE

DATA

HV

AMPLIFIER

COMMAND

DATA LATCH

PROGRAM

DATA LATCH

Q0-Q7

I/O BUFFER

REV. 0.6, JAN. 14, 2002

P/N: PM0768

2

MX26C4000B

to the Read Mode. Robust design features prevent

inadvertentwritecyclesresultingfromV_CCpower-upand

power-downtransitionsorsystemnoise.Toavoidinitiation

ofwritecycleduringV_CCpower-up,awritecycleislocked

outforV_CClessthan4V.Thetwo-commandprogramand

erase write sequence to the command register provide

additional software protection against spurious data

changes.

FUNCTIONAL DESCRIPTION

When the MX26C4000B is delivered, or it is erased, the

chip has all 4M bits in the "ONE", or HIGH state.

"ZEROs" are loaded into the MX26C4000B through the

procedure of programming.

ERASE ALGORITHM

PROGRAM VERIFY MODE

The MX26C4000B do not required preprogramming

beforeaneraseoperation.Theerasealgorithmisaclose

loop flow to simultaneously erase all bits in the entire

array. Erase operation starts with the initial erase

operation. Erase verification begins at address 0000H

by reading data FFH from each byte. If any byte fails

to erase. the entire chip is reerased. to a maximum for

10 pulse counts of 500ms duration for each pulse. The

maximum cumulative erase time is 3s. However. the

deviceisusuallyerasedinnomorethan3pulses. Erase

verification time can be reduced by storing the address

of the last byte that failed. Following the next erase

operation verification may start at the stored address

location. JEDEC standard erase algorithm can also be

used. But erase time will increase by performing the

unnecessarypreprogramming.

Verificationshouldbeperformedontheprogrammedbits

to determine that they were correctly programmed.

Verification should be performed with OE and CE, at

VIL, and VPP at its programming voltage.

ERASE VERIFY MODE

Verification should be performed on the erased chip to

determine that the whole chip(all bits) was correctly

erased. Verification should be performed with OE and

CE at VIL, and VCC = 5V, VPP = 12.5V

AUTO IDENTIFY MODE

Theautoidentifymodeallowsthereadingoutofabinary

code from MTP EPROM that will identify its

manufacturer and device type. This mode is intended

for use by programming equipment for the purpose of

automatically matching the device to be programmed

with its corresponding programming algorithm. This

modeisfunctionalinthe25°C±5°Cambienttemperature

range that is required when programming the

MX26C4000B.

PROGRAM ALGORITHM

The device is programmed byte by byte. A maximum

of 25 pulses. each of 100us duration is allowed for each

byte being programmed. The byte may be programmed

sequentially or by random. After each program pulse,

a program verify is done to determine if the byte has

been successfully programmed.

Programming then proceeds to the next desired byte

location. JEDEC standard program algorithms can be

used.

Toactivatethismode,theprogrammingequipmentmust

force 12.0 ±0.5 V on address line A9 of the device.

Two identifier bytes may then be sequenced from the

device outputs by toggling address line A0 from VIL

to VIH. All other address lines must be held at VIL

during auto identify mode.

DATA WRITE PROTECTION

The design of the device protects against accidental

erasure or programming. The internal state machine is

automaticallyresettothereadmodeonpower-up.Using

control register architecture, alteration of memory can

only occur after completion of proper command

sequences.ThecommandregisterisonlyactivewhenV

_PPisathighvoltage.whenV_PP=V_PPL,thedevicedefaults

Byte 0 ( A0 = VIL) represents the manufacturer code,

and byte 1 (A0 = VIH), the device identifier code. For

the MX26C4000B, these two identifier bytes are given

intheModeSelectTable. Allidentifiersformanufacturer

and device codes will possess odd parity, with the MSB

(DQ7) defined as the parity bit.

REV. 0.6, JAN. 14, 2002

P/N: PM0768

3

MX26C4000B

READ MODE

The MX26C4000B has two control functions, both of

which must be logically satisfied in order to obtain data

at the outputs. Chip Enable (CE) is the power control

and should be used for device selection. Output Enable

(OE) is the output control and should be used to gate

datatotheoutputpins, independentofdeviceselection.

Assuming that addresses are stable, address access

time(tACC)isequaltothedelayfromCEtooutput(tCE).

DataisavailableattheoutputstOEafterthefallingedge

of OE, assuming that CE has been LOW and addresses

have been stable for at least tACC - tOE.

STANDBY MODE

The MX26C4000B has a CMOS standby mode which

reduces the maximum VCC current to 100 uA. It is

placed in CMOS standby when CE is at VCC ±0.3 V.

The MX26C4000B also has a TTL-standby mode which

reduces the maximum VCC current to 1.5 mA. It is

placed in TTL-standby when CE is at VIH. When in

standby mode, the outputs are in a high-impedance

state, independent of the OE input.

SYSTEM CONSIDERATIONS

During the switch between active and standby

conditions, transient current peaks are produced on the

rising and falling edges of Chip Enable. The magnitude

of these transient current peaks is dependent on the

outputcapacitanceloadingofthedevice. Ataminimum,

a0.1uFceramiccapacitor(highfrequency,lowinherent

inductance) should be used on each device between

VCCandGNDtominimizetransienteffects. Inaddition,

to overcome the voltage drop caused by the inductive

effects of the printed circuit board traces on EPROM

arrays, a 4.7 uF bulk electrolytic capacitor should be

used between VCC and GND for each of the eight

devices. The location of the capacitor should be close

to where the power supply is connected to the array.

OUTPUT DISABLE

Output is disabled when OE is at logre high. When in

outputdisabledallcircuitryisenabled.Excepttheoutput

pins are in a high impedance state(Hi-Z).

REV. 0.6, JAN. 14, 2002

P/N: PM0768

4

MX26C4000B

Table 1: BUS OPERATIONS

Mode

VPP(1)

VPPL

VPPH

A0

X

A9

CE

OE

VIL

VIH

X

Q0~Q7

Data Out

Hi-Z

Read

A9

VIL

VIH

VIL

VIH

OutputDisable

Standby

X

Hi-Z

ManufacturerIdentification

Device Identification

Program

VIL

VIH

A0

X

VID(2)

VIL

VIH

VIL

VIH

Data=C2H

Data=C0H

Data In

Data Out

Hi-Z

VID(2)

X

Verify

ProgramInhibit

Note:

1. Refer to DC Characteristics. When VPP=VPPL memory contents can be read but not written or erased.

2. VID is the intelligent identifier high voltage. Refer to DC Characteristics.

3. Read operations with VPP=VPPH may access array data or the intelligent identifier codes.

4. With VPP at high voltage the standby current equals ICC+IPP(standby).

5. Refer to Table 2 for vaild data-in during a write operation.

6. X can be VIL or VIH.

REV. 0.6, JAN. 14, 2002

P/N: PM0768

5

MX26C4000B

PROGRAMMING ALGORITHM FLOW CHART

VCC=6.25V

VPP=12.75V

n=0

CE=100us Pulse

Verify

NO

N=N+1

YES

NO

n=25

Last

NO

Address

YES

Check All Bytes

1st:VCC=6V

Failed

2nd:VCC=4.2V

REV. 0.6, JAN. 14, 2002

P/N: PM0768

6

MX26C4000B

ERASE ALGORITHM FLOW CHART

START

n=0

Erase:

A9=12.5V

VCC=5V

VPP=12.5V

Chip Erase pulse

Verify:

A9=VIL or VIH

VCC=5V

VPP=12.5V

Yes

Erase Verify

No

N=N+1

No

n=10

Yes

Faild

Passed

REV. 0.6, JAN. 14, 2002

P/N: PM0768

7

MX26C4000B

SWITCHING TEST CIRCUITS

DEVICE

UNDER

TEST

1.8K ohm

+5V

DIODES = IN3064

OR EQUIVALENT

CL

6.2K ohm

CL = 100 pF including jig capacitance

SWITCHING TEST WAVEFORMS

2.0V

0.8V

2.0V

TEST POINTS

AC driving levels

0.8V

OUTPUT

INPUT

AC TESTING: AC driving levels are 2.4V/0.4V for commercial grade.

Input pulse rise and fall times are equal to or less than 10ns.

REV. 0.6, JAN. 14, 2002

P/N: PM0768

8

MX26C4000B

NOTICE:

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed under ABSOLUTE

MAXIMUM RATINGS may cause permanent damage to

the device. This is a stress rating only and functional

operation of the device at these or any other conditions

above those indicated in the operational sections of this

specification is not implied. Exposure to absolute

maximum rating conditions for extended period may

affect reliability.

RATING

VALUE

AmbientOperatingTemperature -40^oCto85^oC

StorageTemperature

Applied Input Voltage

AppliedOutputVoltage

VCC to Ground Potential

A9 & VPP

-65^oCto125^oC

-0.5V to 7.0V

-0.5V to VCC + 0.5V

-0.5V to 7.0V

NOTICE:

-0.5V to 13.5V

Specifications contained within the following tables are

subject to change.

DC/AC OPERATING CONDITION FOR READ OPERATION

MX26C4000B

-90

-100

-120

-150

OperatingTemperature Industrial

Vcc Power Supply

-40°C to 85°C

5V ±10%

-40°Cto85°C

5V ±10%

-40°Cto85°C

5V ±10%

-40°Cto85°C

5V ±10%

CAPACITANCE TA = 25^oC, f = 1.0 MHz (Sampled only)

SYMBOL

CIN

PARAMETER

TYP.

MAX.

6

UNIT

pF

CONDITIONS

InputCapacitance

OutputCapacitance

VPP Capacitance

VIN = 0V

COUT

CVPP

12

pF

VOUT = 0V

VPP = 0V

18

25

pF

DC CHARACTERISTICS TA = -45°C ~ 85°C, VCC=5V±10%

SYMBOL PARAMETER

MIN.

-0.3

2.0

MAX.

UNIT CONDITIONS

VIL

Input Low Voltage

0.8

VCC + 1

0.4

V

VIH

Input High Voltage

VOL

VOH

ICC1

ISB

OutputLowVoltage

V

IOL = 2.1mA, VCC=VCC MIN

Output High Voltage (TTL)

OutputHighVoltage(CMOS)

VCC Active Current

2.4

V

IOH = -0.4mA

VCC-0.7V

V

IOH = -0.1mA

30

100

1

mA

uA

mA

uA

V

CE = VIL, OE=VIH, f=5MHz

CE=VCC+0.2V, VCC=VCC MAX

CE=VIH, VCC=VCC MAX

CE=WE=VIL, OE=VIH

VIN = 0 to 5.5V

VCCStandbyCurrent(CMOS)

VCCStandbyCurrent(TTL)

VPPSupplyCurrent(Program)

InputLeakageCurrent

ISB

IPP

10

ILI

-10

10

ILO

OutputLeakageCurrent

Fast Programming Supply Voltage

FastProgrammingVoltage

10

VOUT = 0 to 5.5V

VCC1

VPP1

6.0

6.5

13.0

12.5

V

REV. 0.6, JAN. 14, 2002

P/N: PM0768

9

MX26C4000B

AC RAED CHARACTERISTICS OVER OPERATING RANGE WITH VPP=VCC

Symbol Parameter

Jeded STD

70

90

100

120

150

Unit

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX

tAVAV TRC Read Cycle Time

tELQV TCE CE Access Time

tAVQV TACC Address Access Time

tGLQV TOE OE Access Time

tELQX TLZ CE to Output in Low Z(Note 1)

tEHQZ TDF Chip Disable to Output in

High Z (Note 2)

70

0

90

0

100

0

120

0

150

0

ns

70

35

90

40

100

45

120

50

150

65

0

30

0

30

0

35

0

35

0

50

tGLQX TOLZ OE to Output in Low Z (Note 1)

tGHQZ TDF Output Disable to Output in

High Z (Note 1)

0

ns

30

0

30

0

35

0

35

0

50

0

tAXQX TOH Output Hold from Address,

CE or OE, change

ns

us

tVCS TVCS VCC Setup Time to Valid Read

(Note2)

50

Note:

1. Sampled: not 100% tested.

2. Guaranteed by design. not tested.

REV. 0.6, JAN. 14, 2002

P/N: PM0768

10

MX26C4000B

AC WAVEFORMS FOR READ OPERATIONS

Outputs

enabled

Device and

Address Selection

Data Valid

Power-Up Standby

Standby Power-Up

Address

CE

Addresses Stable

tAVAV(tRC)

tEHQZ(tDF)

tGHQZ(tDF)

OE

tGLQV(tOE)

tELQV(tCE)

tAXQX(tOH)

tGLQX(tOLZ)

tELQX(tLZ)

High Z

tVCS

Data

VCC

Output Valid

tAVQV(tACC)

5.0V

0V

REV. 0.6, JAN. 14, 2002

P/N: PM0768

11

MX26C4000B

AC WAVEFORMS FOR ERASE OPERATIONS

Valid

A9

tAVQ

Q0~Q7

5V

VCC

12V

VPP

tGLQ

tHE

tE

tEH

CE

OE

tAVG

All Matrix Verif

Chip Erase

(1)

Table 2. Erasing Mode AC Characteristics (TA=25°C; VCC=5V±0.25V; VPP=12.5V±0.25V)

Symbol

tA9HEL

tAVGL

tAVQV

tEHA9L

tER

Parameter

Min

2

Max

100

30

Unit

us

A9 High to Chip Enable Low

Address Valid to Output Enable Low

Address Valid to Data Valid

Chip Enable High to A9 Low

First Erase Time

2

us

ns

2

us

500

ms

ns

tGLQV

Output Enable Low to Data Valid

⁽¹⁾VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.

REV. 0.6, JAN. 14, 2002

P/N: PM0768

12

MX26C4000B

AC WAVEFORMS FOR PROGRAMMING OPERATIONS

VALID

A0-A18

Q0~Q7

tAVPL

tQVEL

DATA IN

DATA OUT

tEHQX

VCC

VPP

tGLQV

tGHQZ

tVPHEL

tVCHEL

tGHAX

CE

OE

tELEH

tQXGL

PROGRAM

VERIFY

Table 3. Programming Mode AC Characteristics ⁽¹⁾

(TA=25°C; VCC=6.25V±0.25V; VPP=12.5V±0.25V)

Symbol

tAVPL

Alt

Parameter

Min

2

Max

Unit

us

ns

tAS

Address Valid to Chip Enable Low

Input Valid to Chip Enable Low

VPP High to Chip Enable Low

VCC High to Chip Enable Low

Chip Enable Program Pulse Wodth

Chip Enable High to Input Transition

Input Transition to Output Enable Low

Output Enable Low to Output Valid

Output Enable High to Output Hi-Z

TQVEL

TVPHEL

TVCHEL

TELEH

TEHQX

TQXGL

TGLQV

TGHQZ

TGHAX

tDS

2

tVPS

tVCS

tPW

tDH

2

95

2

105

tOES

tOE

tDFP

tAH

2

100

130

0

Output Enable High to Address Transition

⁽¹⁾VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.

⁽²⁾Sampled only, not 100% tested.

REV. 0.6, JAN. 14, 2002

P/N: PM0768

13

MX26C4000B

ORDERING INFORMATION

PLASTICPACKAGE

PART NO.

ACCESS TIME(ns)

OPERATING

STANDBY

OPERATING

TEMPERATURE

0°C to 70°C

-40°C to 85°C

PACKAGE

Current MAX.(mA)

Current MAX.(uA)

100

MX26C4000BPC-90

MX26C4000BQC-90

MX26C4000BMC-90

MX26C4000BTC-90

MX26C4000BPC-10

MX26C4000BQC-10

MX26C4000BMC-10

MX26C4000BTC-10

MX26C4000BPC-12

MX26C4000BQC-12

MX26C4000BMC-12

MX26C4000BTC-12

MX26C4000BPC-15

MX26C4000BQC-15

MX26C4000BMC-15

MX26C4000BTC-15

MX26C4000BPI-90

MX26C4000BQI-90

MX26C4000BMI-90

MX26C4000BTI-90

MX26C4000BPI-10

MX26C4000BQI-10

MX26C4000BMI-10

MX26C4000BTI-10

MX26C4000BPI-12

MX26C4000BQI-12

MX26C4000BMI-12

MX26C4000BTI-12

MX26C4000BPI-15

MX26C4000BQI-15

MX26C4000BMI-15

MX26C4000BTI-15

90

30

32 Pin DIP

100

32 Pin PLCC

32 Pin SOP

32 Pin TSOP

32 Pin DIP

90

100

90

100

120

150

90

100

32 Pin PLCC

32 Pin SOP

32 Pin TSOP

32 Pin DIP

100

32 Pin PLCC

32 Pin SOP

32 Pin TSOP

32 Pin DIP

100

32 Pin PLCC

32 Pin SOP

32 Pin TSOP

32 Pin DIP

100

90

100

32 Pin PLCC

32 Pin SOP

32 Pin TSOP

32 Pin DIP

90

100

90

100

120

150

100

32 Pin PLCC

32 Pin SOP

32 Pin TSOP

32 Pin DIP

100

32 Pin PLCC

32 Pin SOP

32 Pin TSOP

32 Pin DIP

100

32 Pin PLCC

32 Pin SOP

32 Pin TSOP

100

REV. 0.6, JAN. 14, 2002

P/N: PM0768

14

MX26C4000B

PACKAGE INFORMATION

32-PIN PLASTIC DIP(600 mil)

REV. 0.6, JAN. 14, 2002

P/N: PM0768

15

MX26C4000B

32-PINPLASTICLEADEDCHIPCARRIER(PLCC)

REV. 0.6, JAN. 14, 2002

P/N: PM0768

16

MX26C4000B

32-PIN PLASTIC TSOP

REV. 0.6, JAN. 14, 2002

P/N: PM0768

17

MX26C4000B

32-PIN PLASTIC SOP (450 mil)

REV. 0.6, JAN. 14, 2002

P/N: PM0768

18

MX26C4000B

REVISION HISTORY

RevisionNo. Description

Page

P1

Date

DEC/18/2000

0.1

To add erase/program cycle

ChangetitlefromMX26C4000AtoMX26C4000B

To added 32SOP/TSOP types package and access time 150ns

Modify device ID old 32H-->New C0H

Modify read ID method

Modify erase/program cycle from 100 to 50

Modify VCC Standby Current(TTL) from 1mA to 1.5mA

To added VCC1 & VPP1 to DC Characteristics Table

Modify Package Information

To added chip erase time / chip program time

Modify Package Information

Modify the Programming Operations Timing Waveforms

1.Cancel the command mode

All

0.2

P1,10,11,16,18 MAR/27/2001

P5

P4,5,6,12

P1

P10

P17~20

P1

P17~20

P15

P12

0.3

0.4

APR/23/2001

JUL/04/2001

0.5

0.6

OCT/04/2001

JAN/14/2002

2.Modify the cycle time from 50-->100

3.Modifytheerase/programoperationtimingwaveformand

flowchart

P1

P6,7,12,13

REV. 0.6, JAN. 14, 2002

P/N: PM0768

19

MX26C4000B

MACRONIX INTERNATIONAL CO., LTD.

HEADQUARTERS:

TEL:+886-3-578-6688

FAX:+886-3-563-2888

EUROPE OFFICE:

TEL:+32-2-456-8020

FAX:+32-2-456-8021

JAPAN OFFICE:

TEL:+81-44-246-9100

FAX:+81-44-246-9105

SINGAPORE OFFICE:

TEL:+65-348-8385

FAX:+65-348-8096

TAIPEI OFFICE:

TEL:+886-2-2509-3300

FAX:+886-2-2509-2200

MACRONIX AMERICA, INC.

TEL:+1-408-453-8088

FAX:+1-408-453-8488

CHICAGO OFFICE:

TEL:+1-847-963-1900

FAX:+1-847-963-1909

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.


型号：	MX26C4000BQI-12
厂家：	MACRONIX INTERNATIONAL
描述：	4M-BIT [512K x 8] CMOS MULTIPLE-TIME-PROGRAMMABLE-EPROM 4M- BIT [ 512K ×8 ] CMOS多时间可编程EPROM 闪存存储内存集成电路可编程只读存储器电动程控只读存储器
文件：	总20页 (文件大小：959K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MX26C4000BQI-12 [Macronix]

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