MX26C4000CMC-90 [Macronix]
Flash, 512KX8, 90ns, PDSO32;
| 型号： | MX26C4000CMC-90 |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | Flash, 512KX8, 90ns, PDSO32 光电二极管 |
| 文件： | 总19页 (文件大小：636K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE INFORMATION
MX26C4000C
4M-BIT[512Kx8]CMOS
MULTIPLE-TIME-PROGRAMMABLE-EPROM
FEATURES
• 512Kx 8 organization
• Chip erase time: 2s (typ.)
• Chip program time: 25s (typ.)
• 100 minimum erase/program cycles
• Typical fast programming cycle duration 50us/byte
• Package type:
• Single +5V power supply
• +12V programming voltage
• Fast access time:70/90/100/120/150 ns
• Totally static operation
• CompletelyTTL compatible
• Operating current: 30mA
• Standby current: 100uA
- 32 pin plastic DIP
- 32 pin PLCC
- 32 pin TSOP
- 32 pin SOP
GENERAL DESCRIPTION
The MX26C4000C is a 5V only, 4M-bit, MTP EPROMTM
(MultipleTime Programmable Read Only Memory).It is
organized as 512K words by 8 bits per word, operates
from a single + 5 volt supply, has a static standby
mode, and features fast single address location program-
ming. All programming signals areTTL levels, requiring
a single pulse. It is design to be programmed and erased
by an EPROM programmer or on-board. The
MX26C4000C supports a intelligent fast programming
algorithm which can result in programming time of less
than one minute.
This MTP EPROMTM is packaged in industry standard
32 pin dual-in-line packages, 32 lead PLCC, 32 lead SOP
and 32 leadTSOP packages.
PIN CONFIGURATIONS
32 PDIP/SOP
32 PLCC
VCC
A18
A17
A14
A13
A8
VPP
A16
A15
A12
A7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
4
1
32
30
29
A14
A13
A8
5
A7
A6
A5
A4
A3
A2
A1
A0
Q0
3
4
5
A6
6
A9
A9
A5
7
A11
OE
A10
CE
A4
8
A11
OE
A10
CE
Q7
9
25
MX26C4000C
A3
9
A2
10
11
12
13
14
15
16
A1
Q7
A0
Q6
Q0
13
21
Q5
Q1
14
17
20
Q4
Q2
Q3
GND
32 TSOP
PIN DESCRIPTION
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
SYMBOL PIN NAME
2
A0~A18
Q0~Q7
CE
Address Input
A8
3
A13
A14
A17
A18
VCC
VPP
A16
A15
A12
A7
4
Data Input/Output
Chip Enable Input
5
6
7
8
OE
Output Enable Input
MX26C4000C
9
VPP
NC
Program SupplyVoltage
No Internal Connection
Power Supply Pin (+5V)
Ground Pin
10
11
12
13
14
15
16
VCC
GND
A6
A1
A5
A2
A4
A3
P/N: PM0919
REV. 0.0, APR. 24, 2002
1
MX26C4000C
BLOCK DIAGRAM
WRITE
STATE
CONTROL
INPUT
PROGRAM/ERASE
HIGH VOLTAGE
CE
OE
MACHINE
(WSM)
LOGIC
STATE
MX26C4000C
FLASH
ADDRESS
LATCH
REGISTER
ARRAY
ARRAY
A0-A18
AND
SOURCE
HV
BUFFER
Y-PASS GATE
COMMAND
DATA
DECODER
PGM
SENSE
DATA
HV
AMPLIFIER
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q7
I/O BUFFER
REV. 0.0, APR. 24, 2002
P/N: PM0919
2
MX26C4000C
to the Read Mode. Robust design features prevent inad-
vertent write cycles resulting from VCC power-up and
power-down transitions or system noise.To avoid initia-
tion of write cycle during VCC power-up, a write cycle is
locked out forVCC less than 4V.The two- command pro-
gram and erase write sequence to the command regis-
ter provide additional software protection against spuri-
ous data changes.
FUNCTIONAL DESCRIPTION
When the MX26C4000C is delivered, or it is erased, the
chip has all 4M bits in the "ONE", or HIGH state.
"ZEROs" are loaded into the MX26C4000C through the
procedure of programming.
ERASE ALGORITHM
PROGRAM VERIFY MODE
The MX26C4000C do not required preprogramming be-
fore an erase operation.The erase algorithm is a close
loop flow to simultaneously erase all bits in the entire
array.Erase operation starts with the initial erase opera-
tion. Erase verification begins at address 0000H by read-
ing data FFH from each byte. If any byte fails to erase,
the entire chip is re-erased to a maximum for 10 pulse
counts of 500ms duration for each pulse.The maximum
cumulative erase time is 5s.However, the device is usu-
ally erased in no more than 3 pulses. Erase verification
time can be reduced by storing the address of the last
byte that failed. Following the next erase operation veri-
fication may start at the stored address location.JEDEC
standard erase algorithm can also be used. But erase
time will increase by performing the unnecessary pre-
programming.
Verification should be performed on the programmed bits
to determine that they were correctly programmed.
Verification should be performed with OE and CE, at
VIL, and VPP at its programming voltage.
ERASE VERIFY MODE
Verification should be performed on the erased chip to
determine that the whole chip (all bits) was correctly
erased. Verification should be performed with OE and
CE at VIL, and VCC = 5V, VPP = 12.5V
AUTO IDENTIFY MODE
PROGRAM ALGORITHM
The auto identify mode allows the reading out of a bi-
nary code from MTP EPROM that will identify its manu-
facturer and device type. This mode is intended for use
by programming equipment for the purpose of automati-
cally matching the device to be programmed with its
corresponding programming algorithm. This mode is
functional in the 25°C ±5°C ambient temperature range
that is required when programming the MX26C4000C.
The device is programmed byte by byte.The maximum
program puls is 25 pulses, each of 50us duration is al-
lowed for each byte being programmed. The byte may
be programmed sequentially or by random. After each
program pulse, a program verify is done to determine if
the byte has been successfully programmed.
To activate this mode, the programming equipment must
force 12.0 ±0.5 V on address line A9 of the device. Two
identifier bytes may then be sequenced from the device
outputs by toggling address line A0 from VIL to VIH. All
other address lines must be held atVIL during auto iden-
tify mode.
Programming then proceeds to the next desired byte
location. JEDEC standard program algorithms can be
used.
DATA WRITE PROTECTION
Byte 0 ( A0 = VIL) represents the manufacturer code,
and byte 1 (A0 = VIH), the device identifier code. For
the MX26C4000C, these two identifier bytes are given
in the Mode Select Table. All identifiers for manufac-
turer and device codes will possess odd parity, with the
MSB (DQ7) defined as the parity bit.
The design of the device protects against accidental era-
sure or programming.The internal state machine is auto-
matically reset to the read mode on power-up. Using
control register architecture, alteration of memory can
only occur after completion of proper command se-
quences.The command register is only active whenV PP
is at high voltage. whenV PP = V PPL , the device defaults
REV. 0.0, APR. 24, 2002
P/N: PM0919
3
MX26C4000C
READ MODE
The MX26C4000C has two control functions, both of
which must be logically satisfied in order to obtain data
at the outputs. Chip Enable (CE) is the power control
and should be used for device selection. Output Enable
(OE) is the output control and should be used to gate
data to the output pins, independent of device selection.
Assuming that addresses are stable, address access
time (tACC) is equal to the delay from CE to output (tCE).
Data is available at the outputs tOE after the falling edge
of OE, assuming that CE has been LOW and addresses
have been stable for at least tACC - tOE.
STANDBY MODE
The MX26C4000C has a CMOS standby mode which
reduces the maximum VCC current to 100 uA. It is
placed in CMOS standby when CE is at VCC ± 0.3 V.
The MX26C4000C also has aTTL-standby mode which
reduces the maximumVCC current to 1.5 mA. It is placed
in TTL-standby when CE is at VIH. When in standby
mode, the outputs are in a high-impedance state, inde-
pendent of the OE input.
SYSTEM CONSIDERATIONS
During the switch between active and standby condi-
tions, transient current peaks are produced on the rising
and falling edges of Chip Enable. The magnitude of these
transient current peaks is dependent on the output ca-
pacitance loading of the device. At a minimum, a 0.1 uF
ceramic capacitor (high frequency, low inherent induc-
tance) should be used on each device between VCC
and GND to minimize transient effects. In addition, to
overcome the voltage drop caused by the inductive ef-
fects of the printed circuit board traces on EPROM ar-
rays, a 4.7 uF bulk electrolytic capacitor should be used
between VCC and GND for each of the eight devices.
The location of the capacitor should be close to where
the power supply is connected to the array.
OUTPUT DISABLE
Output is disabled when OE is high.When in output dis-
abled all circuitry is enabled. Except the output pins are
in a high impedance state (Hi-Z).
REV. 0.0, APR. 24, 2002
P/N: PM0919
4
MX26C4000C
Table 1: BUS OPERATIONS
Mode
VPP(1)
VPPL
VPPL
VPPL
VPPL
VPPL
VPPH
VPPH
VPPH
A0
A0
X
A9
CE
OE
VIL
VIH
X
Q0~Q7
Data Out
Hi-Z
Read
A9
VIL
VIL
VIH
VIL
VIL
VIL
VIL
VIH
Output Disable
Standby
X
X
X
Hi-Z
Manufacturer Identification
Device Identification
Program
VIL
VIH
A0
A0
X
VID(2)
VIL
VIL
VIH
VIL
VIH
Data=C2H
Data=14H
Data In
Data Out
Hi-Z
VID(2)
X
X
X
Verify
Program Inhibit
Note:
1. Refer to DC Characteristics.When VPP=VPPL memory contents can be read but not written or erased.
2. VID is the intelligent identifier high voltage. Refer to DC Characteristics.
3. Read operations with VPP=VPPH may access array data or the intelligent identifier codes.
4. With VPP at high voltage the standby current equals ICC+IPP(standby).
5. Refer toTable 2 for valid data-in during a write operation.
6. X can be VIL or VIH.
REV. 0.0, APR. 24, 2002
P/N: PM0919
5
MX26C4000C
PROGRAMMING ALGORITHM FLOW CHART
VCC=6.25V
VPP=12.75V
n=0
CE=50us Pulse
Verify
NO
next
Address
N=N+1
NO
YES
n=25
Last
NO
Address
YES
YES
Check All Bytes
1st:VCC=6V
Failed
2nd:VCC=4.2V
REV. 0.0, APR. 24, 2002
P/N: PM0919
6
MX26C4000C
ERASE ALGORITHM FLOW CHART
START
n=0
Erase:
A9=12.5V
VCC=5V
VPP=12.5V
Chip Erase pulse
Verify:
A9=VIL or VIH
VCC=5V
VPP=12.5V
Yes
Erase Verify
No
N=N+1
No
n=10
Yes
Faild
Passed
REV. 0.0, APR. 24, 2002
P/N: PM0919
7
MX26C4000C
SWITCHING TEST CIRCUITS
DEVICE
UNDER
TEST
1.8K ohm
+5V
DIODES = IN3064
OR EQUIVALENT
CL
6.2K ohm
CL = 100 pF including jig capacitance (CL=30pF for 70ns speed grade)
SWITCHING TEST WAVEFORMS
For normal speed grade (90ns, 100ns, 120ns, 150ns)
2.0V
0.8V
2.0V
0.8V
TEST POINTS
AC driving levels
OUTPUT
INPUT
AC TESTING: AC driving levels are 2.4V/0.4V for standard grade.
Input pulse rise and fall times are equal to or less than 10ns.
For high speed grade (70ns)
3.0V
0V
1.5V
1.5V
TEST POINTS
OUTPUT
INPUT
AC TESTING: AC driving levels are 3.0V/0V for high speed grade.
Input pulse rise and fall times are equal to or less than 10ns.
REV. 0.0, APR. 24, 2002
P/N: PM0919
8
MX26C4000C
NOTICE:
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended period may
affect reliability.
RATING
VALUE
Ambient Operating Temperature -40oC to 85oC
Storage Temperature
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
A9 & VPP
-65oC to 125oC
-0.5V to 7.0V
-0.5V to VCC + 0.5V
-0.5V to 7.0V
NOTICE:
-0.5V to 13.5V
Specifications contained within the following tables are
subject to change.
DC/AC OPERATING CONDITION FOR READ OPERATION
MX26C4000C
-100
Operating Temperature Industrial 0°C to 70°C -40°C to 85°C -40°C to 85°C -40°C to 85°C -40°C to 85°C
Vcc Power Supply 5V ± 5% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%
-70
-90
-120
-150
CAPACITANCE TA = 25oC, f = 1.0 MHz (Sampled only)
SYMBOL
CIN
PARAMETER
TYP.
MAX.
UNIT
pF
CONDITIONS
Input Capacitance
Output Capacitance
VPP Capacitance
6
VIN = 0V
COUT
CVPP
12
25
pF
VOUT = 0V
VPP = 0V
18
pF
DC CHARACTERISTICS TA = -45°C ~ 85°C, VCC=5V±10%
SYMBOL PARAMETER
MIN.
-0.3
2.0
MAX.
0.8
UNIT CONDITIONS
VIL
Input Low Voltage
V
V
VIH
Input High Voltage
VCC + 1
0.4
VOL
VOH
VOH
ICC1
ISB
Output Low Voltage
V
IOL = 2.1mA, VCC=VCC MIN
Output High Voltage (TTL)
Output High Voltage (CMOS)
VCC Active Current
2.4
V
IOH = -0.4mA
VCC-0.7V
V
IOH = -0.1mA
30
100
1
mA
uA
mA
uA
uA
uA
V
CE = VIL, OE=VIH, f=5MHz
CE=VCC+0.2V, VCC=VCC MAX
CE=VIH, VCC=VCC MAX
CE=WE=VIL, OE=VIH
VIN = 0 to 5.5V
VCC Standby Current (CMOS)
VCC Standby Current (TTL)
VPP Supply Current (Program)
Input Leakage Current
ISB
IPP
10
ILI
-10
-10
6.0
12.5
10
ILO
Output Leakage Current
Fast Programming Supply Voltage
Fast Programming Voltage
10
VOUT = 0 to 5.5V
VCC1
VPP1
6.5
13.0
V
REV. 0.0, APR. 24, 2002
P/N: PM0919
9
MX26C4000C
AC RAED CHARACTERISTICS OVER OPERATING RANGE WITH VPP=VCC
Symbol Parameter
Jeded STD
70
90
100
120
150
Unit
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
tAVAV TRC Read Cycle Time
tELQV TCE CE Access Time
tAVQV TACC Address Access Time
tGLQV TOE OE Access Time
tELQX TLZ CE to Output in Low Z(Note 1)
tEHQZ TDF Chip Disable to Output in
High Z (Note 2)
70
0
90
0
100
0
120
0
150
0
ns
ns
ns
ns
ns
ns
70
70
35
90
90
40
100
100
45
120
120
50
150
150
65
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
30
0
30
0
35
0
35
0
50
tGLQX TOLZ OE to Output in Low Z (Note 1)
tGHQZ TDF Output Disable to Output in
High Z (Note 1)
0
0
0
0
0
0
0
0
0
0
ns
ns
30
0
30
0
35
0
35
0
50
0
tAXQX TOH Output Hold from Address,
CE or OE, change
ns
us
tVCS TVCS VCC Setup Time to Valid Read
(Note 2)
50
50
50
50
50
Note:
1. Sampled: not 100% tested.
2. Guaranteed by design, not tested.
REV. 0.0, APR. 24, 2002
P/N: PM0919
10
MX26C4000C
AC WAVEFORMS FOR READ OPERATIONS
Outputs
enabled
Device and
Address Selection
Data Valid
Power-Up Standby
Standby Power-Up
Address
CE
Addresses Stable
tAVAV(tRC)
tEHQZ(tDF)
tGHQZ(tDF)
OE
tGLQV(tOE)
tELQV(tCE)
tAXQX(tOH)
tGLQX(tOLZ)
tELQX(tLZ)
High Z
High Z
tVCS
Data
VCC
Output Valid
tAVQV(tACC)
5.0V
0V
REV. 0.0, APR. 24, 2002
P/N: PM0919
11
MX26C4000C
AC WAVEFORMS FOR ERASE OPERATIONS
Valid
A9
tAVQ
Q0~Q7
5V
VCC
12V
VPP
tGLQ
tHE
tE
tEH
CE
OE
tAVG
All Matrix Verif
Chip Erase
(1)
Table 2. Erasing Mode AC Characteristics (TA=25°C; VCC=5V±0.25V; VPP=12.5V±0.25V)
Symbol
tA9HEL
tAVGL
tAVQV
tEHA9L
tER
Parameter
Min
2
Max
100
30
Unit
us
A9 High to Chip Enable Low
Address Valid to Output Enable Low
Address Valid to DataValid
Chip Enable High to A9 Low
First Erase Time
2
us
ns
2
us
500
ms
ns
tGLQV
Output Enable Low to DataValid
(1) VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
REV. 0.0, APR. 24, 2002
P/N: PM0919
12
MX26C4000C
AC WAVEFORMS FOR PROGRAMMING OPERATIONS
VALID
A0-A18
Q0~Q7
tAVPL
tQVEL
DATA IN
DATA OUT
tEHQX
VCC
VPP
tGLQV
tGHQZ
tVPHEL
tVCHEL
tGHAX
CE
OE
tELEH
tQXGL
PROGRAM
VERIFY
Table 3. Programming Mode AC Characteristics (1)
(TA=25°C; VCC=6.25V±0.25V; VPP=12.5V±0.25V)
Symbol
tAVPL
Alt
Parameter
Min
2
Max
Unit
us
us
us
us
us
us
us
ns
ns
ns
tAS
AddressValid to Chip Enable Low
Input Valid to Chip Enable Low
VPP High to Chip Enable Low
VCC High to Chip Enable Low
Chip Enable Program PulseWodth
Chip Enable High to InputTransition
InputTransition to Output Enable Low
Output Enable Low to Output Valid
Output Enable High to Output Hi-Z
TQVEL
TVPHEL
TVCHEL
TELEH
TEHQX
TQXGL
TGLQV
TGHQZ
TGHAX
tDS
2
tVPS
tVCS
tPW
tDH
2
2
95
2
105
tOES
tOE
tDFP
tAH
2
100
130
0
0
Output Enable High to AddressTransition
(1) VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.
(2) Sampled only, not 100% tested.
REV. 0.0, APR. 24, 2002
P/N: PM0919
13
MX26C4000C
ORDERING INFORMATION
PLASTIC PACKAGE
PART NO.
ACCESS TIME
OPERATING
STANDBY
OPERATING
PACKAGE
(ns)
70
Current MAX.(mA) Current MAX.(uA) TEMPERATURE
MX26C4000CPC-70
MX26C4000CQC-70
MX26C4000CMC-70
MX26C4000CTC-70
MX26C4000CPC-90
MX26C4000CQC-90
MX26C4000CMC-90
MX26C4000CTC-90
MX26C4000CPC-10
MX26C4000CQC-10
MX26C4000CMC-10
MX26C4000CTC-10
MX26C4000CPC-12
MX26C4000CQC-12
MX26C4000CMC-12
MX26C4000CTC-12
MX26C4000CPC-15
MX26C4000CQC-15
MX26C4000CMC-15
MX26C4000CTC-15
MX26C4000CPI-90
MX26C4000CQI-90
MX26C4000CMI-90
MX26C4000CTI-90
MX26C4000CPI-10
MX26C4000CQI-10
MX26C4000CMI-10
MX26C4000CTI-10
MX26C4000CPI-12
MX26C4000CQI-12
MX26C4000CMI-12
MX26C4000CTI-12
MX26C4000CPI-15
MX26C4000CQI-15
MX26C4000CMI-15
MX26C4000CTI-15
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
32 Pin DIP
70
32 Pin PLCC
32 Pin SOP
32 Pin TSOP
32 Pin DIP
70
70
90
90
32 Pin PLCC
32 Pin SOP
32 Pin TSOP
32 Pin DIP
90
90
100
100
100
100
120
120
120
120
150
150
150
150
90
32 Pin PLCC
32 Pin SOP
32 Pin TSOP
32 Pin DIP
32 Pin PLCC
32 Pin SOP
32 Pin TSOP
32 Pin DIP
32 Pin PLCC
32 Pin SOP
32 Pin TSOP
32 Pin DIP
90
32 Pin PLCC
32 Pin SOP
32 Pin TSOP
32 Pin DIP
90
90
100
100
100
100
120
120
120
120
150
150
150
150
32 Pin PLCC
32 Pin SOP
32 Pin TSOP
32 Pin DIP
32 Pin PLCC
32 Pin SOP
32 Pin TSOP
32 Pin DIP
32 Pin PLCC
32 Pin SOP
32 Pin TSOP
REV. 0.0, APR. 24, 2002
P/N: PM0919
14
MX26C4000C
PACKAGE INFORMATION
32-PIN PLASTIC DIP(600 mil)
REV. 0.0, APR. 24, 2002
P/N: PM0919
15
MX26C4000C
32-PIN PLASTIC LEADED CHIP CARRIER (PLCC)
REV. 0.0, APR. 24, 2002
P/N: PM0919
16
MX26C4000C
32-PIN PLASTIC TSOP
REV. 0.0, APR. 24, 2002
P/N: PM0919
17
MX26C4000C
32-PIN PLASTIC SOP (450 mil)
REV. 0.0, APR. 24, 2002
P/N: PM0919
18
MX26C4000C
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
EUROPE OFFICE:
TEL:+32-2-456-8020
FAX:+32-2-456-8021
JAPAN OFFICE:
TEL:+81-44-246-9100
FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-348-8385
FAX:+65-348-8096
TAIPEI OFFICE:
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088
FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
相关型号：
©2020 ICPDF网 联系我们和版权申明