MX25L1021EMC20G [Macronix]
MX25L5121E;
| 型号： | MX25L1021EMC20G |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | MX25L5121E |
| 文件： | 总42页 (文件大小：877K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX25L5121E
MX25L1021E
MX25L5121E, MX25L1021E
DATASHEET
P/N: PM1573
REV. 1.3, NOV. 11, 2013
1
MX25L5121E
MX25L1021E
Contents
FEATURES ..................................................................................................................................................................4
GENERAL ............................................................................................................................................................4
PERFORMANCE .................................................................................................................................................4
SOFTWARE FEATURES .....................................................................................................................................4
HARDWARE FEATURES.....................................................................................................................................4
GENERAL DESCRIPTION .........................................................................................................................................5
PIN CONFIGURATIONS .............................................................................................................................................6
PIN DESCRIPTION......................................................................................................................................................6
BLOCK DIAGRAM.......................................................................................................................................................7
MEMORY ORGANIZATION.........................................................................................................................................8
Table 1-1. Memory Organization (512Kb) ........................................................................................................... 8
Table 1-2. Memory Organization (1Mb)............................................................................................................... 8
DEVICE OPERATION..................................................................................................................................................9
Figure 1. Serial Modes Supported........................................................................................................................ 9
DATA PROTECTION..................................................................................................................................................10
Table 2. Protected Area Sizes ............................................................................................................................ 10
COMMAND DESCRIPTION....................................................................................................................................... 11
Table 3. Command Set....................................................................................................................................... 11
(1) Write Enable (WREN)...................................................................................................................................12
(2) Write Disable (WRDI)....................................................................................................................................12
(3) Read Identification (RDID)............................................................................................................................ 12
Table 4. ID Definitions .......................................................................................................................................12
(4) Read Status Register (RDSR) ...................................................................................................................... 13
Table 5. Status Register .....................................................................................................................................13
(5) Write Status Register (WRSR)...................................................................................................................... 14
Table 6. Protection Modes..................................................................................................................................14
(6) Read Data Bytes (READ) ............................................................................................................................. 15
(7) Read Data Bytes at Higher Speed (FAST_READ) .......................................................................................15
(8) Sector Erase (SE).........................................................................................................................................15
(9) Block Erase (BE)...........................................................................................................................................15
(10) Chip Erase (CE)..........................................................................................................................................16
(11) Page Program (PP).....................................................................................................................................16
(12) Deep Power-Down (DP) ............................................................................................................................. 16
(13) Release from Deep Power-Down (RDP) .................................................................................................... 17
POWER-ON STATE...................................................................................................................................................18
Program/ Erase flow with read array data.......................................................................................................... 19
ELECTRICAL SPECIFICATIONS..............................................................................................................................20
P/N: PM1573
REV. 1.3, NOV. 11, 2013
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MX25L5121E
MX25L1021E
ABSOLUTE MAXIMUM RATINGS..................................................................................................................... 20
Figure 2. Maximum Negative Overshoot Waveform ..........................................................................................20
CAPACITANCE TA = 25°C, f = 1.0 MHz............................................................................................................. 20
Figure 3. Maximum Positive Overshoot Waveform............................................................................................20
Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL..............................................................21
Figure 5. OUTPUT LOADING ........................................................................................................................... 21
Table 7. DC CHARACTERISTICS (Temperature = 0 C to 70 C for Commercial grade, VCC = 2.7V ~ 3.6V) .. 22
°
°
Table 8. AC CHARACTERISTICS (Temperature = 0°C to 70°C for Commercial grade, VCC = 2.7V ~ 3.6V) . 23
Timing Analysis........................................................................................................................................................24
Figure 6. Serial Input Timing .............................................................................................................................. 24
Figure 7. Output Timing......................................................................................................................................24
Figure 8. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 ................................................. 25
Figure 9. Write Enable (WREN) Sequence (Command 06)...............................................................................25
Figure 10. Write Disable (WRDI) Sequence (Command 04)..............................................................................25
Figure 11. Read Identification (RDID) Sequence (Command 9F)......................................................................26
Figure 12-1. Read Status Register (RDSR) Sequence (Command 05).............................................................27
Figure 12-2. Read Status Register (RDSR) Sequence (Command 05).............................................................27
Figure 13. Write Status Register (WRSR) Sequence (Command 01)...............................................................28
Figure 14. Read Data Bytes (READ) Sequence (Command 03) ......................................................................28
Figure 15. Read at Higher Speed (FAST_READ) Sequence (Command 0B)................................................... 29
Figure 16. Sector Erase (SE) Sequence (Command 20)..................................................................................29
Figure 17. Block Erase (BE) Sequence (Command D8 or 52)..........................................................................30
Figure 18. Chip Erase (CE) Sequence (Command 60 or C7)...........................................................................30
Figure 19. Page Program (PP) Sequence (Command 02)................................................................................30
Figure 20. Deep Power Down (DP) Sequence (Command B9) ........................................................................31
Figure 21. Release from Deep Power Down (RDP) Sequence (Command AB)............................................... 31
Figure 23. Power-Up Timing............................................................................................................................... 32
Table 9. Power-Up Timing ..................................................................................................................................32
INITIAL DELIVERY STATE.................................................................................................................................32
OPERATING CONDITIONS.......................................................................................................................................33
Figure 24. AC Timing at Device Power-Up......................................................................................................... 33
Figure 25. Power-Down Sequence .................................................................................................................... 34
ERASE AND PROGRAMMING PERFORMANCE....................................................................................................35
DATA RETENTION ...................................................................................................................................................35
LATCH-UP CHARACTERISTICS..............................................................................................................................35
ORDERING INFORMATION......................................................................................................................................36
PART NAME DESCRIPTION.....................................................................................................................................37
PACKAGE INFORMATION........................................................................................................................................38
REVISION HISTORY .................................................................................................................................................41
P/N: PM1573
REV. 1.3, NOV. 11, 2013
3
MX25L5121E
MX25L1021E
512K-BIT [x 1] CMOS SERIAL FLASH MEMORY
1M-BIT [x 1] CMOS SERIAL FLASH MEMORY
FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 512K: 524,288 x 1 bit structure
1M: 1,048,576 x 1 bit structure
• 16 Equal Sectors with 4K bytes each (512Kb)
32 Equal Sectors with 4K bytes each (1Mb)
- Any Sector can be erased individually
• 1 Equal Blocks with 64K byte each (512Kb)
2 Equal Blocks with 64K byte each (1Mb)
- Any Block can be erased individually
• Program Capability
- Byte base
- Page base (32 bytes)
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• Performance
- Fast Read: 45MHz serial clock
- Fast program time: 180us(typ.) and 650us(max.)/page
- Fast erase time: 40ms (typ.)/sector ; 1s (typ.)/block
• Low Power Consumption
- Low active read current: 5mA(max.) at 25MHz, 10mA(max.) at 45MHz
- Low active programming current: 8mA (typ.)
- Low active erase current: 10mA (typ.)
- Low standby current: 20uA (typ.)
- Deep power down current: 2uA (typ.)
•
Typical 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Block Lock protection
- The BP0~BP1 status bits defines the size of the area to be software protected against Program and Erase
instructions
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
• Status Register Feature
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-bytes device ID
HARDWARE FEATURES
• SCLK Input
Serial clock input
• SI Input
-
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MX25L5121E
MX25L1021E
- Serial Data Input
• SO Output
- Serial Data Output
• WP# pin
- Hardware write protection
• PACKAGE
- 8-pin SOP (150mil)
- 8-pin TSSOP (173mil)
- 8-USON (2x3mm)
- All devices are RoHS Compliant and Halogen-free
GENERAL DESCRIPTION
The device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus.
The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access
to the device is enabled by CS# input.
The device provides sequential read operation on whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci-
fied page or sector locations will be executed. Program command is executed on page (32 bytes) basis, and erase
command is executes on sector, or block, or whole chip.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode.
The device utilizes Macronix proprietary memory cell, which reliably stores memory contents even after typical
100,000 program and erase cycles.
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MX25L5121E
MX25L1021E
PIN CONFIGURATIONS
8-PIN SOP (150mil)
PIN DESCRIPTION
SYMBOL DESCRIPTION
CS#
SI
Chip Select
1
2
3
4
CS#
SO
VCC
NC
8
7
6
5
Serial Data Input (for 1 x I/O)
Serial Data Output (for 1 x I/O)
Clock Input
WP#
GND
SCLK
SI
SO
SCLK
NC
NC pin (Not connect)
Write Protection
WP#
VCC
GND
8-PIN TSSOP (173mil)
2.7V to 3.6V Power Supply
Ground
1
2
3
4
CS#
SO
VCC
NC
8
7
6
5
WP#
GND
SCLK
SI
8-LAND USON (2x3mm)
1
2
3
4
VCC
CS#
SO
8
7
6
5
NC
SCLK
SI
WP#
GND
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REV. 1.3, NOV. 11, 2013
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MX25L5121E
MX25L1021E
BLOCK DIAGRAM
Address
Generator
Memory Array
Page Buffer
Data
Register
SI
Y-Decoder
SRAM
Buffer
Sense
Amplifier
Mode
Logic
State
Machine
HV
Generator
CS#
SCLK
SO
Clock Generator
Output
Buffer
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MX25L1021E
MEMORY ORGANIZATION
Table 1-1. Memory Organization (512Kb)
Table 1-2. Memory Organization (1Mb)
Block
Sector
Address Range
Block
Sector
Address Range
31
:
01F000h
01FFFFh
:
15
00F000h
00FFFFh
1
:
:
:
:
16
010000h
010FFFh
3
2
1
0
003000h
002000h
001000h
000000h
003FFFh
002FFFh
001FFFh
000FFFh
0
15
00F000h
00FFFFh
:
:
:
3
2
1
0
003000h
002000h
001000h
000000h
003FFFh
002FFFh
001FFFh
000FFFh
0
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MX25L1021E
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-
eration.
2. When incorrect command is inputted to this LSI, this LSI becomes Standby Mode and keeps the Standby Mode
until next CS# falling edge. In Standby Mode, all SO pins of this LSI should be High-Z.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK.
The difference of Serial mode 0 and mode 3 is shown as Figure 1.
5. For the following instructions: RDID, RDSR, READ and FAST_READ the shifted-in instruction sequence is fol-
lowed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following
instructions: WREN, WRDI, WRSR, SE, PP, RDP, and DP the CS# must go high exactly at the byte boundary;
otherwise, the instruction will be rejected and not executed.
6. During the progress of Program, Erase operation, to access the memory array is neglected and not affect the
current operation of Program and Erase.
Figure 1. Serial Modes Supported
CPOL CPHA
shift in
shift out
SCLK
SCLK
(Serial mode 0)
(Serial mode 3)
0
1
0
1
SI
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
P/N: PM1573
REV. 1.3, NOV. 11, 2013
9
MX25L5121E
MX25L1021E
DATA PROTECTION
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control register
architecture of the device constrains that the memory contents can only be changed after specific command
sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC power-
up and power-down or from system noise.
•
•
Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data.
•
•
Software Protection Mode (SPM): by using BP0-BP1 bits to set the part of Flash protected from data change.
Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP1 bits and SRWD bit from data
change.
•
Deep Power Down Mode: By entering Deep Power Down Mode, the flash device also is under protected from
writing all commands except Release from Deep Power Down Mode command (RDP).
Table 2. Protected Area Sizes
Status bit
Protect level
BP1
BP0
MX25L5121E
0 (none)
1 (All)
MX25L1021E
0 (none)
1 (1 block)
2 (All)
0
0
1
1
0
1
0
1
2 (All)
3 (All)
3 (All)
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MX25L1021E
COMMAND DESCRIPTION
Table 3. Command Set
WRSR
RDID
RDSR
FAST READ
(fast read
data)
Command WREN (write WRDI (write
READ (read
data)
(write status (read identific- (read status
register)
01 (hex)
(byte)
1st byte
2nd byte
enable)
disable)
ation)
9F (hex)
register)
05 (hex)
06 (hex)
04 (hex)
03 (hex)
AD1
(A23-A16)
AD2
(A15-A8)
AD3
0B (hex)
AD1
AD2
3rd byte
4th byte
5th byte
AD3
(A7-A0)
Dummy
sets the (WEL) resets the
to write new
outputs
JEDEC
to read out n bytes read n bytes read
the values out until CS# out until CS#
write enable (WEL) write values of the
latch bit
enable latch status register ID: 1-byte
of the status
register
goes high
goes high
Action
bit
Manufacturer
ID & 2-bytes
Device ID
RDP (Release
from deep
power down)
Command SE (sector
BE (block
erase)
CE (chip
erase)
PP (page
program)
DP (Deep
power down)
(byte)
erase)
1st byte
2nd byte
3rd byte
4th byte
20 (hex)
AD1
AD2
52 or D8 (hex) 60 or C7 (hex)
02 (hex)
AD1
AD2
B9 (hex)
AB (hex)
AD1
AD2
AD3
AD3
AD3
to erase the to erase the
to erase
whole chip the selected Power Down Deep Power
page Mode Down Mode
to program enters Deep release from
selected
sector
selected
block
Action
Note 1: It is not recommended to adopt any other code not in the command definition table, which will potentially
enter the hidden mode.
Note 2: Value "1" should be input to the un-used significant bits of address bits by user (e.g. A17~A23(MSB) in
MX25L1021E ; A16-A23(MSB) in MX25L5121E)
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MX25L1021E
(1) Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE,
BE, CE and WRSR which are intended to change the device content, should be set every time after the WREN in-
struction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→CS# goes high. (Please
refer to Figure 9)
(2) Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high. (Please
refer to Figure 10)
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
(3) Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-bytes. The MXIC
Manufacturer ID is C2(hex), the memory type ID is 22(hex) as the first-byte device ID, and the individual device ID
of second-byte ID are listed as table of "ID Definitions". (Please refer to table 4)
The sequence of issuing RDID instruction is: CS# goes low→sending RDID instruction code→24-bits ID data out on
SO→ to end RDID operation can use CS# to high at any time during data out. (Please refer to Figure 11)
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cy-
cle of program/erase operation which is currently in progress. When CS# goes high, the device is at Standby Mode.
Table 4. ID Definitions
MX25L5121E
memory type
22
MX25L1021E
memory type
22
manufacturer
memory
density
10
manufacturer
memory
density
11
RDID Command
ID
C2
ID
C2
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MX25L1021E
(4) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even
in program/erase condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before
sending a new instruction when a program or erase operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→sending RDSR instruction code→Status Register
data out on SO (Please refer to Figure 12-1, Figure 12-2)
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase
progress. When WIP bit sets to 1, which means the device is busy in program/erase progress. When WIP bit sets to 0,
which means the device is not in progress of program/erase register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/
erase instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept
program/erase instruction.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits, volatile bits, indicate the protected area(as defined in table 1) of
the device to against the program/erase instruction without hardware protection mode being set. To write the Block
Protect (BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define
the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip
Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed)
SRWD bit. The Status Register Write Disable (SRWD) bit, volatile bit, is operated together with Write Protection (WP#)
pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP# pin
signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer ac-
cepted for execution and the SRWD bit and Block Protect bits (BP1, BP0) are read only.
Table 5. Status Register
bit7
bit6
bit5
bit4
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
bit1
bit0
SRWD (status
register write Reserved
protect)
WEL
(write enable
latch)
WIP
(write in
progress bit)
Reserved
Reserved
1=write
enable
0=not write 0=not in write
1=write
operation
1=status
register write
disable
0
0
0
(note 1)
(note 1)
enable
operation
Note: 1. See the table "Protected Area Sizes". The default BP0-BP2 values are "1" (protected).
2. The SRWD default value is "0"
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MX25L1021E
(5) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ad-
vance. The WRSR instruction can change the value of Block Protect (BP1, BP0) bits to define the protected area
of memory (as shown in table 1). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in
accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware
Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low sending WRSR instruction code Status Register
→
→
data on SI CS# goes high. (see Figure 13)
→
The WRSR instruction has no effect on b6, b5, b4, b1, b0 of the status register.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)
bit is reset.
Table 6. Protection Modes
Mode
Status register condition
WP# and SRWD bit status
Memory
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP1
Software protection
mode (SPM)
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area
cannot
be program or erase.
bits can be changed
The SRWD, BP0-BP1 of
status register bits cannot be
changed
The protected area
cannot
be program or erase.
Hardware protection
mode (HPM)
WP#=0, SRWD bit=1
Note:
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 1.
As the table above showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).
Software Protected Mode (SPM):
- When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can change
the values of SRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected
mode (SPM).
- When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of
SRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected mode (SPM)
Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previ-
ously been set. It is rejected to write the Status Register and not be executed.
Hardware Protected Mode (HPM):
- When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected
mode (HPM). The data of the protected area is protected by software protected mode by BP1, BP0 and hard-
ware protected mode by the WP# to against data modification.
Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is
entered. If the WP# pin is permanently connected to high, the hardware protected mode can never be entered;
only can use software protected mode via BP1, BP0.
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MX25L1021E
(6) Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out
on the falling edge of SCLK at a maximum frequency fC. The first address can be at any location. The address is
automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be
read out at a single READ instruction.
This product does not provide the function of read around. After reading through density 512Kb or 1Mb, CS# must
go high. Otherwise, the data correctness will not be guaranteed. If the device needs to read data again, it must
issue read command once more.
The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→ 3-bytes address
on SI→data out on SO→to end READ operation can use CS# to high at any time during data out. (Please refer to
Figure 14)
(7) Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→
3-byte address on SI→ 1-dummy byte address on SI→data out on SO→ to end FAST_READ operation can use
CS# to high at any time during data out. (Please refer to Figure 15)
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.
(8) Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-bytes sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit be-
fore sending the Sector Erase (SE). Any address of the sector (Please refer to table 1) is a valid address for Sector
Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the eighth bit of last address byte been
latched-in); otherwise, the instruction will be rejected and not executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence of issuing SE instruction is: CS# goes low→sending SE instruction code→3-bytes address on SI
→CS# goes high. (Please refer to Figure 16)
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
(9) Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte sector erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)
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bit before sending the Block Erase (BE). Any address of the block (see table 2) is a valid address for Block Erase (BE)
instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in);
otherwise, the instruction will be rejected and not executed.
The sequence is shown as Figure 17.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
(10) Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-
tion must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the
sector (see table 1) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte
boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not ex-
ecuted.
The sequence is shown as Figure 18.
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE
timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
(11) Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). After the instruction
and address input, data to be programmed is input sequentially. The internal sequence controller will sequentially
program the data from the initial address. If the transmitted data goes beyond the page boundary, the internal se-
quence controller may not function properly and the content of the device will not be guaranteed. Therefore, If the
initial A4-A0 (The five least significant address bits) are set to all 0, maximum 32 bytes of data can be input sequen-
tially. If the initial address A4-A0 (The five least significant address bits) are not set to all 0, maximum bytes of data
input will be the subtraction of the initial address A4-A0 from 32bytes. The data exceeding 32bytes data is not sent
to device. In this case, data is not guaranteed.
The sequence of issuing PP instruction is: CS# goes low → sending PP instruction code → 3-bytes address on SI→
at least 1-byte on data on SI → CS# goes high. (Please refer to Figure 19)
The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary( the eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the
tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
(12) Deep Power-Down (DP)
The Deep Power Down (DP) instruction is for setting the device on the minimizing the power consumption (to enter-
ing the Deep Power Down Mode), the standby current is reduced from ISB1 to ISB2. The Deep Power Down Mode
requires the Deep Power Down (DP) instruction to enter, during the Deep Power Down Mode, the device is not ac-
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tive and all Read/Write/Program/Erase instruction are ignored.
The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→ CS# goes high. (Please
refer to Figure 20)
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power Down Mode (RDP)
instruction. When Power-down, the Deep Power Down Mode automatically stops, and when power-up, the device
automatically is in Standby Mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest
eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#)
goes high, a delay of tDP is required before entering the Deep Power Down Mode.
(13) Release from Deep Power-Down (RDP)
The Release from Deep Power Down (RDP) instruction is terminated by driving Chip Select (CS#) High. When
Chip Select (CS#) is driven High, the device is put in the Standby Mode. If the device was not previously in the
Deep Power Down Mode, the transition to the Standby Mode is immediate. If the device was previously in the Deep
Power Down Mode, though, the transition to the Standby Mode is delayed by tRES1, and Chip Select (CS#) must
remain High for at least tRES1(max), as specified in Table 8. AC Characteristics. Once in the Standby Mode, the
device waits to be selected, so that it can receive, decode and execute instructions. The RDP instruction is only for
releasing from Deep Power Down Mode.
The sequence is shown as Figure 21. Even in Deep Power Down Mode, the RDP is also allowed to be executed,
only except the device is in progress of program/erase cycle; there's no effect on the current program/erase cycle
in progress.
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POWER-ON STATE
The device is at below states when power-up:
- Standby Mode ( please note it is not Deep Power Down Mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The read, write, erase, and program command should be sent after the below time delay:
- tVSL after VCC reached VCC minimum level
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommend-
ed. (generally around 0.1uF)
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Program/ Erase flow with read array data
start
WREN command
RDSR command*
No
WEL=1?
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
RDSR command
Read WEL=0
Read array data
(same address of PGM/ERS)
No
Verify OK?
Yes
Program/erase successfully
Program/erase fail
Yes
Program/erase
another block?
No
Program/erase completed
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ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Ambient Operating Temperature
Storage Temperature
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
Commercial grade
0°C to 70°C
-65°C to 150°C
-0.5V to 4.6V
-0.5V to 4.6V
-0.5V to 4.6V
Notes:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is stress rating only and functional operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, please
refer to Figure 2, 3.
Figure 3. Maximum Positive Overshoot Waveform
Figure 2. Maximum Negative Overshoot Waveform
20ns
20ns
20ns
Vss
Vcc + 2.0V
Vss-2.0V
Vcc
20ns
20ns
20ns
CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol Parameter
Min.
Typ.
Max.
Unit
Conditions
VIN = 0V
CIN
Input Capacitance
6
8
pF
pF
COUT Output Capacitance
VOUT = 0V
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Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing reference level
Output timing reference level
0.8VCC
0.2VCC
0.7VCC
0.3VCC
0.7VCC
0.3VCC
AC
Measurement
Level
Note: Input pulse rise and fall time are <8ns
Notes: Rise time means 0.2VCC to 0.8VCC; Fall time means 0.8VCC to 0.2VCC.
Figure 5. OUTPUT LOADING
DEVICE UNDER
TEST
2.7K ohm
+3.3V
CL
6.2K ohm
DIODES=IN3064
OR EQUIVALENT
CL=30pF Including jig capacitance
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Table 7. DC CHARACTERISTICS (Temperature = 0 C to 70 C for Commercial grade, VCC = 2.7V ~ 3.6V)
°
°
Symbol Parameter
Notes
Min.
Typ.
Max.
Units Test Conditions
VCC = VCC Max,
uA
ILI
Input Load Current
Output Leakage Current
1
± 2
VIN = VCC or GND
VCC = VCC Max,
uA
ILO
1
1
± 2
30
8
VOUT = VCC or GND
VIN = VCC or GND,
CS# = VCC
ISB1 VCC Standby Current
20
2
uA
Deep Power Down
Current
VIN = VCC or GND,
CS# = VCC
ISB2
uA
f=45MHz,
10
5
mA SCLK=0.1VCC/0.9VCC,
SO=Open
f=25MHz,
mA SCLK=0.1VCC/0.9VCC,
SO=Open
ICC1 VCC Read
1
VCC Program Current
Program in Progress,
CS# = VCC
ICC2
(PP)
1
1
1
8
12
15
15
mA
VCC Write Register
ICC3
Program Status Register in
mA
(WRSR) Current
Progress, CS#=VCC
VCC Sector Erase
ICC4
Erase in Progress,
CS#=VCC
10
mA
Current (SE)
VIL
VIH
VOL
Input Low Voltage
Input High Voltage
Output Low Voltage
-0.5
0.2VCC
VCC+0.4
0.4
V
V
0.8VCC
V
V
IOL = 1.6mA
IOH = -100uA
VOH Output High Voltage
VCC-0.2
2.1
Low VCC Write Inhibit
Voltage
VWI
3
2.3
2.5
V
Notes :
1. Typical values at VCC = 3.3V, T = 25 C. These currents are valid for all product versions (package and speeds).
°
2. Typical value is calculated by simulation.
3. Not 100% tested.
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Table 8. AC CHARACTERISTICS (Temperature = 0°C to 70°C for Commercial grade, VCC = 2.7V ~ 3.6V)
Symbol Alt. Parameter
Min.
Typ.
Max. Unit
fSCLK
fC Clock Frequency for FAST_READ
DC
45
MHz
Clock Frequency for the following instructions:
fR READ, PP, SE, BE, CE, DP, RDP, WREN, RDID, RDSR,
WRSR
fRSCLK
DC
25
MHz
@ 25 MHz
18
10
18
10
0.1
ns
ns
ns
ns
V/ns
ns/V
V/ns
ns/V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
us
us
us
ms
ns
s
tCH(1) tCLH Clock High Time
@ 45 MHz
@ 25 MHz
@ 45 MHz
tCL(1)
tCLL Clock Low Time
Clock Rise Time (3) (peak to peak)
tCLCH(2)
tRISE(2)
tCHCL(2)
tFALL(2)
Clock Rise Time (3)
10
10
Clock Fall Time (3) (peak to peak)
Clock Fall Time (3)
0.1
tSLCH tCSS CS# Active Setup Time (relative to SCLK)
tCHSL CS# Not Active Hold Time (relative to SCLK)
tDVCH tDSU Data In Setup Time
20
20
4
tCHDX
tCHSH
tSHCH
tDH Data In Hold Time
6
CS# Active Hold Time (relative to SCLK)
CS# Not Active Setup Time (relative to SCLK)
Read
20
20
50
50
tSHSL(3) tCSH CS# Deselect Time
Write/Erase/Program
tSHQZ(2) tDIS Output Disable Time
20
18
18
@ 25 MHz
@ 45 MHz
tCLQV
tV Clock Low to Output Valid
tCLQX
tWHSL(4)
tSHWL(4)
tW
tHO Output Hold Time
0
Write Protect Setup Time
20
Write Protect Hold Time
100
Write Status Register Cycle Time
CS# High to Deep Power Down Mode
5
15
20
tDP(2)
tRES1(2)
tPP
CS# High to Standby Mode without Electronic Signature Read
Page Program Cycle Time (32 Bytes)
Sector Erase Cycle Time (4K Bytes)
CS# High to Power-Down
20
150
40
650
300
tSE
tRPD1
tBE
100
Block Erase Cycle Time
1
1
2
2
3
512Kb
s
tCE
Chip Erase Cycle Time
1Mb
1.5
s
Notes:
1. tCH + tCL must be greater than or equal to 1/ f (fC).
2. Value guaranteed by characterization, not 100% tested in production.
3. Test condition is shown as Figure 4, 5.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
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Timing Analysis
Figure 6. Serial Input Timing
tSHSL
tSHCH
CS#
tSLCH
tCHSH
tCHSL
SCLK
tCHCL
tDVCH
tCLCH
tCHDX
MSB
LSB
SI
High-Z
SO
Figure 7. Output Timing
CS#
tCH
SCLK
tCLQV
tSHQZ
tCLQV
tCL
tCLQX
SO
tCLQX
LSB
ADDR.LSB IN
SI
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Figure 8. WP# Disable Setup and Hold Timing during WRSR when SRWD=1
WP#
tSHWL
tWHSL
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14
15
SCLK
01
SI
High-Z
SO
Figure 9. Write Enable (WREN) Sequence (Command 06)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
06
SI
High-Z
SO
Figure 10. Write Disable (WRDI) Sequence (Command 04)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
04
SI
High-Z
SO
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Figure 11. Read Identification (RDID) Sequence (Command 9F)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
28 29 30 31
SCLK
SI
Command
9F
Manufacturer ID
Device ID
High-Z
SO
7
6
5
3
2
1
0
15 14 13
MSB
3
2
1
0
MSB
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Figure 12-1. Read Status Register (RDSR) Sequence (Command 05)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
command
05
Status Register Out
Status Register Out
High-Z
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 12-2. Read Status Register (RDSR) Sequence (Command 05)
CS#
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
Command
05
Status Register Out
High-Z
SO
7
6
5
4
3
2
1
0
MSB
CS#
SCLK
SI
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Command
05
Status Register Out
High-Z
SO
7
6
5
4
3
2
1
0
MSB
CS#
SCLK
SI
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Command
05
Status Register Out
High-Z
SO
7
6
5
4
3
2
1
0
MSB
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Figure 13. Write Status Register (WRSR) Sequence (Command 01)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
command
01
Status
Register In
SI
7
6
5
4
3
2
0
1
MSB
High-Z
SO
Figure 14. Read Data Bytes (READ) Sequence (Command 03)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
command
03
24-Bit Address
23 22 21
MSB
3
2
1
0
SI
Data Out 1
Data Out 2
High-Z
2
7
6
5
4
3
1
7
0
SO
MSB
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Figure 15. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCLK
Command
0B
24 BIT ADDRESS
SI
23 22 21
3
2
1
0
High-Z
SO
CS#
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
Dummy Byte
7
6
5
4
3
2
0
1
SI
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
Figure 16. Sector Erase (SE) Sequence (Command 20)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
20
24 Bit Address
2
SI
23 22
MSB
1
0
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Figure 17. Block Erase (BE) Sequence (Command D8 or 52)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
D8
24 Bit Address
SI
23 22
MSB
2
0
1
Note: BE command is D8(hex).
Figure 18. Chip Erase (CE) Sequence (Command 60 or C7)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
60 or C7
SI
Note: CE command is 60(hex) or C7(hex).
Figure 19. Page Program (PP) Sequence (Command 02)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
02
24-Bit Address
Data Byte 1
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
SI
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 32
Data Byte 2
Data Byte 3
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
SI
MSB
MSB
MSB
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Figure 20. Deep Power Down (DP) Sequence (Command B9)
CS#
t
DP
0
1
2
3
4
5
6
7
SCLK
SI
Command
B9
Standby Mode
Deep Power Down Mode
Figure 21. Release from Deep Power Down (RDP) Sequence (Command AB)
CS#
t
RES1
0
1
2
3
4
5
6
7
SCLK
SI
Command
AB
High-Z
SO
Deep Power Down Mode Standby Mode
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Figure 23. Power-Up Timing
V
CC
V
(max)
CC
Chip Selection is Not Allowed
V
(min)
CC
tVSL
Device is fully
accessible
time
Note: VCC (max.) is 3.6V and VCC (min.) is 3.0V.
Table 9. Power-Up Timing
Symbol
Parameter
Min.
Max.
Unit
tVSL(1)
VCC(min) to CS# low
300
us
Note: 1. The parameter is characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
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OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in Figure 24 and Figure 25 are for the supply voltages and the control signals at device power-
up and power-down. If the timing in the figures is ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 24. AC Timing at Device Power-Up
VCC(min)
VCC
GND
tVR
tSHSL
CS#
tSHCH
tSLCH
tCHSL
tCHSH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
SI
High Impedance
SO
Symbol
tVR
tRH
Parameter
VCC Rise Time
Reset High Time Before Read
Notes
Min.
10
5
Max.
500000
Unit
us/V
ms
1
Notes :
1. Sampled, not 100% tested.
2. For AC spec tSLCH, tDVCH, tCHDX, tCHSH in the figure, please refer to "AC CHARACTERISTICS" table.
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Figure 25. Power-Down Sequence
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
VCC
CS#
SCLK
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ERASE AND PROGRAMMING PERFORMANCE
Parameter
Min.
Typ. (1)
Max. (2)
Unit
Sector Erase Time
Block Erase Time
40
1
300
2
ms
s
512Kb
1
2
s
s
Chip Erase Time
1Mb
1.5
3
Page Program Time
Erase/Program Cycle
150
100,000
650
us
cycles
Note:
1. Typical program and erase time assumes the following conditions: 25 C, 3.3V, and checker board pattern.
°
2. Under worst conditions of 70 C and 2.7V.
°
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming com-
mand.
4. Erase/Program cycles comply with JEDEC JESD-47E & A117A standard.
DATA RETENTION
Parameter
Condition
Min.
Max.
Unit
Data retention
70˚C
20
years
LATCH-UP CHARACTERISTICS
Min.
Max.
Input Voltage with respect to GND on all power pins, SI, CS#
Input Voltage with respect to GND on SO
Current
-1.0V
-1.0V
2 VCCmax
VCC + 1.0V
+100mA
-100mA
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
P/N: PM1573
REV. 1.3, NOV. 11, 2013
35
MX25L5121E
MX25L1021E
ORDERING INFORMATION
512Kb
CLOCK
(MHz)
PART NO.
TEMPERATURE
0 C~70 C
PACKAGE
Remark
MX25L5121EMC-20G
MX25L5121EOC-20G
MX25L5121EZUC-20G
45
45
45
8-SOP (150mil)
8-TSSOP (173mil)
8-USON (2x3mm)
°
°
0 C~70 C
°
°
0 C~70 C
°
°
1Mb
CLOCK
(MHz)
PART NO.
TEMPERATURE
PACKAGE
Remark
MX25L1021EMC-20G
45
0 C~70 C
8-SOP (150mil)
°
°
P/N: PM1573
REV. 1.3, NOV. 11, 2013
36
MX25L5121E
MX25L1021E
PART NAME DESCRIPTION
MX 25
L
1021E
M
C
20 G
OPTION:
G: RoHS Compliant & Halogen-free
SPEED:
20: 45MHz
TEMPERATURE RANGE:
C: Commercial (0°C to 70°C)
PACKAGE:
M: 150mil 8-SOP
O: 173mil 8-TSSOP
ZU: 2x3mm 8-USON
DENSITY & MODE:
5121E: 512Kb
1021E: 1Mb
TYPE:
L: 3V
DEVICE:
25: Serial Flash
P/N: PM1573
REV. 1.3, NOV. 11, 2013
37
MX25L5121E
MX25L1021E
PACKAGE INFORMATION
P/N: PM1573
REV. 1.3, NOV. 11, 2013
38
MX25L5121E
MX25L1021E
P/N: PM1573
REV. 1.3, NOV. 11, 2013
39
MX25L5121E
MX25L1021E
P/N: PM1573
REV. 1.3, NOV. 11, 2013
40
MX25L5121E
MX25L1021E
REVISION HISTORY
Revision No. Description
Page
P12
Date
APR/07/2010
0.01
1. Corrected 25L5121 ID code
2. Added VWI into table 7
P22
3. Modified ISB1, ISB2, ICC1, ICC2 & ICC4
4. Modified tDVCH, tCHDX & tCLQV
5. Modified EPN
P4,22,36
P23
P36,37
1.0
1. Removed "Advanced Information"
2. Modified Chip Erase time (1Mb)
3. Modified "At Device Power-Up and Power-Down" description
4. Modified ILO test conditions from VIN to VOUT
5. Added 8-USON package information
P4
P23,35
P33
P22
P5,6,36,37,40
NOV/02/2011
DEC/29/2011
1.1
Removed "Advanced Information".
Modified Storage Temperature to "-65°C to 150°C"
P5,6,36,37
P20
1.2
1.3
Modified fSCLK & fRSCLK (Min.)
P23
OCT/11/2013
NOV/11/2013
1. Updated parameters for DC/AC Characteristics
2. Updated Erase and Programming Performance
P4,22,23
P4,35
P/N: PM1573
REV. 1.3, NOV. 11, 2013
41
MX25L5121E
MX25L1021E
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MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
42
相关型号：
MX25L1026EM1I-10G
Flash, 512KX2, PDSO8, 0.150 INCH, HALOGEN FREE AND ROHS COMPLIANT, MS-012, SOP-8
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