MX25L1025CMI-12G [Macronix]
Flash, 1MX1, PDSO8, 0.150 INCH, ROHS COMPLIANT, MS-012, SOP-8;
| 型号： | MX25L1025CMI-12G |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | Flash, 1MX1, PDSO8, 0.150 INCH, ROHS COMPLIANT, MS-012, SOP-8 时钟 光电二极管 内存集成电路 |
| 文件： | 总39页 (文件大小：1705K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX25L1025C
1M-BIT [x 1] CMOS SERIAL FLASH
FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 1,048,576 x 1 bit structure
• 32 Equal Sectors with 4K byte each
- Any Sector can be erased individually
• 2 Equal Blocks with 64K byte each
- Any Block can be erased individually
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast access time: 85MHz serial clock and 66MHz serial clock
- Fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page)
- Fast erase time: 60ms(typ.)/sector (4K-byte per sector) ; 1s(typ.) and 2s(max.)/block (64K-byte per block)
• Low Power Consumption
- Low active read current: 12mA(max.) at 85MHz, 8mA(max.) at 66MHz and 4mA(max.) at 33MHz
- Low active programming current: 15mA (max.)
- Low active erase current: 15mA (max.)
- Low standby current: 10uA (max.)
- Deep power-down mode 1uA (typical)
• Minimum 100,000 erase/program cycles
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Block Lock protection
- The BP0~BP1 status bit defines the size of the area to be software protected against Program and Erase
instructions.
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
• Status Register Feature
• Electronic Identification
- JEDEC 2-byte Device ID
- RES command, 1-byte Device ID
HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI Input
- Serial Data Input
• SO Output
P/N: PM1480
REV. 1.1, JUL. 21, 2009
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MX25L1025C
- Serial Data Output
• WP# pin
- Hardware write protection
• HOLD# pin
- pause the chip without diselecting the chip
• PACKAGE
- 8-pin SOP (150mil)
- All Pb-free devices are RoHS Compliant
GENERAL DESCRIPTION
MX25L1025C is a CMOS 1,048,576 bit serial Flash memory, which is configured as 131,072 x 8 internally.The
MX25L1025C feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus.
The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access
to the device is enabled by CS# input.
The MX25L1025C provide sequential read operation on whole chip.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the speci-
fied page or sector/block locations will be executed. Program command is executed on page (256 bytes) basis, and
erase command is executes on chip or sector(4K-bytes) or block(64K-bytes).
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 10uA DC cur-
rent.
The MX25L1025C utilize Macronix's proprietary memory cell, which reliably stores memory contents even after
100,000 program and erase cycles.
P/N: PM1480
REV. 1.1, JUL. 21, 2009
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MX25L1025C
PIN CONFIGURATIONS
8-PIN SOP (150mil)
PIN DESCRIPTION
SYMBOL DESCRIPTION
CS#
SI
SO
Chip Select
Serial Data Input
Serial Data Output
Clock Input
1
2
3
4
CS#
SO
VCC
HOLD#
SCLK
SI
8
7
6
5
SCLK
WP#
GND
Hold, to pause the device without
deselecting the device
+ 3.3V Power Supply
Ground
HOLD#
VCC
GND
WP#
Write Protection
P/N: PM1480
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MX25L1025C
BLOCK DIAGRAM
Address
Generator
Memory Array
Page Buffer
Data
Register
SI
Y-Decoder
SRAM
Buffer
Output
Buffer
Sense
Amplifier
Mode
Logic
State
Machine
CS#
HV
Generator
SO
SCLK
Clock Generator
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MX25L1025C
DATA PROTECTION
The MX25L1025C is designed to offer protection against accidental erasure or programming caused by spurious
system level signals that may exist during power transition. During power up the device automatically resets the
state machine in the standby mode. In addition, with its control register architecture, alteration of the memory con-
tents only occurs after successful completion of specific command sequences. The device also incorporates sev-
eral features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system
noise.
•
Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
•
•
Software Protection Mode (SPM): by using BP0-BP1 bits to set the part of Flash protected from data change.
Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP1 bits and SRWD bit from data
change.
•
Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from
writing all commands except Release from deep power down mode command (RDP) and Read Electronic Sig-
nature command (RES).
P/N: PM1480
REV. 1.1, JUL. 21, 2009
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MX25L1025C
Table 1. Protected Area Sizes
Status bit
Protect level
1Mb
BP1
BP0
0
0
1
1
0
1
0
1
0 (none)
1 (1 block)
2 (2 blocks)
3 (All)
None
Block 1
All
All
HOLD FEATURE
HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the
operation of write status register, programming, or erasing in progress.
The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal
while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start
until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Se-
rial Clock(SCLK) signal is being low( if Serial Clock signal is not being low, HOLD operation will not end until Serial
Clock being low), see Figure 1.
Figure 1. Hold Condition Operation
CS#
SCLK
HOLD#
Hold
Hold
Condition
(standard)
Condition
(non-standard)
The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care
during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of
the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low.
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MX25L1025C
Table 2. COMMAND DEFINITION
RDSR
WRSR
FAST READ
Command WREN (write WRDI (write RDID (read
READ (read
data)
SE (sector
erase)
(read status (write status
register)
05 (hex)
(fast read
data)
0B (hex)
AD1
(byte)
enable)
disable)
identification)
register)
01 (hex)
1st byte
2nd byte
3rd byte
4th byte
5th byte
06 (hex)
04 (hex)
9F (hex)
03 (hex)
AD1
AD2
20 (hex)
AD1
AD2
AD2
AD3
x
AD3
AD3
sets the
(WEL) write (WEL) write
enable latch enable latch
resets the
outputs
JEDEC
ID: 1-byte
Manufacturer
ID & 2-byte
Device ID
to read out to write new n bytes read n bytes read to erase the
the values
of the status
register
values of
the status
register
out until CS# out until CS#
goes high goes high
selected
sector
Action
bit
bit
REMS (read
electronic
electronic ID) manufacturer &
device ID)
RDP (Release
from deep
power down)
Command
(byte)
BE (block
erase)
PP (page
program)
DP (Deep
power down)
RES (read
CE (chip erase)
60 or C7 (hex)
1st byte
2nd byte
3rd byte
4th byte
D8 (hex)
AD1
AD2
02 (hex)
AD1
AD2
B9 (hex)
AB (hex)
AB (hex)
90 (hex)
x
x
x
x
x
AD3
AD3
ADD (1)
to erase the to erase whole to program the enters deep
release from
deep power
down mode
to read out
1-byte Device Manufacturer
output the
selected block
chip
selected page
power down
mode
ID
ID & Device ID
Action
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.
(2) It is not allowed to adopt any other code which is not in the above command definition table.
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MX25L1025C
Table 3. Memory Organization
Block
Sector
31
:
Address Range
01F000h 01FFFFh
1
:
:
16
15
:
010000h
00F000h
:
010FFFh
00FFFFh
:
3
2
1
0
003000h
002000h
001000h
000000h
003FFFh
002FFFh
001FFFh
000FFFh
0
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MX25L1025C
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-
eration.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode
until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until
next CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK.
The difference of Serial mode 0 and mode 3 is shown as Figure 2.
5. For the following instructions: RDID, RDSR, READ, FAST_READ, RES and REMS the shifted-in instruction se-
quence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the
following instructions: WREN, WRDI, WRSR, SE, BE, CE, PP, RDP and DP the CS# must go high exactly at the
byte boundary; otherwise, the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglect-
ed and not affect the current operation of Write Status Register, Program, Erase.
Figure 2. Serial Modes Supported
CPOL CPHA
shift in
shift out
SCLK
SCLK
(Serial mode 0)
(Serial mode 3)
0
1
0
1
SI
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
P/N: PM1480
REV. 1.1, JUL. 21, 2009
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MX25L1025C
COMMAND DESCRIPTION
(1) Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE,
BE, CE, and WRSR, which are intended to change the device content, should be set every time after the WREN in-
struction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes high. (see
Figure 11)
(2) Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes high. (see
Figure 12)
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
(3) Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC
Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID
of second-byte ID is as followings: 11(hex) for MX25L1025C.
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code → 24-bits ID data out
on SO→ to end RDID operation can use CS# to high at any time during data out. (see Figure. 13)
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cy-
cle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
P/N: PM1480
REV. 1.1, JUL. 21, 2009
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MX25L1025C
(4) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in
program/erase/write status register condition) and continuously. It is recommended to check the Write in Progress (WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register
data out on SO (see Figure. 14)
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write
status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status
register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status
register cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the de-
vice will not accept program/erase/write status register instruction.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits, volatile bits, indicate the protected area(as defined in table 1) of
the device to against the program/erase instruction without hardware protection mode being set. To write the Block
Protect (BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define
the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip
Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed)
SRWD bit. The Status Register Write Disable (SRWD) bit, volatile bit, is operated together with Write Protection (WP#)
pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP# pin
signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer ac-
cepted for execution and the SRWD bit and Block Protect bits (BP1, BP0) are read only.
bit7
bit6
bit5
bit4
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
bit1
bit0
SRWD (status
register write
protect)
WEL
(write enable
latch)
WIP
(write in
progress bit)
0
0
0)
1=write
enable
0=not write 0=not in write
enable operation
1=write
operation
1=status
register write
disable
(note 1)
(note 1)
Note: 1. See the table "Protected Area Sizes".
2. The endurance cycles of protect bits are 100,000 cycles; however, the tW time out spec of protect bits is
relaxed as tW = N x 15ms (N is a multiple of 10,000 cycles, ex. N = 2 for 20,000 cycles) after 10,000 cycles
on those bits.
P/N: PM1480
REV. 1.1, JUL. 21, 2009
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MX25L1025C
(5) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the
Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in ad-
vance. The WRSR instruction can change the value of Block Protect (BP1, BP0) bits to define the protected area
of memory (as shown in table 1). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in
accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware
Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register
data on SI→ CS# goes high. (see Figure 15)
The WRSR instruction has no effect on b6, b5, b4, b1, b0 of the status register.
The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1
during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)
bit is reset.
Table 4. Protection Modes
Mode
Status register condition
WP# and SRWD bit status
Memory
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP1
Software protection
mode(SPM)
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area
cannot
be program or erase.
bits can be changed
The SRWD, BP0-BP1 of
status register bits cannot be
changed
The protected area
cannot
be program or erase.
Hardware protection
mode (HPM)
WP#=0, SRWD bit=1
Note:
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 1.
As the above table showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM).
Software Protected Mode (SPM):
-
When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can change
the values of SRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected
mode (SPM).
-
When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of
SRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected mode (SPM)
Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously
been set. It is rejected to write the Status Register and not be executed.
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MX25L1025C
Hardware Protected Mode (HPM):
-
When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected
mode (HPM). The data of the protected area is protected by software protected mode by BP1, BP0 and hard-
ware protected mode by the WP# to against data modification.
Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered.
If the WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can use
software protected mode via BP1, BP0.
(6) Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→ 3-byte address on
SI→data out on SO→ to end READ operation can use CS# to high at any time during data out. (see Figure. 16)
(7) Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ instruction code→3-
byte address on SI→1-dummy byte address on SI→data out on SO→ to end FAST_READ operation can use CS#
to high at any time during data out. (see Figure. 17)
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.
(8) Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable (WREN) in-
struction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address
of the sector (see table 3) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the
byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not
executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte address on SI
→CS# goes high. (see Figure 19)
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MX25L1025C
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.
(9) Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". A Write Enable (WREN) in-
struction must execute to set the Write Enable Latch (WEL) bit before sending the Block Erase (BE). Any address
of the block (see table 3) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the
byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not
executed.
The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on SI →
CS# goes high. (see Figure 20)
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the
tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page.
(10) Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-
tion must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the
sector (see table 3) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte
boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not ex-
ecuted.
The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→ CS# goes high. (see Fig-
ure 20)
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE
timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip
is protected by BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when
BP1, BP0 all set to "0".
(11) Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). If the eight least sig-
nificant address bits (A7-A0) are not all 0, all transmitted data which goes beyond the end of the current page are
programmed from the start address if the same page (from the address whose 8 least significant address bits (A7-
A0) are all 0). The CS# must keep during the whole Page Program cycle. The CS# must go high exactly at the
byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not
executed. If more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request
page and previous data will be disregarded. If less than 256 bytes are sent to the device, the data is programmed
at the request address of the page without effect on other address of the same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→
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MX25L1025C
at least 1-byte on data on SI→CS# goes high. (see Figure 18)
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the
tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP1, BP0 bits, the Page Program (PP) instruction will not be executed.
(12) Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to enter-
ing the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode
requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not ac-
tive and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in standby mode not deep
power-down mode. It's different from Standby mode.
The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→CS# goes high. (see Fig-
ure 22)
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode (RDP)
and Read Electronic Signature (RES) instruction. (RES instruction to allow the ID been read out). When Power-
down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby
mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction
code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay
of tDP is required before entering the Deep Power-down mode and reducing the current to ISB2.
(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in
the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip
Select (CS#) must remain High for at least tRES2(max), as specified in Table 6. Once in the Stand-by Power mode,
the device waits to be selected, so that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID
Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new deisng,
please use RDID instruction. Even in Deep power-down mode, the RDP and RES are also allowed to be executed,
only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/
write cycle in progress.
The sequence is shown as Figure 23,24.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat-
edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously
in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in
Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least
tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute
instruction.
The RDP instruction is for releasing from Deep Power Down Mode.
P/N: PM1480
REV. 1.1, JUL. 21, 2009
15
MX25L1025C
(14) Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the
JEDEC assigned manufacturer ID and the specific device ID.
The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is
initiated by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes
address (A7~A0). After which, the Manufacturer ID for MXIC (C2h) and the Device ID are shifted out on the falling
edge of SCLK with most significant bit (MSB) first as shown in figure 25. The Device ID values are listed in Table of
ID Definitions on page 16. If the one-byte address is initially set to 01h, then the device ID will be read first and then
followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one
to the other. The instruction is completed by driving CS# high.
Table of ID Definitions:
manufacturer ID
C2
memory type
memory density
RDID Command
RES Command
REMS Command
20
electronic ID
10
device ID
10
11
manufacturer ID
C2
P/N: PM1480
REV. 1.1, JUL. 21, 2009
16
MX25L1025C
POWER-ON STATE
The device is at below states when power-up:
- Standby mode ( please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state.
For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not
guaranteed. The read, write, erase, and program command should be sent after the below time delay:
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.
Please refer to the figure of "power-up timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommend-
ed.(generally around 0.1uF)
P/N: PM1480
REV. 1.1, JUL. 21, 2009
17
MX25L1025C
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Industrial grade
-40°C to 85°C
-55°C to 125°C
-0.5V to 4.6V
-0.5V to 4.6V
-0.5V to 4.6V
Ambient Operating Temperature
Storage Temperature
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is stress rating only and functional operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot to 4.6V or -0.5V for period up to 20ns.
4. All input and output pins may overshoot to VCC+0.5V while VCC+0.5V is smaller than or equal to 4.6V.
Figure 4. Maximum Positive Overshoot Waveform
Figure 3.Maximum Negative Overshoot Waveform
20ns
4.6V
0V
3.6V
-0.5V
20ns
CAPACITANCE TA = 25 C, f = 1.0 MHz
°
SYMBOL PARAMETER
MIN.
TYP
MAX.
UNIT
pF
CONDITIONS
VIN = 0V
CIN
Input Capacitance
6
COUT Output Capacitance
8
pF
VOUT = 0V
P/N: PM1480
REV. 1.1, JUL. 21, 2009
18
MX25L1025C
Figure 5. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing referance level
Output timing referance level
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AC
Measurement
Level
0.5VCC
Note: Input pulse rise and fall time are <5ns
Figure 6. OUTPUT LOADING
DEVICE UNDER
TEST
2.7K ohm
+3.3V
CL
6.2K ohm
DIODES=IN3064
OR EQUIVALENT
CL=30pF Including jig capacitance
(CL=15pF Including jig capacitance for 85MHz)
P/N: PM1480
REV. 1.1, JUL. 21, 2009
19
MX25L1025C
Table 5. DC CHARACTERISTICS (Temperature = -40 C to 85 C for Industrial grade, VCC = 2.7V ~ 3.6V)
°
°
SYMBOL PARAMETER
NOTES
MIN.
TYP.
MAX. UNITS TEST CONDITIONS
ILI
Input Load Current
1
± 2
uA VCC = VCC Max,
VIN = VCC or GND
ILO
Output Leakage Current
1
1
± 2
uA VCC = VCC Max,
VIN = VCC or GND
VIN = VCC or GND,
ISB1 VCC Standby Current
10
uA
CS# = VCC
Deep Power-down
Current
VIN = VCC or GND,
CS# = VCC
ISB2
1
5
uA
f=85MHz,
SCLK=0.1VCC/0.9VCC,
SO=Open
12
8
mA
mA
mA
f=66MHz,
SCLK=0.1VCC/0.9VCC,
SO=Open
ICC1 VCC Read
1
1
f=33MHz,
SCLK=0.1VCC/0.9VCC,
SO=Open
4
VCC Program Current
Program in Progress,
CS# = VCC
ICC2
(PP)
15
mA
mA
VCC Write Status
ICC3
Program status register in
progress, CS#=VCC
15
15
15
Register (WRSR) Current
VCC Sector Erase
Current (SE)
ICC4
1
1
mA Erase in Progress, CS#=VCC
mA Erase in Progress, CS#=VCC
VCC Chip Erase Current
ICC5
(CE)
VIL
VIH
VOL
Input Low Voltage
Input High Voltage
Output Low Voltage
-0.5
0.3VCC
VCC+0.4
0.4
V
V
0.7VCC
V
V
IOL = 1.6mA
IOH = -100uA
VOH Output High Voltage
VCC-0.2
Low VCC Write Inhibit
Voltage
VWI
3
2.1
2.3
2.5
V
Notes :
1. Typical values at VCC = 3.3V, T = 25 C. These currents are valid for all product versions (package and speeds).
°
2. Typical value is calculated by simulation.
3. Not 100% tested.
P/N: PM1480
REV. 1.1, JUL. 21, 2009
20
MX25L1025C
Table 6. AC CHARACTERISTICS (Temperature = -40 C to 85 C for Industrial grade, VCC = 2.7V ~ 3.6V)
°
°
Symbol Alt. Parameter
Min.
Typ.
Max.
85
Unit
Clock Frequency for the following instructions:
fC FAST_READ, PP, SE, BE, CE, DP, RES,RDP
WREN, WRDI, RDID, RDSR, WRSR
fR Clock Frequency for READ instructions
@33MHz
fSCLK
1KHz
MHz
fRSCLK
1KHz
15
5.5
15
5.5
0.1
0.1
5
33
MHz
ns
ns
ns
ns
V/ns
V/ns
ns
ns
ns
tCH(1) tCLH Clock High Time
@85MHz
@33MHz
@85MHz
tCL(1)
tCLL Clock Low Time
tCLCH(2)
tCHCL(2)
Clock Rise Time (3) (peak to peak)
Clock Fall Time (3) (peak to peak)
tSLCH tCSS CS# Active Setup Time (relative to SCLK)
tCHSL CS# Not Active Hold Time (relative to SCLK)
tDVCH tDSU Data In Setup Time
5
2
tCHDX
tCHSH
tSHCH
tDH Data In Hold Time
5
5
5
ns
ns
ns
CS# Active Hold Time (relative to SCLK)
CS# Not Active Setup Time (relative to SCLK)
tSHSL tCSH CS# Deselect Time
tSHQZ(2) tDIS Output Disable Time
100
ns
ns
ns
ns
ns
ns
ns
ns
6
8
6
30pF
15pF
tCLQV
tV Clock Low to Output Valid
tHO Output Hold Time
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
0
5
5
5
5
HOLD# Setup Time (relative to SCLK)
HOLD# Hold Time (relative to SCLK)
HOLD Setup Time (relative to SCLK)
HOLD Hold Time (relative to SCLK)
ns
tHHQX(2) tLZ HOLD to Output Low-Z
tHLQZ(2) tHZ HOLD# to Output High-Z
6
6
ns
ns
tWHSL(4)
tSHWL(4)
tDP(2)
Write Protect Setup Time
Write Protect Hold Time
20
100
ns
ns
us
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic
Signature Read
CS# High to Standby Mode with Electronic
Signature Read
3
3
tRES1(2)
tRES2(2)
us
us
1.8
tW
Write Status Register Cycle Time
Page Program Cycle Time
Sector Erase Cycle Time
Block Erase Cycle Time
Chip Erase Cycle Time
5
1.4
60
1
15
5
ms
ms
ms
s
tPP
tSE
tBE
tCE
2
2
1
s
Note:
1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
5. Test condition is shown as Figure 3.
P/N: PM1480
REV. 1.1, JUL. 21, 2009
21
MX25L1025C
Table 7. Power-Up Timing
Symbol
Parameter
Min.
Max.
Unit
tVSL(1)
VCC(min) to CS# low
10
us
Note: 1. The parameter is characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
P/N: PM1480
REV. 1.1, JUL. 21, 2009
22
MX25L1025C
Figure 7. Serial Input Timing
tSHSL
tSHCH
tCHCL
CS#
tCHSL
tSLCH
tCHSH
SCLK
tDVCH
tCHDX
tCLCH
MSB
LSB
SI
High-Z
SO
Figure 8. Output Timing
CS#
tCH
SCLK
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
LSB
SO
tQLQH
tQHQL
ADDR.LSB IN
SI
P/N: PM1480
REV. 1.1, JUL. 21, 2009
23
MX25L1025C
Figure 9. Hold Timing
CS#
tHLCH
tCHHH
tCHHL
tHLQZ
tHHCH
tHHQX
SCLK
SO
HOLD#
* SI is "don't care" during HOLD operation.
Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1
WP#
tSHWL
tWHSL
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14
15
SCLK
01
SI
High-Z
SO
P/N: PM1480
REV. 1.1, JUL. 21, 2009
24
MX25L1025C
Figure 11. Write Enable (WREN) Sequence (Command 06)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
06
SI
High-Z
SO
Figure 12. Write Disable (WRDI) Sequence (Command 04)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
04
SI
High-Z
SO
Figure 13. Read Identification (RDID) Sequence (Command 9F)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
28 29 30 31
SCLK
SI
Command
9F
Manufacturer Identification
Device Identification
High-Z
SO
7
6
5
3
2
1
0
15 14 13
MSB
3
2
1
0
MSB
P/N: PM1480
REV. 1.1, JUL. 21, 2009
25
MX25L1025C
Figure 14. Read Status Register (RDSR) Sequence (Command 05)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCLK
SI
command
05
Status Register Out
Status Register Out
High-Z
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 15. Write Status Register (WRSR) Sequence (Command 01)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCLK
command
01
Status
Register In
SI
7
6
5
4
3
2
0
1
MSB
High-Z
SO
Figure 16. Read Data Bytes (READ) Sequence (Command 03)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
command
03
24-Bit Address
23 22 21
MSB
3
2
1
0
SI
Data Out 1
Data Out 2
High-Z
2
7
6
5
4
3
1
7
0
SO
MSB
P/N: PM1480
REV. 1.1, JUL. 21, 2009
26
MX25L1025C
Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCLK
Command
0B
24 BIT ADDRESS
SI
23 22 21
3
2
1
0
High-Z
SO
CS#
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
Dummy Byte
7
6
5
4
3
2
0
1
SI
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
P/N: PM1480
REV. 1.1, JUL. 21, 2009
27
MX25L1025C
Figure 18. Page Program (PP) Sequence (Command 02)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
02
24-Bit Address
Data Byte 1
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
SI
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 2
Data Byte 3
Data Byte 256
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
SI
MSB
MSB
MSB
P/N: PM1480
REV. 1.1, JUL. 21, 2009
28
MX25L1025C
Figure 19. Sector Erase (SE) Sequence (Command 20)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
20
24 Bit Address
SI
7
6
2
1
0
MSB
Note: SE command is 20(hex).
Figure 20. Block Erase (BE) Sequence (Command 52 or D8)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
52 or D8
24 Bit Address
SI
23 22
MSB
2
0
1
Note: BE command is 52 or D8(hex).
P/N: PM1480
REV. 1.1, JUL. 21, 2009
29
MX25L1025C
Figure 21. Chip Erase (CE) Sequence (Command 60 or C7)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
60 or C7
SI
Note: CE command is 60(hex) or C7(hex).
Figure 22. Deep Power-down (DP) Sequence (Command B9)
CS#
t
DP
0
1
2
3
4
5
6
7
SCLK
SI
Command
B9
Stand-by Mode
Deep Power-down Mode
Figure 23. Release from Deep Power-down and Read Electronic Signature (RES) Sequence (Command AB)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Command
AB
t
3 Dummy Bytes
RES2
SI
23 22 21
MSB
3
2
1
0
Electronic Signature Out
High-Z
7
6
5
4
3
2
0
1
SO
MSB
Deep Power-down Mode
Stand-by Mode
P/N: PM1480
REV. 1.1, JUL. 21, 2009
30
MX25L1025C
Figure 24. Release from Deep Power-down (RDP) Sequence (Command AB)
CS#
t
RES1
0
1
2
3
4
5
6
7
SCLK
Command
AB
SI
High-Z
SO
Deep Power-down Mode
Stand-by Mode
Figure 25. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)
CS#
0
1
2
3
4
5
6
7
8
9 10
SCLK
Command
90
2 Dummy Bytes
SI
15 14 13
3
2
1
0
High-Z
SO
CS#
47
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
ADD (1)
7
6
5
4
3
2
0
1
SI
Manufacturer ID
Device ID
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
X
SO
MSB
MSB
MSB
Notes:
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first
P/N: PM1480
REV. 1.1, JUL. 21, 2009
31
MX25L1025C
Figure 26. Power-up Timing
V
CC
V
(max)
CC
Chip Selection is Not Allowed
V
(min)
CC
tVSL
Device is fully
accessible
time
P/N: PM1480
REV. 1.1, JUL. 21, 2009
32
MX25L1025C
RECOMMENDED OPERATING CONDITIONS
At Device Power-Up
AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
VCC(min)
VCC
GND
tSHSL
tVR
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
SI
High Impedance
SO
Figure A. AC Timing at Device Power-Up
Symbol
tVR
Parameter
VCC Rise Time
Notes
Min.
0.5
Max.
500000
Unit
us/V
1
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
"AC CHARACTERISTICS" table.
P/N: PM1480
REV. 1.1, JUL. 21, 2009
33
MX25L1025C
ERASE AND PROGRAMMING PERFORMANCE
PARAMETER
Min.
TYP. (1)
Max. (2)
UNIT
ms
Write Status Register Cycle Time
Sector Erase Time
Block Erase Time
5
60
1
15
ms
2
2
5
s
Chip Erase Time
1
s
Page Program Time
Erase/Program Cycle
1.4
ms
100,000
cycles
Note:
1. Typical program and erase time assumes the following conditions: 25 C, 3.3V, and checker board pattern.
°
2. Under worst conditions of 85 C and 2.7V.
°
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming com-
mand.
LATCH-UP CHARACTERISTICS
MIN.
-1.0V
MAX.
12.5V
Input Voltage with respect to GND on ACC
Input Voltage with respect to GND on all power pins, SI, CS#
Input Voltage with respect to GND on SO
-1.0V
2 VCCmax
VCC + 1.0V
+100mA
-1.0V
Current
-100mA
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
P/N: PM1480
REV. 1.1, JUL. 21, 2009
34
MX25L1025C
ORDERING INFORMATION
OPERATING
CURRENT
MAX. (mA)
STANDBY
CURRENT
MAX. (uA)
CLOCK
(MHz)
PART NO.
TEMPERATURE PACKAGE
Remark
8-SOP
(150mil)
MX25L1025CMI-12G
85
12
10
-40~85 C
Pb-free
°
P/N: PM1480
REV. 1.1, JUL. 21, 2009
35
MX25L1025C
PART NAME DESCRIPTION
MX 25 L 1025C
M
I
12 G
OPTION:
G: Pb-free
SPEED:
12: 85MHz
TEMPERATURE RANGE:
I: Industrial (-40°C to 85°C)
PACKAGE:
M: 150mil 8-SOP
DENSITY & MODE:
1025C: 1Mb
TYPE:
L: 3V
DEVICE:
25: Serial Flash
P/N: PM1480
REV. 1.1, JUL. 21, 2009
36
MX25L1025C
PACKAGE INFORMATION
P/N: PM1480
REV. 1.1, JUL. 21, 2009
37
MX25L1025C
REVISION HISTORY
Revision No. Description
Page
P1
Date
MAY/14/2009
1.0
1. Removed "Preliminary" title
2. Added "Low Vcc write inhibit" voltage (VWI) parameter
1. Removed the loading description of fSCLK
2. Removed Sector Erase maximum timing
P20
P21
P1,21,34
1.1
JUL/21/2009
P/N: PM1480
REV. 1.1, JUL. 21, 2009
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MX25L1025C
Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which
the failure of a single component could cause death, personal injury, severe physical damage, or other substan-
tial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft
and military application. Macronix and its suppliers will not be liable to you and/or any third party for any claims,
injuries or damages that may be incurred due to use of Macronix's products in the prohibited applications.
Copyright© Macronix International Co., Ltd. 2009. All Rights Reserved. Macronix, MXIC, MXIC Logo, MX
Logo, are trademarks or registered trademarks of Macronix International Co., Ltd.. The names and brands
of other companies are for identification purposes only and may be claimed as the property of the respective
companies.
ACRONIX NTERNATIONAL O., TD.
M
I
C L
Macronix Offices : Japan
Macronix Asia Limited.
Macronix Offices : Taiwan
Headquarters, FAB2
Macronix, International Co., Ltd.
16, Li-Hsin Road, Science Park, Hsinchu,
Taiwan, R.O.C.
NKF Bldg. 5F, 1-2 Higashida-cho,
Kawasaki-ku Kawasaki-shi,
Kanagawa Pref. 210-0005, Japan
Tel: +81-44-246-9100
Tel: +886-3-5786688
Fax: +81-44-246-9105
Fax: +886-3-5632888
Taipei Office
Macronix Offices : Korea
Macronix Asia Limited.
#906, 9F, Kangnam Bldg., 1321-4, Seocho-Dong, Seocho-Ku,
135-070, Seoul, Korea
Tel: +82-02-588-6887
Fax: +82-02-588-6828
Macronix, International Co., Ltd.
19F, 4, Min-Chuan E. Road, Sec. 3, Taipei,
Taiwan, R.O.C.
Tel: +886-2-2509-3300
Fax: +886-2-2509-2200
Macronix Offices : China
Macronix Offices : Singapore
Macronix Pte. Ltd.
1 Marine Parade Central, #11-03 Parkway Centre,
Macronix (Hong Kong) Co., Limited.
702-703, 7/F, Building 9, Hong Kong Science Park,
5 Science Park West Avenue, Sha Tin,
N.T.
Tel: +86-852-2607-4289
Fax: +86-852-2607-4229
Singapore 449408
Tel: +65-6346-5505
Fax: +65-6348-8096
Macronix Offices : Europe
Macronix Europe N.V.
Koningin Astridlaan 59, Bus 1 1780
Macronix (Hong Kong) Co., Limited,
SuZhou Office
No.5, XingHai Rd, SuZhou Industrial Park,
SuZhou China 215021
Tel: +86-512-62580888 Ext: 3300
Fax: +86-512-62586799
Wemmel Belgium
Tel: +32-2-456-8020
Fax: +32-2-456-8021
Macronix Offices : USA
Macronix (Hong Kong) Co., Limited,
Shenzhen Office
Room 1401 & 1404, Blcok A, TianAN Hi-Tech PLAZA Tower,
Che Gong Miao, FutianDistrict, Shenzhen PRC 518040
Tel: +86-755-83433579
Macronix America, Inc.
680 North McCarthy Blvd. Milpitas, CA 95035,
U.S.A.
Tel: +1-408-262-8887
Fax: +1-408-262-8810
Fax: +86-755-83438078
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
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相关型号：
MX25L1026EM1I-10G
Flash, 512KX2, PDSO8, 0.150 INCH, HALOGEN FREE AND ROHS COMPLIANT, MS-012, SOP-8
Macronix
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