MX23L12824XI-12G [Macronix]
128M-BIT MASK ROM; 128M - BIT MASK ROM
| 型号： | MX23L12824XI-12G |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | 128M-BIT MASK ROM |
| 文件： | 总7页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX23L12824
128M-BIT MASK ROM
FEATURES
PIN DESCRIPTION
• Bit organization
Symbol
Pin Function
- 16Mb x 8 (byte mode)
- 8Mb x 16 (word mode)
• Fast access time
A0~A23
Address Inputs, A0 not used in
word mode
D0~D15
Data Outputs
- Random access:120/25ns(max.) in 3.0~3.6V
120/30ns(max.) in 2.7~3.6V
• Page size
CE0#,CE1#,CE2# Chip Enable Input
OE#
Output Enable Input
Word/Byte mode Selection
Power Supply Pin
Output VCC Pin
- 8 words per page
BYTE#
VCC
VCCQ
GND
NC
• Current
- Operating:50mA
- Standby:15uA(max.)
• Supply voltage
Ground Pin
- VCC : 2.7 ~ 3.6V
No Connection
- VCCQ : 2.7 ~ 3.6V
• Package
- 64 ball mini BGA (10.0mm X 13.0mm, ball pitch
1.0mm), Pb-free, RoHS compliant
• Temperature
--25~85°C
MODE SELECTION
CE#
OE#
X
BYTE#
D0~D15
D8~D15
Power
Stand-by
Active
Disabled
Enabled
Enabled
Enabled
X
X
L
High Z
High Z
D0~D7
D0~D7
HighZ
HighZ
HighZ
D8~D15
H
L
Active
L
H
Active
Chip Enable Truth Table
CE2#
CE1#
CE0#
DEVICE
L
L
L
Enabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Disabled
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
Note:For single-chip applications, CE2#, CE1# can be strapped to GND.
P/N:PM1063
REV. 1.3, NOV. 15, 2005
1
MX23L12824
PIN CONFIGURATION
64 Mini BGA (Top View, Ball Down)
A1
A1
A2
A6
A3
A8
A4
A5
A6
A7
A8
NC
A13
VCC
A18
A22
B1
A2
C1
A3
D1
A4
E1
D8
B2
GND
C2
A7
B3
A9
B4
CE0#
C4
B5
A14
C5
B6
NC
C6
NC
D6
NC
E6
B7
B8
CE1#
C8
A19
C7
C3
A10
D3
A11
E3
A12
D4
A15
D5
A20
D7
A21
D8
D2
A5
NC
E4
NC
E5
A16
E7
A17
13.0 mm
E8
E2
D1
D9
D3
D4
NC
D15
NC
F1
BYTE#
G1
F2
D0
G2
A0
H2
NC
F3
F4
D11
G4
F5
D12
G5
F6
F7
F8
D10
G3
NC
G6
NC
G7
D14
H7
OE#
G8
NC
H8
A23
D2
VCCQ
H4
D5
D6
H1
H3
H5
H6
CE2#
VCC
GND
D13
GND
D7
NC
10.0 mm
P/N:PM1063
REV. 1.3, NOV. 15, 2005
2
MX23L12824
ORDER INFORMATION
Part No.
Speed
Package
Grade
Remark
MX23L12824XI-12G
120ns
64 ball mini BGA
Industrial
Pb-free, RoHS compliant
ABSOLUTE MAXIMUM RATINGS
Item
Symbol
VIN
Ratings
Voltage on any Pin Relative to VSS
Ambient OperatingTemperature
Storage Temperature
-0.3V to 3.9V
-25°C to 85°C
-65°C to 125°C
Topr
Tstg
DC CHARACTERISTICS (Ta = -25°C ~ 85° C, VCC = 2.7V~3.6V)
Item
Symbol
VOH
VOL
VIH
MIN.
MAX.
-
Conditions
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Leakage Current
Output Leakage Current
Operating Current
2.4V
IOH = -400uA
IOL = 1.6mA
-
0.4V
2.2V
VCCQ+0.5V
0.8V
VIL
-0.5V
ILI
-
-
-
5uA
0V, VCC
ILO
5uA
0V, VCC
ICC
50mA
f=5MHz, CE#=VIL, OE#=VIH
all output open
Standby Current (CMOS)
Input Capacitance
ISTB
CIN
-
-
-
15uA
10pF
10pF
CE#>VCC-0.2V
Ta = 25° C, f = 1MHZ
Ta = 25° C, f = 1MHZ
Output Capacitance
COUT
AC CHARACTERISTICS (Ta = -25° C ~ 85° C, VCC = 2.7V~3.6V)
Item
Symbol
23L12824-12
MIN. MAX.
Read Cycle Time
tRC
tAA
120ns
-
Address Access Time
Chip Enable Access Time
Page Access Time
-
120ns
120ns
tACE
tPA
-
-
30ns (VCC=2.7~3.6V)
-
25ns (VCC=3.0~3.6V)
Output EnableTime
tOE
tOH
tHZ
-
30ns
-
Output Hold After Address
Output High Z Delay
0ns
-
20ns
Note:Output high-impedance delay (tHZ) is measured from OE# or CE# going high, and this parameter guaranteed
by design over the full voltage and temperature operating range - not tested.
P/N:PM1063
REV. 1.3, NOV. 15, 2005
3
MX23L12824
AC Test Conditions
Input Pulse Levels
0.4V~2.4V
Input Rise and Fall Times 5ns
IOH (load)=-400uA
Input Timing Level
Output Timing Level
Output Load
1.5V
DOUT
1.5V
See Figure
100pF output load
capacitance
IOL (load)=1.6mA
C<100pF
Note:No output loading is present in tester load board.
Active loading is used and under software programming control.
Output loading capacitance includes load board's and all stray capacitance.
TIMING DIAGRAM
RANDOM READ
ADD
ADD
tACE
ADD
ADD
tRC
CE#
OE#
tOE
tHZ
tOH
tAA
VALID
VALID
VALID
DATA
PAGE READ
A4-A23
VALID ADD
2'nd ADD
tPA
3'rd ADD
A0,A1,A2,A3
DATA
1'st ADD
tAA
VALID
VALID
VALID
Note: CE#, OE# are enable.
Page size is 8 words in 16-bit mode, 16 bytes in 8-bit mode.
P/N:PM1063
REV. 1.3, NOV. 15, 2005
4
MX23L12824
PACKAGE INFORMATION
P/N:PM1063
REV. 1.3, NOV. 15, 2005
5
MX23L12824
REVISION HISTORY
Revision No. Description
Page
P1,3
P1,3
P3
Date
1.1
1.2
1.3
1. Modify page access time from 30ns to 25ns
1. Added tPA:25ns in 3.0~3.6V
1.Added Pb-free package in order information
MAR/22/2004
APR/12/2004
NOV/15/2005
P/N:PM1063
REV. 1.3, NOV. 15, 2005
6
MX23L12824
MACRONIX INTERNATIONALCO., LTD.
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MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
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