MX23L12854 [Macronix]
128M-BIT Low Voltage, Serial Mask ROM Memory with 50MHz SPI Bus Interface; 128M位低电压，串行掩膜ROM的内存与50MHz的SPI总线接口
| 型号： | MX23L12854 |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | 128M-BIT Low Voltage, Serial Mask ROM Memory with 50MHz SPI Bus Interface |
| 文件： | 总18页 (文件大小：204K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX23L12854
128M-BIT Low Voltage, Serial Mask ROM Memory with
50MHz SPI Bus Interface
FEATURES
DESCRIPTION
TheMX23L12854isa128Mbit(16Mx8)SerialMaskROM
accessed by a high speed SPI-compatible bus.
•
•
•
•
128Mbit of Mask ROM
3.0 to 3.6V Single Supply Voltage
SPI Bus Compatible Serial Interface
50MHz Clock Rate (maximum)
PIN DESCRIPTION
PIN CONFIGURATIONS
16-PIN SOP (300 mil)
SYMBOL DESCRIPTION
C
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Hold
1
2
3
4
5
6
7
8
C
HOLD#
VCC
NC
16
15
14
13
12
11
10
9
D
D
Q
NC
NC
NC
NC
VSS
NC
S#
NC
HOLD#
VCC
VSS
NC
SupplyVoltage
Ground
NC
S#
Q
Note:
1.NC=NoConnection
2. See page 16 (onwards) for package dimensions, and
how to identify pin-1.
ORDER INFORMATION
Part No.
Speed
Package
Remark
MX23L12854MC-20G
20ns
16-SOP
Pb-free
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MX23L12854
MEMORY ORGANIZATION
The memory is organized as:
- 16M bytes (8 bits each)
BLOCK DIAGRAM
HOLD#
Control Logic
S#
C
D
Q
I/O Shift Register
Address Register
and Counter
512 Byte
Data Buffer
Size of the
read-only
memory area
X Decoder
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MX23L12854
SIGNAL DESCRIPTION
Serial Data Output (Q). This output signal is used to
transfer data serially out of the device. Data is shifted out
on the falling edge of Serial Clock (C).
device is deselected. Driving Chip Select (S#) Low ena-
bles the device, placing it in the active power mode.
After Power-up, a falling edge on Chip Select (S#) is
required prior to the start of any instruction.
SerialDataInput(D).Thisinputsignalisusedtotransfer
data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are
latched on the rising edge of Serial Clock (C).
Hold(HOLD#).TheHold(HOLD#)signalisusedtopause
any serial communications with the device without
deselecting the device.
Serial Clock (C). This input signal provides the timing of
the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising
edge of Serial Clock (C). Data on Serial Data Output (Q)
changes after the falling edge of Serial Clock (C).
DuringtheHoldcondition,theSerialDataOutput(Q)ishigh
impedance,andSerialDataInput(D)andSerialClock(C)
areDon'tCare.
To start the Hold condition, the device must be selected,
with Chip Select (S#) driven Low.
Chip Select (S#). When this input signal is High, the
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MX23L12854
SPI MODES
These devices can be driven by a microcontroller with its
SPIperipheralrunningineitherofthetwofollowingmodes:
the falling edge of Serial Clock (C).
Thedifferencebetweenthetwomodes,asshowninFigure
2, is the clock polarity when the bus master is in Stand-by
mode and not transferring data:
- CPOL=0, CPHA=0
- CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising
edgeofSerialClock(C), andoutputdataisavailablefrom
- C remains at 0 for (CPOL=0, CPHA=0)
- C remains at 1 for (CPOL=1, CPHA=1)
Figure 1. Bus Master and Memory Devices on the SPI Bus
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
C
Q
D
C
Q
D
C Q D
Bus Master
(ST6, ST7, ST9,
ST10, Others)
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CS3 CS2 CS1
S#
S#
S#
HOLD#
HOLD#
HOLD#
Note: 1. Hold (HOLD#) signals should be driven, High or Low as appropriate.
Figure 2. SPI Modes Supported
CPOL CPHA
C
C
0
1
0
1
D
MSB
Q
MSB
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MX23L12854
OPERATING FEATURES
ActivePower, Stand-byPower
The Hold condition starts on the falling edge of the Hold
(HOLD) signal, provided that this coincides with Serial
Clock (C) being Low (as shown in Figure 3).
When Chip Select (S#) is Low, the device is enabled, and
intheActivePowermode.WhenChipSelect(S#)isHigh,
the device is disabled, but could remain in the Active
Power mode until all internal cycles have completed. The
device then goes in to the Stand-by Power mode. The
device consumption drops to ICC1 .
The Hold condition ends on the rising edge of the Hold
(HOLD#) signal, provided that this coincides with Serial
Clock (C) being Low.
If the falling edge does not coincide with Serial Clock (C)
being Low, the Hold condition starts after Serial Clock (C)
next goes Low. Similarly, if the rising edge does not
coincide with Serial Clock (C) being Low, the Hold condi-
tion ends after Serial Clock (C) next goes Low. (This is
shown in Figure 2).
Protection Modes
Theenvironmentswherenon-volatilememorydevicesare
used can be very noisy. No SPI device can operate
correctly in the presence of excessive noise. To help
combat this, the MX23L12854 boasts the following data
protectionmechanisms:
During the Hold condition, the Serial Data Output (Q) is
highimpedance,andSerialDataInput(D)andSerialClock
(C)areDon'tCare.
-Power-OnResetandaninternaltimer(tPUW)canprovide
protection against inadvertant changes while the power
supply is outside the operating specification.
Normally, the device is kept selected, with Chip Select
(S#) driven Low, for the whole duration of the Hold condi-
tion. This is to ensure that the state of the internal logic
remainsunchangedfromthemomentofenteringtheHold
condition.
Hold Condition
The Hold (HOLD#) signal is used to pause any serial
communications with the device without resetting the
clocking sequence.
IfChipSelect(S#)goesHighwhilethedeviceisintheHold
condition, this has the effect of resetting the internal logic
of the device. To restart communication with the device,
it is necessary to drive Hold (HOLD#) High, and then to
driveChipSelect(S#)Low. Thispreventsthedevicefrom
going back to the Hold condition.
To enter the Hold condition, the device must be selected,
with Chip Select (S#) Low.
Figure 3. Hold Condition Activation (for data output only)
C
HOLD#
Q2
Q0
Q5
Q1
Q2 Q3
Q4
Q
C
HOLD#
Q
Q2
Q0
Q4 Q5
Q1
Q2
Q3
Q6
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MX23L12854
INSTRUCTIONS
All instructions, addresses and data are shifted inand out
of the device, most significant bit first.
Everyinstructionsequencestartswithaone-byteinstruc-
tion code. Depending on the instruction, this might be
followed by address bytes, or by data bytes, or by both or
none.
Serial Data Input (D) is sampled on the first rising edge of
SerialClock(C)afterChipSelect(S#)isdrivenLow.Then,
the one-byte instruction code must be shifted in to the
device, most significant bit first, on Serial Data Input (D),
each bit being latched on the rising edges of Serial Clock
(C).
In the case of a Read Data Bytes (READ), Read Data
BytesatHigherSpeed(Fast_Read), theshifted-ininstruc-
tion sequence is followed by a data-out sequence. Chip
Select(S#)canbedrivenHighafteranybitofthedata-out
sequence is being shifted out.
The instruction set is listed in Table 1.
Table 1. Instruction Set
Address Dummy
Data
Bytes
Instruction
Description
Read Data Bytes
One-byte Instruction Code
Bytes
Bytes
READ
0000 0011
0000 1011
03h
0Bh
3
3
0
1
1 to ∞
1 to ∞
FAST_READ Read Data Bytes at Higher Speed
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MX23L12854
Figure 4. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
S#
C
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
Instruction
24-Bit Address
23 22 21
MSB
3
2
1
0
D
Q
Data Out 1
Data Out 2
High Impedance
2
7
6
5
4
3
1
7
0
MSB
ReadDataBytes(READ)
ThedeviceisfirstselectedbydrivingChipSelect(S#)Low.
The instruction code for the Read Data Bytes (READ)
instructionisfollowedbya3-byteaddress(A23-A0),each
bit being latched-in during the rising edge of Serial Clock
(C). Then the memory contents, at that address, is shifted
outonSerialDataOutput(Q),eachbitbeingshiftedout,at
a maximum frequency fR, during the falling edge of Serial
Clock (C).
The instruction sequence is shown in Figure 4. The first
byte addressed can be at any location. The address is
automaticallyincrementedtothenexthigheraddressafter
each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ)
instruction.When the highest address is reached, the
address counter rolls over to 000000h, allowing the read
sequence to be continued indefinitely.
TheReadDataBytes(READ)instructionisterminatedby
driving Chip Select (S#) High. Chip Select (S#) can be
driven High at any time during data output.
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MX23L12854
Figure 5. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out
Sequence
S#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
C
Instruction
24 BIT ADDRESS
D
Q
23 22 21
3
2
1
0
High Impedance
S#
C
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Dummy Byte
7
6
5
4
3
2
0
1
D
Q
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
MSB
MSB
MSB
automaticallyincrementedtothenexthigheraddressafter
each byte of data is shifted out. The whole memory can,
therefore,bereadwithasingleReadDataBytesatHigher
Speed (FAST_READ) instruction. When the highest ad-
dressisreached,theaddresscounterrollsoverto000000h,
allowing the read sequence to be continued indefinitely.
ReadDataBytesatHigherSpeed(FAST_READ)
The device is first selected by driving Chip Select (S#)
Low. The instruction code for the Read Data Bytes at
HigherSpeed(FAST_READ)instructionisfollowedbya3-
byte address (A23-A0) and a dummy byte, each bit being
latched-in during the rising edge of Serial Clock (C). Then
the memory contents, at that address, is shifted out on
Serial Data Output (Q), each bit being shifted out, at a
maximum frequency fC, during the falling edge of Serial
Clock (C).
The Read Data Bytes at Higher Speed (FAST_READ)
instruction is terminated by driving Chip Select (S#) High.
ChipSelect(S#)canbedrivenHighatanytimeduringdata
output.
The instruction sequence is shown in Figure 5. The first
byte addressed can be at any location. The address is
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MX23L12854
POWER-UP AND POWER-DOWN
If the delay, tVSL, has elapsed, after VCC has risen
above VCC (min), the device can be selected for READ
instructions even if the tPUW delay is not yet fully
elapsed.
At Power-up and Power-down, the device must not be
selected (that is Chip Select (S#) must follow the voltage
applied on VCC ) until VCC reaches the correct value:
At Power-up, the device is in the following state:
- The device is in the Standby mode.
- VCC(min) at Power-up, and then for a further delay of
tVSL
- VSS at Power-down
Normal precautions must be taken for supply rail
decoupling, to stablise the VCC feed. Each device in a
systemshouldhavetheVCCraildecoupledbyasuitable
capacitor close to the package pins.
Usually a simple pull-up resistor on Chip Select (S#) can
be used to insure safe and proper Power-up and Power-
down.
Toavoiddatacorruptionandinadvertentwriteoperations
during power up, a Power On Reset (POR) circuit is
included. The logic inside the device is held reset while
VCC is less than the POR threshold value, VWI -- all
operationsaredisabled,andthedevicedoesnotrespond
to any instruction.
(Generally, this capacitor is of the order of 0.1uF).
At Power-down, when VCC drops from the operating
voltage, to below the POR threshold value, VWI , all
operationsaredisabledandthedevicedoesnotrespond
to any instruction.
These values are specified in Table 2.
Figure 6. Power-up Timing
V
CC
V
(max)
CC
Chip Selection Not Allowed
V
(min)
CC
tVSL
Read Access allowed
Device fully
accessible
Reset State
of the
Device
V
WI
tPUW
time
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MX23L12854
Table 2. Power-Up Timing
Symbol
Parameter
Min.
Max.
Unit
1
V
CC
(min) to S# low
30
us
tVSL
Note: 1. These parameters are characterized only.
MAXIMUM RATING
Stressingthedeviceabovetheratinglistedinthe"Absolute
MaximumRatings"tablemaycausepermanentdamageto
the device. These are stress ratings only and operation of
the device at these or any other conditions above those
indicated in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device reliability.
Table 3. Absolute Maximum Ratings
Symbol
Parameter
Min.
Max.
Unit
T
Storage Temperature
- 65
150
˚C
˚C
STG
1
2
TLEAD
VIO
Lead Temperature during Soldering
Input and Output Voltage (with respect to Ground)
Supply Voltage
260
- 0.6
- 0.6
4.0
4.0
V
V
V
V
CC
3
VESD
- 2000
2000
Electrostatic Discharge Voltage (Human Body model)
®
Note: 1. Compliant with the ECOPACK 7191395 specifiication for lead-free soldering processes
2. Not exceeding 250˚C for more than 30 seconds, and peaking at 260˚C
3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
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MX23L12854
DC AND AC PARAMETERS
tables that follow are derived from tests performed under
the Measurement Conditions summarized in the relevant
tables. Designers should check that the operating condi-
tions in their circuit match the measurement conditions
when relying on the quoted parameters.
Thissectionsummarizestheoperatingandmea-surement
conditions, and the DC and AC characteristics of the
device. The parameters in the DC and AC Characteristic
Table 4. Operating Conditions
Symbol
Parameter
Min.
Max.
Unit
V
Supply Voltage
Ambient Operating Temperature
CC
3.0
3.6
85
V
TA
- 40
˚C
Table 5. AC Measurement Conditions
Symbol
Parameter
Min.
Max.
Unit
pF
ns
V
C
Load Capacitance
30
L
Input Rise and Fall Times
Input Pulse Voltages
5
0.2V to 0.8V
CC
CC
CC
0.3V to 0.7V
Input Timing Reference Voltages
Output Timing Reference Voltages
V
CC
V
/ 2
V
CC
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 7. AC Measurement I/O Waveform
Input Levels
Input and Output
Timing Reference Levels
0.8V
0.2V
CC
CC
0.7V
CC
CC
0.3V
CC
0.5V
Table 6. Capacitance
Symbol
Parameter
Test Condition
= 0V
Min.
Max.
Unit
pF
COUT
CIN
Output Capacitance (Q)
V
8
6
OUT
Input Capacitance (other pins)
V
IN
= 0V
pF
Note: Sampled only, not 100% tested, at T =25˚C and a frequency of 20 MHz.
A
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MX23L12854
Table 7. DC Characteristics
Test Condition
(in addition to those in Table 8)
Symbol
Parameter
Min.
Max.
Unit
ILI
ILO
Input Leakage Current
Output Leakage Current
Standby Current
± 2
± 2
50
uA
uA
uA
ICC1
S# = VCC, VIN = VSS or VCC
C = 0.1VCC / 0.9.VCC at 50MHz,
Q = open
8
4
mA
mA
ICC2
Operating Current (READ)
C = 0.1VCC / 0.9.VCC at 20MHz,
Q = open
VIL
VIH
0.3VCC
Input Low Voltage
Input High Voltage
Output Low Voltage
- 0.5
V
V
V
0.7VCC
VCC+0.4
I
OL = 1.6mA
0.4
VOL
VOH
I
OH = -100 uA
VCC- 0.2
Output High Voltage
V
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MX23L12854
Table 8. AC Characteristics
Test conditions specified in Table 4 and Table 5
Symbol
Alt.
Parameter
Min.
Typ.
Max.
50
Unit
Clock Frequency for the following instructions:
FAST_READ
f
f
C
D.C.
MHz
C
f
Clock Frequency for READ instructions
Clock High Time
D.C.
9
20
MHz
ns
R
1
t
t
CLH
CH
1
t
Clock Low Time
9
ns
t
CLL
CL
2
2
3
0.1
0.1
V/ns
V/ns
t
t
Clock Rise Time (peak to peak)
CLCH
3
Clock Fall Time (peak to peak)
CHCL
t
t
t
S# Active Setup Time (relative to C)
S# Not Active Hold Time (relative to C)
Data In Setup Time
5
5
2
5
ns
ns
ns
ns
SLCH
CHSL
CSS
t
t
DVCH
CHDX
CHSH
SHCH
DSU
t
t
t
t
Data In Hold Time
DH
S# Active Hold Time (relative to C)
S# Not Active Setup Time (relative to C)
S# Deselect Time
5
ns
5
ns
ns
t
t
CSH
100
SHSL
2
t
Output Disable Time
8
8
ns
t
DIS
SHQZ
t
t
V
Clock Low to Output Valid
Output Hold Time
ns
ns
ns
CLQV
CLQX
HLCH
t
t
t
t
HO
0
5
HOLD# Setup Time (relative to C)
HOLD# Hold Time (relative to C)
HOLD Setup Time (relative to C)
HOLD Hold Time (relative to C)
HOLD to Output Low-Z
CHHH
HHCH
5
5
5
ns
ns
ns
t
t
CHHL
2
2
t
8
8
ns
ns
t
LZ
HHQX
t
HOLD# to Output High-Z
t
HZ
HLQZ
Note: 1. t + t must be greater than or equal to 1/ f
C
CH
CL
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
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MX23L12854
Figure 8. Serial Input Timing
tSHSL
tSHCH
tCHCL
S#
tCHSL
tSLCH
tCHSH
C
tDVCH
tCHDX
tCLCH
MSB IN
LSB IN
D
Q
High Impedance
Figure 9. Hold Timing
S#
tHLCH
tCHHL
tHHCH
C
Q
tCHHH
tHLQZ
tHHQX
D
HOLD#
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MX23L12854
Figure 10. Output Timing
S#
tCH
C
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
tCLQX
LSB OUT
D
Q
tQLQH
tQHQL
ADDR.LSB IN
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MX23L12854
PACKAGE INFORMATION
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MX23L12854
REVISION HISTORY
Revision Description
Page
P1
P1,11
Date
APR/06/2005
MAY/04/2005
1.0
1.1
1. Added "Order Information"
1. Changed VCC from "2.7V to 3.6V" to "3.0V to 3.6V"
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MX23L12854
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