MPQ8632-20 [MPS]
High Efficiency 18V Synchronous Step-down Converter Family for 4A to 20A; 高效率18V同步降压型转换器系列为4A至20A
| 型号： | MPQ8632-20 |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | High Efficiency 18V Synchronous Step-down Converter Family for 4A to 20A |
| 文件： | 总46页 (文件大小：1890K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MPQ8632
High Efficiency 18V Synchronous
Step-down Converter Family for 4A to 20A
FEATURES
Current
Rating (A)
Part Number
Input Voltage
OVP Mode
Low Input Voltage Range from 2.5V:
-- 2.5V to 18V with External 5V Bias
-- 4.5V to 18V with Internal Bias
Scalable Family of Products for 4A to 20A
Output Current Applications
-- 4A/6A/8A/10A/12A Share the Same
Footprint
--15A/20A Share the Same Footprint, with
Slight Change on Power Stage Section
from 4A/6A/8A/10A/12A
MPQ8632GLE-4
MPQ8632GLE-6
MPQ8632GLE-8
MPQ8632HGLE-10
MPQ8632GLE-10
4
6
2.5V to 18V
2.5V to 18V
2.5V to 18V
2.5V to 18V
2.5V to 18V
Non-Latch
Non-Latch
Non-Latch
Non-Latch
Latch-Off
8
10
10
12
2.5V to 18V
Non-Latch
MPQ8632GLE-12
15
20
2.5V to 18V
2.5V to 18V
Non-Latch
Non-Latch
MPQ8632GVE-15
MPQ8632GVE-20
Optimal Low RDS(ON) Internal Power
MOSFETs Per Device
Proprietary Switching Loss Reduction
Technique
Adaptive COT for Ultrafast Transient
Response
0.5% Reference Voltage Over 0C to
70C Junction Temperature Range
Programmable Soft Start Time
Pre-Bias Start up
DESCRIPTION
The MPQ8632 is a fully integrated high
frequency synchronous rectified step-down
switch mode converter. It offers a very compact
solution to achieve 4A/6A/8A/10A/12A/15A/20A
output current over a wide input supply range
with excellent load and line regulation.
The MPQ8632 uses Constant-On-Time (COT)
control mode to provide fast transient response
and ease loop stabilization.
Programmable Switching Frequency from
200kHz to 1MHz
Non-latch OCP, OVP and Thermal
Shutdown Protection
An external resistor programs the operating
frequency from 200kHz to 1MHz and the
frequency keeps nearly constant as input
supply
varies
with
the
feedforward
Output Adjustable from 0.611V to 13V
compensation.
The default under voltage lockout threshold is
internally set at 4.1V, but a resistor network on
the enable pin can increase this threshold. The
soft start pin controls the output voltage startup
ramp. An open drain power good signal
indicates that the output is within nominal
voltage range.
APPLICATIONS
Telecom and Networking Systems
Base Stations
Servers
Personal Video Recorders
Flat Panel Television and Monitors
Distributed Power Systems
It has fully integrated protection features that
include over-current protection, over-voltage
protection and thermal shutdown.
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
The MPQ8632 requires a minimal number of
readily available standard external components
and is available in a 16-Pin QFN 3mm×4mm or
a 29-Pin QFN 5mm×4mm package.
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
1
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
TYPICAL APPLICATION
VIN
BST
SW
IN
C3
L1
RFREQ
C1
C5
VOUT
FREQ
EN
C4
R4
R1
R2
C2
ON/OFF
MPQ8632
FB
SS
VCC
R3
C6
PG
PGND
AGND
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
2
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
ORDERING INFORMATION
Part Number
Package
Top Marking
MP8632
E4
MPQ8632GLE-4*
QFN(3X4mm)
MP8632
E6
MP8632
E8
MP8632
E10
MP8632H
E10
MP8632
E12
MP8632
E15
MP8632
E20
MPQ8632GLE-6
MPQ8632GLE-8
MPQ8632GLE-10
MPQ8632HGLE-10
MPQ8632GLE-12
MPQ8632GVE-15
MPQ8632GVE-20
QFN(3X4mm)
QFN(3X4mm)
QFN(3X4mm)
QFN(3X4mm)
QFN(3X4mm)
QFN(5X4mm)
QFN(5X4mm)
* For Tape & Reel, add suffix –Z (e.g. MPQ8632GLE–4–Z)
PACKAGE REFERENCE
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
EN
1
2
3
4
5
6
7
8
EN
FREQ
FREQ
FB
SS
FB
SS
AGND
PG
AGND
PG
VCC
BST
VCC
BST
Part Number*
Package
Part Number*
Package
MPQ8632GLE-4
QFN (3x4mm)
MPQ8632GLE-6
QFN (3x4mm)
Junction Temperature
Junction Temperature
Top Marking
Top Marking
MP8632
E4
MP8632
E6
–40C to +125C
–40C to +125C
* For Tape & Reel, add suffix –Z (eg. MPQ8632GLE-4–Z)
* For Tape & Reel, add suffix –Z (eg. MPQ8632GLE-6–Z)
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
3
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
EN
EN
FREQ
FREQ
FB
SS
FB
SS
AGND
PG
AGND
PG
VCC
BST
VCC
BST
Part Number*
Package
Part Number*
Package
MPQ8632GLE-8
QFN (3x4mm)
MPQ8632GLE-10
QFN (3x4mm)
Junction Temperature
Junction Temperature
Top Marking
Top Marking
MP8632
E8
MP8632
E10
–40C to +125C
–40C to +125C
* For Tape & Reel, add suffix –Z (eg. MPQ8632GLE-8–Z)
* For Tape & Reel, add suffix –Z (eg. MPQ8632GLE-10–Z)
TOP VIEW
TOP VIEW
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
EN
EN
FREQ
FREQ
FB
SS
FB
SS
AGND
PG
AGND
PG
VCC
BST
VCC
BST
Part Number*
Package
Part Number*
Package
MPQ8632HGLE-10
QFN (3x4mm)
MPQ8632GLE-12
QFN (3x4mm)
Junction Temperature
Junction Temperature
Top Marking
Top Marking
MP8632H
E10
MP8632
E12
–40C to +125C
–40C to +125C
* For Tape & Reel, add suffix –Z (eg. MPQ8632HGLE-10–Z) * For Tape & Reel, add suffix –Z (eg. MPQ8632GLE-12–Z)
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
4
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
TOP VIEW
TOP VIEW
EN
EN
1
2
3
4
20 PGND
1
2
3
4
20
19
18
PGND
PGND
SW
19
18
PGND
SW
FREQ
FREQ
FB
SS
FB
SS
17 SW
17 SW
SW
SW
SW
SW
5
6
7
16
15
5
6
7
16
15
AGND
PG
AGND
PG
14 PGND
14 PGND
VCC
BST
VCC
BST
8
13
8
13
PGND
PGND
Part Number*
Package
Part Number*
Package
MPQ8632GVE-15
QFN (5x4mm)
MPQ8632GVE-20
QFN (5x4mm)
Junction Temperature
Junction Temperature
Top Marking
Top Marking
MP8632
E15
MP8632
E20
–40C to +125C
–40C to +125C
* For Tape & Reel, add suffix –Z (eg. MPQ8632GVE-15–Z)
* For Tape & Reel, add suffix –Z (eg. MPQ8632GVE-20–Z)
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
5
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
ABSOLUTE MAXIMUM RATINGS (1)
Thermal Resistance (5)
θJA θJC
Supply Voltage VIN .......................................21V
VSW .......................................-0.3V to VIN + 0.3V
VSW (30ns) ..................................-3V to VIN + 3V
VBST .....................................................VSW + 6V
VBST (30ns)........................................VSW + 6.5V
Enable Current IEN(2)................................ 2.5mA
All Other Pins................................ –0.3V to +6V
QFN (3x4mm) ........................ 46....... 9.... C/W
QFN (5x4mm) ........................ 38....... 6.... C/W
Notes:
1) Exceeding these ratings may damage the device.
2) Refer to the section “Configuring the EN Control”.
3) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)-
TA)/θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
(3)
Continuous Power Dissipation (TA=+25)
QFN3X4……………………….…..…………2.7W
QFN5X4……………………….…..…………3.3W
Junction Temperature..............................150C
Lead Temperature ...................................260C
Storage Temperature...............-65C to +150C
4) The device is not guaranteed to function outside of its
operating conditions.
5) Measured on JESD51-7, 4-layer PCB.
Recommended Operating Conditions (4)
Supply Voltage VIN .......................... 4.5V to 18V
Output Voltage VOUT.................... 0.611V to 13V
Enable Current IEN...................................... 1mA
Operating Junction Temp. (TJ).-40°C to +125°C
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
6
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
ELECTRICAL CHARACTERISTICS
VIN = 12V, TJ = -40C to +125C, unless otherwise noted.
Parameters
Symbol
Condition
Min
Typ
Max
Units
Supply Current
Supply Current (Shutdown)
Supply Current (Quiescent)
MOSFET
IIN
IIN
VEN = 0V
0
1
μA
μA
VEN = 2V, VFB = 1V
700
860
1000
MPQ8632GLE-4,6,8,
TJ =25C
28
19.6
9.9
mΩ
mΩ
mΩ
MPQ8632GLE-10,12,
MPQ8632HGLE-10,
TJ =25C
High-side Switch On Resistance
HSRDS-ON
MPQ8632GVE-15,20,
TJ =25C
16.4
15.8
15.3
MPQ8632GLE-4, TJ =25C
MPQ8632GLE-6, TJ =25C
MPQ8632GLE-8, TJ =25C
MPQ8632GLE-10,
MPQ8632HGLE-10,
TJ =25C
Low-side Switch On Resistance
LSRDS-ON
5.7
mΩ
5.2
3
MPQ8632GLE-12, TJ =25C
MPQ8632GVE-15, TJ =25C
2.4
0
MPQ8632GVE-20, TJ =25C
Switch Leakage
SWLKG
VEN = 0V, VSW = 0V or 12V
10
μA
Current Limit
High-side Peak Current Limit
ILIMIT_PEAK
MPQ8632GLE-10
MPQ8632GLE-4
MPQ8632GLE-6
MPQ8632GLE-8
MPQ8632GLE-10
MPQ8632HGLE-10
MPQ8632GLE-12
MPQ8632GVE-15
MPQ8632GVE-20
13
4
17.3
5
21.6
6
A
6.5
8
7.5
10
11
13
15
20
25
8.5
12
9.5
10
12
15
20
12.5
16
Low-side Valley Current Limit(6)
ILIMIT_VALLEY
A
A
18
25
30
MPQ8632GVE-15
All other parts
-6.6
-4
-5.6
-2.5
-4.6
-1
Low-side Negative Current
Limit(6)
ILIMIT_NEGATIVE
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
7
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V, TJ = -40C to +125C, unless otherwise noted.
Parameters
Timer
Symbol Condition
Min
Typ
Max
Units
One-Shot On Time
Minimum On Time(6)
TON
RFREQ=453kΩ, VOUT=1.2V
250
30
ns
ns
TON_MIN
20
40
MPQ8632GLE-10
Other parts
50
100
360
150
420
Minimum Off Time(6)
TOFF_MIN
ns
200
Over-voltage and Under-voltage Protection
OVP Latch Threshold(6)
VOVP_LATCH MPQ8632GLE-10
127%
117%
130%
120%
133%
123%
VFB
VFB
VOVP_NON-
LATCH
OVP Non-latch Threshold
OVP Delay
UVP Threshold(6)
TOVP
2
μs
VUVP
47%
50%
53%
VFB
Reference And Soft Start
TJ = 0°C to +70°C
608
605
602
611
611
611
50
614
617
620
100
25
mV
mV
mV
nA
Reference Voltage
VREF
TJ = 0°C to +125°C
TJ = -40°C to +125°C
VFB = 611mV
Feedback Current
IFB
ISS
Soft Start Charging Current
VSS=0V
16
20
μA
Enable And UVLO
Enable Input Low Voltage
Enable Hysteresis
VILEN
1.1
1.3
250
0
1.5
V
VEN-HYS
mV
VEN = 2V
VEN = 0V
Enable Input Current
IEN
μA
0
VCC Regulator
VCC Under Voltage Lockout
Threshold Rising
VCCVth
3.8
V
VCC Under Voltage Lockout
Threshold Hysteresis
VCCHYS
VCC
500
mV
VCC Regulator
4.8
0.5
V
VCC Load Regulation
Icc=5mA
%
Power Good
Power Good Rising Threshold
Power Good Falling Threshold
Power Good Lower to High Delay
PGVth-Hi
PGVth-Lo
PGTd
87%
91%
80%
2.5
94%
12
VFB
VFB
ms
Power Good Sink Current
Capability
IOL
VOL=600mV
VPG = 3.3V
mA
nA
Power Good Leakage Current
IPG_LEAK
10
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
8
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V, TJ = -40C to +125C, unless otherwise noted.
Parameters
Symbol Condition
Min
Typ
Max
Units
Thermal Protection (6)
Thermal Shutdown
TSD
150
°C
°C
Thermal Shutdown Hysteresis
25
Note:
6) Guaranteed by design.
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
9
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
PIN FUNCTIONS
MPQ8632GLE-4, MPQ8632GLE-6,
MPQ8632HGLE-10, MPQ8632GLE-12
MPQ8632GLE-8,
MPQ8632GLE-10,
PIN #
Name
Description
Enable. Digital input that turns the regulator on or off. Drive EN high to turn on the
regulator, drive it low to turn it off. Connect EN to IN through a pull-up resistor or a
resistive voltage divider for automatic startup. Do not float this pin.
1
EN
Frequency Set. Require a resistor connected between FREQ and IN to set the
switching frequency. The input voltage and the resistor connected to the FREQ pin
determine the ON time. The connection to the IN pin provides line feed-forward and
stabilizes the frequency during input voltage’s variation.
2
3
FREQ
FB
Feedback. Connect to the tap of an external resistor divider from the output to GND
to set the output voltage. FB is also configured to realize over-voltage protection
(OVP) by monitoring output voltage. MPQ8632 and MPQ8632H provide different
OVP mode. Please refer to the section “Over-Voltage-Protection (OVP)”. Place the
resistor divider as close to FB pin as possible. Avoid using vias on the FB traces.
Soft Start. Connect an external capacitor to program the soft start time for the
switch mode regulator.
4
5
SS
AGND
Analog ground. The control circuit reference.
Power Good. The output is an open drain signal. Require a pull-up resistor to a DC
voltage to indicate high if the output voltage exceeds 91% of the nominal voltage.
There is a delay from FB ≥ 91% to PG goes high.
6
PG
Internal 4.8V LDO Output. Power the driver and control circuits. 5V external bias
can disable the internal LDO. Decouple with a ≥ 1µF ceramic capacitor as close to
the pin as possible. For best results, use X7R or X5R dielectric ceramic capacitors
for their stable temperature characteristics.
7
VCC
BST
IN
Bootstrap. Require a capacitor connected between SW and BST pins to form a
floating supply across the high-side switch driver.
8
Supply Voltage. Supply power to the internal MOSFET and regulator. The
MPQ8632 operates from a +2.5V to +18V input rail with 5V external bias and a
+4.5V to +18V input rail with internal bias. Require an input decoupling capacitor.
Connect using wide PCB traces and multiple vias.
9, 14
10-13
System Ground. Reference ground of the regulated output voltage. PCB layout
requires extra care. Connect using wide PCB traces.
PGND
Switch Output. Connect to the inductor and bootstrap capacitor. The high-side
switch drives the pin up to the VIN during the PWM duty cycle’s ON time. The
inductor current drives the SW pin negative during the OFF-time. The low-side
switch’s ON-resistance and the internal Schottky diode clamp the negative voltage.
Connect using wide PCB traces.
15, 16
SW
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
10
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
MPQ8632GVE-15, MPQ8632GVE-20
PIN #
Name Description
Enable. Digital input that turns the regulator on or off. Drive EN high to turn on the
1
EN
regulator; drive it low to turn it off. Connect EN to IN through a pull-up resistor or a
resistive voltage divider for automatic startup. Do not float this pin.
Frequency Set. Require a resistor connected between FREQ and IN to set the
switching frequency. The input voltage and the resistor connected to the FREQ pin
determine the ON time. The connection to the IN pin provides line feed-forward and
stabilizes the frequency during input voltage’s variation.
2
3
FREQ
Feedback. Connect to the tap of an external resistor divider from the output to GND
to set the output voltage. Place the resistor divider as close to FB pin as possible.
Avoid using vias on the FB traces.
FB
SS
Soft-Start. Connect an external capacitor to program the soft start time for the switch
mode regulator.
4
5
AGND Analog Ground. The control circuit reference.
Power-Good. The output is an open drain signal. Requires a pull-up resistor to a DC
6
PG
voltage to indicate HIGH if the output voltage exceeds 91% of the nominal voltage.
There is a delay from FB ≥ 91% to when PG goes high.
Internal 4.8V LDO Output. Powers the driver and control circuits. 5V external bias
can disable the internal LDO. Decouple with a ≥1µF ceramic capacitor as close to the
pin as possible. For best results, use X7R or X5R dielectric ceramic capacitors for
their stable temperature characteristics.
7
8
VCC
BST
Bootstrap. Require a capacitor connected between SW and BST pins to form a
floating supply across the high-side switch driver.
Switch Output. Connect to the inductor and bootstrap capacitor. The high-side switch
drives these pins up to VIN during the PWM duty cycle’s ON time. The inductor
current drives the SW pin negative during the OFF-time. The low-side switch’s ON-
resistance and the internal Schottky diode holds the negative voltage. Connect all
SW pins using wide PCB traces.
15-18,
25-29
SW
System Ground. Reference ground of the regulated output voltage. PCB layout
requires extra care. Connect using wide PCB traces.
10-14, 19-23
9, 24
PGND
IN
Supply Voltage. Supplies power to the internal MOSFET and regulator. The
MPQ8632GVE operate from a 4.5V-to-18V input rail. If 5V external bias is tied to
VCC pin, the input voltage can be low as 2.5V. Requires an input decoupling
capacitor. Connect using wide PCB traces and multiple vias.
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
11
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
TYPICAL CHARACTERISTICS
MPQ8632GLE-10, VIN = 12V, VOUT = 1V, L = 1µH, TA = 25ºC, unless otherwise noted.
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
12
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
TYPICAL CHARACTERISTICS (continued)
MPQ8632GLE-10, VIN = 12V, VOUT = 1V, L = 1µH, TA = 25ºC, unless otherwise noted.
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
13
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
MPQ8632GLE-10, VIN = 12V, VOUT = 1V, L = 1µH, TA = 25ºC, unless otherwise noted.
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
14
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
MPQ8632GLE-10, VIN=12V, VOUT =1V, L=1µH, TA=+25°C, unless otherwise noted.
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
15
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
MPQ8632GLE-10, VIN=12V, VOUT =1V, L=1µH, TA=+25°C, unless otherwise noted.
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MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
MPQ8632GLE-10, VIN=12V, VOUT =1V, L=1µH, TA=+25°C, unless otherwise noted.
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MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
BLOCK DIAGRAM
IN
FREQ
VCC
LDO
VCC
BST
BIAS
BST
Minimum
OFF Timer
REFERENCE
EN
SS
ON
HS
HS-FET
Timer
Driver
LOGIC
SW
SOFT START
VCC
FB
PG
LS
Driver
LS-FET
FB
Comparator
ZCD
Current
Modulator
UV
GND
UV Detect
Comparator
PGOOD
Comparator
LS Current
Limit
AGND
OV
OV Detect
Comparator
Figure 1—Functional Block Diagram
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MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
OPERATION
PWM Operation
interval determined by the one- shot on-timer as
per equation 1. When the HS-FET turns off, the
LS-FET turns on until the next period.
The MPQ8632 is a fully integrated synchronous
rectified step-down switch mode converter. It
uses Constant-on-time (COT) control to provide a
fast transient response and ease loop
stabilization.
In CCM operation, the switching frequency is
fairly constant and is also called PWM mode.
Light-Load Operation
As the load decreases, the inductor current
decreases too. When the inductor current
touches zero, the operation is transited from
At the beginning of each cycle, the high-side
MOSFET (HS-FET) turns ON when the feedback
voltage (VFB) drops below the reference voltage
(VREF), which indicates an insufficient output
voltage. The input voltage and the frequency-set
resistor determine the ON period as follows:
continuous-conduction-mode
(CCM)
to
discontinuous-conduction-mode (DCM).
Figure 3 shows the light load operation. When
VFB drops below VREF, HS-FET turns on for a
fixed interval determined by the one- shot on-
timer as per equation 1. When the HS-FET turns
off, the LS-FET turns on until the inductor current
reaches zero. In DCM operation, the VFB does
not reach VREF when the inductor current is
approaching zero. The LS-FET driver turns into
tri-state (high Z) whenever the inductor current
reaches zero. A current modulator takes over the
control of LS-FET and limits the inductor current
less than -1mA. Hence, the output capacitors
discharge slowly to GND through LS-FET. As a
result, this mode improves greatly the light load
efficiency. At light load condition, the HS-FET
does not turns ON as frequently as at heavy load
condition. This is called skip mode.
6.1RFREQ(k)
(1)
TON(ns)
V (V) 0.4
IN
After the ON period elapses, the HS-FET turns
off. It turns ON again when VFB drops below VREF
.
By repeating this operation, the converter
regulates the output voltage. The integrated low-
side MOSFET (LS-FET) turns on when the HS-
FET is OFF to minimize the conduction loss.
There is a dead short (or shoot-through)
between input and GND if both HS-FET and LS-
FET turn on at the same time. A dead-time (DT)
internally generated between HS-FET OFF and
LS-FETON, or LS-FET OFF and HS-FET ON
avoids shoot-through.
Heavy-Load Operation
At light load or no load condition, the output
drops very slowly and the MPQ8632 reduces the
switching frequency naturally and then achieves
high efficiency at light load.
Figure 3—Light Load Operation
Figure 2—Heavy Load Operation
When the output current is high and the inductor
current is always above zero amps, it is called
continuous-conduction-mode (CCM). Figure 2
shows the CCM operation. When VFB is below
VREF
,
HS-FET turns on for
a
fixed
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MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
As the output current increases from the light
high switching frequencies allow for physically
smaller LC filter components to reduce the PCB
footprint.
load condition, the current modulator regulates
the operating period that becomes shorter. The
HS-FET turns ON more frequently. Hence, the
switching frequency increases correspondingly.
The output current reaches the critical level when
the current modulator time decreases to zero.
Determine the critical output current level as
follows:
Jitter and FB Ramp Slope
Figure 4 and Figure 5 show jitter occurring in
both PWM mode and skip mode. When there is
noise on the VFB descending slope, the HS-FET
ON time deviates from its intended point and
produces jitter and influences system stability.
The VFB ripple’s slope steepness dominates the
noise immunity though its magnitude has no
direct effect.
(V VOUT ) VOUT
IN
(2)
IOUT
2LFSW V
IN
Where FSW is the switching frequency.
The IC turns into PWM mode once the output
current exceeds the critical level. After that, the
switching frequency stays fairly constant over the
output current range.
Switching Frequency
Selecting the switching frequency requires
trading off between efficiency and component
size. Low frequency operation increases
efficiency by reducing MOSFET switching losses,
but requires larger inductor and capacitor values
to minimize the output voltage ripple.
Figure 4—Jitter in PWM Mode
For MPQ8632，set the on time using the FREQ
pin to set the frequency for steady state
operation at CCM.
The MPQ8632 uses adaptive constant-on-time
(COT) control, though the IC lacks a dedicated
oscillator. Connect the FREQ pin to the IN pin
through the resistor (RFREQ) so that the input
voltage is feed-forwarded to the one-shot on-time
timer. When operating in steady state at CCM,
the duty ratio stays at VOUT/VIN, so the switching
frequency is fairly constant over the input voltage
range. Set the switching frequency as follows:
Figure 5—Jitter in Skip Mode
Ramp with a Large ESR Capacitor
Using POSCAPs or other large-ESR capacitors
as the output capacitor results in the ESR ripple
dominating the output ripple. The ESR also
significantly influences the VFB slope. Figure 6
shows the simplified equivalent circuit in PWM
mode with the HS-FET off and without an
external ramp circuit.
106
(3)
FSW (kHz)
6.1RFREQ(k)
V (V)
IN
TDELAY (ns)
V (V) 0.4
VOUT (V)
IN
Where TDELAY is the comparator delay of about
5ns.
Typically, the MPQ8632 is set to 200kHz to
1MHz applications. It is optimized to operate at
high switching frequencies at high efficiency:
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MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
Where:
SW
FB
L
VOUT
(6)
(7)
IR4 IC4 IFB IC4
ESR
POSCAP
R1
R2
Then estimate the ramp on VFB as:
VIN VOUT
R4 C4
R1//R2
VRAMP
TON
R1//R2 R9
The VFB ripple’s descending slope then follows:
Figure 6—Simplified Circuit in PWM Mode
without External Ramp Compensation
VRAMP
TOFF
VOUT
R4C4
(8)
VSLOPE1
To realize the stability without an external ramp,
usually select the ESR value as follows:
Equation 8 shows that if there is instability in
PWM mode, reduce either R4 or C4. If C4 is
irreducible due to equation 5 limitations, then
reduce R4. For a stable PWM operation, design
Vslope1 based on equation 9.
TSW
TON
2
0.7
(4)
RESR
COUT
TSW
TON
2
2LCOUT
Where TSW is the switching period.
RESR COUT
IOUT 103
TSW TON
0.7
(9)
VSLOPE1
VOUT
Ramp with a Small ESR Capacitor
Use an external ramp when using ceramic output
capacitors, because the ESR ripple is not high
enough to stabilize the system.
Where IOUT is the load current.
In skip mode, The VFB ripple’s descending slope
is almost same whether the external ramp is
used or not. Figure 8 shows the simplified circuit
in skip mode when both the HS-FET and LS-FET
are off.
L
VOUT
SW
R4 C4
R1
R2
IR4
IC4
VOUT
R9
IFB
Ceramic
R1
FB
FB
ROUT
COUT
R2
Figure 7—Simplified Circuit in PWM Mode
with External Ramp Compensation
Figure 8—Simplified Circuit in skip Mode
Figure 7 shows the simplified circuit in PWM
mode with the HS-FET OFF and an external
ramp compensation circuit (R4, C4). Design the
external ramp based on the inductor ripple
current. Select C4, R9, R1 and R2 to meet the
following condition:
Determine the VFB ripple’s descending slope in
skip mode as follows:
VREF
[(R1R2) // ROUT ]COUT
(10)
VSLOPE2
Where ROUT is the equivalent load resistor.
1
1
5
R1R2
R1R2
Figure 5 shows that VSLOPE2 in skip mode is lower
than that is in PWM mode, so it is
(5)
R9
2FSW C4
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MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
reasonable that the jitter in skip mode is larger
A typical pull-up resistor is 100kΩ.
To achieve less jitter during ultra light load
condition, reduce R1 and R2, but that will
decrease the light load efficiency.
External VCC bias
An external 5V VCC bias can disable the internal
LDO, in this case, Vin can be as low as 2.5V.
Configuring the EN Control
Soft Start
The regulator turns on when En goes high;
conversely it turns off when EN goes low. Do not
float the pin.
The MPQ8632 employs a soft start (SS)
mechanism to ensure a smooth output during
power-up. When the EN pin goes high, an
internal current source (20μA) charges the SS
capacitor. The SS capacitor voltage takes over
the REF voltage to the PWM comparator. The
output voltage smoothly ramps up with the SS
voltage. Once the SS voltage reaches the REF
voltage, it continues ramping up while VREF takes
over the PWM comparator. At this point, soft start
finishes and the device enters steady state
operation.
For automatic start-up, pull the EN pin up to input
voltage through a resistive voltage divider.
Choose the values of the pull-up resistor (RUP
from the IN pin to the EN pin) and the pull-down
resistor (RDOWN from the EN pin to GND) to
determine the automatic start-up voltage:
(RUP RDOWN
)
(11)
V
1.5
(V)
INSTART
RDOWN
For example, for RUP=100kΩ and RDOWN=51kΩ,
the VIN-START is set at 4.44V.
Determine the SS capacitor value as follows:
TSS ms I A
SS
To reduce noise, add a 10nF ceramic capacitor
from EN to GND.
(14)
CSS nF
VREF
V
An internal zener diode on the EN pin clamps the
EN pin voltage to prevent run away. The
maximum pull up current assuming the worst
case 6V for the internal zener clamp should be
less than 1mA.
If the output capacitors are large, then avoid
setting a short SS time or risk hitting the current
limit during SS. Use a minimum value of 4.7nF if
the output capacitance value exceeds 330μF.
Pre-Bias Startup
Therefore, when driving EN with an external logic
signal, use an EN voltage less than 6V. When
connecting EN to IN through a pull-up resistor or
a resistive voltage divider, select a resistance
that ensures a maximum pull-up current less than
1mA.
The MPQ8632 has been designed for monotonic
startup into pre-biased loads. If the output is pre-
biased to a certain voltage during startup, the IC
will disable switching for both high-side and low-
side switches until the voltage on the soft-start
capacitor exceeds the sensed output voltage at
the FB pin.
If using a resistive voltage divider and VIN
exceeds 6V, then the minimum resistance for the
pull-up resistor RUP should meet:
Power Good (PG)
The MPQ8632 has a power-good (PG) output.
The PG pin is the open drain of a MOSFET.
Connect it to VCC or some other voltage source
that measures less than 5.5V through a pull-up
resistor (typically 100kΩ). After applying the input
voltage, the MOSFET turns on so that the PG pin
is pulled to GND before the SS is ready. After the
FB voltage reaches 91% of the REF voltage, the
PG pin is pulled high after a 2.5ms delay.
V 6V
6V
IN
(12)
1mA
RUP
RDOWN
With only RUP (the pull-down resistor, RDOWN, is
not connected), then the VCC UVLO threshold
determines VIN-START, so the minimum resistor
value is:
V 6V
IN
(13)
RUP
()
1mA
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MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
soft-start capacitor and then automatically retries
When the FB voltage drops to 80% of the REF
voltage or exceeds 120% of the nominal REF
voltage, the PG pin is pulled low.
soft-start. If the over-current condition still holds
after soft-start ends, the device repeats this
operation cycle until the over-current conditions
disappear and then output rises back to
regulation level. OCP offers non-latch protection.
If the input supply fails to power the MPQ8632,
the PG pin is also pulled low even though this pin
is tied to an external DC source through a pull-up
resistor (typically 100kΩ).
Low-Side Negative Current Limit: If the sensed
LS-FET negative current exceeds the negative
current limit, the LS-FET turns off immediately
and stays OFF for the remainder of the OFF
period. In this situation, both MOSFETs are OFF
until the end of a fixed interval. The HS-FET body
diode conducts the inductor current for the fixed
time.
Over-Current Protection (OCP)
The MPQ8632 features three current limit levels
for over-current conditions: high-side peak
current limit, low-side valley current limit and low-
side negative current limit.
However, the OCP operation mechanism of
MPQ8632GL-10 is different from other parts in
this family.
Over -Voltage Protection (OVP)
The MPQ8632 monitors the output voltage using
the FB pin connected to the tap of a resistor
divider to detect over-voltage. MPQ8632 and
MPQ8632H provide non-latch and latch off OVP
mode as showed in Table 1.
For MPQ8632GLE-10:
High-Side Peak Current Limit: The part has a
cycle-by-cycle over-current limiting function. The
device monitors the inductor current during the
HS-FET ON state. When the sensed inductor
current hits the peak current limit, the output
over-current comparator goes high, the device
enters OCP mode immediately and turns off the
HS-FET and turns on the LS-FET.
Table 1—OVP Mode
OVP Mode
Non-Latch Mode
MPQ8632-4
Latch-Off Mode
MPQ8632-6
MPQ8632-8
Part #
MPQ8632H-10
MPQ8632-12
MPQ8632-15
MPQ8632-20
MPQ8632-10
Low-Side Valley Current Limit: The device also
monitors the inductor current during the LS-FET
ON state. When ILIM=1 and at the end of the
OFF time, the LS-FET sourcing current is
compared to the internal positive-valley–current
limit. If the valley current limit is less than the LS-
FET sourcing current, the HS-FET remains OFF
and the LS-FET remains ON for the next ON time.
When the LS-FET sourcing current drops below
the valley current limit, the HS-FET turns on
again.
For MPQ8632GLE-10:
If the FB voltage exceeds the nominal REF
voltage but remains lower than 120% of the REF
voltage (0.611V), both MOSFETs are off.
If the FB voltage exceeds 120% of the REF
voltage but remains below 130%, the LS-FET
turns on while the HS-FET remains off. The LS-
FET remains on until the FB voltage drops below
110% of the REF voltage or the low-side
negative current limit is hit.
For other parts except MPQ8632GLE-10:
These parts enter OCP mode if only the LS-FET
sourcing valley current exceeds the valley current
limit. Once the OCP is triggered, the LS-FET
keeps ON state until the LS-FET sourcing valley
current is less than the valley current limit. And
then the LS-FET turns off, the HS-FET turns on
for a fixed time determined by frequency-set
resistor RFREQ and input voltage.
If the FB voltage exceeds 130% of the REF
voltage, then the device is latched off. Need
cycle the input power supply or EN to restart.
During OCP, the device tries to recover from the
over-current fault with hiccup mode: the chip
disables the output power stage, discharges the
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MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
Thermal Shutdown
For other parts except MPQ8632GLE-10:
The MPQ8632 has thermal shutdown. The IC
internally monitors the junction temperature. If
the junction temperature exceeds the threshold
value (minimum 150ºC), the converter shuts off.
This is a non-latch protection. There is about
25ºC hysteresis. Once the junction temperature
drops to about 125ºC, it initiates a soft startup.
Even the FB voltage exceeds 130% of the REF
voltage, these parts enter a non-latch off mode.
Once the FB voltage comes back to the
reasonable value, they will exit this OVP mode
and operate normally again.
UVLO protection
The MPQ8632 has under-voltage lock-out
protection (UVLO). When the VCC voltage
exceeds the UVLO rising threshold voltage, the
MPQ8632 powers up. It shuts off when the VCC
voltage falls below the UVLO falling threshold
voltage. This is non-latch protection.
The MPQ8632 is disabled when the VCC voltage
falls below 3.3 V. If an application requires a
higher UVLO threshold, use the two external
resistors connected to the EN pin as shown in
Figure 9 to adjust the startup input voltage. For
best results, use the enable resistors to set the
input voltage falling threshold (VSTOP) above 3.6 V.
Set the rising threshold (VSTART) to provide
enough hysteresis to account for any input
supply variations.
IN
RUP
EN Comparator
EN
RDOWN
Figure 9—Adjustable UVLO Threshold
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MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
APPLICATION INFORMATION
Setting the Output Voltage-Large ESR
Capacitors
to the FB pin consisting of R4 and C4.The ramp
voltage, VRAMP, and the resistor divider influence
the output voltage as shown in Figure 11.
Calculate VRAMP as shown in equation 7. Select
R2 to balance between high quiescent current
loss and FB noise sensitivity. Choose R2 within
5kΩ to 50kΩ, using a larger R2 when VOUT is low,
and a smaller R2 when VOUT is high. Determine
the value of R1 as follows:
For applications that electrolytic capacitor or POS
capacitor with a large ESR is set as output
capacitors. The feedback resistors—R1 and R2
as shown in Figure 10—set the output voltage.
SW
L
VOUT
FB
R2
ESR
POSCAP
R1
R2
(16)
R1
VFB(AVG)
R2
VOUT VFB(AVG) R4 R9
Where VFB(AVG) is the average FB voltage. VFB(AVG)
varies with the VIN, VOUT, and load condition,
where the load regulation is strictly related to the
VFB(AVG). Also the line regulation is related to the
VFB(AVG); improving the load or line regulation
involves a lower VRAMP that meets equation 9.
Figure10—Simplified POSCAP Circuit
First, choose a value for R2 that balances
between high quiescent current loss (low R2) and
high noise sensitivity on FB (high R2). A typical
value falls within 5kΩ to 50kΩ, using a
comparatively larger R2 when VOUT is low, and a
smaller R2 when VOUT is high. Then calculate R1
as follows, which considers the output ripple:
For PWM operation, estimate VFB(AVG) from
equation 17.
1
2
R1//R2
(17)
VFB(AVG) VREF
VRAMP
R1//R2 R9
1
Usually, R9 is 0Ω, though it can also be set
following equation 18 for better noise immunity. It
should also be less than 20% of R1//R2 to
VOUT VOUT VREF
2
(15)
R1
R2
VREF
minimize its influence on VRAMP
.
Where VOUT is the output ripple determined by
1 R1R2
equation 24.
(18)
R9
5 R1 R2
Setting the Output Voltage-Small ESR
Capacitors
Using equations 16 and 17 to calculate the
output voltage can be complicated. To simplify
the R1 calculation in equation 16, add a DC-
blocking capacitor, CDC, to filter the DC influence
from R4 and R9. Figure 12 shows a simplified
circuit with external ramp compensation and a
DC-blocking capacitor. The addition of this
capacitor, simplifies the R1 calculation as per
equation 19 for PWM mode operation.
SW
L
VOUT
R4
C4
R9
R1
R2
FB
Ceramic
Figure11—Simplified Ceramic Capacitor
Circuit
When using a low ESR ceramic capacitor on the
output, add an external voltage ramp
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MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
The worst-case condition occurs at VIN = 2VOUT
where:
,
1
2
VOUT VREF
VRAMP
(19)
R1
R2
1
2
IOUT
VREF
VRAMP
ICIN
(21)
2
For best results, select a CDC Value at least 10×
C4 for better DC blocking performance, but
smaller than 0.47µF account for start-up
performance. To use a larger CDC for better FB
noise immunity, reduce R1 and R2 to limit effects
on system start-up. Note that even with Cdc, the
For simplification, choose an input capacitor with
an RMS current rating that exceeds half the
maximum load current.
The input capacitance value determines the
converter input voltage ripple. Select a capacitor
value that meets any input voltage ripple
requirements.
load and line regulation are still related to VRAMP
.
SW
L
VOUT
Estimate the input voltage ripple as follows:
IOUT
VOUT
VOUT
(22)
V
(1
)
R4
C4
CDC
IN
FB
R1
R2
FSW CIN
V
V
IN
IN
Ceramic
The worst-case condition occurs at VIN = 2VOUT
where:
,
IOUT
4 FSW CIN
1
(23)
V
IN
Figure12—Simplified Ceramic Capacitor
Circuit with DC Blocking Capacitor
Output Capacitor
Input Capacitor
The output capacitor maintains the DC output
voltage. Use ceramic capacitors or POSCAPs.
Estimate the output voltage ripple as:
The input current to the step-down converter is
discontinuous, and therefore, requires
a
capacitor to supply the AC current to the step-
down converter while maintaining the DC input
voltage. Use ceramic capacitors for best
performance. During layout, Place the input
capacitors as close to the IN pin as possible.
VOUT
V
1
VOUT
(1 OUT )(RESR
)
FSW L
V
8FSW COUT
IN
(24)
When using ceramic capacitors, the capacitance
dominates the impedance at the switching
frequency. The capacitance also dominates the
output voltage ripple. For simplification, estimate
the output voltage ripple as:
The capacitance can vary significantly with
temperature. Use capacitors with X5R and X7R
ceramic dielectrics because they are fairly stable
over a wide temperature range.
VOUT
VOUT
(25)
The capacitors must also have a ripple current
rating that exceeds the converter’s maximum
input ripple current. Estimate the input ripple
current as follows:
VOUT
(1
)
8FSW2 L COUT
V
IN
The ESR only contributes minimally to the output
voltage ripple, thus requiring an external ramp to
stabilize the system. Design the external ramp
with R4 and C4 as per equation 5, 8 and 9.
VOUT
VOUT
(20)
ICIN IOUT
(1
)
V
V
IN
IN
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MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
The ESR dominates the switching-frequency
to 40% of the maximum switch current limit. Also,
design for a peak inductor current that is below
the maximum switch current limit. Calculate the
inductance value as:
impedance for POSCAPs,. The ESR ramp
voltage is high enough to stabilize the system.
thus eliminating the need for an external ramp.
Select a minimum ESR value around 12mΩ to
ensure stable operation. For simplification, the
output ripple can be approximated as:
VOUT
VOUT
(27)
L
(1
)
FSW IL
V
IN
Where ΔIL is the peak-to-peak inductor ripple
current.
VOUT
V
(1 OUT )RESR
(26)
VOUT
FSW L
V
IN
Choose an inductor that will not saturate under
the maximum inductor peak current. The peak
inductor current can be calculated as:
Inductor
The inductor supplies constant current to the
output load while being driven by the switching
input voltage. A larger value inductor results in
less ripple current and lower output ripple voltage,
but is larger physical size, has a higher series
resistance, and/or lower saturation current.
Generally, select an inductor value that allows
the inductor peak-to-peak ripple current to 30%
VOUT
VOUT
(28)
ILP IOUT
(1
)
2FSW L
V
IN
Table 2 lists a few highly-recommended high-
efficiency inductors.
Table 2—Inductor Selection Guide
Switching
Frequency
(kHz)
Inductance DCR
Current
Dimensions
Part Number
Manufacturer
(µH)
(mΩ) Rating (A) L x W x H (mm3)
744325072
FDU1250C-1R0M
FDA1055-1R5M
744325180
FDA1055-2R2M
FDA1055-3R3M
HC7-3R9-R
Wurth
TOKO
TOKO
Wurth
TOKO
TOKO
Cooper
0.72
1
1.5
1.8
2.2
3.3
3.9
1.35
1.72
2.8
35
31.3
24
10.2 x 10.5 x 4.7
13.3 x 12.1 x 5
11.6 x 10.8 x 5.5
10.2 x 10.5 x 4.7
11.6 x 10.8 x 5.5
11.6 x 10.8 x 5.5
13.8 x 13 x 5.5
500
500
500
500
500
500
500
3.5
18
3.94
5.92
7.9
20.6
15.6
10.6
Table 3—MPQ8632-4, FSW=500kHz, VIN=12V
Typical Design Parameter Tables
VOUT
(V)
L
(μH)
R1
(kΩ)
R2
(kΩ)
R7
(kΩ)
The following tables include recommended
component values for typical output voltages (1V,
2.5V, 3.3V) and switching frequency (500kHz).
Refer to Tables 3-9 for design cases without
external ramp compensation. And Tables 10-16
are for design cases with external ramp
compensation. An external ramp is not needed
when using high-ESR output capacitors, such as
electrolytic or POSCAPs. Use an external ramp
when using low-ESR capacitors, such as ceramic
capacitors. For cases not listed in this datasheet,
an excel spreadsheet provided by local sales
representatives can assist with the calculations.
1
1.8
3.3
3.9
13.3
63.4
91
20
20
20
357
887
2.5
3.3
1200
Table 4—MPQ8632-6, FSW=500kHz, VIN=12V
VOUT
(V)
L
(μH)
R1
(kΩ)
R2
(kΩ)
R7
(kΩ)
1
1
13.3
63.4
91
20
20
20
357
887
2.5
3.3
2.2
3.3
1200
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
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27
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
Table 5—MPQ8632-8, FSW=500kHz, VIN=12V
Table 11—MPQ8632-6, FSW=500kHz, VIN=12V
VOUT
(V)
L
(μH)
R1
(kΩ)
R2
(kΩ)
R7
(kΩ)
VOUT
(V)
L
(μH)
R1
(kΩ)
R2
(kΩ)
R4
(kΩ) (pF)
750 220
C4
R7
(kΩ)
1
0.72
1.8
13.3
63.4
91
20
20
20
357
887
1
1
13.7
66.5
95.3
20
20
20
357
887
2.5
3.3
2.5
3.3
2.2
3.3
1000 220
1200 220
2.2
1200
1200
Table 6—MPQ8632-10, MPQ8632H-10,
Table 12—MPQ8632-8, FSW=500kHz, VIN=12V
FSW=500kHz, VIN=12V
VOUT
(V)
L
(μH)
R1
(kΩ)
R2
(kΩ)
R4
(kΩ) (pF)
750 220
C4
R7
(kΩ)
VOUT
(V)
L
R1
R2
R7
(kΩ)
(μH)
(kΩ)
(kΩ)
1
0.72
1.8
13.7
66.5
95.3
20
20
20
357
887
1
0.72
1.5
13.3
63.4
91
20
20
20
357
887
2.5
3.3
1000 220
1200 220
2.5
3.3
2.2
1200
1.8
1200
Table 13—MPQ8632-10, MPQ8632H-10,
Table 7—MPQ8632-12, FSW=500kHz, VIN=12V
FSW=500kHz, VIN=12V
VOUT
(V)
L
(μH)
R1
(kΩ)
R2
(kΩ)
R7
(kΩ)
VOUT
(V)
L
(μH)
R1
(kΩ)
R2
(kΩ)
R4
(kΩ) (pF)
750 220
C4
R7
(kΩ)
1
0.72
1.5
13.3
63.4
91
20
20
20
357
887
1
0.72
1.5
13.7
66.5
95.3
20
20
20
357
887
2.5
3.3
2.5
3.3
1000 220
1200 220
1.8
1200
1.8
1200
Table 8—MPQ8632GVE-15, FSW=500kHz,
Table 14—MPQ8632-12, FSW=500kHz, VIN=12V
VIN=12V
R1
(kΩ)
VOUT
(V)
L
(μH)
R1
(kΩ)
R2
(kΩ)
R4
(kΩ) (pF)
750 220
C4
R7
(kΩ)
VOUT
(V)
L
(μH)
R2
(kΩ)
R7
(kΩ)
1
0.72
1.5
13.7
66.5
95.3
20
20
20
357
887
1
0.72
0.72
1
13.3
63.4
91
20
20
20
357
887
2.5
3.3
1000 220
1200 220
2.5
3.3
1.8
1200
1200
Table 15—MPQ8632GVE-15, FSW=500kHz,
Table 9— MPQ8632GVE-20, FSW=500kHz,
VIN=12V
VIN=12V
VOUT
(V)
L
(μH)
R1
(kΩ)
R2
(kΩ)
R4
(kΩ) (pF)
750 220
C4
R7
(kΩ)
VOUT
(V)
L
(μH)
R1
(kΩ)
R2
(kΩ)
R7
(kΩ)
1
0.72
0.72
1
13.7
68
20
20
20
357
887
1
0.72
0.72
0.72
13.3
63.4
91
20
20
20
357
887
2.5
3.3
1000 220
1200 220
2.5
3.3
95.3
1200
1200
Table 16—MPQ8632GVE-20, FSW=500kHz,
Table 10—MPQ8632-4, FSW=500kHz, VIN=12V
VIN=12V
VOUT
(V)
L
(μH)
R1
(kΩ)
R2
(kΩ)
R4
(kΩ) (pF)
750 220
C4
R7
(kΩ)
VOUT
(V)
L
(μH)
R1
(kΩ)
R2
(kΩ)
R4
(kΩ) (pF)
750 220
C4
R7
(kΩ)
1
1.8
3.3
3.9
13.7
66.5
95.3
20
20
20
357
887
1
0.72
0.72
0.72
13.7
68
20
20
20
357
887
2.5
3.3
1000 220
1200 220
2.5
3.3
1000 220
1200 220
1200
95.3
1200
MPQ8632 Rev.1.24
8/28/2013
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28
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
TYPICAL APPLICATION (7)
R3
0
VIN
BST
SW
IN
C3
0.1uF
C1A
C1B
C1C C1D
R7
L1
R5
1uH, TOKO FDU1250C-1R0M
10uF 10uF
0.1uF 0.1uF
357K
VOUT
100K
FREQ
+
R1
C2A
220uF/20m
C2B
0.1uF
Ω
13.7K
EN
MPQ8632
FB
SS
VCC
R2
C5
R6
1uF
20K
100K
C6
33nF
PG
AGND
PGND
Figure 13 — Typical Application Circuit with No External Ramp
MPQ8632-10, VIN=12V, VOUT=1V, IOUT=10A, FSW=500kHz
R3
VIN
BST
IN
0
C3
C1A
C1B
C1C C1D
R7
0.1uF
L1
R5
1uH, TOKO FDU1250C-1R0M
10uF 10uF
0.1uF 0.1uF
357K
SW
VOUT
100K
FREQ
C4
C2A
C2B
R4
C2C C2D
C2E
R1
47uF 47uF 47uF
0.1uF 0.1uF
330K
220pF
R9
13.7K
EN
MPQ8632
100
FB
SS
VCC
R2
C5
R6
1uF
20K
100K
C6
33nF
PG
AGND
PGND
Figure 14 — Typical Application Circuit with Low ESR Ceramic Capacitor
MPQ8632-10, VIN=12V, VOUT=1V, IOUT=10A, FSW=500kHz
VIN
BST
IN
0
C3
0.1uF
C1A
C1B
C1C C1D
R7
L1
R5
1uH, TOKO FDU1250C-1R0M
10uF 10uF
0.1uF 0.1uF
357K
SW
VOUT
100K
FREQ
C4
C2A
C2B
R4
C2C C2D
47uF
C2E
R1
47uF 47uF
0.1uF
0.1uF
330K
220pF
CDC
13.7K
EN
MPQ8632
10nF
FB
SS
VCC
R2
C5
R6
1uF
20K
100K
C6
33nF
PG
AGND
PGND
Figure 15 — Typical Application Circuit with Low ESR Ceramic Capacitor
and DC-Blocking Capacitor.
MPQ8632-10, VIN=12V, VOUT=1V, IOUT=10A, FSW=500kHz
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
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© 2013 MPS. All Rights Reserved.
29
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
Figure 16 — Efficiency Curve
MPQ8632-10, VOUT=1V, IOUT=0.01A-10A, FSW=500kHz
R3
VIN
BST
IN
0
C3
C1A
C1B
C1C C1D
R7
0.1uF
L1
R5
1uH, TOKO FDU1250C-1R0M
10uF 10uF
0.1uF 0.1uF
604K
SW
VOUT
100K
FREQ
C4
C2A
C2B
R4
C2C C2D
C2E
R1
47uF 47uF 47uF
0.1uF 0.1uF
270K
390pF
R9
13.7K
EN
MPQ8632
100
FB
SS
VCC
R2
C5
R6
1uF
20K
100K
C6
33nF
PG
AGND
PGND
Figure 17 — Typical Application Circuit with Low ESR Ceramic Capacitor
MPQ8632-10, VIN=12V, VOUT=1V, IOUT=10A, FSW=300kHz
Figure 18 — Efficiency Curve
MPQ8632-10, VOUT=1V, IOUT=0.01A-10A, FSW=300kHz
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
30
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
R3
VIN
BST
IN
0
C3
C1A
C1B
C1C C1D
R7
0.1uF
L1
R5
1uH, TOKO FDU1250C-1R0M
10uF 10uF
0.1uF 0.1uF
220K
SW
VOUT
100K
FREQ
C4
C2A
C2B
R4
C2C C2D
C2E
R1
47uF 47uF 47uF
0.1uF 0.1uF
301K
220pF
R9
28K
EN
MPQ8632
100
FB
SS
VCC
R2
C5
R6
1uF
40.2K
100K
C6
33nF
PG
AGND
PGND
Figure 19 — Typical Application Circuit with Low ESR Ceramic Capacitor
MPQ8632-10, VIN=12V, VOUT=1V, IOUT=10A, FSW=800kHz
Figure 20 — Efficiency Curve
MPQ8632-10, VOUT=1V, IOUT=0.01A-10A, FSW=800kHz
R3
VIN
BST
IN
0
C3
C1A
C1B
C1C C1D
R7
0.1uF
L1
R5
1uH, TOKO FDU1250C-1R0M
10uF 10uF
0.1uF 0.1uF
475K
SW
VOUT
100K
FREQ
C4
C2A
C2B
R4
C2C C2D
C2E
R1
47uF 47uF 47uF
0.1uF 0.1uF
330K
330pF
R9
12.7K
EN
MPQ8632
100
FB
SS
VCC
R2
C5
R6
1uF
40.2K
100K
C6
33nF
PG
AGND
PGND
Figure 21 — Typical Application Circuit with Low ESR Ceramic Capacitor
MPQ8632-10, VIN=12V, VOUT=0.8V, IOUT=10A, FSW=300kHz
MPQ8632 Rev.1.24
8/28/2013
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© 2013 MPS. All Rights Reserved.
31
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
Figure 22 — Efficiency Curve
MPQ8632-10, VOUT=0.8V, IOUT=0.01A-10A, FSW=300kHz
R3
VIN
BST
IN
0
C3
C1A
C1B
C1C C1D
R7
0.1uF
L1
R5
1uH, TOKO FDU1250C-1R0M
10uF 10uF
0.1uF 0.1uF
287K
SW
VOUT
100K
FREQ
C4
C2A
C2B
R4
C2C C2D
C2E
R1
47uF 47uF 47uF
0.1uF 0.1uF
330K
220pF
R9
12.7K
EN
MPQ8632
100
FB
SS
VCC
R2
C5
R6
1uF
40.2K
100K
C6
33nF
PG
AGND
PGND
Figure 23 — Typical Application Circuit with Low ESR Ceramic Capacitor
MPQ8632-10, VIN=12V, VOUT=0.8V, IOUT=10A, FSW=500kHz
Figure 24 — Efficiency Curve
MPQ8632-10, VOUT=0.8V, IOUT=0.01A-10A, FSW=500kHz
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
32
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
R3
VIN
BST
IN
0
C3
C1A
C1B
C1C C1D
R7
0.1uF
L1
R5
2.2uH, TOKO FDA1254-2R2M
10uF 10uF
0.1uF 0.1uF
715K
SW
VOUT
100K
FREQ
C4
C2A
C2B
R4
C2C C2D
C2E
R1
47uF 47uF 47uF
0.1uF 0.1uF
330K
330pF
R9
20.5K
EN
MPQ8632
100
FB
SS
VCC
R2
C5
R6
1uF
20K
100K
C6
33nF
PG
AGND
PGND
Figure 25 — Typical Application Circuit with Low ESR Ceramic Capacitor
MPQ8632-10, VIN=12V, VOUT=1.2V, IOUT=10A, FSW=300kHz
Figure 26 — Efficiency Curve
MPQ8632-10, VOUT=1.2V, IOUT=0.01A-10A, FSW=300kHz
R3
VIN
BST
IN
0
C3
C1A
C1B
C1C C1D
R7
0.1uF
L1
R5
1uH, TOKO FDU1250C-1R0M
10uF 10uF
0.1uF 0.1uF
432K
SW
VOUT
100K
FREQ
C4
C2A
C2B
R4
C2C C2D
C2E
R1
47uF 47uF 47uF
0.1uF 0.1uF
220K
330pF
R9
10K
EN
MPQ8632
100
FB
SS
VCC
R2
C5
R6
1uF
10K
100K
C6
33nF
PG
AGND
PGND
Figure 27 — Typical Application Circuit with Low ESR Ceramic Capacitor
MPQ8632-10, VIN=12V, VOUT=1.2V, IOUT=10A, FSW=500kHz
MPQ8632 Rev.1.24
8/28/2013
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MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
33
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
Figure 28 — Efficiency Curve
MPQ8632-10, VOUT=1.2V, IOUT=0.01A-10A, FSW=500kHz
R3
VIN
BST
IN
0
C3
C1A
C1B
C1C C1D
R7
0.1uF
L1
R5
1uH, TOKO FDU1250C-1R0M
10uF 10uF
0.1uF 0.1uF
270K
SW
VOUT
100K
FREQ
C4
C2A
C2B
R4
C2C C2D
C2E
R1
47uF 47uF 47uF
0.1uF 0.1uF
220K
220pF
R9
10K
EN
MPQ8632
100
FB
SS
VCC
R2
C5
R6
1uF
10K
100K
C6
33nF
PG
AGND
PGND
Figure 29 — Typical Application Circuit with Low ESR Ceramic Capacitor
MPQ8632-10, VIN=12V, VOUT=1.2V, IOUT=10A, FSW=800kHz
Figure 30 — Efficiency Curve
MPQ8632-10, VOUT=1.2V, IOUT=0.01A-10A, FSW=800kHz
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
34
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
R3
VIN
BST
IN
0
C3
C1A
C1B
C1C C1D
R7
0.1uF
L1
R5
2.2uH, TOKO FDA1254-2R2M
10uF 10uF
0.1uF 0.1uF
887K
SW
VOUT
100K
FREQ
C4
C2A
C2B
R4
C2C C2D
C2E
R1
47uF 47uF 47uF
0.1uF 0.1uF
470K
470pF
R9
15K
EN
MPQ8632
100
FB
SS
VCC
R2
C5
R6
1uF
10K
100K
C6
33nF
PG
AGND
PGND
Figure 31 — Typical Application Circuit with Low ESR Ceramic Capacitor
MPQ8632-10, VIN=12V, VOUT=1.5 V, IOUT=10A, FSW=300kHz
Figure 32 — Efficiency Curve
MPQ8632-10, VOUT=1.5V, IOUT=0.01A-10A, FSW=300kHz
R3
VIN
BST
IN
0
C3
C1A
C1B
C1C C1D
R7
0.1uF
L1
R5
1.2uH, TOKO FDA1254-1R2M
10uF 10uF
0.1uF 0.1uF
536K
SW
VOUT
100K
FREQ
C4
C2A
C2B
R4
C2C C2D
C2E
R1
47uF 47uF 47uF
0.1uF 0.1uF
470K
330pF
R9
15.4K
EN
MPQ8632
100
FB
SS
VCC
R2
C5
R6
1uF
10K
100K
C6
33nF
PG
AGND
PGND
Figure 33 — Typical Application Circuit with Low ESR Ceramic Capacitor
MPQ8632-10, VIN=12V, VOUT=1.5 V, IOUT=10A, FSW=500kHz
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
35
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
Figure 34 — Efficiency Curve
MPQ8632-10, VOUT=1.5V, IOUT=0.01A-10A, FSW=500kHz
R3
VIN
BST
IN
0
C3
C1A
C1B
C1C C1D
R7
0.1uF
L1
R5
1.2uH, TOKO FDA1254-1R2M
10uF 10uF
0.1uF 0.1uF
332K
SW
VOUT
100K
FREQ
C4
C2A
C2B
R4
C2C C2D
C2E
R1
47uF 47uF 47uF
0.1uF 0.1uF
470K
220pF
R9
15.4K
EN
MPQ8632
100
FB
SS
VCC
R2
C5
R6
1uF
10K
100K
C6
33nF
PG
AGND
PGND
Figure 35 — Typical Application Circuit with Low ESR Ceramic Capacitor
MPQ8632-10, VIN=12V, VOUT=1.5 V, IOUT=10A, FSW=800kHz
Figure 36 — Efficiency Curve
MPQ8632-10, VOUT=1.5V, IOUT=0.01A-10A, FSW=800kHz
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
36
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
R3
VIN
BST
IN
0
C3
C1A
C1B
C1C C1D
R7
0.1uF
L1
R5
2.2uH, TOKO FDA1254-2R2M
10uF 10uF
0.1uF 0.1uF
1.1M
SW
VOUT
100K
FREQ
C4
C2A
C2B
R4
C2C C2D
C2E
R1
47uF 47uF 47uF
0.1uF 0.1uF
470K
220pF
R9
19.6K
EN
MPQ8632
100
FB
SS
VCC
R2
C5
R6
1uF
10K
100K
C6
33nF
PG
AGND
PGND
Figure 37 — Typical Application Circuit with Low ESR Ceramic Capacitor
MPQ8632-10, VIN=12V, VOUT=1.8 V, IOUT=10A, FSW=300kHz
Figure 38 — Efficiency Curve
MPQ8632-10, VOUT=1.8V, IOUT=0.01A-10A, FSW=300kHz
R3
VIN
BST
IN
0
C3
C1A
C1B
C1C C1D
R7
0.1uF
L1
R5
2.2uH, TOKO FDA1254-2R2M
10uF 10uF
0.1uF 0.1uF
634K
SW
VOUT
100K
FREQ
C4
C2A
C2B
R4
C2C C2D
C2E
R1
47uF 47uF 47uF
0.1uF 0.1uF
470K
220pF
R9
21K
EN
MPQ8632
100
FB
SS
VCC
R2
C5
R6
1uF
10K
100K
C6
33nF
PG
AGND
PGND
Figure 39 — Typical Application Circuit with Low ESR Ceramic Capacitor
MPQ8632-10, VIN=12V, VOUT=1.8 V, IOUT=10A, FSW=500kHz
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
37
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
Figure 40 — Efficiency Curve
MPQ8632-10, VOUT=1.8V, IOUT=0.01A-10A, FSW=500kHz
VIN
BST
IN
RFREQ
C1B C1C
C1A
C3
L1
SW
VOUT
FREQ
R5
C4
R4
C2
R1
R2
EN
MPQ8632
FB
SS
VCC
C5
R3
C6
PG
AGND
PGND
Figure 41 — Typical Application Circuit with Low ESR Ceramic Capacitor
MPQ8632-10, VIN=12V, VOUT=1.8 V, IOUT=10A, FSW=800kHz
Figure 42 — Efficiency Curve
MPQ8632-10, VOUT=1.8V, IOUT=0.01A-10A, FSW=800kHz
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
38
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
R3
VIN
BST
IN
0
C3
C1A
C1B
C1C C1D
R7
0.1uF
L1
R5
2.2uH, TOKO FDA1254-2R2M
10uF 10uF
0.1uF 0.1uF
2M
SW
VOUT
100K
FREQ
C4
C2A
C2B
R4
C2C C2D
C2E
R1
47uF 47uF 47uF
0.1uF 0.1uF
470K
220pF
R9
48.7K
EN
MPQ8632
100
FB
SS
VCC
R2
C5
R6
1uF
10K
100K
C6
33nF
PG
AGND
PGND
Figure 43 — Typical Application Circuit with Low ESR Ceramic Capacitor
MPQ8632-10, VIN=12V, VOUT=3.3 V, IOUT=10A, FSW=300kHz
Figure 44 — Efficiency Curve
MPQ8632-10, VOUT=3.3V, IOUT=0.01A-10A, FSW=300kHz
R3
VIN
BST
IN
0
C3
C1A
C1B
C1C C1D
R7
0.1uF
L1
R5
2.2uH, TOKO FDA1254-2R2M
10uF 10uF
0.1uF 0.1uF
1.2M
SW
VOUT
100K
FREQ
C4
C2A
C2B
R4
C2C C2D
C2E
R1
47uF 47uF 47uF
0.1uF 0.1uF
470K
220pF
R9
48.7K
EN
MPQ8632
100
FB
SS
VCC
R2
C5
R6
1uF
10K
100K
C6
33nF
PG
AGND
PGND
Figure 45 — Typical Application Circuit with Low ESR Ceramic Capacitor
MPQ8632-10, VIN=12V, VOUT=3.3 V, IOUT=10A, FSW=500kHz
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
39
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
Figure 46 — Efficiency Curve
MPQ8632-10, VOUT=3.3V, IOUT=0.01A-10A, FSW=500kHz
R3
VIN
BST
IN
0
C3
C1A
C1B
C1C C1D
R7
0.1uF
L1
R5
2.2uH, TOKO FDA1254-2R2M
10uF 10uF
0.1uF 0.1uF
715K
SW
VOUT
100K
FREQ
C4
C2A
C2B
R4
C2C C2D
C2E
R1
47uF 47uF 47uF
0.1uF 0.1uF
470K
220pF
R9
48.7K
EN
MPQ8632
100
FB
SS
VCC
R2
C5
R6
1uF
10K
100K
C6
33nF
PG
AGND
PGND
Figure 47 — Typical Application Circuit with Low ESR Ceramic Capacitor
MPQ8632-10, VIN=12V, VOUT=3.3 V, IOUT=10A, FSW=800kHz
Figure 48 — Efficiency Curve
MPQ8632-10, VOUT=3.3V, IOUT=0.01A-10A, FSW=800kHz
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
40
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
R3
VIN
BST
IN
0
C3
C1A
C1B
C1C C1D
R7
0.1uF
L1
R5
3.3uH, TOKO FDA1254-3R3M
10uF 10uF
0.1uF 0.1uF
2.7M
SW
VOUT
100K
FREQ
C4
C2A
C2B
R4
C2C C2D
C2E
R1
47uF 47uF 47uF
0.1uF 0.1uF
470K
330pF
R9
82.5K
EN
MPQ8632
100
FB
SS
VCC
R2
C5
R6
1uF
10K
100K
C6
33nF
PG
AGND
PGND
Figure 49 — Typical Application Circuit with Low ESR Ceramic Capacitor
MPQ8632-10, VIN=12V, VOUT=5 V, IOUT=10A, FSW=300kHz
Figure 50 — Efficiency Curve
MPQ8632-10, VOUT=5V, IOUT=0.01A-10A, FSW=300kHz
R3
VIN
BST
IN
0
C3
C1A
C1B
C1C C1D
R7
0.1uF
L1
R5
3.3uH, TOKO FDA1254-3R3M
10uF 10uF
0.1uF 0.1uF
1.8M
SW
VOUT
100K
FREQ
C4
C2A
C2B
R4
C2C C2D
C2E
R1
47uF 47uF 47uF
0.1uF 0.1uF
470K
330pF
R9
84.5K
EN
MPQ8632
100
FB
SS
VCC
R2
C5
R6
1uF
10K
100K
C6
33nF
PG
AGND
PGND
Figure 51 — Typical Application Circuit with Low ESR Ceramic Capacitor
MPQ8632-10, VIN=12V, VOUT=5 V, IOUT=10A, FSW=500kHz
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
41
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
Figure 52 — Efficiency Curve
MPQ8632-10, VOUT=5V, IOUT=0.01A-10A, FSW=500kHz
R3
VIN
BST
IN
0
C3
C1A
C1B
C1C C1D
R7
0.1uF
L1
R5
1uH, TOKO FDU1250C-1R0M
10uF 10uF
0.1uF 0.1uF
1.1M
SW
VOUT
100K
FREQ
C4
C2A
C2B
R4
C2C C2D
C2E
R1
47uF 47uF 47uF
0.1uF 0.1uF
330K
220pF
R9
82K
EN
MPQ8632
100
FB
SS
VCC
R2
C5
R6
1uF
10K
100K
C6
33nF
PG
AGND
PGND
Figure 53 — Typical Application Circuit with Low ESR Ceramic Capacitor
MPQ8632-10, VIN=12V, VOUT=5 V, IOUT=10A, FSW=800kHz
Figure 54 — Efficiency Curve
MPQ8632-10, VOUT=5V, IOUT=0.01A-10A, FSW=800kHz
NOTE:
7) The all application circuits’ steady states are OK, but other performances are not tested.
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
42
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
LAYOUT RECOMMENDATION
GND
1. Place high current paths (GND, IN, and SW)
very close to the device with short, direct and
wide traces.
C1E
C3
C1D
2. Two-layer IN copper layers are required to
achieve better performance. Place at least
one 0.1uF-1uF 0603 or 0402 decoupling input
capacitor on each side of the IC. The input
capacitors should be placed as close to the
IN and GND pins as possible (maximum 2mm
edge-to-edge distance is allowed). Multiple
vias with 18mil diameter and 8mil hole-size
are required to be placed under the device
and near input capacitors. These vias can
help to reduce the parasitic inductance and
optimize the thermal dissipation.
PGND
PGND
BST
VCC
PG
SW
SW
SW
SW
AGND
SS
6 C
FB
PGND
PGND
FREQ
EN
C1B
C1A
C2
GND
VIN
VOUT
Top Layer
3. Put a decoupling capacitor as close to the
VCC and AGND pins as possible.
4. Keep the switching node (SW) plane as small
as possible and far away from the feedback
network.
GND
5. Place the external feedback resistors next to
the FB pin. Make sure that there are no vias
on the FB trace. The feedback resistors
should refer to AGND instead of PGND.
6. Keep the BST voltage path (BST, C3, and
SW) as short as possible.
7. Recommend strongly a four-layer layout to
improve thermal performance.
Inner1 Layer
VIN
BST
IN
RFREQ
C1B C1C C1D C1E
C1A
C3
L1
SW
VOUT
FREQ
R5
C4
R4
C2
R1
MPQ8632
EN
MPQ8632H
FB
SS
VCC
C5
R3
R2
C6
PG
AGND
PGND
Figure 55—Schematic for PCB Layout
GND
Guideline
8
7
6
5
4
3
2
1
SW
SW
CIN
CIN
CIN
CIN
PGN
ND
PGND
PGND
To Inductor
Inner2 Layer
Figure 56—Recommend Input Capacitor
Placement for 16-Pin QFN 3mmx4mm
Package Part, including MPQ8632-4/6/8/10/12
and MPQ8632H-10.
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
43
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
Design Example
Below is a design example following the
application guidelines for the specifications:
Table 13—Design Example
VIN
VOUT
FSW
4.5-18V
1V
500kHz
C1C
GND
The detailed application schematic is shown in
Figure 14. The typical performance and circuit
waveforms have been shown in the Typical
Performance Characteristics section. For more
device applications, please refer to the related
Evaluation Board Datasheets.
VIN
Bottom Layer
Figure 57—PCB Layout Guideline For 29-Pin
QFN 5mmx4mm Package Part, Including
MPQ8632-15 and MPQ8632-20.
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
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© 2013 MPS. All Rights Reserved.
44
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
PACKAGE INFORMATION
QFN(3X4mm)
PIN 1 ID
0.125x45° TYP.
PIN 1 ID
MARKING
PIN 1 ID
INDEX AREA
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NOTE:
0.125x45°
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE
MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10
MILLIMETERS MAX.
4) JEDEC REFERENCE IS MO-220.
5) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
45
MPQ8632 HIGH EFFICIENCY 18V SYNCHRONOUS STEP-DOWN CONVERTER FAMILY FOR 4A TO 20A
QFN(5X4mm)
PIN 1 ID
0.125x45° TYP.
PIN 1 ID
MARKING
PIN 1 ID
INDEX AREA
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE
MOLD FLASH.
0.125x45°
3) LEAD COPLANARITY SHALL BE 0.10
MILLIMETERS MAX.
4) JEDEC REFERENCE IS MO-220.
5) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MPQ8632 Rev.1.24
8/28/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
46
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