MPQ8632D-12 [MPS]
High Efficiency, 6A/12A, 18V Synchronous Step-down Converter;
| 型号： | MPQ8632D-12 |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | High Efficiency, 6A/12A, 18V Synchronous Step-down Converter |
| 文件： | 总23页 (文件大小：2205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MPQ8632D-6, MPQ8632D-12
High Efficiency, 6A/12A, 18V
Synchronous Step-down Converter
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MPQ8632D-6/MPQ8632D-12 is a fully
integrated high frequency synchronous rectified
step-down switch mode converter. It offers a
very compact solution to achieve 6A/12A output
current over a wide input supply range with
excellent load and line regulation. The
MPQ8632D-6/MPQ8632D-12 operates at high
efficiency over a wide output current load range.
•
2.5V to 18V Operating Input Range with
External 5V Bias
4.5V to 18V Operating Input Range with
Internal Bias
•
•
•
•
6A/12A Output Current
Low RDS(ON) Internal Power MOSFETs
Proprietary Switching Loss Reduction
Technique
•
•
•
Adaptive COT for Ultrafast Transient
Response
0.5% Reference Voltage Over 0°C to 70°C
Junction Temperature Range
Programmable Soft Start and Shut-down
Time
Pre-Bias Start up
Programmable Switching Frequency from
200kHz to 1MHz
The
MPQ8632D-6/MPQ8632D-12
uses
Constant-On-Time (COT) control mode to
provide fast transient response and ease loop
stabilization.
An external resistor programs the operating
frequency from 200kHz to 1MHz and the
frequency keeps nearly constant as input
supply
compensation.
•
•
varies
with
the
feedforward
•
•
Non-latch OCP, OVP and Thermal
Shutdown
Output Adjustable from 0.611V to 13V
The default under voltage lockout threshold is
internally set at 4.1V, but a resistor network on
the enable pin can increase this threshold. An
open drain power good signal indicates that the
output is within nominal voltage range.
APPLICATIONS
•
•
•
•
•
•
Telecom and Networking Systems
Base Stations
Servers
Personal Video Recorders
Flat Panel Television and Monitors
Distributed Power Systems
The MPQ8632D-6/MPQ8632D-12 employs a
programmable soft start and shut-down scheme.
With the soft shut-down feature, it discharges
the output voltage smoothly when the enable
signal is deserted.
It has fully integrated protection features that
include over-current protection, over-voltage
protection and thermal shutdown.
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Products, Quality Assurance page.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
The MPQ8632D-6/MPQ8632D-12 requires a
minimal number of readily available standard
external components and is available in a
3mm×4mm package.
MPQ8632D-6_MPQ8632D-12 Rev. 1.01
3/9/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
www.MonolithicPower.com
1
MPQ8632D-6, MPQ8632D-12 ― 6A/12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL APPLICATION
BST
SW
VIN
IN
C1
R
C3
FREQ
L1
VOUT
FREQ
R1
R4
C4
MPQ8632D
EN
ON/OFF
C2
FB
SS
VCC
C5
PG
C6
R2
PGND
AGND
MPQ8632D-6_MPQ8632D-12 Rev. 1.01
www.MonolithicPower.com
2
3/9/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
MPQ8632D-6, MPQ8632D-12 ― 6A/12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER
ORDERING INFORMATION
Part Number
Package
Top Marking
MP8632D
6
MPQ8632DGLE-6*
QFN(3X4mm)
MP8632D
12
MPQ8632DGLE-12
QFN(3X4mm)
* For Tape & Reel, add suffix –Z (e.g. MPQ8632DGLE–6–Z)
PACKAGE REFERENCE
TOP VIEW
TOP VIEW
8
9
7
6
5
4
3
2
1
8
9
7
6
5
4
3
2
1
VIN
14 VIN
VIN
14 VIN
15
SW
15
SW
PGND 10
PGND 11
13 PGND
PGND 10
PGND 11
13 PGND
12 PGND
SW 16
SW 16
12 PGND
Part Number*
MPQ8632DGLE-6
Package
Part Number*
MPQ8632DGLE-12
Package
QFN (3x4mm)
QFN (3x4mm)
Top Marking
Junction Temperature
Top Marking
Junction Temperature
MP8632D
6
MP8632D
12
–40°C to +125°C
–40°C to +125°C
* For Tape & Reel, add suffix –Z (eg. MPQ8632DGLE-6–Z) * For Tape & Reel, add suffix –Z (eg. MPQ8632DGLE-12–Z)
Thermal Resistance (5)
QFN (3x4mm) .........................46 ....... 9....°C/W
θJA
θJC
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage VIN ....................................... 21V
V
SW........................................-0.3V to VIN + 0.3V
Notes:
1) Exceeding these ratings may damage the device.
2) Refer to the section “Configuring the EN Control”.
3) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)-
TA)/θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
VSW (30ns)...................................-3V to VIN + 3V
V
BST ......................................................VSW + 6V
Enable Current IEN(2)................................ 2.5mA
All Other Pins.................................–0.3V to +6V
(3)
Continuous Power Dissipation (TA=+25°)
QFN3X4……………………….…..…………2.7W
Junction Temperature...............................150°C
Lead Temperature ....................................260°C
Storage Temperature............... -65°C to +150°C
Recommended Operating Conditions (4)
Supply Voltage VIN ...........................4.5V to 18V
Output Voltage VOUT.....................0.611V to 13V
Enable Current IEN...................................... 1mA
Operating Junction Temp. (TJ).-40°C to +125°C
4) The device is not guaranteed to function outside of its
operating conditions.
5) Measured on JESD51-7, 4-layer PCB.
MPQ8632D-6_MPQ8632D-12 Rev. 1.01
3/9/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
www.MonolithicPower.com
3
MPQ8632D-6, MPQ8632D-12 ― 6A/12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS
VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted.
Parameters
Symbol
Condition
Min
Typ
Max
Units
Supply Current
Supply Current (Shutdown)
Supply Current (Quiescent)
MOSFET
IIN
IIN
VEN = 0V
0
1
μA
μA
VEN = 2V, VFB = 1V
700
860
1000
MPQ8632DGLE-6
TJ =25°C
28
mΩ
mΩ
High-side Switch On Resistance
Low-side Switch On Resistance
HSRDS-ON
MPQ8632DGLE-12
TJ =25°C
19.6
15.8
MPQ8632DGLE-6, TJ =25°C
LSRDS-ON
SWLKG
mΩ
μA
5.2
0
MPQ8632DGLE-12,TJ=25°C
Switch Leakage
VEN = 0V, VSW = 0V or 12V
10
Current Limit
6.5
12
7.5
15
8.5
18
MPQ8632DGLE-6
MPQ8632DGLE-12
Low-side Valley Current Limit(6)
ILIMIT_VALLEY
A
A
Low-side Negative Current
Limit(6)
ILIMIT_NEGATIVE
-4
-2.5
-1
Timer
One-Shot On Time
TON
RFREQ=453kΩ, VOUT=1.2V
250
ns
Minimum On Time(6)
Minimum Off Time(6)
Under-voltage Protection
UVP Threshold(6)
TON_MIN
20
30
40
ns
ns
TOFF_MIN
200
360
420
VUVP
47%
50%
53%
VFB
Reference And Soft Start/Shut-down
TJ = 0°C to +70°C
TJ = 0°C to +125°C
TJ = -40°C to +125°C
VFB = 611mV
608
605
602
611
611
611
50
614
617
620
100
25
mV
mV
mV
nA
Reference Voltage
VREF
Feedback Current
IFB
ISS
Soft Start Charging Current
VSS=0V
16
6
20
μA
Soft Shut-down Discharging
Current
ISD
VSS=0V
10
15
μA
MPQ8632D-6_MPQ8632D-12 Rev. 1.01
www.MonolithicPower.com
4
3/9/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
MPQ8632D-6, MPQ8632D-12 ― 6A/12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted.
Parameters
Symbol Condition
Min
Typ
Max
Units
Enable And UVLO
Enable Input Low Voltage
Enable Hysteresis
VILEN
1.1
1.3
250
0
1.5
V
VEN-HYS
mV
VEN = 2V
IEN
Enable Input Current
μA
VEN = 0V
0
VCC Regulator
VCC Under Voltage Lockout
Threshold Rising
VCCVth
3.8
V
VCC Under Voltage Lockout
Threshold Hysteresis
VCCHYS
VCC
500
mV
VCC Regulator
4.8
0.5
V
VCC Load Regulation
Power Good
Icc=5mA
%
PGVth-Hi-Rise FB from low to high
PGVth-Hi-Fall FB from high to low
PGVth-Lo-Rise FB from low to high
PGVth-Lo-Fall FB from high to low
PGTd
86%
90%
109%
120%
85%
2.5
94%
VFB
VFB
VFB
VFB
ms
Power Good High Threshold
116%
124%
Power Good Low Threshold
Power Good Lower to High Delay
Power Good Sink Current
Capability
IOL
VOL=600mV
VPG = 3.3V
12
mA
nA
Power Good Leakage Current
Thermal Protection (6)
IPG_LEAK
10
25
Thermal Shutdown
TSD
150
°C
°C
Thermal Shutdown Hysteresis
Note:
6) Guaranteed by design.
MPQ8632D-6_MPQ8632D-12 Rev. 1.01
www.MonolithicPower.com
5
3/9/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
MPQ8632D-6, MPQ8632D-12 ― 6A/12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER
PIN FUNCTIONS
MPQ8632D-6/MPQ8632D-12
PIN #
Name
Description
Enable. Digital input that turns the regulator on or off. Drive EN high to turn on the
regulator, drive it low to turn it off. Connect EN to IN through a pull-up resistor or a
resistive voltage divider for automatic startup. Do not float this pin.
1
EN
Frequency Set. Require a resistor connected between FREQ and IN to set the
switching frequency. The input voltage and the resistor connected to the FREQ pin
determine the ON time. The connection to the IN pin provides line feed-forward and
stabilizes the frequency during input voltage’s variation.
2
3
FREQ
FB
Feedback. Connect to the tap of an external resistor divider from the output to GND
to set the output voltage. FB is also configured to realize over-voltage protection
(OVP) by monitoring output voltage. MPQ8632D-6 and MPQ8632D-12 provide non-
latch OVP mode. Please refer to the section “Over-Voltage-Protection (OVP)”.
Place the resistor divider as close to FB pin as possible. Avoid using vias on the FB
traces.
Soft Start/Shut-Down. Connect an external capacitor to program the soft start/shut-
down time for the switch mode regulator. The soft start time is the half of the soft
shut-down time.
4
5
SS
AGND
Analog ground. The control circuit reference.
Power Good. The output is an open drain signal. Require a 100kꢀ typical pull-up
resistor to a DC voltage to indicate high if the output voltage exceeds 90% of the
nominal voltage. Recommend a 10nF capacitor from PG to GND when the PG pull
up resistor is <100kꢀ. There is a delay from FB ≥ 90% to PG goes high.
6
PG
Internal 4.8V LDO Output. Power the driver and control circuits. 5V external bias
can disable the internal LDO. Decouple with a ≥ 1µF ceramic capacitor as close to
the pin as possible. For best results, use X7R or X5R dielectric ceramic capacitors
for their stable temperature characteristics.
7
8
VCC
BST
IN
Bootstrap. Require a capacitor connected between SW and BST pins to form a
floating supply across the high-side switch driver.
Supply Voltage. Supply power to the internal MOSFET and regulator. The
MPQ8632D-6/MPQ8632D-12 operates from a +2.5V to +18V input rail with 5V
external bias and a +4.5V to +18V input rail with internal bias. Require an input
decoupling capacitor. Connect using wide PCB traces and multiple vias.
9, 14
10, 11, 12,
13
System Ground. Reference ground of the regulated output voltage. PCB layout
requires extra care. Connect using wide PCB traces.
PGND
Switch Output. Connect to the inductor and bootstrap capacitor. The high-side
switch drives the pin up to the VIN during the PWM duty cycle’s ON time. The
inductor current drives the SW pin negative during the OFF-time. The low-side
switch’s ON-resistance and the internal Schottky diode clamp the negative voltage.
Connect using wide PCB traces.
15, 16
SW
MPQ8632D-6_MPQ8632D-12 Rev. 1.01
www.MonolithicPower.com
6
3/9/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
MPQ8632D-6, MPQ8632D-12 ― 6A/12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL CHARACTERISTICS
MPQ8632DGLE-12, VIN = 12V, VOUT = 1V, L = 1µH, TA = 25ºC, unless otherwise noted.
2
25
20
15
10
1000
800
1.5
1
600
0.5
0
400
0
5
10
15
20
25
0
5
10
15
20
25
-50
0
50
100
150
5
4
3
2
10
7
2
1.5
1
4
0.5
0
1
-50
0
50
100
150
-50
0
50
100
150
-50
0
50
100
150
3
100
2.5
2
90
80
1.5
70
60
1
-50
-50
0
50
100
150
0
50
100
150
MPQ8632D-6_MPQ8632D-12 Rev. 1.01
www.MonolithicPower.com
7
3/9/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
MPQ8632D-6, MPQ8632D-12 ― 6A/12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL CHARACTERISTICS (continued)
MPQ8632DGLE-12, VIN = 12V, VOUT = 1V, L = 1µH, TA = 25ºC, unless otherwise noted.
Valley Current Limit vs.
Input Voltage
V
Voltage vs.
BST Voltage vs.
Temperature
CC
Temperature
20
18
16
14
12
5
4.8
4.6
4.4
5
4.8
4.6
4.4
4.2
4
4.2
4
10
8
0
5
10
15
20
25
-50
0
50
100
150
-50
0
50
100
150
Switching Frequency
vs. R
FREQ
800
700
600
500
1200
700
600
500
400
300
200
1000
800
600
400
200
0
400
300
100
0
-50
0
50
100
150
0
200
400 600
800 1000
0
2
4
6
8
10
12
60
50
40
30
20
10
0
0
2
4
6
8
10
12
MPQ8632D-6_MPQ8632D-12 Rev. 1.01
www.MonolithicPower.com
8
3/9/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
MPQ8632D-6, MPQ8632D-12 ― 6A/12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
MPQ8632DGLE-12, VIN = 12V, VOUT = 1V, L = 1µH, TA = 25ºC, unless otherwise noted.
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
3000
2500
2000
1500
1000
500
0
0.01
0.1
1
10
100
0.01
0.1
1
10
100
0.01
0.1
1
10
100
0.6
0.5
0.4
0.3
0.2
0.1
0
2500
2000
1500
1000
100
90
80
70
60
-0.1
-0.2
-0.3
-0.4
50
500
0
40
30
0.01
0.1
1
10
100
0.01
0.1
1
10
100
0
2
4
6
8
10 12
0.5
0.2
-0.1
-0.4
-0.7
-1
0
5
10
15
20
MPQ8632D-6_MPQ8632D-12 Rev. 1.01
www.MonolithicPower.com
9
3/9/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
MPQ8632D-6, MPQ8632D-12 ― 6A/12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
MPQ8632DGLE-12, VIN=12V, VOUT =1V, L=1µH, TA=+25°C, unless otherwise noted.
V
(AC)
OUT
20mV/div.
V
(AC)
IN
20mV/div.
V
SW
10V/div.
V
V
SW
200mV/div.
SW
200mV/div.
I
L
10A/div.
V
(AC)
V
(AC)
OUT
20mV/div.
OUT
20mV/div.
V
OUT
1V/div.
V
(AC)
V
(AC)
IN
IN
200mV/div.
20mV/div.
V
IN
10V/div.
V
V
V
SW
SW
SW
10V/div.
10V/div.
10V/div.
I
I
I
L
L
L
5A/div.
10A/div.
2A/div.
V
V
OUT
V
OUT
OUT
1V/div.
1V/div.
1V/div.
V
V
V
IN
IN
IN
10V/div.
10V/div.
10V/div.
V
V
V
SW
SW
SW
10V/div.
10V/div.
10V/div.
I
I
I
L
L
L
2A/div.
10A/div.
10A/div.
MPQ8632D-6_MPQ8632D-12 Rev. 1.01
www.MonolithicPower.com
10
3/9/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
MPQ8632D-6, MPQ8632D-12 ― 6A/12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
MPQ8632DGLE-12, VIN=12V, VOUT =1V, L=1µH, TA=+25°C, unless otherwise noted.
V
V
V
OUT
OUT
OUT
500mV/div.
500mV/div.
500mV/div.
V
EN
5V/div.
V
V
EN
EN
5V/div.
5V/div.
V
V
V
SW
SW
SW
10V/div.
10V/div.
10V/div.
I
I
L
L
5A/div.
2A/div.
I
L
10A/div.
V
V
(AC)
V
(AC)
OUT
OUT
OUT
500mV/div.
500mV/div.
100mV/div.
V
EN
5V/div.
V
SW
10V/div.
I
V
L
SW
1A/div.
10V/div.
I
L
10A/div.
I
L
10A/div.
V
V
OUT
OUT
500mV/div.
500mV/div.
V
V
SW
SW
10V/div.
10V/div.
I
I
L
L
2A/div.
2A/div.
MPQ8632D-6_MPQ8632D-12 Rev. 1.01
www.MonolithicPower.com
11
3/9/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
MPQ8632D-6, MPQ8632D-12 ― 6A/12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER
BLOCK DIAGRAM
Figure 1—Functional Block Diagram
MPQ8632D-6_MPQ8632D-12 Rev. 1.01
www.MonolithicPower.com
12
3/9/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
MPQ8632D-6, MPQ8632D-12 ― 6A/12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER
OPERATION
PWM Operation
interval determined by the one- shot on-timer as
per equation 1. When the HS-FET turns off, the
LS-FET turns on until the next period.
The MPQ8632D-6/MPQ8632D-12 is a fully
integrated synchronous rectified step-down
switch mode converter. It uses Constant-on-time
(COT) control to provide a fast transient
response and ease loop stabilization.
In CCM operation, the switching frequency is
fairly constant and is also called PWM mode.
Light-Load Operation
As the load decreases, the inductor current
decreases too. When the inductor current
touches zero, the operation is transited from
At the beginning of each cycle, the high-side
MOSFET (HS-FET) turns ON when the feedback
voltage (VFB) drops below the reference voltage
(VREF), which indicates an insufficient output
voltage. The input voltage and the frequency-set
resistor determine the ON period as follows:
continuous-conduction-mode
(CCM)
to
discontinuous-conduction-mode (DCM).
Figure 3 shows the light load operation. When
VFB drops below VREF, HS-FET turns on for a
fixed interval determined by the one- shot on-
timer as per equation 1. When the HS-FET turns
off, the LS-FET turns on until the inductor current
reaches zero. In DCM operation, the VFB does
not reach VREF when the inductor current is
approaching zero. The LS-FET driver turns into
tri-state (high Z) whenever the inductor current
reaches zero. A current modulator takes over the
control of LS-FET and limits the inductor current
less than -1mA. Hence, the output capacitors
discharge slowly to GND through LS-FET. As a
result, this mode improves greatly the light load
efficiency. At light load condition, the HS-FET
does not turns ON as frequently as at heavy load
condition. This is called skip mode.
6.1×RFREQ(kΩ)
(1)
TON(ns) =
V (V) − 0.4
IN
After the ON period elapses, the HS-FET turns
off. It turns ON again when VFB drops below VREF
.
By repeating this operation, the converter
regulates the output voltage. The integrated low-
side MOSFET (LS-FET) turns on when the HS-
FET is OFF to minimize the conduction loss.
There is a dead short (or shoot-through) between
input and GND if both HS-FET and LS-FET turn
on at the same time. A dead-time (DT) internally
generated between HS-FET OFF and LS-FETON,
or LS-FET OFF and HS-FET ON avoids shoot-
through.
Heavy-Load Operation
At light load or no load condition, the output
drops very slowly and the MPQ8632D-
6/MPQ8632D-12
reduces
the
switching
frequency naturally and then achieves high
efficiency at light load.
Figure 2—Heavy Load Operation
Figure 3—Light Load Operation
When the output current is high and the inductor
current is always above zero amps, it is called
continuous-conduction-mode (CCM). Figure 2
shows the CCM operation. When VFB is below
VREF
,
HS-FET turns on for
a
fixed
MPQ8632D-6_MPQ8632D-12 Rev. 1.01
www.MonolithicPower.com
13
3/9/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
MPQ8632D-6, MPQ8632D-12 ― 6A/12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER
As the output current increases from the light
physically smaller LC filter components to reduce
the PCB footprint.
load condition, the current modulator regulates
the operating period that becomes shorter. The
HS-FET turns ON more frequently. Hence, the
switching frequency increases correspondingly.
The output current reaches the critical level when
the current modulator time decreases to zero.
Determine the critical output current level as
follows:
Jitter and FB Ramp Slope
Figure 4 and Figure 5 show jitter occurring in
both PWM mode and skip mode. When there is
noise on the VFB descending slope, the HS-FET
ON time deviates from its intended point and
produces jitter and influences system stability.
The VFB ripple’s slope steepness dominates the
noise immunity though its magnitude has no
direct effect.
(V − VOUT )× VOUT
IN
(2)
IOUT
=
2×L ×FSW × V
IN
Where FSW is the switching frequency.
The IC turns into PWM mode once the output
current exceeds the critical level. After that, the
switching frequency stays fairly constant over the
output current range.
Switching Frequency
Selecting the switching frequency requires
trading off between efficiency and component
size. Low frequency operation increases
efficiency by reducing MOSFET switching losses,
but requires larger inductor and capacitor values
to minimize the output voltage ripple.
Figure 4—Jitter in PWM Mode
For MPQ8632D-6/MPQ8632D-12 ， set the on
time using the FREQ pin to set the frequency for
steady state operation at CCM.
The MPQ8632D-6/MPQ8632D-12 uses adaptive
constant-on-time (COT) control, though the IC
lacks a dedicated oscillator. Connect the FREQ
pin to the IN pin through the resistor (RFREQ) so
that the input voltage is feed-forwarded to the
one-shot on-time timer. When operating in steady
state at CCM, the duty ratio stays at VOUT/VIN, so
the switching frequency is fairly constant over the
input voltage range. Set the switching frequency
as follows:
Figure 5—Jitter in Skip Mode
Ramp with a Large ESR Capacitor
Using POSCAPs or other large-ESR capacitors
as the output capacitor results in the ESR ripple
dominating the output ripple. The ESR also
significantly influences the VFB slope. Figure 6
shows the simplified equivalent circuit in PWM
mode with the HS-FET off and without an
external ramp circuit.
106
(3)
FSW (kHz) =
6.1×RFREQ(kΩ)
V (V)
IN
×
+ TDELAY(ns)
V (V)−0.4
VOUT(V)
IN
Where TDELAY is the comparator delay of about
5ns.
Typically, the MPQ8632D-6/MPQ8632D-12 is set
to 200kHz to 1MHz applications. It is optimized to
operate at high switching frequencies at high
efficiency high switching frequencies allow for
MPQ8632D-6_MPQ8632D-12 Rev. 1.01
www.MonolithicPower.com
14
3/9/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
MPQ8632D-6, MPQ8632D-12 ― 6A/12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER
VIN − VOUT
R4 × C4
R1//R2
⎛
⎜
⎞
⎟
SW
FB
(7)
VRAMP
=
× TON ×
L
VOUT
R1//R2 + R9
⎝
⎠
ESR
POSCAP
The VFB ripple’s descending slope then follows:
R1
R2
VRAMP
TOFF
− VOUT
R4×C4
(8)
VSLOPE1
=
=
Equation 8 shows that if there is instability in
PWM mode, reduce either R4 or C4. If C4 is
irreducible due to equation 5 limitations, then
reduce R4. For a stable PWM operation, design
Figure 6—Simplified Circuit in PWM Mode
without External Ramp Compensation
To realize the stability without an external ramp,
usually select the ESR value as follows:
Vslope1 based on equation 9.
TSW
TON
2
2×L×COUT
+
−RESR ×COUT
IOUT ×10−3
TSW − TON
TSW
TON
2
0.7× π
(9)
−VSLOPE1
≥
× VOUT +
+
0.7× π
(4)
RESR
≥
COUT
Where IOUT is the load current.
Where TSW is the switching period.
In skip mode, The VFB ripple’s descending slope
is almost same whether the external ramp is
used or not. Figure 8 shows the simplified circuit
in skip mode when both the HS-FET and LS-FET
are off.
Ramp with a Small ESR Capacitor
Use an external ramp when using ceramic output
capacitors, because the ESR ripple is not high
enough to stabilize the system.
VOUT
L
VOUT
SW
R1
FB
R4 C4
ROUT
R1
R2
COUT
IR4
IC4
R2
R9
IFB
Ceramic
FB
Figure 8—Simplified Circuit in skip Mode
Determine the VFB ripple’s descending slope in
skip mode as follows:
Figure 7—Simplified Circuit in PWM Mode
with External Ramp Compensation
− VREF
(10)
VSLOPE2
=
[(R1+ R2) // ROUT ]×COUT
Figure 7 shows the simplified circuit in PWM
mode with the HS-FET OFF and an external
ramp compensation circuit (R4, C4). Design the
external ramp based on the inductor ripple
current. Select C4, R9, R1 and R2 to meet the
following condition:
Where ROUT is the equivalent load resistor.
Figure 5 shows that VSLOPE2 in skip mode is lower
than that is in PWM mode, so it is reasonable
that the jitter in skip mode is larger To achieve
less jitter during ultra light load condition, reduce
R1 and R2, but that will decrease the light load
efficiency.
1
1
5
R1×R2
R1+ R2
⎛
⎜
⎞
⎟
(5)
<
×
+ R9
2π×FSW ×C4
⎝
⎠
Where:
(6)
IR4 = IC4 + IFB ≈ IC4
Then estimate the ramp on VFB as:
MPQ8632D-6_MPQ8632D-12 Rev. 1.01
www.MonolithicPower.com
15
3/9/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
MPQ8632D-6, MPQ8632D-12 ― 6A/12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER
Configuring the EN Control
Soft Start/Stop
The regulator turns on when En goes high;
conversely it turns off when EN goes low. Do not
float the pin.
The MPQ8632D-6/MPQ8632D-12 employs a soft
start/stop (SS) mechanism to ensure a smooth
output during power-up and power shutdown.
When the EN pin goes high, an internal current
source (20μA) charges the SS capacitor. The SS
capacitor voltage takes over the REF voltage to
the PWM comparator. The output voltage
smoothly ramps up with the SS voltage. Once the
SS voltage reaches the REF voltage, it continues
ramping up while VREF takes over the control of
the PWM comparator. At this point, soft start
finishes and the device enters steady state
operation.
When the EN pin becomes low, the SS capacitor
voltage is discharged through a 10uA internal
current source. Once the SS voltage reaches
REF voltage, it takes over the control of the PWM
comparator. The output voltage will decrease
smoothly with SS voltage until zero level.
For automatic start-up, pull the EN pin up to input
voltage through a resistive voltage divider.
Choose the values of the pull-up resistor (RUP
from the IN pin to the EN pin) and the pull-down
resistor (RDOWN from the EN pin to GND) to
determine the automatic start-up voltage:
(RUP + RDOWN
)
(11)
V
= 1.5×
(V)
IN−START
RDOWN
For example, for RUP=100kꢀ and RDOWN=51kꢀ,
the VIN-START is set at 4.44V.
To reduce noise, add a 10nF ceramic capacitor
from EN to GND.
An internal zener diode on the EN pin clamps the
EN pin voltage to prevent run away. The
maximum pull up current assuming the worst
case 6V for the internal zener clamp should be
less than 1mA.
Determine the SS capacitor value as follows:
TSS ms ×I μA
(
SS
(14)
CSS nF =
(
)
VREF
V
(
)
Therefore, when driving EN with an external logic
signal, use an EN voltage less than 6V. When
connecting EN to IN through a pull-up resistor or
a resistive voltage divider, select a resistance
that ensures a maximum pull-up current less than
1mA.
If the output capacitors are large, then avoid
setting a short SS time otherwise it would risk
hitting the current limit during SS. Use a
minimum value of 4.7nF if the output capacitance
value exceeds 330μF.
If using a resistive voltage divider and VIN
exceeds 6V, then the minimum resistance for the
pull-up resistor RUP should meet:
Pre-Bias Startup
The MPQ8632D-6/MPQ8632D-12 has been
designed for monotonic startup into pre-biased
loads. If the output is pre-biased to a certain
voltage during startup, the IC will disable
switching for both high-side and low-side
switches until the voltage on the soft-start
capacitor exceeds the sensed output voltage at
the FB pin.
V − 6V
6V
IN
(12)
−
≤1mA
RUP
RDOWN
With only RUP (the pull-down resistor, RDOWN, is
not connected), then the VCC UVLO threshold
determines VIN-START, so the minimum resistor
value is:
Power Good (PG)
V − 6V
1mA
The MPQ8632D-6/MPQ8632D-12 has a power-
good (PG) output. The PG pin is the open drain
of a MOSFET. Connect it to VCC or some other
voltage source that measures less than 5.5V
through a pull-up resistor (typically 100kꢀ).
Recommend a 10nF capacitor from PG to GND
when the PG pull up resistor is <100kꢀ. After
VCC is ready, the MOSFET turns on so that the
PG pin is pulled to GND before the SS is ready.
IN
(13)
RUP
≥
(Ω)
A typical pull-up resistor is 100kꢀ.
External VCC bias
An external 5V VCC bias can disable the internal
LDO, in this case, Vin can be as low as 2.5V.
MPQ8632D-6_MPQ8632D-12 Rev. 1.01
www.MonolithicPower.com
16
3/9/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
MPQ8632D-6, MPQ8632D-12 ― 6A/12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER
After the FB voltage reaches 90% of the REF
Over -Voltage Protection (OVP)
voltage, the PG pin is pulled high after a 2.5ms
delay.
The MPQ8632D-6/MPQ8632D-12 monitors the
output voltage using the FB pin connected to the
tap of a resistor divider to detect over-voltage.
MPQ8632D-6 and MPQ8632D-12 provide non-
latch OVP mode.
When the FB voltage drops to 85% of the REF
voltage or exceeds 120% of the nominal REF
voltage, the PG pin is pulled low.
If the FB voltage exceeds the nominal REF
voltage but remains lower than 120% of the REF
voltage (0.611V), both MOSFETs are off.
If the input supply fails to power the MPQ8632D-
6/MPQ8632D-12, the PG pin is also pulled low
even though this pin is tied to an external DC
source through a pull-up resistor (typically
100kꢀ).
If the FB voltage exceeds 120% of the REF
voltage but remains below 130%, the LS-FET
turns on while the HS-FET remains off. The LS-
FET remains on until the FB voltage drops below
110% of the REF voltage or the low-side
negative current limit is hit.
Over-Current Protection (OCP)
The MPQ8632D-6/MPQ8632D-12 features TWO
current limit levels for over-current conditions:
low-side valley current limit and low-side negative
current limit.
If the FB voltage exceeds 130% of the REF
voltage, these parts enter a non-latch off mode.
Once the FB voltage comes back to the
reasonable value, they will exit this OVP mode
and operate normally again.
Low-Side Valley Current Limit: The device
monitors the inductor current during the LS-FET
ON state. When ILIM=1 and at the end of the
OFF time, the LS-FET sourcing current is
compared to the internal positive-valley–current
limit. If the valley current limit is less than the LS-
FET sourcing current, the HS-FET remains OFF
and the LS-FET remains ON for the next ON time.
When the LS-FET sourcing current drops below
the valley current limit, the HS-FET turns on
again.
UVLO protection
The MPQ8632D-6/MPQ8632D-12 has under-
voltage lock-out protection (UVLO). When the
VCC voltage exceeds the UVLO rising threshold
voltage,
the
MPQ8632D-6/MPQ8632D-12
powers up. It shuts off when the VCC voltage
falls below the UVLO falling threshold voltage.
This is non-latch protection.
These parts enter OCP mode if the LS-FET
sourcing valley current exceeds the valley current
limit for about 40us. During OCP, the device tries
to recover from the over-current fault with hiccup
mode: the chip disables the output power stage,
discharges the soft-start capacitor and then
automatically retries soft-start. If the over-current
condition still holds after soft-start ends, the
device repeats this operation cycle until the over-
current conditions disappear and then output
rises back to regulation level. OCP offers non-
latch protection.
The MPQ8632D-6/MPQ8632D-12 is disabled
when the VCC voltage falls below 3.3 V. If an
application requires a higher UVLO threshold,
use the two external resistors connected to the
EN pin as shown in Figure 9 to adjust the startup
input voltage. For best results, use the enable
resistors to set the input voltage falling threshold
(VSTOP) above 3.6 V. Set the rising threshold
(VSTART) to provide enough hysteresis to account
for any input supply variations.
Low-Side Negative Current Limit: If the sensed
LS-FET negative current exceeds the negative
current limit, the LS-FET turns off immediately
and stays OFF for the remainder of the OFF
period. In this situation, both MOSFETs are OFF
until the end of a fixed interval. The HS-FET body
diode conducts the inductor current for the fixed
time.
MPQ8632D-6_MPQ8632D-12 Rev. 1.01
3/9/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
www.MonolithicPower.com
17
MPQ8632D-6, MPQ8632D-12 ― 6A/12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER
IN
RUP
EN Comparator
EN
RDOWN
Figure 9—Adjustable UVLO Threshold
Thermal Shutdown
The MPQ8632D-6/MPQ8632D-12 has thermal
shutdown protection. The IC internally monitors
the junction temperature. If the junction
temperature exceeds the threshold value
(minimum 150ºC), the converter shuts off. This is
a non-latch protection. There is about 25ºC
hysteresis. Once the junction temperature drops
to about 125ºC, it initiates a soft startup.
MPQ8632D-6_MPQ8632D-12 Rev. 1.01
3/9/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
www.MonolithicPower.com
18
MPQ8632D-6, MPQ8632D-12 ― 6A/12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER
APPLICATION INFORMATION
balance between high quiescent current loss and
FB noise sensitivity. Choose R2 within 5kꢀ to
50kꢀ, using a larger R2 when VOUT is low, and a
smaller R2 when VOUT is high. Determine the
value of R1 as follows:
Setting the Output Voltage-Large ESR
Capacitors
For applications that electrolytic capacitor or POS
capacitor with a large ESR is set as output
capacitors. The feedback resistors—R1 and R2
as shown in Figure 10—set the output voltage.
R2
(16)
R1=
VFB(AVG)
R2
−
VOUT − VFB(AVG) R4 + R9
SW
L
VOUT
Where VFB(AVG) is the average FB voltage. VFB(AVG)
varies with the VIN, VOUT, and load condition,
where the load regulation is strictly related to the
FB
ESR
POSCAP
R1
R2
V
V
FB(AVG). Also the line regulation is related to the
FB(AVG); improving the load or line regulation
involves a lower VRAMP that meets equation 9.
For PWM operation, estimate VFB(AVG) from
equation 17.
Figure10—Simplified POSCAP Circuit
1
2
R1//R2
First, choose a value for R2 that balances
between high quiescent current loss (low R2) and
high noise sensitivity on FB (high R2). A typical
value falls within 5kꢀ to 50kꢀ, using a
comparatively larger R2 when VOUT is low, and a
smaller R2 when VOUT is high. Then calculate R1
as follows, which considers the output ripple:
(17)
VFB(AVG) = VREF
+
× VRAMP ×
R1//R2 + R9
Usually, R9 is 0ꢀ, though it can also be set
following equation 18 for better noise immunity. It
should also be less than 20% of R1//R2 to
minimize its influence on VRAMP
.
1 R1×R2
(18)
R9 < ×
5 R1+ R2
1
VOUT − ×ΔVOUT − VREF
2
Using equations 16 and 17 to calculate the
output voltage can be complicated. To simplify
the R1 calculation in equation 16, add a DC-
blocking capacitor, CDC, to filter the DC influence
from R4 and R9. Figure 12 shows a simplified
circuit with external ramp compensation and a
DC-blocking capacitor. The addition of this
capacitor, simplifies the R1 calculation as per
equation 19 for PWM mode operation.
(15)
R1 =
×R2
VREF
Where ΔVOUT is the output ripple determined by
equation 24.
Setting the Output Voltage-Small ESR
Capacitors
SW
L
VOUT
1
R4
C4
R9
VOUT − VREF
−
× VRAMP
R1
R2
FB
2
(19)
R1=
×R2
Ceramic
1
2
VREF
+
× VRAMP
For best results, select a CDC Value at least 10×
C4 for better DC blocking performance, but
smaller than 0.47µF account for start-up
performance. To use a larger CDC for better FB
noise immunity, reduce R1 and R2 to limit effects
on system start-up. Note that even with Cdc, the
Figure11—Simplified Ceramic Capacitor
Circuit
When using a low ESR ceramic capacitor on the
output, add an external voltage ramp to the FB
pin consisting of R4 and C4.The ramp voltage,
VRAMP, and the resistor divider influence the
output voltage as shown in Figure 11. Calculate
load and line regulation are still related to VRAMP
.
VRAMP as shown in equation 7. Select R2 to
MPQ8632D-6_MPQ8632D-12 Rev. 1.01
www.MonolithicPower.com
19
3/9/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
MPQ8632D-6, MPQ8632D-12 ― 6A/12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER
The worst-case condition occurs at VIN = 2VOUT
where:
,
SW
FB
L
VOUT
IOUT
4 FSW × CIN
1
(23)
ΔV
=
×
IN
R4
C4
CDC
R1
R2
Ceramic
Output Capacitor
The output capacitor maintains the DC output
voltage. Use ceramic capacitors or POSCAPs.
Estimate the output voltage ripple as:
Figure12—Simplified Ceramic Capacitor
Circuit with DC Blocking Capacitor
VOUT
V
1
ΔVOUT
=
×(1− OUT )×(RESR
+
)
FSW ×L
V
8×FSW × COUT
IN
Input Capacitor
(24)
The input current to the step-down converter is
discontinuous, and therefore, requires
When using ceramic capacitors, the capacitance
dominates the impedance at the switching
frequency. The capacitance also dominates the
output voltage ripple. For simplification, estimate
the output voltage ripple as:
a
capacitor to supply the AC current to the step-
down converter while maintaining the DC input
voltage. Use ceramic capacitors for best
performance. During layout, Place the input
capacitors as close to the IN pin as possible.
VOUT
8×FSW2 ×L× COUT
VOUT
(25)
ΔVOUT
=
×(1−
)
V
The capacitance can vary significantly with
temperature. Use capacitors with X5R and X7R
ceramic dielectrics because they are fairly stable
over a wide temperature range.
IN
The ESR only contributes minimally to the output
voltage ripple, thus requiring an external ramp to
stabilize the system. Design the external ramp
with R4 and C4 as per equation 5, 8 and 9.
The capacitors must also have a ripple current
rating that exceeds the converter’s maximum
input ripple current. Estimate the input ripple
current as follows:
The ESR dominates the switching-frequency
impedance for POSCAPs,. The ESR ramp
voltage is high enough to stabilize the system.
thus eliminating the need for an external ramp.
Select a minimum ESR value around 12mꢀ to
ensure stable operation. For simplification, the
output ripple can be approximated as:
VOUT
VOUT
(20)
ICIN = IOUT
×
×(1−
)
V
V
IN
IN
The worst-case condition occurs at VIN = 2VOUT
,
where:
VOUT
V
IOUT
(26)
ΔVOUT
=
×(1− OUT )×RESR
ICIN
=
(21)
FSW ×L
V
IN
2
For simplification, choose an input capacitor with
an RMS current rating that exceeds half the
maximum load current.
Inductor
The inductor supplies constant current to the
output load while being driven by the switching
input voltage. A larger value inductor results in
less ripple current and lower output ripple voltage,
but is larger physical size, has a higher series
resistance, and/or lower saturation current.
Generally, select an inductor value that allows
the inductor peak-to-peak ripple current to 30%
to 40% of the maximum switch current limit. Also,
design for a peak inductor current that is below
the maximum switch current limit. Calculate the
inductance value as:
The input capacitance value determines the
converter input voltage ripple. Select a capacitor
value that meets any input voltage ripple
requirements.
Estimate the input voltage ripple as follows:
IOUT
VOUT
VOUT
(22)
ΔV =
×
×(1−
)
IN
FSW ×CIN
V
V
IN
IN
MPQ8632D-6_MPQ8632D-12 Rev. 1.01
www.MonolithicPower.com
20
3/9/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
MPQ8632D-6, MPQ8632D-12 ― 6A/12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER
inductor current can be calculated as:
VOUT
FSW × ΔIL
VOUT
(27)
L =
×(1−
)
VOUT
VOUT
V
IN
(28)
ILP = IOUT
+
×(1−
)
2×FSW ×L
V
IN
Where ΔIL is the peak-to-peak inductor ripple
current.
Table 1 lists a few highly-recommended high-
efficiency inductors.
Choose an inductor that will not saturate under
the maximum inductor peak current. The peak
Table 1—Inductor Selection Guide
Inductance DCR Current
Switching
Frequency
(kHz)
500
Dimensions
(mΩ) Rating (A) L x W x H (mm3)
Part Number
Manufacturer
(µH)
744325072
FDU1250C-1R0M
FDA1055-1R5M
744325180
FDA1055-2R2M
FDA1055-3R3M
HC7-3R9-R
Wurth
TOKO
TOKO
Wurth
TOKO
TOKO
Cooper
0.72
1
1.5
1.8
2.2
3.3
3.9
1.35
1.72
2.8
35
31.3
24
10.2 x 10.5 x 4.7
13.3 x 12.1 x 5
11.6 x 10.8 x 5.5
10.2 x 10.5 x 4.7
11.6 x 10.8 x 5.5
11.6 x 10.8 x 5.5
13.8 x 13 x 5.5
500
500
500
500
500
500
3.5
18
3.94
5.92
7.9
20.6
15.6
10.6
Typical Design Parameter Tables
Table 4—MPQ8632D-6, FSW=500kHz, VIN=12V
VOUT
(V)
L
(μH)
R1
(kꢀ)
R2
(kꢀ)
R4
(kꢀ) (pF)
750 220
C4
R7
(kꢀ)
The following tables include recommended
component values for typical output voltages (1V,
2.5V, 3.3V) and switching frequency (500kHz).
Refer to Tables 2-3 for design cases without
external ramp compensation and Tables 4-5 for
design cases with external ramp compensation.
An external ramp is not needed when using high-
ESR capacitors, such as electrolytic or
POSCAPs. Use an external ramp when using
low-ESR capacitors, such as ceramic capacitors.
For cases not listed in this datasheet, an excel
1
1
13.7
66.5
95.3
20
20
20
357
887
2.5
3.3
2.2
3.3
1000 220
1200 220
1200
Table 5—MPQ8632D-12, FSW=500kHz, VIN=12V
VOUT
(V)
L
(μH)
R1
(kꢀ)
R2
(kꢀ)
R4
(kꢀ) (pF)
750 220
C4
R7
(kꢀ)
1
0.72
1.5
13.7
66.5
95.3
20
20
20
357
887
2.5
3.3
1000 220
1200 220
spreadsheet
provided
by
local
sales
1.8
1200
representatives can assist with the calculations.
Table 2—MPQ8632D-6, FSW=500kHz, VIN=12V
VOUT
(V)
L
(μH)
R1
(kꢀ)
R2
(kꢀ)
R7
(kꢀ)
1
1
13.3
63.4
91
20
20
20
357
887
2.5
3.3
2.2
3.3
1200
Table 3—MPQ8632D-12, FSW=500kHz, VIN=12V
VOUT
(V)
L
(μH)
R1
(kꢀ)
R2
(kꢀ)
R7
(kꢀ)
1
0.72
1.5
13.3
63.4
91
20
20
20
357
887
2.5
3.3
1.8
1200
MPQ8632D-6_MPQ8632D-12 Rev. 1.01
www.MonolithicPower.com
21
3/9/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
MPQ8632D-6, MPQ8632D-12 ― 6A/12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER
LAYOUT RECOMMENDATION
1. Place high current paths (GND, IN, and SW)
very close to the device with short, direct and
wide traces.
2. Two-layer IN copper layers are required to
achieve better performance. Respectively put
at least a decoupling capacitor on either side
of the IC that has VIN pin and as close to the
IN and GND pins as possible. Also, several
vias with 18mil diameter and 8mil hole- size
are recommended to be placed under the
device and are required near input capacitors
to help on the thermal dissipation, also
reduce the parasitic inductance.
Top Layer
Figure 14—PCB Layout Guide
Design Example
Below is a design example following the
application guidelines for the specifications:
3. Put a decoupling capacitor as close to the
VCC and AGND pins as possible.
4. Keep the switching node (SW) plane as small
as possible and far away from the feedback
network.
Table 6—Design Example
VIN
VOUT
FSW
4.5-18V
1V
500kHz
5. Place the external feedback resistors next to
the FB pin. Make sure that there are no vias
on the FB trace. The feedback resistors
should refer to AGND instead of PGND.
The detailed application schematic is shown in
Figure 14. The typical performance and circuit
waveforms have been shown in the Typical
Performance Characteristics section. For more
device applications, please refer to the related
Evaluation Board Datasheets.
6. Keep the BST voltage path (BST, C3, and
SW) as short as possible.
7. Keep FREQ signal away from noise signals,
like SW, BST and VIN plane and vias close to
the MP8632D VIN pins. The VIN pin of
frequency setting resistor (RFREQ) should
connect to a quiet VIN node before input
decoupling capacitor.
8. Strongly recommend a four-layer layout to
improve thermal performance.
BST
VIN
IN
C1
R
FREQ
C3
L1
SW
VOUT
FREQ
R1
R4
C4
MPQ8632D
EN
ON/OFF
C2
FB
SS
VCC
C5
PG
C6
R2
PGND
AGND
Figure 13—Schematic for PCB Layout Guide
MPQ8632D-6_MPQ8632D-12 Rev. 1.01
www.MonolithicPower.com
22
3/9/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
MPQ8632D-6, MPQ8632D-12 ― 6A/12A, 18V, SYNCHRONOUS STEP-DOWN CONVERTER
PACKAGE INFORMATION
QFN(3X4mm)
° TYP.
°
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE
MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10
MILLIMETERS MAX.
4) JEDEC REFERENCE IS MO-220.
5) DRAWING IS NOT TO SCALE.
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MPQ8632D-6_MPQ8632D-12 Rev. 1.01
www.MonolithicPower.com
23
3/9/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
相关型号：
©2020 ICPDF网 联系我们和版权申明