MP86963DUT-LF-Z [MPS]
Half Bridge Based Peripheral Driver, PDSO18, TQFN-18;
| 型号： | MP86963DUT-LF-Z |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Half Bridge Based Peripheral Driver, PDSO18, TQFN-18 驱动 光电二极管 接口集成电路 |
| 文件： | 总11页 (文件大小：379K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP86963
High Efficiency, 20A, 27V Intelli-PhaseTM Solution
(Integrated HS/LS FETs and Driver) in a 5x5mm QFN
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP86963 is a monolithic Half Bridge with
built-in internal power MOSFETs and gate
driver. It achieves 20A continuous output
current over a wide input supply range.
•
•
•
•
•
•
•
•
Wide 4.5V to 21V Operating Input Range
20A Output Current
Simple Logic Interface (3.3V)
Operate from 100kHz to 1MHz
Accepts 3-state PWM Input
Suitable for single-/multi-phase operation
Available in a 5mm x 5mm TQFN Package
ROHS6 Compliant
Integrating the Driver and MOSFETs results in
high efficiency due to optimal dead time control
and parasitic inductance reduction.
The MP86963 is a Monolithic IC designed to
drive up to 20A per phase. Housed in a very
small 5x5mm TQFN Packge, this device can be
operated from 100kHz to 1MHz operation.
APPLICATIONS
•
•
•
Power modules
Notebook, Core Voltage
Graphic Card Core Regulators
The IC is intended to work with 3.3V tri-state
output controllers.
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Quality Assurance. “MPS” and “The
Future of Analog IC Technology” are Registered Trademarks of Monolithic
Power Systems, Inc.
The MP86963 is ideal for notebook applications
where efficiency and small size are a premium.
This Product is Patent Pending.
TYPICAL APPLICATION
V
IN
4.5V-21V
100
95
C
IN
9
90
IN
4
85
ON/OFF
EN
8
BST
SW
7
VCC IO
80
C6
100nF
L
0.8V to 1.2V @ 20A
75
70
65
60
55
50
6
5
PWM
2
C
OUT
VCC
Cs
1 F
MP86963
V =12V
IN
10-18
SYNC
GND
V
=1.2V
OUT
AGND
3
V
CC
5V
2
4
6
8
10 12 14 16 18 20
OUTPUT CURRENT (A)
MP86963 Rev.1.22
12/26/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
1
MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN
ORDERING INFORMATION
Part Number*
Package
Top Marking
Free Air Temperature(TA)
MP86963DUT
5x5 TQFN
86963UT
-40°C to +85°C
* For Tape & Reel, add suffix –Z (e.g. MP86963DUT–Z);
For RoHS compliant packaging, add suffix –LF (e.g. MP86963DUT–LF–Z)
PACKAGE REFERENCE
PIN 1 ID
1
18 GND
N/C
VCC
IN
IN
IN
IN
GND
GND
GND
GND
2
17
GND
SW
SW
SW
SW
16
3
4
5
6
7
8
9
GND
AGND
EN
15
GND
14
GND
SYNC
PWM
VCC IO
BST
13
GND
12
GND
11
GND
10
GND
IN
EXPOSED PAD
CONNECT TO PIN
Thermal Resistance (4)
5x5 TQFN...............................33....... 8.... °C/W
θJA
θJC
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage VIN ....................................... 27V
VSW(DC) .................................-0.3V to VIN +0.3V
VSW(20ns) ....................................-3V to VIN +3V
VBST ......................................................VSW + 6V
All Other Pins..................................-0.3V to +6V
Continuous Power Dissipation (TA = +25°C) (2)
............................................................. 3.8W
Junction Temperature...............................150°C
Lead Temperature ....................................260°C
Storage Temperature............... -65°C to +150°C
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)-
TA)/ θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
Recommended Operating Conditions (3)
Supply Voltage VIN ...........................4.5V to 21V
VCC Driver Voltage………………….4.5V to 5.5V
Operating Junct. Temp (TJ)...... -40°C to +125°C
MP86963 Rev.1.22
12/26/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
2
MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN
ELECTRICAL CHARACTERISTICS
VIN = 12V, TA = +25°C, unless otherwise noted.
Parameters
Symbol Condition
ICC_Stdby VCC =5V, PWM=EN=LO
IIN (Off) VCC = 0V
Min
Typ
550
1
Max
610
5
Units
μA
μA
μA
ns
ICC Standby
IIN (Shutdown)
IIN Standby
IIN_Stdby VCC =5V, PWM=EN=LO
IOUT = 20A
1
Rise Time
5
Fall Time
IOUT = 20A
3
ns
Minimum On-Time
Dead-Time Rising
Dead-Time Falling
55
5
ns
ns
10
ns
VCC Under Voltage Lockout Threshold
Rising
3.7
4.2
V
VCC Under Voltage Lockout Threshold
Hysteresis
470
-14
mV
SYNC Pull-Up Current
SYNC Logic High Voltage
SYNC Logic Low Voltage
EN Input Low Voltage
En Input High Voltage
PWM Input
ISYNC
SYNC=0V
μA
V
V
V
V
2
2
0.4
0.4
VPWM=3.3V
PWM=0V
370
-370
3.3
μA
μA
V
Input Current
IPWM
V
VCCIO
2.9
3.6
PWM Low to Tri-State Threshold
PWM Tri-State to High Threshold
PWM High to Tri-State Threshold
PWM Tri-State to Low Threshold
1.10
2.25
2.10
0.75
V
V
V
V
VCC=5V,
Temperature=25°C
Tri-State Shutdown Holdoff Time
tTSSHD
100
ns
UG/LG Three-State Propagation Delay
USW Turn-Off Propagation Delay
LSW Turn-Off Propagation Delay
USW Turn-On Propagation Delay
LSW Turn-On Propagation Delay
tPTS
tPDUL
tPDLL
tPDUH
tPDLH
20
40
25
30
50
ns
ns
ns
ns
ns
VCC=5V
VCC=5V
VCC=5V
VCC=5V
MP86963 Rev.1.22
www.MonolithicPower.com
3
12/26/2013
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN
PWM
t
t
PDUH
PDLH
t
TSSHD
SW
0V
V
OUT
t
PDUL
t
PDLL
Figure 1—Timing Diagram
PIN FUNCTIONS
Pin #
Name
Description
Not Connected.
1
2
3
NC
VCC
Low-Side Driver Bias Supply. Decouple with a 1µF ceramic capacitor.
Signal Ground.
AGND
Active High On/Off Control. Pulling this Pin Low forces the SW Pin to be in a high
impedance state.
4
5
EN
Leaving this pin Open enables theLower Synchronous Switch. Pulling it Low forces
the Lower Switch into Diode Emulation mode.
SYNC
Pulse Width Modulation Control. Accepts three-state input. Force PWM to midstate or
open to place SW into high impedance state.
6
7
PWM
VCC IO
Reference voltage that connects to PWM driver supply.
Bootstrap. This capacitor is needed to drive the power switch’s gate above the supply
voltage. It is connected between SW and BST pins to form a floating supply across
the power switch driver.
8
BST
IN
9
Supply Voltage. CIN is needed to prevent large voltage spikes from appearing at the
input.
Exposed Pad
10–18
Exposed Pad
GND
SW
Power Ground.
Exposed Pad
Switch Output. These pins are fused together.
MP86963 Rev.1.22
12/26/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
4
MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VCC = 5V, VOUT = 1.2V, TA = +25ºC, unless otherwise noted.
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
2
4
6
8
10 12 14 16 18 20
2
4
6
8
10 12 14 16 18 20
2
4
6
8
10 12 14 16 18 20
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
4.5
4
3.5
3
4
3.5
3
3.5
3
2.5
2
2.5
2
2.5
2
1.5
1
1.5
1
1.5
1
0.5
0
0.5
0
0.5
0
0
5
10
15
20
0
5
10
15
20
0
5
10
15
20
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
I
=15A
I
=15A, Fsw=600kHz
OUT
OUT
2.35
2.3
4
3.5
3
4.5
4
2.25
2.2
3.5
3
1.0MHz
600kHz
20A
15A
2.5
2
2.15
2.1
2.5
2
1.5
1
300kHz
2.05
2
1.5
1
0.5
0
1.95
1.9
0.5
0
300 400 500 600 700 800 900 1000
SWITCHING FREQUENCY (kHz)
8
10 12 14 16 18 20
INPUT VOLTAGE (V)
0.8
1
1.2 1.4 1.6 1.8
2
2.2
OUTPUT VOLTAGE (V)
MP86963 Rev.1.22
12/26/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
5
MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VCC = 5V, VOUT = 1.2V, TA = +25ºC, unless otherwise noted.
Temperature Rise vs.
SW Rising Edge Dead Time
SW Falling Edge Dead Time
I
= 15A
I
= 15A
OUT
OUT
Output Current
No airflow
70
60
50
40
30
20
10
0
600kHz
V
V
SW
1V/div.
SW
500mV/div.
300kHz
0
5
10
15
20
OUTPUT CURRENT (A)
Output Waveform
SOA Waveform
I
= 20A
V
= 19V, V = 1.2V
OUT
OUT
IN
I
= 20Α to 80A, F = 600kHz
OUT
SW
V
SW
10V/div.
V
OUT
1V/div.
V
SW
5V/div.
I
OUT
25A/div.
MP86963 Rev.1.22
12/26/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
6
MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN
EFFICIENCY MEASUREMENT SETUP
MP86963 Rev.1.22
12/26/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
7
MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN
BLOCK DIAGRAM
BST
IN
V
CC
EN
V
EN
HGate
EN
V
cc
IO
CC
VOUT
10.8
SW
PWM
PWM
Logic
V
IO
CC
PWM
Tri-State
5.4
VCC
V
cc
150
Diode
Emulation
LGate
Logic
SYNC
M2
EN
LGate
GND
Figure 2—Function Block Diagram
MP86963 Rev.1.22
12/26/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
8
MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN
OPERATION
The MP86963 is a 20A Monolithic Half Bridge
driver with MOSFETs ideally suited for single-
/multi-phase Buck regulators.
3) The recommended external BST cap is 100nF.
Do not use a capacitance value lower than
100nF. Place a 1.0Ω resistor between the BST
capacitor and BST pin for optimized performance.
Once the EN, VIN, VCCIO, VCC and VBST signals
are sufficiently high, operation begins. BST
voltage has a typical rising UVLO of 2.2V and a
falling UVLO of 2.0V. When BST is below the
UVLO voltage, the device will be off.
4) Do not place via on the pad or on the pin
footprint. Doing so may cause soldering issue
during the assembling process. Use Figure 3 as
a via placement reference.
MP86963 can work with most PWM controllers.
The device accepts PWM signal from 100kHz up
to 1MHz. There is an internal resistor divider to
put PWM voltage to tri-state region if the PWM
pin is open.
5) Connect IN, SW and GND to large copper
area and use vias to cool the chip to improve
thermal performance and long-term reliability.
See Figure 4 as an example.
Internally, SYNC is tied to VCC through a resistor.
By default, the device will operate in synchronous
mode. To enter Diode Emulation mode, drive
SYNC pin LOW.
Startup and Shutdown Sequence
MP86963 can work with any startup or shutdown
sequencing combination of VIN, VCC, VCCIO and
EN. If PWM signal is present, the MP86963 will
start working whenever VIN, VCC, VCCIO and EN
are ready. On the other hand, if any of these
signals is not ready, the MP86963 will stop
working. However, it is recommended to turn on
and turn off the device through the EN pin.
Figure 3—Via Placement Guideline
Do not put via on the device’s pad footprint or pin
footprint to avoid assembly issue. Use as many
vias as possible to cool down the device.
PCB Layout Guideline
PCB layout is very important to achieve stable
operation. Please follow these guidelines to
achieve optimal performance.
6) Place the VCC decouple capacitor close to the
IC. Connect AGND and PGND at the point of
VCC capacitor's ground connection.
1) Keep the path of switching current short and
minimize the loop area formed by input capacitor.
Keep the connection between SW pin and input
power ground as short and wide as possible.
Recommended SMT Setting
Stencil thickness: 0.12mm
EP Pad Opening: (Stencil opening : Real PCB
Size)
2) Always place some input bypass ceramic
capacitors next to the device and on the same
layer as the device. Do not put all of the input
bypass capacitors on the back side of the device.
Use as many vias and input voltage planes as
possible to reduce the switching spike. BST
capacitor and VCC capacitor should also be as
close to the device as possible.
Length: 0.85:1
Width: 1:1
Note: The EP pad for Intelli-Phase are IN,
SW and GND pad on the bottom.
Solder type: #3
MP86963 Rev.1.22
12/26/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
9
MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN
CVCC
RBST
Input Capacitors
(Vin Plane)
CBST
(SW Plane)
Intelli
Phase
(GND Plane)
Inductor
Output
Capacitors
Figure 4—Copper Area Guideline
Use large copper area, many vias and many IN, SW and GND inner layer planes to achieve optimal
thermal performance.
MP86963 Rev.1.22
12/26/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
10
MP86963 –20A, 27V INTELLI-PHASETM SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN
PACKAGE INFORMATION
FCTQFN18L (EXPOSED PAD)
2.80
BSC
1.30
1.50
PIN 1 ID
SEE DETAIL A
4.90
5.10
0.50
0.70
PIN 1 ID
MARKING
0.40
18
1
0.60
0.40
0.60
4.90
0.59 1.77 2.95 4.13
BSCBSCBSCBSC
0.50
5.10
PIN 1 ID
INDEX AREA
BSC
0.18
0.30
10
9
9
0.30
0.40
TOP VIEW
BOTTOM VIEW
PIN 1 ID OPTION A
0.20x45”TYP.
PIN 1 ID OPTION B
R0.20 TYP.
0.70
0.80
0.20 REF
0.00
0.05
SIDE VIEW
DETAIL A
4.90
2.80
1.50
NOTE:
0.70
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE
MOLD FLASH.
0.60
0.60
3) LEAD COPLANARITY SHALL BE0.10 MILLIMETER
MAX.
4) JEDEC REFERENCE IS MO-229, VARIATION WJJD.
5) DRAWING IS NOT TO SCALE.
0.59 1.77 2.95 4.13
0.50
0.25
0.70
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP86963 Rev.1.22
12/26/2013
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2013 MPS. All Rights Reserved.
11
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