MP86981DU [MPS]
Half Bridge Based MOSFET Driver, PDSO18, 5 X 5 MM, MO-229VJJD, FCTQFN-18;
| 型号： | MP86981DU |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Half Bridge Based MOSFET Driver, PDSO18, 5 X 5 MM, MO-229VJJD, FCTQFN-18 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总8页 (文件大小：277K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP86981
20A, 27V Intelli-Phase Solution (Single IC
with Integrated HS/LS FETs and Driver)
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP86981 is a monolithic Half Bridge with
built in internal power MOSFETs and gate
drivers. It achieves 20A continuous output
current over a wide input supply range.
•
•
•
•
Wide 4.5V to 21V Operating Input Range
20A Output Current
Simple Logic Interface(5.0V)
Synchronous Gate Driver Delivers up to
95% Efficiency
Operation from 100KHz to 1MHz
Accepts 3-state PWM Input
Thermal Shutdown
Integration of the Driver and MOSFETs results
in high efficiency due to optimal dead time
control and parasitic inductance reduction.
•
•
•
•
•
The MP86981 is a Monolithic IC approach to
drive up to 20A per phase. This very small 5x5
QFN can be used from 100KHz to 1MHz
operation.
Used for multi phase operation
Available in a 5mm x 5mm QFN Package
APPLICATIONS
This device is designed to work with tri state
output controller.
•
•
•
Power modules
Notebook, Core Voltage
Graphic Card Core Regulators
The MP86981 is ideal for notebook applications
where efficiency and small size are a premium.
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
The information in this datasheet about the product and its associated
technologies are proprietary and intellectual property of Monolithic Power
Systems and are protected by copyright and pending patent applications.
TYPICAL APPLICATION
Efficiency vs,
Output Current
100
95
90
85
80
75
70
V
IN=12V, VOUT=1.2V
65
60
20
0
5
10
15
OUTPUT CURRENT (A)
MP86981 Rev. 0.91
1/25/2010
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2010 MPS. All Rights Reserved.
1
MP86981 –20A, 27V INTELLI-PHASESOLUTION (SINGLE IC WITH INTEGRATED HS/LS FETS AND DRIVER)
ORDERING INFORMATION
Part Number*
Package
Top Marking
Temperature
MP86981DU
5x5 QFN
MP86981DU
–40°C to +85°C
* For Tape & Reel, add suffix –Z (e.g. MP86981DU–Z); For RoHS compliant packaging, add suffix –LF (e.g.
MP86981DU–LF–Z)
PACKAGE REFERENCE
PIN 1 ID
1
18 GND
17 GND
N/C
VCC
AGND
EN
IN
IN
IN
IN
GND
GND
GND
GND
2
SW
SW
SW
SW
3
4
5
6
7
8
9
16
GND
15
GND
14
GND
SYNC
PWM
PG
13
GND
12
GND
11
GND
BST
IN
10
GND
EXPOSED PAD
CONNECT TO PIN
Thermal Resistance (4)
5x5 QFN .................................36....... 8.... °C/W
θJA
θJC
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage VIN ....................................... 27V
V
V
SW....................................... –0.3V to VIN + 0.3V
BS .......................................................VSW + 6V
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)-
TA)/ θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
All Other Pins.................................–0.3V to +6V
Continuous Power Dissipation
............................................................. 3.5W
Junction Temperature...............................150°C
Lead Temperature ....................................260°C
Storage Temperature.............. –65°C to +150°C
(TA = +25°C)(2)
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on approximately 4” square of 4-layer PCB.
Recommended Operating Conditions (3)
Supply Voltage VIN ...........................4.5V to 21V
Operating Temperature............. –40°C to +85°C
MP86981 Rev. 0.91
1/25/2010
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2010 MPS. All Rights Reserved.
2
MP86981 –20A, 27V INTELLI-PHASESOLUTION (SINGLE IC WITH INTEGRATED HS/LS FETS AND DRIVER)
ELECTRICAL CHARACTERISTICS
VIN = 12V, TA = +25°C, unless otherwise noted.
Parameters
Symbol Condition
ICC_Stdby VCC =5V, PWM=EN=LO
Min
Typ
Max
300
5
Units
uA
uA
uA
ns
ICC Standby
230
IIN (Shutdown)
IIN (Off)
VCC = 0V
IIN Standby
IIN_Stdby
VCC =5V, PWM=EN=LO
IOUT = 20A
40
70
5
100
8
Rise Time (5)
Fall Time(5)
IOUT = 20A
3
6
ns
PWM to SW Delay Rising
PWM to SW Delay Falling
Minimum On-Time
Dead-Time Rising(5)
Dead-Time Falling(5)
Under Voltage Lockout Threshold Rising
Tdh
Tdl
PWM to SW
PWM to SW
20
38
40
5
ns
ns
ns
8
8
ns
5
ns
3.7
4.2
V
Under Voltage Lockout Threshold
Hysteresis
470
mV
Thermal Shutdown Rising
SYNC Pull-Up Current
SYNC Logic High Voltage
SYNC Logic Low Voltage
EN Input Low Voltage
En Input High Voltage
Power Good Rds(on)
PWM Input
160
-14
°C
µA
V
V
V
ISYNC
SYNC=0V
EN=0V
2
2
0.4
0.4
V
Ω
20
VPWM=5V
VPWM=0V
VCC=5V
VCC=5V
90
-90
1.7
3.5
80
20
35
16
26
48
85
µA
µA
V
Input Current
IPWM
PWM Tri-State Rising Threshold
PWM Tri-State Falling Threshold
Tri-State Shutdown Holdoff Time
UG/LG Three-State Propagation Delay
USW Turn-Off Propagation Delay
LSW Turn-Off Propagation Delay
USW Turn-On Propagation Delay
LSW Turn-On Propagation Delay
Diode Emulation Delay
V
tTSSHD
tPTS
tPDUL
tPDLL
tPDUH
tPDLH
tDE delay
VCC=5V, Temperature=25°C
ns
ns
ns
ns
ns
ns
ns
VCC=5V
VCC=5V
VCC=5V
VCC=5V
Notes:
5) Guaranteed by design.
PWM
t
t
PDUH
PDLH
t
TSSHD
SW
OV
V
OUT
t
PDUL
t
PDLL
Figure 1—Timing Diagram
MP86981 Rev. 0.91
1/25/2010
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2010 MPS. All Rights Reserved.
3
MP86981 –20A, 27V INTELLI-PHASESOLUTION (SINGLE IC WITH INTEGRATED HS/LS FETS AND DRIVER)
PIN FUNCTIONS
Pin #
Name
NC
Description
1
2
3
4
Not Connected.
VCC
AGND
EN
BG Driver Bias Supply. Decouple with a 1µF ceramic capacitor.
Signal Ground.
On/Off Control. A LOW places SW into high impedance state.
An open enables Lower Synchronous Switch. Pull down low puts Low Switch into
Diode Emulation mode.
5
6
7
SYNC
PWM
PG
Pulse Width Modulation Control. Accepts three state input. Force PWM to midstate or
open to place SW into high impedance state.
Power Good. Open drain output is low impedance to ground until internal supplies are
good.
Bootstrap. This capacitor is needed to drive the power switch’s gate above the supply
voltage. It is connected between SW and BST pins to form a floating supply across
the power switch driver.
8
BST
IN
9
Supply Voltage. CIN is needed to prevent large voltage spikes from appearing at the
input.
Exposed Pad
10–18
Exposed Pad
GND
SW
Power Ground.
Exposed Pad
Switch Output. These pins are fused together.
MP86981 Rev. 0.91
1/25/2010
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2010 MPS. All Rights Reserved.
4
MP86981 –20A, 27V INTELLI-PHASESOLUTION (SINGLE IC WITH INTEGRATED HS/LS FETS AND DRIVER)
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VCC = 5V, VOUT = 1.2V, TA = +25ºC, unless otherwise noted.
Efficiency vs.
Output Current
300kHz, L=0.82uH
Efficiency vs.
Output Current
600kHz, L=0.44uH
Efficiency vs.
Output Current
1MHz, L=0.27uH
95
90
85
80
75
70
65
60
95
90
85
80
75
70
65
60
100
95
90
85
80
75
70
65
60
0
5
10
15
20
25
0
5
10
15
20
20
25
0
5
10
15
20
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Power Loss vs.
Output Current
300kHz
Power Loss vs.
Output Current
600kHz
Power Loss vs.
Output Current
1MHz
4.5
4
4
3.5
3
5
4.5
4
3.5
3
3.5
3
2.5
2
2.5
2
2.5
2
1.5
1
1.5
1
1.5
1
0.5
0
0.5
0
0.5
0
0
5
10
15
20
25
0
5
10
15
0
5
10
15
20
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Temperature vs.
Airflow
Temperature vs.
Output Current
(No Airflow)
Power Loss vs.
Switching Frequency
3.5
3
110
100
90
80
75
70
65
60
55
50
45
40
2.5
2
20A, PCB
80
70
60
1.5
1
20A, IC Case
50
40
0.5
0
30
20
300 400 500 600 700 800 9001000
0
50
100 150 200 250
AIRFLOW (LFM)
0
5
10
15
20
SWITCHING FREQUENCY (kHZ)
OUTPUT CURRENT (A)
MP86981 Rev. 0.91
1/25/2010
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2010 MPS. All Rights Reserved.
5
MP86981 –20A, 27V INTELLI-PHASESOLUTION (SINGLE IC WITH INTEGRATED HS/LS FETS AND DRIVER)
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VCC = 5V, VOUT = 1.2V, TA = +25ºC, unless otherwise noted.
Power Loss vs.
Power Loss vs.
Output Voltage
Input Voltage
6
3
2.5
2
5
4
3
2
1
0
1MHz
300kHz
600kHz
1.5
0.8
1.3
1.8
2.3
2.8
3.3
5
10
INPUT VOLTAGE (V)
15
OUTPUT VOLTAGE (V)
SOA Waveform
Output Waveform
V
/AC
OUT
50mV/div
V
SW
5V/div
I
OUT
25A/div
400us/div
40ns/div
MP86981 Rev. 0.91
1/25/2010
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2010 MPS. All Rights Reserved.
6
MP86981 –20A, 27V INTELLI-PHASESOLUTION (SINGLE IC WITH INTEGRATED HS/LS FETS AND DRIVER)
OPERATION
The MP86981 is a 20A Half Bridge driver
ideally suited for Multi-Phase Buck regulators.
high and Thermal Shutdown is not tripped, the
operation begins.
When the EN transitions from Low to High, the
internal voltage regulators are enabled. Once
both the VCC and VBST signals are sufficiently
To allow M2, the lower DMOS, to enter Diode
Emulation, the SYNC pin is driven Low.
V
BST
BST
Voltage
Regulator
EN
EN
IN
HGate
EN
Vcc
VOUT
SW
50
50
PWM
PWM
Logic
PWM
Tri-State
VCC
Vcc
150
Diode
Emulation
LGate
Logic
SYNC
M2
EN
LGate
GND
PG
V
BST
TSD
CC
V
Figure 2—Functional Block Diagram
MP86981 Rev. 0.91
1/25/2010
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2010 MPS. All Rights Reserved.
7
MP86981 –20A, 27V INTELLI-PHASESOLUTION (SINGLE IC WITH INTEGRATED HS/LS FETS AND DRIVER)
PACKAGE INFORMATION
FCTQFN18L (EXPOSED PAD)
2.80
BSC
1.30
1.50
PIN 1 ID
4.90
5.10
0.50
0.70
SEE DETAIL A
PIN 1 ID
MARKING
0.40
1
18
0.60
0.40
0.60
4.90
0.59 1.77 2.95 4.13
BSC BSC BSC BSC
0.50
5.10
PIN 1 ID
INDEX AREA
BSC
0.18
0.30
10
9
9
0.30
0.40
TOP VIEW
BOTTOM VIEW
PIN 1 ID OPTION A
0.20x45”TYP.
PIN 1 ID OPTION B
R0.20 TYP.
0.80
1.00
0.20 REF
0.00
0.05
SIDE VIEW
DETAIL A
4.90
2.80
1.50
NOTE:
0.70
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE
MOLD FLASH.
0.60
0.60
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER
MAX.
4) JEDEC REFERENCE IS MO-229, VARIATION VJJD.
5) DRAWING IS NOT TO SCALE.
0.59 1.772.954.13
0.50
0.25
0.70
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP86981 Rev. 0.91
1/25/2010
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2010 MPS. All Rights Reserved.
8
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