MP5010B [MPS]

3V-18V, 1A-5A Programmable-Current- Limit Switch with Over-Voltage Clamp; 3V- 18V , 1A -5A可编程限流开关具有过压钳位
MP5010B
型号: MP5010B
厂家: MONOLITHIC POWER SYSTEMS    MONOLITHIC POWER SYSTEMS
描述:

3V-18V, 1A-5A Programmable-Current- Limit Switch with Over-Voltage Clamp
3V- 18V , 1A -5A可编程限流开关具有过压钳位

开关
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中文:  中文翻译
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MP5010B  
3V-18V, 1A-5A Programmable-Current-  
Limit Switch with Over-Voltage Clamp  
The Future of Analog IC Technology  
DESCRIPTION  
FEATURES  
The MP5010B is a protection device designed to  
protect circuitry on the output (source) from  
transients on the input (VCC). It also protects the  
input from undesired shorts and transients  
coming from the source.  
Wide 3V-to-18V Operating Input Range  
5.7V Output Over-Voltage Clamp  
Integrated 40mPower FET  
Enable/Fault Pin  
Adjustable Output Voltage Slew Rate  
Adjustable Current Limit  
A small capacitor on the dv/dt pin controls the  
slew rate that limit the inrush current at the  
source. For instance, a 1nF capacitor results in a  
source ramp-up time of 3ms.  
Thermal Protection  
APPLICATIONS  
The maximum load at the source is current  
limited using a sense FET topology. An external  
resistor between the I-Limit pin and the Source  
pins controls the magnitude of the current limit.  
Hot-Swappable Devices  
Wireless Modem Data Cards  
PC Cards  
Laptops  
An internal charge pump drives the gate of the  
power device, allowing the DMOS power FET to  
have a very low ON-resistance of just 40m.  
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green  
status, please visit MPS website under Products, Quality Assurance page.  
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks  
of Monolithic Power Systems, Inc.  
The MP5010B also protects the source from the  
input being too low or too high. Under-voltage  
lockout ensures that the input remains above the  
minimum operating threshold before the power  
device turns on. If the input rises above the high  
output threshold, the MP5010B limits the source  
voltage.  
TYPICAL APPLICATION  
VIN  
11  
VCC  
6
5
N/C  
Source  
VOUT  
4
3
2
7
I-Limit  
Source  
MP5010B  
Enable/Fault Source  
8
9
EN  
dv/dt  
GND  
Source  
Source  
10  
1
MP5010B Rev. 1.0  
4/3/2013  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2012 MPS. All Rights Reserved.  
1
MP5010B – 3V-18V, 1A-5A PROGRAMMABLE CURRENT LIMIT SWITCH  
ORDERING INFORMATION  
Part Number*  
Package  
Top Marking  
MP5010BDQ  
QFN10 (3mm×3mm)  
AFN  
* For Tape & Reel, add suffix –Z (e.g. MP5010BDQ–Z).  
For RoHS compliant packaging, add suffix –LF (e.g. MP5010BDQ-LF-Z).  
PACKAGE REFERENCE  
1
2
3
4
5
10  
9
8
7
6
Thermal Resistance (4)  
QFN10 (3mmx3mm) ...............50 ...... 12...°C/W  
θJA  
θJC  
ABSOLUTE MAXIMUM RATINGS (1)  
VCC, SOURCE, I-LIMIT ..................0.3V to 22V  
dv/dt, ENABLE/FAULT ....................0.3V to 6V  
Storage Temperature.............. –65°C to +155°C  
Junction Temperature................................ +150°C  
Lead Temperature .................................... +260°C  
Notes:  
1) Exceeding these ratings may damage the device.  
2) The maximum allowable power dissipation is a function of the  
maximum junction temperature TJ(MAX) the junction-to-  
ambient thermal resistance θJAand the ambient temperature  
TA, the maximum allowable power dissipation at any ambient  
temperature is calculated using: PD(MAX)=(TJ(MAX)-TA)/ θJA.  
Exceeding the maximum allowable power dissipation will  
cause excessive die temperature, and the regulator will go  
into thermal shutdown. Internal thermal shutdown circuitry  
protects the device from permanent damage.  
(2)  
Continuous Power Dissipation (TA=+25°C)  
................................................................... 2.5W  
(3)  
Recommended Operating Conditions  
Input Voltage Operating Range ......... 3V to 18V  
Operating Junction Temp. (TJ)...... -40°C to +125°C  
Reduce 0.2 Watts for every 10oC ambient temperature  
increasing  
3) The device is not guaranteed to function outside of its  
operating conditions.  
4) Measured on JESD51-7 4-layer board.  
MP5010B Rev. 1.0  
4/3/2013  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2012 MPS. All Rights Reserved.  
2
MP5010B – 3V-18V, 1A-5A PROGRAMMABLE CURRENT LIMIT SWITCH  
ELECTRICAL CHARACTERISTICS  
VCC = 5V, RLIMIT=22, Capacitive Load= 10μF, TA=25°C, unless otherwise noted.  
Parameters  
Power FET  
Symbol Condition  
Min  
Typ  
Max  
Units  
Enabling of chip to  
Delay Time  
τDLY  
ID=40mA with a 5  
resistive load  
TJ=25°C  
44  
μs  
40  
52  
55  
ON Resistance  
RDSon  
VOFF  
mꢀ  
mV  
A
TJ=85°C(5)  
VCC=18V, VEN=0V,  
RL=500ꢀ  
0.5 in2 pad, TA=25°C  
OFF-State Output Voltage  
120  
4.2  
2.3  
Continuous Current  
ID  
minimum copper, TA=80°C  
Thermal Latch  
Shutdown Temperature(5)  
Under/Over-Voltage Protection  
TSD  
175  
°C  
Over-Voltage Protection  
VCC=8V  
Rising Edge  
Output Clamp Voltage  
VCLAMP  
VUVLO  
VHYST  
5.5  
5.7  
2.8  
5.9  
2.9  
V
V
V
Under-Voltage Lockout  
Under-Voltage Lockout (UVLO)  
Hysteresis  
2.65  
0.15  
Current Limit (6) (For Direct Current-Sense, refer to typical application in Figure 5)  
0Short Resistance,  
Hold Current  
ILIM-SS  
2.2  
2.8  
4.3  
3.4  
A
A
R
LIM=22ꢀ  
Trip Current  
ILIM-OL  
RLIM=22ꢀ  
Current Limit (6) (For Kelvin Sense, refer to typical application in Figure 4)  
0Short Resistance,  
Hold Current  
ILIM-SS  
ILIM-OL  
0.77  
2
1.10  
2.18  
1.43  
4
A
A
R
LIM=22ꢀ  
Trip Current  
RLIM=22ꢀ  
dv/dt Circuit  
Rise Time (7)  
τr  
Cdv/dt =1nF  
3
ms  
Enable/Fault  
Low-Level Input Voltage  
VIL  
Output Disabled  
Thermal Fault, Output  
Disabled  
0.5  
V
V
Intermediate-Level Input Voltage  
VI (INT)  
0.82  
2.5  
1.4  
1.95  
High-Level Input Voltage  
HIGH-State Maximum Voltage  
Pull-Up Current (Source)  
VIH  
VI (MAX)  
IIL  
Output Enabled  
V
V
μA  
4.95  
25  
VENABLE=0V  
Maximum number of chips  
for simultaneous shutdown  
15  
35  
3
Maximum Fanout for Fault Signal  
Maximum Voltage on EN(8)  
Units  
V
VMAX  
VCC  
MP5010B Rev. 1.0  
4/3/2013  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2012 MPS. All Rights Reserved.  
3
MP5010B – 3V-18V, 1A-5A PROGRAMMABLE CURRENT LIMIT SWITCH  
ELECTRICAL CHARACTERISTICS (continued)  
VCC = 5V, RLIMIT=22, Capacitive Load= 10μF, TA=25°C, unless otherwise noted.  
Parameters  
Total Device  
Symbol Condition  
Min  
Typ  
Max  
Units  
Device Operational  
860  
580  
950  
650  
Bias Current  
IBIAS  
VMIN  
μA  
Thermal Shutdown  
Enable<0.5V  
Minimum Operating Voltage for  
UVLO  
2.5  
V
Notes:  
5) Guaranteed by design.  
6) Guaranteed by Characterization Test.  
7) Measured from 10% to 90%.  
8) Maximum Input Voltage on Enable pin to be 6V if Vcc 6V. Maximum Input Voltage on Enable pin to be Vcc if Vcc 6V.  
MP5010B Rev. 1.0  
4/3/2013  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2012 MPS. All Rights Reserved.  
4
MP5010B – 3V-18V, 1A-5A PROGRAMMABLE CURRENT LIMIT SWITCH  
TYPICAL PERFORMANCE CHARACTERISTICS  
VIN = 5V, VEN=5V, RLIMIT=22, COUT=10μF, Cdv/dt =1nF, TA=25°C, unless otherwise noted.  
2.6  
2.4  
2.2  
2.0  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
1000  
950  
900  
850  
800  
750  
700  
650  
600  
550  
20 30 40 50 60 70 80 90 100  
0 10 20 30 40 50 60 70 80 90100110  
3
3.5  
4
4.5  
5
5.5  
600  
550  
500  
450  
400  
350  
300  
140  
120  
100  
80  
60  
55  
50  
45  
40  
35  
30  
60  
40  
20  
0
3
3.5  
4
4.5  
5
5.5  
3
3.5  
4
4.5  
5
5.5  
0
0.5  
1
1.5  
2
2.5  
15  
4
3.5  
3
5.5  
5
12  
9
4.5  
4
6
2.5  
2
3
0
3.5  
3
3
3.5  
4
4.5  
5
5.5  
3
3.5  
4
4.5  
5
5.5  
4
8
12  
16  
20  
MP5010B Rev. 1.0  
4/3/2013  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2012 MPS. All Rights Reserved.  
5
MP5010B – 3V-18V, 1A-5A PROGRAMMABLE CURRENT LIMIT SWITCH  
TYPICAL PERFORMANCE CHARACTERISTICS (continued)  
VIN = 5V, VEN=5V, RLIMIT=22, COUT=10μF, Cdv/dt =1nF, TA=25°C, unless otherwise noted.  
V
V
V
OUT  
2V/div  
OUT  
OUT  
2V/div  
2V/div  
V
V
V
IN  
IN  
IN  
5V/div  
5V/div  
5V/div  
EN  
EN  
EN  
5V/div  
OUT  
1A/div  
5V/div  
OUT  
1A/div  
5V/div  
OUT  
1A/div  
I
I
I
V
V
V
OUT  
OUT  
OUT  
2V/div  
2V/div  
2V/div  
V
V
V
IN  
IN  
IN  
5V/div  
5V/div  
5V/div  
EN  
EN  
EN  
5V/div  
OUT  
1A/div  
5V/div  
OUT  
1A/div  
5V/div  
OUT  
2A/div  
I
I
I
V
OUT  
2V/div  
V
OUT  
2V/div  
V
OUT  
2V/div  
V
IN  
V
IN  
5V/div  
5V/div  
V
IN  
EN  
EN  
5V/div  
5V/div  
5V/div  
EN  
5V/div  
I
I
I
OUT  
OUT  
OUT  
1A/div  
1A/div  
2A/div  
MP5010B Rev. 1.0  
4/3/2013  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2012 MPS. All Rights Reserved.  
6
MP5010B – 3V-18V, 1A-5A PROGRAMMABLE CURRENT LIMIT SWITCH  
TYPICAL PERFORMANCE CHARACTERISTICS (continued)  
VIN = 5V, VEN=5V, RLIMIT=22, COUT=10μF, Cdv/dt =1nF, TA=25°C, unless otherwise noted.  
MP5010B Rev. 1.0  
4/3/2013  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2012 MPS. All Rights Reserved.  
7
MP5010 – PROGRAMMABLE CURRENT 12V/5A ELECTRONIC FUSE  
PIN FUNCTIONS  
Pin #  
1-5  
6
Name  
Description  
SOURCE Source. Internal power FET source. IC output.  
N/C  
DO NOT CONNECT—leave floating.  
Current Limit. Using a resistor between this pin and Source to set the overload  
and short-circuit current-limit levels.  
7
I-Limit  
Enable/Fault. A tri-state, bi-directional interface. Leave floating to enable the  
output. Pull to ground (using an open drain or open collector device) to disable  
the output. If a thermal fault occurs, this voltage enters an intermediate state to  
signal that the device is in thermal shutdown.  
8
Enable/Fault  
Slew Rate. The internal dv/dt circuit controls the slew rate of the output voltage  
at turn-on.  
9
dv/dt  
GND  
VCC  
10  
Ground. Internal IC reference.  
11  
Input. Positive input voltage.  
Exposed Pad  
MP5010B Rev. 1.0  
4/3/2013  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
8
© 2013 MPS. All Rights Reserved.  
MP5010 – PROGRAMMABLE CURRENT 12V/5A ELECTRONIC FUSE  
BLOCK DIAGRAM  
VCC  
5V  
Charge  
Pump  
U1  
25 A  
2V Hys  
2.5V  
U3  
D1  
Enable/  
Fault  
R1  
28k  
U2  
RESET  
Source  
M1  
Latch  
Control Logic  
SET  
Current Limit  
I-Limit  
Thermal  
Shutdown  
Voltage  
Clamp  
dv/dt  
Control  
VCC UVLO  
dv/dt  
GND  
Figure 1: Functional Block Diagram  
MP5010B Rev. 1.0  
4/3/2013  
www.MonolithicPower.com  
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9
© 2013 MPS. All Rights Reserved.  
MP5010B – 3V-18V, 1A-5A PROGRAMMABLE CURRENT LIMIT SWITCH  
OPERATION  
The MP5010B limits the inrush current to the  
load when a circuit card connects to a live  
backplane power source, thereby limiting the  
backplane’s voltage drop and the dV/dt of the  
voltage to the load. It offers an integrated solution  
to monitor the input voltage, output voltage,  
output current, and die temperature, eliminating  
the external current-sense power resistor, power  
MOSFET, and thermal sensor.  
The MP5010B requires a heat sink during  
constant-current mode (such as from a short-  
circuit) to prevent unwanted shutdown: In  
constant-current mode, the chip must dissipate  
the power from a 5V drop. Without additional  
heat dissipation at 50°C/Watt, the temperature  
would exceed the thermal threshold (+175°C)  
and the MP5010B will shutdown to force the  
temperature to drop below a hysteresis level.  
Without a heat sink, maintain the current below  
600mA at + 25°C and below 360mA at +85°C to  
prevent thermal shutdown.  
Under-Voltage Lockout Operation  
If the supply (input) is below the UVLO threshold,  
the output is disabled, and the EN/Fault line is  
driven low.  
Thermal Protection  
When the supply rises above the UVLO threshold,  
the output is enabled and the EN/Fault is pulled  
high through a 25μA current source without an  
external pull-up resistor. The pull-up voltage is  
limited to 4.95V.  
If the temperature exceeds the thermal threshold,  
the MP5010B disables its output and drives the  
Enable/Fault line to the middle (MID) level (read  
the following Enable/Fault Pin section for more  
information). The thermal fault condition is  
latched, and the part remains OFF until the  
Enable/Fault line goes low. Cycling the power  
below the UVLO threshold will also reset the fault  
flag.  
Output Over-Voltage Protection  
If the input voltage exceeds the over-voltage  
protection (OVP) threshold, the output is clamped  
at 5.7V (typ).  
Fault and Enable Pin  
Current Limiting  
The Enable/Fault pin is a bi-directional, three-  
level I/O with a weak pull-up current (25μA, typ.).  
The three levels are LOW, MID, and HIGH. It  
functions to enable/disable the part and to relay  
fault information.  
When the chip is active, if load reaches the over-  
current protection (OCP) threshold (trip current)  
or a short is present, the part switches to  
constant-current mode (hold current). The chip  
shuts down only if the over-current condition  
eventually triggers thermal protection. However,  
when the part is powered up by VCC or EN, the  
load current should be smaller than the hold  
current. Otherwise, the part can’t be fully turned  
on.  
Enable/Fault as an input:  
1. LOW and MID disable the part.  
2. LOW, in addition to disabling the part,  
clears the fault flag.  
3. HIGH enables the part (if the fault flag is  
clear).  
In a typical application with a current-limiting  
resistor of 22, the trip current is 2.18A for Kelvin  
current sensing and 4.3A for direct current  
sensing. If the device is in normal operation and  
passing 2.0A, it will only need to dissipate  
160mW with the low ON resistance of 40m. For  
Enable/Fault as an output:  
1. The pull-up current will allow a “wired  
nor” pull-up to enable the part (if not  
overridden).  
2. An under-voltage condition will cause a  
LOW on the Enable/Fault pin, and will  
clear the fault flag.  
3. A thermal fault will set a MID on the  
Enable/Fault pin, and will set the fault  
flag  
a
package dissipation of 50°C/Watt, the  
temperature rise is +8°C. Given a 25°C ambient  
temperature, the typical package temperature is  
33°C.  
MP5010B Rev. 1.0  
4/3/2013  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2012 MPS. All Rights Reserved.  
10  
MP5010B – 3V-18V, 1A-5A PROGRAMMABLE CURRENT LIMIT SWITCH  
The Enable/Fault line must remain above the  
MID level for the output to turn ON.  
Given a fault, the Enable/Fault pin is driven to  
MID.  
The fault flag is an internal flip-flop that can be  
set or reset under the following conditions:  
There are 4 types of faults, and each fault has a  
direct and indirect effect on the Enable/Fault pin  
and the internal fault flag. In a typical  
application there are one or more of the  
MP5010B chips in a system. The Enable/Fault  
lines are typically be connected together.  
1. Thermal Shutdown: set fault flag  
2. Under-Voltage: reset fault flag  
3. LOW on Enable/Fault pin: reset fault  
flag  
4. MID on Enable/Fault pin: no effect  
Table 1—Fault Function Influence in Application  
Fault description Internal action  
Effect on Fault Pin Effect on Flag Effect on secondary Part  
Short/Over  
Limit current  
Current  
none  
none  
none  
Internally drives  
Enable/Fault pin to  
logic LOW  
Disables secondary output,  
and resets fault flag.  
Under Voltage  
Over Voltage  
Output turns OFF  
Flag is reset  
None  
Limit output voltage None  
None  
Shutdown. The part  
is latched OFF until Internally drives  
Thermal  
Shutdown  
Disables secondary part  
output.  
a UVLO or  
Enable/Fault pin  
to MID  
Flag is Set  
externally driven to  
ground.  
MP5010B Rev. 1.0  
4/3/2013  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2012 MPS. All Rights Reserved.  
11  
MP5010B – 3V-18V, 1A-5A PROGRAMMABLE CURRENT LIMIT SWITCH  
APPLICATION INFORMATION  
Current Limit  
Rise Time  
The rise time is a function of the capacitor (Cdv/dt  
on the dv/dt pin. Table 4 lists typical rise times as  
a function of capacitance.  
)
The current limit is a function of the external  
current-limit resistor. Table 2 and Table 3 list  
examples of current values as a function of the  
resistor value for both Kelvin current sensing and  
direct current sensing.  
Table 2: Current Limit vs. Current Limit Resistor (VCC=5V, Kelvin Current Sensing)  
RLIMIT ()  
10  
22  
51  
75  
100  
1.99  
0.47  
Trip Current (A)  
Hold Current (A)  
2.31  
1.45  
2.18  
1.10  
2.05  
0.71  
2.00  
0.56  
Table 3: Current Limit vs. Current Limit Resistor (VCC=5V, Direct Current Sensing)  
RLIMIT ()  
22  
51  
75  
100  
220  
Trip Current (A)  
Hold Current (A)  
4.31  
2.79  
3.10  
1.29  
2.69  
0.91  
2.52  
2.43  
2.31  
0.40  
Table 4: Rise Time vs. Cdv/dt  
Cdv/dt  
330pF  
1.1  
1nF  
3
3.3nF  
9.4  
6.8nF  
19.2  
Rise Time  
(typ., ms)  
* Notes: Rise Time = KRT*(50pF+Cdv/dt), KRT =2.8E6  
The “rise time” is measured by from 10% to 90%  
of output voltage.  
U
Input  
Output  
90%  
Enable  
10%  
t
Rise Time  
Figure 2—Rise Time  
MP5010B Rev. 1.0  
4/3/2013  
www.MonolithicPower.com  
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© 2012 MPS. All Rights Reserved.  
12  
MP5010B – 3V-16V, 3A PROGRAMMABLE CURRENT LIMIT SWITCH  
Design Example  
Below is a direct-current-sensing design example  
following the application guidelines for the given  
specifications:  
PCB Layout  
PCB layout is very important to achieve stable  
operation. Please follow these guidelines and  
use Figure 3 as reference.  
Table 5: Design Example  
Place RLIMIT close to the I-limit pin  
Place Cdv/dt close to dv/dt pin  
VIN  
5V  
Trip Current  
Hold Current  
4.3A  
2.8A  
Place the input capacitor close to the VCC  
pin.  
Figure 5 shows the application schematic. The  
Typical Performance Characteristics section  
shows the circuit waveforms. For more device  
applications, please refer to the related  
Evaluation Board Datasheet.  
Leave the N/C pin floating.  
Place vias in the thermal pad and provide  
enough copper area near the VCC pin and  
Source pin for thermal dissipation.  
GND  
RLIMIT  
N/C  
6
5
4
3
2
1
SOURCE  
SOURCE  
SOURCE  
SOURCE  
VIN  
7
8
I_LIMIT  
EN/ FAULT  
EN/ FAULT  
dv/dt  
9
10  
GND  
SOURCE  
C3  
VIN  
VOUT  
Top Layer  
VIN  
Bottom Layer  
Figure 3: PCB Layout  
MP5010B Rev. 1.0  
4/3/2013  
www.MonolithicPower.com  
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13  
© 2013 MPS. All Rights Reserved.  
MP5010B – 3V-18V, 1A-5A PROGRAMMABLE CURRENT LIMIT SWITCH  
TYPICAL APPLICATION CIRCUITS  
R1  
VIN  
11  
VCC  
6
7
5
4
N/C  
Source  
Source  
I-Limit  
VOUT  
MP5010B  
8
3
2
1
EN  
Enable/Fault Source  
9
dv/dt  
GND  
Source  
Source  
C1  
1nF  
10  
Figure 4: Typical Application Schematic with Kelvin Current Sensing  
R1  
VIN  
EN  
11  
VCC  
6
7
5
4
N/C  
Source  
Source  
I-Limit  
VOUT  
MP5010B  
Enable/Fault Source  
8
3
2
1
9
dv/dt  
GND  
Source  
Source  
C1  
1nF  
10  
Figure 5: Typical Application Schematic with Direct Current Sensing  
MP5010B Rev. 1.0  
4/3/2013  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2012 MPS. All Rights Reserved.  
14  
MP5010B – 3V-18V, 1A-5A PROGRAMMABLE CURRENT LIMIT SWITCH  
PACKAGE INFORMATION  
QFN10 (3mm × 3mm)  
2.90  
3.10  
0.30  
0.50  
1.45  
1.75  
PIN 1 ID  
SEE DETAIL A  
PIN 1 ID  
MARKING  
0.18  
10  
1
5
0.30  
2.25  
2.55  
2.90  
3.10  
PIN 1 ID  
INDEX AREA  
0.50  
BSC  
6
TOP VIEW  
BOTTOM VIEW  
PIN 1 ID OPTION A  
R0.20 TYP.  
PIN 1 ID OPTION B  
R0.20 TYP.  
0.80  
1.00  
0.20 REF  
0.00  
0.05  
SIDE VIEW  
DETAIL A  
NOTE:  
2.90  
1.70  
1) ALL DIMENSIONS ARE IN MILLIMETERS.  
0.70  
0.25  
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.  
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX.  
4) DRAWING CONFORMS TO JEDEC MO-229, VARIATION VEED-5.  
5) DRAWING IS NOT TO SCALE.  
2.50  
0.50  
RECOMMENDED LAND PATTERN  
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third  
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not  
assume any legal responsibility for any said applications.  
MP5010B Rev. 1.0  
4/3/2013  
www.MonolithicPower.com  
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.  
© 2013 MPS. All Rights Reserved.  
15  

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