MP5010DQ [MPS]
Power Supply Support Circuit, Fixed, 1 Channel, PDSO10, 3 X 3 MM, MO-229VEED-5, QFN-10;
| 型号： | MP5010DQ |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Power Supply Support Circuit, Fixed, 1 Channel, PDSO10, 3 X 3 MM, MO-229VEED-5, QFN-10 光电二极管 |
| 文件： | 总12页 (文件大小：530K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP5010
5V, 1A- 5A Programmable Current
Limit Switch
The Future of Analog IC Technology
The Enable/Fault pin allows the IC to be turned
off and enter a low current shutdown state. This
pin is bi-directional and allows feedback of fault
information. Momentary current spikes are not
considered as faults, neither is the momentary
over voltage. However prolonged over current or
over voltage conditions will cause excessive
power dissipation and result in a thermal
shutdown. And the thermal shutdown will cause a
fault condition.
DESCRIPTION
The MP5010 is a protection device designed to
protect circuitry on the output (source) from
transients on input (VCC). It also protects VCC from
undesired shorts and transients coming from the
source.
At start up, inrush current is limited by limiting the
slew rate at the source. The slew rate is
controlled by a small capacitor at the dv/dt pin.
The dv/dt pin has an internal circuit that allows
the customer to float this pin (no connect) and
still receive 1.5ms ramp time at the source.
FEATURES
•
•
•
•
•
•
Integrated 44mΩ Power FET
Enable/Fault Pin
Adjustable Slew Rate for Output Voltage
Adjustable Current Limit
Thermal Protection
The max load at the output (source) is current
limited. This is accomplished by utilizing a sense
FET topology. The magnitude of the current limit
is controlled by an external resistor from the I-
Limit pin to the Source pin.
Over Voltage Limit
An internal charge pump drives the gate of the
power device, allowing a very low on-resistance
DMOS power FET of just 44mΩ.
APPLICATIONS
•
•
•
Hot Swap
PC Cards
Laptops
The source is protected from the VCC input being
too low or too high. Under Voltage Lockout
(UVLO) assures that VCC is above the minimum
operating threshold, before the power device is
turned on. If VCC goes above the high output
threshold, the source voltage will be limited.
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks
of Monolithic Power Systems, Inc.
TYPICAL APPLICATION
RLIMIT
VIN
11
VCC
6
5
N/C
Source
Source
VOUT
4
7
I-Limit
MP5010
8
3
2
1
EN
Enable/Fault Source
9
dv/dt
GND
Source
Source
C
dv/dt
10
MP5010 Rev.0.91
9/23/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
1
MP5010 – 5V, 5A PROGRAMMABLE CURRENT LIMIT SWITCH
ORDERING INFORMATION
Part Number*
Package
Top Marking
Temperature
MP5010DQ
QFN10 (3x3)
8E
–40°C to +85°C
* For Tape & Reel, add suffix –Z (e.g. MP5010DQ–Z). For RoHS Compliant Packaging, add suffix –LF (e.g.
MP5010DQ–LF–Z)
PACKAGE REFERENCE
1
2
3
4
5
10
9
8
7
6
Thermal Resistance (4)
QFN10 ....................................50 ...... 12...°C/W
θJA
θJC
ABSOLUTE MAXIMUM RATINGS (1)
VCC, SOURCE, I-LIMIT ................................ 22V
dv/dt, ENABLE/FAULT .................................. 6V
Storage Temperature.............. –65°C to +155°C
Operating Junction Temperature.. –40°C to +150°C
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX) ， the junction-to-
(2)
Continuous Power Dissipation (TA=+25oC)
ambient thermal resistance θJA，and the ambient temperature
TA, the maximum allowable power dissipation at any ambient
temperature is calculated using: PD(MAX)=(TJ(MAX)-TA)/ θJA.
Exceeding the maximum allowable power dissipation will
cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
…………………………………………………2.5W
(3)
Recommended Operating Conditions
Input Voltage Operating Range ......... 4V to 10V
Reduce 0.2 Watts for every 10oC ambient temperature
increasing
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7 4-layer board.
MP5010 Rev.0.91
9/23/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
2
MP5010 – 5V, 5A PROGRAMMABLE CURRENT LIMIT SWITCH
ELECTRICAL CHARACTERISTICS
VCC = 5V, RLIMIT=22Ω, Capacitive Load= 10µF, TA=25°C, unless otherwise noted.
Parameters
Power FET
Symbol Condition
Min
Typ
Max
Units
Enabling of chip to
Delay Time
tDLY
ID=100mA with a 12ꢀ
resistive load
0.2
ms
TJ=25°C
TJ=80°C, Note 5
44
95
82
ON Resistance
RDSon
VOFF
mꢀ
VCC=18Vdc, Enable=0Vdc,
Off State Output Voltage
120
mV
RL=500ꢀ
0.5 in2 pad, TA=25°C
4.2
2.3
A
Continuous Current
ID
minimum copper, TA=80°C
Thermal Latch
Shutdown Temperature
Under/Over Voltage Protection
TSD
175
°C
Overvoltage Protection
Output Clamping Voltage
Under Voltage Lockout
VCLAMP
VUVLO
VHYST
5.95
3.2
6.65
3.6
7.35
4.0
V
V
V
VCC=8V
Turn on,
Voltage going high
Under Voltage Lockout (UVLO)
Hysteresis
0.4
Current Limit
0ꢀ short resistance,
RLIM=22ꢀ, Note 5
RLIM=22ꢀ,
Hold Current
ILIM-SS
ILIM-OL
1.5
0.8
2.1
3.3
2.8
2.5
A
A
Trip Current
dv/dt Circuit
Enable to VOUT=4.7V,
Note 6
Slew Rate
dv/dt
1.5
1.4
ms
Enable/Fault
Low Level Input Voltage
VIL
Output Disabled
Thermal Fault, Output
Disabled
0.5
V
V
Intermediate Level Input Voltage
VI (INT)
0.82
2.5
1.95
High Level Input Voltage
High State Maximum Voltage
Low Level Input Current (Sink)
VIH
VI (MAX)
IIL
Output Enabled
V
V
µA
4.8
-28
VENABLE=0V
Total number of chips that
can be connected for
simultaneous shutdown
Note 7
-50
3
Maximum Fanout for Fault Signal
Units
V
Maximum Voltage on Enable Pin
VMAX
VCC
Total Device
Device Operational
Thermal Shutdown
2
3
Bias Current
IBIAS
VMIN
mA
V
1.3
Minimum Operating Voltage for
UVLO
Enable<0.5V
3.0
Notes:
5) Guaranteed by design.
6) Measure at (30% to 90%)/0.6.
7) Maximum Input Voltage on Enable pin to be ≤6.65V if Vcc ≥ 6.65V. Maximum Input Voltage on Enable pin to be Vcc if Vcc ≤ 6.65V.
MP5010 Rev.0.91
9/23/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
3
MP5010 – 5V, 5A PROGRAMMABLE CURRENT LIMIT SWITCH
PIN FUNCTIONS
Pin #
1-5
6
Name
SOURCE
N/C
Description
This pin is the source of the internal power FET and the output terminal of the IC.
DO NOT CONNECT, The pin must be float.
A resistor between this pin and the Source pin sets the overload and short circuit
current limit levels.
7
I-Limit
The Enable/Fault pin is a tri-state, bi-directional interface. It can be used to enable the
output of the device by floating the pin, or disable the chip by pulling it to ground
8
Enable/Fault (using an open drain or open collector device). If a thermal fault occurs, the voltage
on this pin will go to an intermediate state to signal a monitoring circuit that the device
is in thermal shutdown.
The internal dv/dt circuit controls the slew rate of the output voltage at turn on. It has
an internal capacitor that allows it to ramp up over the period of 1.5ms. An external
capacitor can be added to this pin to increase the ramp time. If an additional time
9
dv/dt
delay is not required, this pin should be left open.
10
11
GND
VCC
Negative Input Voltage to the Device. This is used as the internal reference for the IC.
Positive input voltage to the device (Exposed Pad).
MP5010 Rev.0.91
9/23/2009
www.MonolithicPower.com
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© 2009 MPS. All Rights Reserved.
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MP5010 – 5V, 5A PROGRAMMABLE CURRENT LIMIT SWITCH
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 5V, VEN=3.3V, RLIMIT=22Ω, COUT=10uF, Cdv/dt =1nF, TA=25°C, unless otherwise noted.
Supply Current, Ouput Enabled
vs. Input Voltage
no load
1.3
1.25
1.2
2.1
2.05
2
52
51
50
49
48
47
46
45
1.95
1.9
1.15
1.1
3.5
1.85
4
4.5
5
5.5
6
3.5
4
4.5
5
5.5
6
3.5
4
4.5
5
5.5
6
INPUT VOLTAGE(V)
INPUT VOLTAGE (V)
INPUT VOLTAGE(V)
Input-to-output Voltage vs.
Load Current
Hold Current vs.
Input Voltage
Trip Current vs.
Input Voltage
140
120
100
80
3.4
3.3
3.2
3.1
3
2.2
2.1
2
60
40
1.9
1.8
20
0
2.9
3.5
4
4.5
5
5.5
6
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
LOAD CURRENT (A)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Current Limit Response vs.
Peak Current
Trip Current & Hold Current
vs. Rlimit
4
3
2
1
0
60
50
40
30
20
Trip Current
Hold Current
0
20 40 60 80 100 120
RLIMIT
0
5
10 15 20 25 30 35 40
PEAK CURRENT (A)
MP5010 Rev.0.91
9/23/2009
www.MonolithicPower.com
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© 2009 MPS. All Rights Reserved.
5
MP5010 – 5V, 5A PROGRAMMABLE CURRENT LIMIT SWITCH
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VEN=3.3V, RLIMIT=22Ω, COUT=10uF, Cdv/dt=1nF, TA=25°C, unless otherwise noted.
V
OUT
2V/div
V
V
OUT
OUT
2V/div
2V/div
EN
2V/div
EN
2V/div
EN
2V/div
4ms/div
V
V
OUT
OUT
EN
2V/div
2V/div
2V/div
EN
5V/div
EN
5V/div
I
I
OUT
OUT
I
500mA/div
OUT
1A/div
500mA/div
4ms/div
V
OUT
2V/div
EN
EN
2V/div
2V/div
I
I
I
OUT
OUT
1A/div
OUT
1A/div
1A/div
MP5010 Rev.0.91
9/23/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
6
MP5010 – 5V, 5A PROGRAMMABLE CURRENT LIMIT SWITCH
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 5V, VEN=3.3V, RLIMIT=22Ω, COUT=10uF, Cdv/dt=1nF, TA=25°C, unless otherwise noted.
V
OUT
2V/div
Trip Current=3.2A
V
V
Hold Current=2.0A
OUT
2V/div
OUT
2V/div
Thermal Shutdown
I
OUT
1A/div
I
I
OUT
2A/div
OUT
5A/div
100ms/div
100us/div
V
OUT
2V/div
Trip Current=1.9A
Hold Current=0.8A
Thermal Shutdown
I
OUT
0.5A/div
200ms/div
MP5010 Rev.0.91
9/23/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
7
MP5010 – 5V, 5A PROGRAMMABLE CURRENT LIMIT SWITCH
BLOCK DIAGRAM
V
CC
Enable/
Fault
Charge
Pump
Enable
Source
I-Limit
Thermal
Shutdown
Current
Limit
UVLO
dv/dt
Control
Voltage
Clamp
dv/dt
GND
Figure 1—Functional Block Diagram
MP5010 Rev.0.91
9/23/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
8
MP5010 – 5V, 5A PROGRAMMABLE CURRENT LIMIT SWITCH
Rise Time
Current Limit
The desired current limit is a function of the
external current limit resistor.
The rise time is a function of the capacitor
(Cdv/dt) on the dv/dt pin.
Current Limit vs. Current Limit Resistor (VCC=5V)
Rise Time vs. Cdv/dt
Rise Time = KRT*(50pF+Cdv/dt), KRT =28E6
Current Limit Resistor (Ω)
Trip Current (A)
22
3.3 2.0
2.1 0.9
50
100
1.9
0.6
Cdv/dt
Rise Time
(TYPICAL)
(ms)
none 50pF 500pF 1nF
Hold Current (A)
1.4 2.8 15.4 29.4
The hold current refers to the current limit.
However, the current limit is set to the “trip
current” level when the output (source voltage)
is near Vcc. As the output decreasing, the
current limit is decreased to the “hold current”
level.
The “start-up rise time” is measured by taking
the 10% to 90% time and multiplied by 1.25 to
get the “interpolated” 0% to 100% rise time.
In a typical application using a current limit
resistor of 22ꢀ, the trip current will be 3.3A and
the hold current will be 2.1A. If the device is in
its normal operating state and passing 2.0A it
will need to dissipate only 176mW with the very
low on resistance of 44mꢀ. For the package
dissipation of 50°C/Watt, the temperature rise
will only be + 9°C. Combined with a 25°C
ambient, this is only 34°C total package
temperature.
Supply
100%
Output
90%
Enable
10%
10_90 Rise Time
Start-Up Rise
During a short circuit condition, the device now
has 5V across it and the hold current clamps at
2.1A and therefore must dissipate 10.5W. At
50°C/watt, if uncontrolled, the temperature
would rise above the MP5010 thermal
protection (+175°C) and shutdown the device to
cause the temperature to drop below a
hysteresis level. Proper heat sink must be used
if the device is intended to supply the hold
current and not shutdown. Without a heat sink,
hold current should be maintained below
600mA at + 25°C and below 360mA at +85°C to
prevent the device from activating the thermal
shutdown feature.
Fault and Enable Pin
The Enable/Fault Pin is a Bi-Directional three
levels I/O with a weak pull up current (25uA
typical). The three levels are low, mid and high.
It functions to enable/disable the part and to
relay Fault information.
Enable pin as an input:
1. Low and mid disable the part.
2. Low, in addition to disabling the part,
clears the fault flag.
3. High enables the part (if the fault flag is
clear).
Trip Current
Enable pin as an output:
Hold Current
1. The pull up current may (if not over
ridden) allow a “wired nor” pull up to
enable the part.
Output Current (Amps)
2. An under voltage will cause a low on
the enable pin, and will clear the fault
flag.
V
V
IN - OUT
V
OLTS
3. A thermal fault will cause a mid level on
the enable pin, and will set the fault
flag.
MP5010 Rev.0.91
9/23/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
9
MP5010 – 5V, 5A PROGRAMMABLE CURRENT LIMIT SWITCH
The Enable/Fault line must be above the mid
level for the output to be turned on.
When the supply goes above the UVLO
threshold, the output is enabled and the fault
line is released. When the fault line is released
it will be pulled high by a 25uA current source.
No external pull up resistor is required. In
addition, the pull up voltage is limited to 5 volts.
The fault flag is an internal flip-flop that can be
set or reset under various conditions:
1. Thermal Shutdown: set fault flag
2. Under Voltage: reset fault flag
3. Low voltage on Enable/Fault pin: reset
fault flag
4. Mid voltage on Enable/Fault pin: no
effect
Thermal Protection
When thermal protection is triggered, the output
is disabled and the fault line is driven to the mid
level. The thermal fault condition is latched
(meaning the fault flag is set), and the part will
remain latched off until the fault (enable) line is
brought low. Cycling the power below the UVLO
threshold will also reset the fault flag.
Under a fault, the Enable/Fault pin is driven to
the mid level.
There are 4 types of faults, and each fault has a
direct and indirect effect on the Enable/Fault pin
and the internal fault flag. In a typical
application there are one or more of the
MP5010 chips in a system. The Enable/Fault
lines will typically be connected together.
Under Voltage Lock Out Operation
If the supply (input) is below the UVLO
threshold, the output is disabled, and the fault
line is driven low.
Effect on Fault
Pin
Effect on
Flag
Effect on secondary
Part
Fault description
Internal action
Short/over current
Limit current
none
Internally drives
Enable/Fault pin to
Logic low
none
none
Secondary part output is
disabled, and fault flag is
reset.
Flag is
reset
Under Voltage
Over Voltage
Output is turned off
Limit output voltage
Shutdown part. The
part is latched off
until a UVLO or
externally driven to
ground.
None
None
None
Internally drives
Enable/Fault pin
to mid level
Secondary part output is
disabled.
Thermal Shutdown
Flag is Set
MP5010 Rev.0.91
9/23/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
10
MP5010 – 5V, 5A PROGRAMMABLE CURRENT LIMIT SWITCH
PCB Layout
PCB layout is very important to achieve stable
operation. Please follow these guidelines and
take below figure for reference.
dv/dt pin and input cap close to Vcc pin. Keep the
N/C pin float. Put vias in thermal pad and ensure
enough copper area near Vcc and source to
achieve better thermal performance.
Place Rlimit close to I_limit pin, Cdv/dt close to
Top Layer
Bottom Layer
Figure 2―PCB Layout
MP5010 Rev.0.91
9/23/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
11
MP5010 – 5V, 5A PROGRAMMABLE CURRENT LIMIT SWITCH
QFN10 (3mm x 3mm)
PACKAGE INFORMATION
2.90
3.10
0.30
0.50
1.45
1.75
PIN 1 ID
SEE DETAIL A
PIN 1 ID
MARKING
0.18
0.30
10
1
5
2.25
2.55
2.90
3.10
PIN 1 ID
INDEX AREA
0.50
BSC
6
TOP VIEW
BOTTOM VIEW
PIN 1 ID OPTION A
R0.20 TYP.
PIN 1 ID OPTION B
R0.20 TYP.
0.80
1.00
0.20 REF
0.00
0.05
SIDE VIEW
DETAIL A
NOTE:
2.90
1) ALL DIMENSIONS ARE IN MILLIMETERS.
0.70
1.70
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX.
4) DRAWING CONFORMS TO JEDEC MO-229, VARIATION VEED-5.
5) DRAWING IS NOT TO SCALE.
0.25
0.50
2.50
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP5010 Rev. 0.91
9/23/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
12
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