MP1531DQ [MPS]
Low Power, Triple Output Step-Up Plus Charge Pump for TFT Bias; 低功耗，三路输出升压加电荷泵为TFT偏置
| 型号： | MP1531DQ |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Low Power, Triple Output Step-Up Plus Charge Pump for TFT Bias |
| 文件： | 总12页 (文件大小：349K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP1531
Low Power, Triple Output Step-Up
Plus Charge Pump for TFT Bias
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP1531 is a triple output step-up converter
with charge-pumps to make a complete DC/DC
converter to power a TFT LCD panel from a
2.7V to 5.5V supply.
•
•
•
2.7V to 5.5V Operating Input Range
500mA Switch Current Limit
3 Outputs in a Single Package
•
•
•
Step-Up Converter up to 22V
Positive 10mA Linear Regulator
Negative 10mA Linear Regulator
The MP1531 includes a 250KHz fixed frequency
step-up converter and a positive and negative
linear regulator. The linear regulators are
powered via charge-pumps driven by the step-up
converter switch node.
•
•
•
•
•
•
•
•
•
•
•
•
•
250mΩ Internal Power MOSFET Switch
95% Efficiency
1µA Shutdown Mode
Fixed 250KHz Frequency
Positive Regulator up to 38V
Negative Regulator down to -20V
Internal Power-On Sequencing
Adjustable Soft-Start/Fault Timer
Thermal Shutdown
Cycle-By-Cycle Over Current Protection
Under Voltage Lockout
Ready Flag
A single on/off control enables all 3 outputs.
The outputs are internally sequenced at
power-on for ease of use. An internal soft-start
prevents overloading the input source at
startup. Cycle-by-cycle current limit reduces
component stress.
The MP1531 is available in both a tiny 16-pin
QFN package (3mm x 3mm) and a 16-pin
TSSOP package.
16-Pin TSSOP and QFN (3mm x 3mm) Packages
EVALUATION BOARD REFERENCE
APPLICATIONS
Board Number
Dimensions
•
•
•
•
TFT LCD Displays
Portable DVD Players
Tablet PCs
EV1531DQ-002A
2.3”X x 2.3”Y x 0.5”Z
Car Navigation Displays
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
V
IN
2.7V-4.2V
Efficiency vs
Load Current
100
V
= 4.2V
IN
90
80
70
60
50
40
30
20
V
= 3.3V
CT RDY IN
IN
OFF ON
EN
V
MAIN
5V
SW
COMP
FB1
TO
SW
IN2
MP1531
IN3
V
GL
-4V
GL
FB2
V
GH
12V
V
= 5V
MAIN
GH
FB3
REF
0
100 200 300 400 500 600
LOAD CURRENT (mA)
GND
PGND
MP1531 Rev. 1.2
5/22/2006
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2006 MPS. All Rights Reserved.
1
MP1531 – LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS
PACKAGE REFERENCE
TOP VIEW
PIN 1 ID
TOP VIEW
PGND IN3
GH
IN2
13
16 15
14
RDY
FB1
1
2
3
4
5
6
7
8
16 CT
15 SW
14 PGND
13 IN3
12 GH
11 IN2
10 GL
SW
CT
1
2
3
4
12 GL
COMP
IN
11
EN
RDY
FB1
10 FB3
GND
REF
FB2
9
FB2
5
6
7
8
FB3
9
EN
COMP IN
GND REF
EXPOSED PAD
CONNECT TO PIN 13
Part Number*
Package
Temperature
Part Number**
Package
Temperature
QFN16
(3mmx3mm)
MP1531DQ
–40°C to +85°C
MP1531DM
TSSOP16
–40°C to +85°C
For Tape & Reel, add suffix –Z (eg. MP1531DQ–Z)
For RoHS compliant packaging, add suffix –LF
(eg. MP1531DQ–LF–Z)
** For Tape & Reel, add suffix –Z (eg. MP1531DM–Z)
*
For RoHS compliant packaging, add suffix –LF
(eg. MP1531DM–LF–Z)
Recommended Operating Conditions (2)
Input Voltage .................................. 2.7V to 5.5V
Main Output Voltage...........................VIN to 22V
IN2, GL Voltage................................ 0V to –20V
IN3, GH Voltage ................................. 0V to 38V
Operating Temperature .............–40°C to +85°C
ABSOLUTE MAXIMUM RATINGS (1)
IN Supply Voltage..........................–0.3V to +6V
SW Voltage..................................–0.3V to +25V
IN2, GL Voltage ...........................+0.3V to –25V
IN3, GH Voltage...........................–0.3V to +40V
IN2 to IN3 Voltage .......................–0.3V to +60V
All Other Pins.................................–0.3V to +6V
Junction Temperature...............................125°C
Lead Temperature ....................................260°C
Storage Temperature ............. –65°C to +150°C
Thermal Resistance (3)
θJA
θJC
QFN16....................................60..... 120.. °C/W
TSSOP16 ...............................90...... 30... °C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The device is not guaranteed to function outside of its
operating conditions.
3) Measured on approximately 1” square of 1 oz copper.
ELECTRICAL CHARACTERISTICS (4)
VIN = 5.0V, TA = +25°C, unless otherwise noted.
Parameter
Symbol Condition
Min
2.7
2.25
Typ
Max
5.5
2.65
Units
V
V
mV
µA
mA
V
V
mV
µA
Input Voltage Range
IN Undervoltage Lockout Threshold
IN Undervoltage Lockout Hysteresis
IN Shutdown Current
IN Quiescent Current
EN Input High Voltage
EN Input Low Voltage
EN Hysteresis
VIN
VUVLO IN Rising
100
0.5
0.8
VEN < 0.3V
VEN > 2V, VFB1 = 1.4V
VEN-HIGH EN Rising
1
1.5
1.6
0.3
1
100
EN Input Bias Current
MP1531 Rev. 1.2
5/22/2006
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2006 MPS. All Rights Reserved.
2
MP1531 – LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS
ELECTRICAL CHARACTERISTICS (4) (continued)
VIN = 5.0V, TA = +25°C, unless otherwise noted.
Parameter
Symbol Condition
Min
Typ
Max
Units
Oscillator
Switching Frequency
Maximum Duty Cycle
Soft-Start Period
fSW
DM
200
85
250
90
6
300
KHz
%
ms
µs
C4 = 10nF
Turn-Off Delay
3
Error Amplifier
Error Amplifier Voltage Gain
Error Amplifier Transconductance
COMP Maximum Output Current
FB1, FB3 Regulation Voltage
FB2 Regulation Voltage
FB1, FB3 Input Bias Current
FB2 Input Bias Current
Reference (REF)
AvEA
GmEA
400
1000
±100
1.25
0
V/V
µA/V
µA
V
mV
nA
1.22
–25
1.28
+25
VFB1 = VFB3 = 1.25V
VFB2 = 0V
±100
±100
nA
REF Regulation Voltage
REF Load Regulation
Output Switch (SW)
IREF = 50µA
0µA < IREF < 200µA
1.22
0.5
1.25
1
1.28
1.2
V
%
VIN = 5V
VIN = 3V
250
400
0.65
0.5
mΩ
mΩ
A
µA
V
SW On Resistance
SW Current Limit
ILIM
SW Leakage Current
GL Dropout Voltage (5)
GH Dropout Voltage (5)
GL Leakage Current
GH Leakage Current
Thermal Shutdown
VSW = 22V
1
0.15
0.5
1
VGL = –10V, IGL = 10mA
VGH = 20V, IGH = 10mA
VIN2 = –15V, VGL = GND
VIN3 = 25V, VGH = GND
V
µA
µA
°C
1
160
Notes:
4) Typical values are guaranteed by design, not production tested.
5) Dropout voltage is the input to output differential at which the circuit ceases to regulate against further reduction in input voltage.
TYPICAL PERFORMANCE CHARACTERISTICS
Circuit of Figure 3, unless otherwise noted.
Load Transient
Power-Up Sequencing
V
= 3.3V, V = 5V,
V
= 3.3V, V
= 5V, I = 100mA,
IN
MAIN
IN
MAIN
MAIN
5mA-50mA Step, V = 15V,
GH
Efficiency vs Load Current
Delivered by Step-Up Converter
V
= 15V, I = 5mA, V = -10V,
GH GL
GH
= 5mA
I
= 5mA, V = -10V, I = 5mA
GL GL
I
GH
GL
100
90
80
70
60
50
40
30
20
V
= 4.2V
IN
V
= 3.3V
IN
V
V
EN
MAIN
5V/div
50mV/div
V
MAIN
5V/div
V
GH
10V/div
I
V
MAIN
GL
50mA/div
10V/div
V
= 5V
MAIN
0
100 200 300 400 500 600
LOAD CURRENT (mA)
10ms/div
MP1531 Rev. 1.2
5/22/2006
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2006 MPS. All Rights Reserved.
3
MP1531 – LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS
PIN FUNCTIONS
QFN16 TSSOP16
Pin #
Pin #
Name Description
1
15
SW Step-Up Converter Power Switch Node. Connect an inductor between the input source
and SW, and connect a rectifier from SW to the main output to complete the step-up
converter. SW is the drain of the internal 250mΩ N-Channel MOSFET switch.
2
3
16
1
CT
Timing Capacitor for Soft-Start and Power-On Sequencing. A capacitor from CT to
GND controls the soft-start and sequencing turn-on delay periods. See Power-On
Sequencing and Start-Up Timing Diagram.
Regulators Not Ready. This pin is an open drain output, and an external 100kꢀ
RDY
pull-up resistor is required for proper operation. During startup RDY will be high
impedance. Once the turn-on sequence is complete, this pin will be pulled low if all
FB voltages exceed 80% of their specified thresholds. After all regulators are
turned-on, a fault in any regulator that causes the respective FB voltage to fall
below 80% of its threshold will cause RDY to go high after approximately 15µs. If
the fault persists for more than approximately 6ms (for C4 = 10nF), the entire chip
will shut down. See Fault Sensing and Timer.
4
2
FB1 Step-Up Converter Feedback Input. FB1 is the inverting input of the internal error
amplifier. Connect a resistive voltage divider from the output of the step-up
converter to FB1 to set the step-up converter output voltage.
5
6
3
4
COMP Step-Up Converter Compensation Node. COMP is the output of the error amplifier. Connect
a series RC network to compensate the regulation control loop of the step-up converter.
IN
Internal Power Input. IN supplies the power to the MP1531. Bypass IN to PGND
with a 10µF or greater capacitor.
7
8
5
6
GND Signal Ground.
REF Reference Output. REF is the 1.25V reference voltage output. Bypass REF to GND
with a 0.1µF or greater capacitor. Connect REF to the low-side resistor of the
negative linear regulator feedback string.
9
7
8
9
FB2 Negative Linear Regulator Feedback Input. Connect the FB2 feedback resistor
string between GL and REF to set the negative linear regulator output voltage. FB2
regulation threshold is GND.
FB3 Positive Linear Regulator Feedback Input. Connect the FB3 feedback resistor string
between GH and GND to set the positive linear regulator output voltage. FB3
regulation threshold is 1.25V.
EN On/Off Control Input. Drive EN high to turn on the MP1531, drive EN low to turn it
off. For automatic startup, connect EN to IN. Once the MP1531 is turned on, it
sequences the outputs on (See Power-On Sequencing). When turned off, all
outputs are immediately disabled.
10
11
12
13
14
15
16
10
11
12
13
14
GL Negative Linear Regulator Output. GL is the output of the negative linear regulator.
GL can supply up to 10mA to the load. Bypass GL to GND with a 1µF or greater,
low-ESR, ceramic capacitor.
IN2 Negative Linear Regulator Input. IN2 is the input of the negative linear regulator. Drive
IN2 with an inverting charge pump powered from SW. IN2 can go as low as –20V. For
QFN package IN2 connects to exposed pad.
GH Positive Linear Regulator Output. GH is the output of the positive linear regulator.
GH can supply as much as 10mA to the load. Bypass GH to GND with a 1µF or
greater, low-ESR, ceramic capacitor.
IN3 Positive Linear Regulator Input. IN3 is the input to the positive linear regulator.
Drive IN3 with a doubling, tripling, or quadrupling charge pump from SW. IN3
voltage can go as high as 38V.
PGND Power Ground. PGND is the source of the internal 250mꢀ N-Channel MOSFET
switch. Connect PGND to GND as close to the MP1531 as possible.
MP1531 Rev. 1.2
5/22/2006
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2006 MPS. All Rights Reserved.
4
MP1531 – LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS
OPERATION
The MP1531 is a step-up converter with two
integrated linear regulators to power TFT LCD
panels. Typically the linear regulators are
powered from diode charge-pumps driven from
the switch node (SW). The user can set the
positive charge-pump to be a doubler, tripler, or
quadrupler to achieve the required linear
regulator input voltage for the selected output
voltage. Typically the negative charge-pump is
configured as a 1x or 2x inverter.
IN
REFERENCE
REF
SW
V
REF
+
--
G
M
PULSE-WIDTH
MODULATOR
FB1
COMP
OSCILLATOR
0.8V
0.2V
REF
REF
+
--
PGND
0.8V
REF
SOFT-START
FAULT TIMER
&
+
--
SEQUENCING
+
--
EN
CT
V
REF
--
+
FB2
+
--
FB3
IN3
IN2
GL
GH
RDY
GND
Figure 1—Functional Block Diagram
MP1531 Rev. 1.2
5/22/2006
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2006 MPS. All Rights Reserved.
5
MP1531 – LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS
Step-Up Converter
Power-On Sequencing and Soft-Start
The MP1531 automatically sequences its
outputs at startup. When EN goes from low to
high, or if EN is held high and the input voltage
VIN rises above the under-voltage lockout
threshold, the outputs turn on in the following
sequence:
The 250KHz fixed-frequency step-up converter
employs a current-mode control architecture
that maximizes loop bandwidth to provide fast-
transient responses needed for TFT LCD
drivers. High switching frequency allows for
smaller inductors and capacitors minimizing
board space and thickness.
1. Step-up converter
Linear Regulators
2. Negative linear regulator (GL)
3. Positive linear regulator (GH)
The positive linear regulator (GH) uses a
P-Channel pass element to drop the input
voltage down to the regulated output voltage.
The feedback of the positive linear regulator is
Each output turns on with a soft-start voltage
ramp. The soft-start ramp period is set by the
timing capacitor connected between CT and
GND. A 10nF capacitor at CT sets the soft-start
ramp period to 6ms. The timing diagram is
shown in Figure 2.
a
conventional error amplifier with the
regulation threshold at 1.25V.
The negative linear regulator (GL) uses a
N-Channel pass element to raise the negative
input voltage up to the regulated output voltage.
The feedback threshold for the negative linear
regulator is ground. The resistor string goes
from REF (1.25V) to FB2 and from FB2 to GL to
set the negative output voltage, VGL.
After the MP1531 is enabled, the power-on
reset spans three periods of the CT ramp. First
the step-up converter is powered up with
reference to the CT ramp and allowed one
period of the CT ramp to settle. Next the
negative linear regulator (GL) is soft-started by
ramping REF, which coincides with the CT
ramp, and also allowed one CT ramp period to
settle.
The difference between the voltage at IN3 and
the voltage at IN2 is limited to 60V abs. max.
Fault Sensing and Timer
Each of the 3 outputs has an internal
comparator that monitors its respective output
voltage by measuring the voltage at its
respective FB input. When any FB input
indicates that the output voltage is below
approximately 80% of the correct regulation
The positive linear regulator (GH) is then
soft-started and allowed to settle in one period
of CT ramp. Nine periods of the CT ramp have
occurred since the chip enabled. If all outputs
are in regulation (>80%), the CT will stop
ramping and be held at ground. The RDY pin
will be pulled down to an active low. If any FB
voltage remains below regulation (<80%) after
voltage, the fault timer enables and the RDY
pin goes high impedance. The fault timer uses
the same CT capacitor as the soft-start
sequencer. If any fault persists to the end of the
fault timer (One CT cycle is 6ms for a 10nF
capacitor), all outputs are disabled. Once the
outputs are shut down due to the fault timer, the
MP1531 must be re-enabled by either cycling
EN or by cycling the input power. When re-
enabled, the MP1531 cycles through the normal
power-on sequence. If the fault persists for less
the nine CT periods, RDY will remain high and
CT will begin its fault timer pulse.
than the fault timer period, RDY will be pulled
low and the part will function as though no fault
has occurred.
MP1531 Rev. 1.2
5/22/2006
www.MonolithicPower.com
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© 2006 MPS. All Rights Reserved.
6
MP1531 – LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS
V
GH
OUTPUT
VOLTAGES
V
MAIN
V
IN
0V
V
GL
V
IN
IN
0V
V
EN-HIGH
EN
0V
POWER ON RESET
START 1
START 2
START 3
1.25V
CT
0V
V
IN
RDY
0V
TIME
Figure 2—Start-Up Timing Diagram
APPLICATION INFORMATION
Setting the Output Voltages
For the positive charge-pump, determine the
high-side resistor R9 by the equation:
Set the output voltage on each output by
selecting the resistive voltage divider ratio. The
voltage divider drops the output voltage to the
feedback threshold voltage. Use 10kꢀ to 50kꢀ
for the low-side resistor of the voltage divider.
VGH − VFB3
R9 =
V
⎛
⎞
FB3
⎜
⎜
⎟
⎟
R8
⎝
⎠
For the step-up converter, determine the
high-side resistor R1 by the equation:
For the negative charge-pump, determine the
high-side resistor R7 by the equation:
VMAIN − VFB1
R1 =
−VGL
R7 =
V
⎛
⎞
V
REF
⎛
⎞
FB1
⎜
⎜
⎟
⎟
⎜
⎜
⎟
⎟
R2
R5
⎝
⎠
⎝
⎠
Where VMAIN is the output voltage of the step-up
converter.
MP1531 Rev. 1.2
5/22/2006
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2006 MPS. All Rights Reserved.
7
MP1531 – LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS
Selecting the Inductor
VIN
(
VMAIN − VIN
)
L1 =
The inductor is required to force the higher
output voltage while being driven by the input
voltage. A larger value inductor results in less
ripple current that results in lower peak inductor
current. However, the larger value inductor has
a larger physical size, higher series resistance,
lower saturation current for a given package
size.
VMAIN × fSW × ∆I
Where VIN is the input voltage, fSW is the
switching frequency, and ∆I is the peak-to-peak
inductor ripple current.
Selecting the Input Capacitor
An input capacitor is required to supply the AC
ripple current to the inductor, while limiting noise
at the input source. A low ESR capacitor is
required to keep the noise at the IC to a minimum.
Since it absorbs the input switching current it
requires an adequate ripple current rating. Use a
capacitor with RMS current rating greater than the
inductor ripple current (see Selecting The Inductor
to determine the inductor ripple current). The
input capacitor in Figure 3 is necessary in most
lab setups, but can be reduced in typical
application circuits if the source impedance is
lower.
Choose an inductor that does not saturate at
heavy load transients and start-up conditions. A
good rule for determining the inductance is to
allow the peak-to-peak ripple current to be
approximately 30-50% of the maximum input
current. Make sure that the peak inductor
current is below the device current limit to
prevent loss of regulation. Calculate the
required inductance value by the equation:
V
IN
2.7V to 4.2V
C4
10nF
D1
B0530W
CT
EN
IN
SW
V
MAIN
5V
OFF ON
RDY
RDY
FB1
SW
COMP
C3
10nF
D2
BAS40-04-7
IN2
MP1531
D6
D7
D5
BAS40-04-7
BAS40-04-7
BAS40-04-7
IN3
V
GL
-10V
GL
D4
D3
BAS40-04-7
BAS40-04-7
V
FB2
GH
15V
GH
C9
56pF
FB3
REF
C7
56pF
GND
PGND
Figure 3—Triple Output Boost Application Circuit
MP1531 Rev. 1.2
5/22/2006
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2006 MPS. All Rights Reserved.
8
MP1531 – LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS
To insure stable operation place the input
dropout margin for the linear regulator. The
positive charge-pump can also be configured
based on VIN for better efficiency. Then the
equation will be:
capacitor as close to the IC as possible.
Alternately a smaller high quality 0.1µF ceramic
capacitor may be placed closer to the IC if the
larger capacitor is placed further away.
VGH + VDROPOUT − VIN
VMAIN − 2× VD
)
NPOS
≅
Selecting the Rectifier Diodes
Schottky diodes are recommended for most
applications because of their fast recovery time
and low forward voltage. Use Schottky diodes
with a current rating equal to or greater than 4
times the average output current, and a voltage
rating at least 1.5 times VGH for the positive
charge-pump and VGL for the negative charge-
pump. 100mA Schottky diodes such as Central
Semiconductor CMPSH-3 are recommended
for low current charge-pump circuits.
The number of negative charge-pump stages
NEG is approximately given by:
N
−VGL + VDROPOUT
VMAIN − 2× VD
NNEG
≅
Use VDROPOUT = 0.5V for positive charge-pump
and VDROPOUT = 0.15V for negative charge-pump.
Selecting the Flying Capacitor in Charge-
Pump Stages
Selecting the Output Capacitor of the Step-
Up Converter
Increasing the flying capacitor CX values
increases the output current capability. A
0.33µF ceramic capacitor works well in most
low current applications. The flying capacitor’s
voltage rating must exceed the following:
The output capacitor is required to maintain the
DC output voltage. Low ESR capacitors are
preferred to keep the output voltage ripple to a
minimum. The characteristics of the output
capacitor also affect the stability of the
regulation control system. A 10-22µF ceramic
capacitor works well in most applications. In the
case of ceramic capacitors, the impedance of
the capacitor at the switching frequency is
dominated by the capacitance, and so the
output voltage ripple is mostly independent of
the ESR. The output voltage ripple is estimated
to be:
VCX > N× VMAIN
Where N is the stage number in which the flying
capacitor appears.
Step-Up Converter Compensation
The MP1531 uses current-mode control which
unlike voltage mode has only a single pole roll
off due to the output filter. The DC gain (AVDC) is
equated from the product of current control to
output gain (AVCSCONTROL), error amplifier gain
(VMAIN − VIN )×ILOAD
(AV ), and the feedback divider.
EA
VRIPPLE
≅
VMAIN × C2× fSW
AvDC = ACSCONTROL × AvEA × AFB1
Where VRIPPLE is the output ripple voltage, ILOAD
is the load current, and C2 is the capacitance of
the output capacitor of the step-up converter.
VIN
ACSCONTROL = 4 ×
ILOAD
VFB1
Selecting the Number of Charge-Pump
Stages
AFB1
=
VMAIN
For highest efficiency, always choose the
lowest number of charge-pump stages that
meets the output requirement.
1600 × VIN × VFB1
ILOAD × VMAIN
AvDC
=
The number of positive charge-pump stages
NPOS is approximately given by:
The output filter pole is given in hertz by:
ILOAD
fFILTERPOLE
=
(
VGH + VDROPOUT − VMAIN
VMAIN − 2× VD
)
π × VMAIN × C2
NPOS
≅
Where VD is the forward voltage drop of the
charge-pump diode, and VDROPOUT is the
MP1531 Rev. 1.2
5/22/2006
www.MonolithicPower.com
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MP1531 – LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS
The output filter zero is given in hertz by:
For the positive linear regulator:
1
1
fFILTERZERO
=
fPOSPOLE1 =
2× π × RESR × C2
2 × π ×
(
R10 + R9 || R8 × C7
)
Where RESR is the equivalent series resistance
of the output capacitor.
1
fPOSZERO1
=
2 × π ×
(
R10 + R9 × C7
)
With all boost regulators the right half plane
zero (RHPZ) is given in hertz by:
For the negative linear regulator:
1
fNEGPOLE1
=
2
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
VIN
VMAIN
2× π ×
(
R6 + R7 || R5 × C9
)
fRHPZ
=
×
VMAIN
2 × π ×ILOAD × L1
1
fNEGZERO1
=
2× π ×
(
R6 + R7 × C9
)
Error Amplifier Compensation
To stabilize the feedback loop dynamics the
error amplifier compensation is as follows:
fPOSPOLE1 and fNEGPOLE1 are necessary to cancel
out the zero created by the equivalent series
resistance (RLDOESR) of the output capacitor.
1
fPOLE1
≈
2 × π ×106 × C3
1
fLDOZERO
=
2× π × RLDOESR × CLDO
1
fZERO1
=
2π × R3 × C3
For component values shown in Figure 3 a 10ꢀ
and 56pF RC network gives about 45° of phase
margin and a bandwidth of about 35KHz on
both regulators.
Where R3 and C3 are part of the compensation
network in Figure 3. A good start is 5.6kꢀ and
10nF. This combination gives about 70° of
phase margin and bandwidth of about 35KHz
for most load conditions. Increasing R3 and/or
reducing C3 increases the loop bandwidth and
improves the load transient.
Layout Considerations
Careful PC board layout is important to
minimize ground bounce and noise. First, place
the main boost converter inductor, output diode
and output capacitor as close to the SW and
PGND pins as possible with wide traces. Then
place ceramic bypass capacitors near IN, IN2
and IN3 pins to the PGND pin. Keep the
charge-pump circuitry close to the IC with wide
traces. Locate all FB resistive dividers as close
to their respective FB pins as possible.
Separate GND and PGND areas and connect
them at one point as close to the IC as
possible. Avoid having sensitive traces near the
SW node and high current lines. Refer to the
MP1531 demo board for an example of proper
board layout.
Linear Regulator Compensation
The positive or negative regulated voltages of
two linear regulators are controlled by a
transconductance amplifier and a P-channel or
N-Channel pass transistor respectively. The DC
gain of either LDO is approximately 100dB with
a slight dependency on load current. The output
capacitor (CLDO) and resistance load (RLOAD
)
make-up the dominant pole.
1
fLDOPOLE1
=
2× π × RLOAD × CLDO
The pass transistor’s internal pole is about
10Hz to 30Hz. To compensate for the two pole
system and add more phase and gain margin, a
lead-lag
resistor
capacitor
network
is
necessary.
MP1531 Rev. 1.2
5/22/2006
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2006 MPS. All Rights Reserved.
10
MP1531 – LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS
PACKAGE INFORMATION
QFN16 (3mm x 3mm)
MP1531 Rev. 1.2
5/22/2006
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2006 MPS. All Rights Reserved.
11
MP1531 – LOW POWER, TRIPLE OUTPUT STEP-UP PLUS CHARGE PUMP FOR TFT BIAS
TSSOP16
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP1531 Rev. 1.2
5/22/2006
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2006 MPS. All Rights Reserved.
12
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