MP1474SGJ-Z [MPS]
Switching Regulator;
| 型号： | MP1474SGJ-Z |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Switching Regulator |
| 文件： | 总19页 (文件大小：615K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP1474S
High-Efficiency, 2A, 16V, 500kHz
Synchronous, Step-Down Converter
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The
MP1474S
is
a
high-frequency,
•
•
Wide 4.5V to 16V Operating-Input Range
150mΩ/70mΩ Low RDS(ON) Internal Power
MOSFETs
High-Efficiency Synchronous-Mode
Operation
Fixed 500kHz Switching Frequency
Synchronizes from a 300kHz to 2MHz
External Clock
Power-Save Mode at Light Load
Internal Soft-Start
Power Good Indicator
Over-Current Protection and Hiccup
Thermal Shutdown
Output Adjustable from 0.8V
Available in a 8-pin TSOT-23 Package
synchronous, rectified, step-down, switch-mode
converter with built-in power MOSFETs. It
offers a compact solution to achieve a 2A
continuous output current with excellent load
and line regulation over a wide input-supply
range. The MP1474S has synchronous-mode
operation for higher efficiency over the output
current-load range.
•
•
•
•
•
•
•
•
•
•
Current-mode operation provides fast, transient
response and eases loop stabilization.
Full protection features include over-current
protection (OCP) and thermal shutdown (TSD).
The MP1474S requires a minimal number of
readily
available,
standard,
external
APPLICATIONS
components and is available in a space-saving
8-pin TSOT23 package.
•
•
•
•
Notebook Systems and I/O Power
Digital Set-Top Boxes
Flat-Panel Television and Monitors
Distributed Power Systems
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Quality Assurance. “MPS” and “The
Future of Analog IC Technology” are Registered Trademarks of Monolithic
Power Systems, Inc.
TYPICAL APPLICATION
100
95
90
VIN=5V
85
80
VIN=12V
75
70
VIN=16V
65
60
0
0.5
1
1.5
2
2.5
LOAD CURRENT(A)
MP1474S Rev.1.0
1/8/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
1
MP1474S – HIGH-EFFICIENCY, 2A, 16V, 500kHz SYNCHRONOUS STEP-DOWN CONVERTER
ORDERING INFORMATION
Part Number*
Package
Top Marking
MP1474SGJ
TSOT23-8
See Below
* For Tape & Reel, add suffix –Z (e.g. MP1474SGJ–Z).
TOP MARKING
ALD: product code of MP1474SGJ;
Y: year code;
PACKAGE REFERENCE
TOP VIEW
PG
IN
FB
1
2
3
4
8
7
6
5
VCC
SW
GND
EN/SYNC
BST
TSOT23-8
MP1474S Rev.1.0
1/8/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
2
MP1474S – HIGH-EFFICIENCY, 2A, 16V, 500kHz SYNCHRONOUS STEP-DOWN CONVERTER
ABSOLUTE MAXIMUM RATINGS (1)
VIN ................................................ -0.3V to 17V
VSW ....................................................................
-0.3V (-5V for <10ns) to 17V (19V for <10ns)
VBST ...................................................... VSW+6V
All Other Pins................................-0.3V to 6V(2)
Thermal Resistance (5)
TSOT23-8 ............................. 100..... 55... °C/W
θJA θJC
Notes:
1) Exceeding these ratings may damage the device.
2) About the details of EN/SYNC pin’s ABS MAX rating, please
refer to Page 12, Enable/SYNC control section.
3) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation will cause excessive die temperature, and the
regulator will go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
(3)
Continuous Power Dissipation (TA = +25°C)
..........................................................1.25W
Junction Temperature..............................150°C
Lead Temperature ...................................260°C
Storage Temperature.................-65°C to 150°C
Recommended Operating Conditions (4)
Supply Voltage VIN .......................... 4.5V to 16V
Output Voltage VOUT................. 0.8V to VIN*DMAX
Operating Junction Temp. (TJ). -40°C to +125°C
4) The device is not guaranteed to function outside of its
operating conditions.
5) Measured on JESD51-7, 4-layer PCB.
MP1474S Rev.1.0
1/8/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
3
MP1474S – HIGH-EFFICIENCY, 2A, 16V, 500kHz SYNCHRONOUS STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS
VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted. Typical value is tested at TJ=+25°C
Parameter
Symbol Condition
Min
Typ
2
Max
Units
μA
Supply Current (Shutdown)
Supply Current (Quiescent)
HS Switch-On Resistance
LS Switch-On Resistance
Switch Leakage
IIN
Iq
VEN = 0V
VEN = 2V, VFB = 1V
0.5
150
70
1
mA
mΩ
mΩ
μA
HSRDS-ON VBST-SW=5V
LSRDS-ON VCC =5V
SWLKG VEN = 0V, VSW =12V or 0V
1
Current Limit (6)
ILIMIT
Under 40% Duty Cycle
3
A
TJ=+25°C
410
350
500
630
650
kHz
kHz
fSW
Oscillator Frequency
fSW
VFB=0.75V
TJ=-40°C to +125°C
Foldback Frequency
Maximum Duty Cycle
Minimum On Time(6)
Sync Frequency Range
fFB
VFB<400mV
VFB=700mV
0.5
95
40
DMAX
TON-MIN
fSYNC
90
%
ns
0.3
791
787
2
MHz
TJ =25°C
807
807
10
823
827
50
Feedback Voltage
VFB
mV
-40°C<TJ<+125°C (7)
Feedback Current
IFB
VFB=830mV
nA
V
EN Rising Threshold
EN Falling Threshold
VEN-RISING
VEN-FALLING
1
1.4
1.75
1.6
0.9
1.25
V
VEN=2V
VEN=0
2
0
μA
μA
EN Input Current
IEN
EN Turn-Off Delay
ENtd-off
PGvth-Hi
PGvth-Lo
PGTd
8
μs
VFB
VFB
ms
Power-Good Rising Threshold
Power-Good Falling Threshold
Power-Good Delay
0.9
0.85
0.6
Power-Good Sink-Current
Capability
VPG
Sink 2mA
0.4
1
V
μA
V
Power-Good Leakage Current
IPG-LEAK
INUVVth
VIN Under-Voltage Lockout
Threshold—Rising
3.6
3.9
4.3
VIN Under-Voltage Lockout
Threshold—Hysteresis
INUVHYS
VCC
700
mV
VCC Regulator
5
2
V
%
VCC Load Regulation
Soft-Start Period
Thermal Shutdown (6)
Thermal Hysteresis (6)
ICC=5mA
TSS
TSD
Vo from 10% to 90%
1.2
150
20
ms
°C
°C
TSD HYS
Notes:
6) Guaranteed by design.
7) Not tested in production; guaranteed by over-temperature correlation.
MP1474S Rev.1.0
1/8/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
4
MP1474S – HIGH-EFFICIENCY, 2A, 16V, 500kHz SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL CHARACTERISTICS
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 12V, VOUT = 3.3V, L=5.5μH, TA = 25°C, unless otherwise noted.
100
95
90
85
80
75
70
65
60
0.4
0.3
0.2
0.1
0
100
95
90
85
80
75
70
65
60
VIN=12V
VIN=7V
0.5
V
IN=5V
VIN=7V
V
IN=16V
V
IN=12V
V
IN=12V
-0.1
-0.2
-0.3
-0.4
VIN=16V
VIN=16V
0
0.5
1
1.5
2
2.5
0
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
LOAD CURRENT(A)
LOAD CURRENT(A)
LOAD CURRENT(A)
0.4
0.3
0.2
0.1
0
0.4
0.3
0.2
0.1
0
100
95
90
85
80
75
70
65
60
VIN=16V
V
IN=16V
VIN=5V
V
IN=12V
V
IN=12V
V
IN=12V
-0.1
-0.2
-0.3
-0.4
-0.1
-0.2
-0.3
-0.4
VIN=5V
V
IN=5V
V
IN=16V
0
0.5
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
0
0.5
1
1.5
2
2.5
LOAD CURRENT(A)
LOAD CURRENT(A)
LOAD CURRENT(A)
0.4
0.3
0.2
0.1
0
100
90
80
70
60
50
40
100
90
80
70
60
50
VIN=16V
V
=5V
IN
VIN=5V
VIN=12V
VIN=12V
-0.1
-0.2
-0.3
-0.4
VIN=12V
V
IN=16V
VIN=16V
VIN=5V
1.5
0
0.5
1
1.5
2
2.5
0
0.5
1
2
2.5
0
0.5
1
1.5
2
2.5
LOAD CURRENT(A)
LOAD CURRENT(A)
LOAD CURRENT(A)
MP1474S Rev.1.0
1/8/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
5
MP1474S – HIGH-EFFICIENCY, 2A, 16V, 500kHz SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 12V, VOUT = 3.3V, L=5.5μH, TA = 25°C, unless otherwise noted.
MP1474S Rev.1.0
1/8/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
6
MP1474S – HIGH-EFFICIENCY, 2A, 16V, 500kHz SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 12V, VOUT = 3.3V, L=5.5μH, TA = 25°C, unless otherwise noted.
V
OUT
V
V
OUT
OUT
2V/div.
V
5V/div.
2V/div.
V
5V/div.
2V/div.
V
5V/div.
PG
PG
PG
V
IN
V
V
EN
IN
10V/div.
5V/div.
10V/div.
V
SW
V
V
SW
SW
10V/div.
10V/div.
10V/div.
I
INDUCTOR
5A/div.
I
I
INDUCTOR
2A/div.
INDUCTOR
5A/div.
V
V
OUT
V
OUT
OUT
2V/div.
2V/div.
2V/div.
V
V
PG
V
PG
PG
5V/div.
5V/div.
5V/div.
V
V
EN
V
EN
EN
5V/div.
5V/div.
5V/div.
V
V
SW
V
SW
SW
10V/div.
10V/div.
10V/div.
I
I
INDUCTOR
2A/div.
I
INDUCTOR
2A/div.
INDUCTOR
2A/div.
V
V
OUT
V
OUT
OUT
2V/div.
2V/div.
2V/div.
V
V
PG
V
PG
PG
5V/div.
5V/div.
5V/div.
V
V
IN
V
IN
IN
5V/div.
5V/div.
5V/div.
V
V
SW
V
SW
SW
5V/div.
5V/div.
5V/div.
I
I
INDUCTOR
2A/div.
I
INDUCTOR
2A/div.
INDUCTOR
2A/div.
MP1474S Rev.1.0
1/8/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
7
MP1474S – HIGH-EFFICIENCY, 2A, 16V, 500kHz SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Performance waveforms are tested on the evaluation board of the Design Example section.
VIN = 12V, VOUT = 3.3V, L=5.5μH, TA = 25°C, unless otherwise noted.
Shutdown Through
Input Voltage
Input / Output Ripple
Load Transient Response
I
=2A
I
=1A-2A
OUT
OUT
I
=2A
OUT
V
/AC
OUT
V
20mV/div.
OUT
2V/div.
V
V
/AC
PG
OUT
V
AC
IN/
5V/div.
50mV/div.
200mV/div.
V
IN
5V/div.
V
SW
V
SW
10V/div.
5V/div.
I
OUT
I
INDUCTOR
1A/div.
I
INDUCTOR
2A/div.
2A/div.
MP1474S Rev.1.0
1/8/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
8
MP1474S – HIGH-EFFICIENCY, 2A, 16V, 500kHz SYNCHRONOUS STEP-DOWN CONVERTER
PIN FUNCTIONS
Package
Pin #
Name Description
Power Good Indicator. PG is the open drain of the internal MOSFET. Connect PG to VCC
(or another voltage source) through a resistor (e.g. 100k). When the FB voltage reaches
90% of the REF voltage, PG is pulled high (after a 0.6ms delay). After the FB voltage
drops to 85% of the REF voltage, PG is pulled low.
1
2
3
PG
IN
Supply Voltage. IN supplies power to the internal MOSFET and regulator. The MP1474S
operates from a +4.5V to +16V input rail; it requires a low ESR and low-inductance
capacitor (C1) to decouple the input rail. Place the input capacitor very close to PG and
connect it with wide PCB traces and multiple vias.
Switch Output. Connect SW to the inductor and bootstrap capacitor. SW is driven up to VIN
by the high-side switch during the PWM duty cycle on-time. The inductor current drives
SW negative during the off-time. The on resistance of the low-side switch and the internal
body diode fixes the negative voltage. Connect using wide PCB traces and multiple vias.
SW
System Ground. Reference ground of the regulated output voltage. PCB layout requires
extra care (see recommended “PCB Layout Guidelines” on page 16). For best results,
connect to GND with copper and vias.
4
5
6
7
GND
BST
Bootstrap. BST requires a capacitor connected between SW and BST to form a floating
supply across the high-side switch driver.
Enable/Synchronize. EN/SYNC=high to enable the MP1474S. Apply an external clock to
EN/SYNC change the switching frequency. For automatic start-up, connect EN/SYNC to VIN with a
100kꢀ resistor.
Internal 5V LDO Output. VCC powers the driver and control circuits. Decouple with a
0.1μF to 0.22μF capacitor. Do NOT use a capacitor ≥0.22μF.
VCC
Feedback. Connect FB to the tap of an external resistor divider from the output to GND to
set the output voltage. To prevent current-limit runaway during a short-circuit fault, the
8
FB
frequency foldback comparator lowers the oscillator frequency when the FB voltage is
below 400mV. Place the resistor divider as close to FB as possible. Avoid placing vias on
the FB traces.
MP1474S Rev.1.0
1/8/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
9
MP1474S – HIGH-EFFICIENCY, 2A, 16V, 500kHz SYNCHRONOUS STEP-DOWN CONVERTER
FUNCTIONAL BLOCK DIAGRAM
Figure 1. Functional Block Diagram
MP1474S Rev.1.0
1/8/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
10
MP1474S – HIGH-EFFICIENCY, 2A, 16V, 500kHz SYNCHRONOUS STEP-DOWN CONVERTER
OPERATION
The MP1474S is a high-frequency, synchronous,
rectified, step-down, switch-mode converter with
built-in power MOSFETs. It offers a compact
solution that achieves a 2A continuous output
current with excellent load and line regulation
over a 4.5V to 16V input-supply range.
dead time), and the low-side MOSFET (LS-FET)
turns on and remains on until the inductor-current
value decreases to zero. The device repeats the
same operation in every clock cycle to regulate
the output voltage (see Figure 3).
The MP1474S has three working modes:
advanced asynchronous modulation (AAM) mode,
discontinuous conduction mode (DCM), and
continuous conduction mode (CCM). The load
current increases as the device operates from
AAM mode to DCM to CCM.
IL
AAM Control Operation
Figure 3. DCM Control Operation
In a light-load condition, MP1474S works in
advanced asynchronous modulation (AAM) mode
(see Figure 2). The VAAM is an internally fixed
voltage when input and output voltages are fixed.
VCOMP is the error amplifier output (which
represents the peak inductor-current information).
When VCOMP is lower than VAAM, the internal clock
is blocked. This causes the MP1474S to skip
pulses, achieving the light-load power save.
Refer to AN032 for additional details.
CCM Control Operation
The device enters continuous conduction mode
(CCM) from DCM once the inductor current no
longer drops to zero in a clock cycle. In CCM, the
internal clock initiates the PWM cycle, the HS-
FET turns on and remains on until VILsense
reaches the value set by VCOMP (after a period of
dead time), and the LS-FET turns on and
remains on until the next clock cycle begins. The
device repeats the same operation in every clock
cycle to regulate the output voltage.
The internal clock re-sets every time VCOMP is
higher than VAAM. At the same time, the high-side
MOSFET (HS-FET) turns on and remains on until
If VILsense does not reach the value set by VCOMP
within 95% of one PWM period, the HS-FET is
forced off.
VILsense reaches the value set by VCOMP.
The light-load feature in this device is optimized
for 12V input applications.
Internal Regulator
A 5V internal regulator powers most of the
internal circuitries. This regulator is supplied by
VIN and operates in the full VIN range. When VIN
exceeds 5V, the output of the regulator is in full
regulation. When VIN is less than 5V, the output
decreases, and the device requires a 0.1µF
ceramic decoupling capacitor.
Error Amplifier (EA)
Figure 2. Simplified AAM Control Logic
The error amplifier compares the FB voltage to
the internal 0.807V reference (VREF) and outputs
a current proportional to the difference between
the two. This output current then charges or
discharges the internal compensation network to
form the COMP voltage, which controls the
DCM Control Operation
The VCOMP voltage ramps up as the output
current increases. When its minimum value
exceeds VAAM, the device enters discontinuous
conduction mode (DCM). In DCM, the internal
clock initiates the PWM cycle, the
HS-FET turns on and remains on until VILsense
reaches the value set by VCOMP (after a period of
MP1474S Rev.1.0
1/8/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
11
MP1474S – HIGH-EFFICIENCY, 2A, 16V, 500kHz SYNCHRONOUS STEP-DOWN CONVERTER
power MOSFET current. The optimized, internal
(VSTOP) above 4.5V using the enable resistors.
Set the rising threshold (VSTART) to provide
enough hysteresis to allow for input-supply
variations.
compensation network minimizes the external
component count and simplifies the control loop
design.
Enable/SYNC Control
EN/SYNC is a digital control pin that turns the
regulator on and off. Drive EN/SYNC high to turn
on the regulator; drive EN/SYNC low to turn off
the regulator. An internal 1Mꢀ resistor from
EN/SYNC to GND allows EN/SYNC to be floated
to shut down the chip.
REN_UP
EN/SYNC
REN_DOWN
EN/SYNC is clamped internally using a 6.5V
series-Zener-diode (see Figure 4). Connecting
EN/SYNC through a pull-up resistor to the
voltage on IN limits the EN/SYNC input current to
less than 100µA.
Figure 5. Adjustable UVLO
Internal Soft-Start
For example, with 12V connected to IN, RPULLUP
≥
The soft-start prevents the converter output
voltage from overshooting during start-up. When
the chip starts up, the internal circuitry generates
a soft-start voltage (VSS) that ramps up from 0V
to 1.2V. When VSS is less than VREF, the error
amplifier uses VSS as the reference. When VSS
exceeds VREF, the error amplifier uses VREF as
the reference. The SS time is set internally to
1.2ms.
(12V – 6.5V) ÷ 100µA = 55kꢀ.
Connecting EN/SYNC directly to a voltage
source without a pull-up resistor requires limiting
the amplitude of the voltage source to ≤6V to
prevent damage to the Zener diode.
Pre-Bias Start-Up
The MP1474S is designed for a monotonic start-
up into pre-biased loads. If the output is pre-
biased to a certain voltage during start-up, the
BST voltage is refreshed and charged. Also, the
voltage on the soft-start capacitor is charged. If
BST voltage exceeds its rising threshold voltage,
and the soft-start capacitor voltage exceeds the
sensed-output voltage at FB, the device starts to
operate normally.
Figure 4. 6.5V Zener Diode Connection
For external clock synchronization, connect a
clock with a frequency range between 300kHz
and 2MHz. The internal clock rising edge
synchronizes with the external clock rising edge.
Select an external clock signal with a pulse width
less than 1.7μs.
Under-Voltage Lockout (UVLO)
Power Good Indicator (PG)
The MP1474S has under-voltage lockout
protection (UVLO). When the VCC voltage
exceeds the UVLO rising threshold voltage, the
device begins to power up. It shuts off when the
VCC voltage drops below the UVLO falling
threshold voltage. This is non-latch protection.
MP1474S has an open-drain pin as the power
good indicator (PG). Pull PG up to VCC (or
another external source) through a 100kꢀ
resistor. When VFB exceeds 90% of VREF, PG
goes high (after a 0.6ms delay time). If VFB goes
below 85% of VREF, an internal MOSFET pulls
PG down to ground.
The MP1474S is disabled when the input voltage
falls below 3.2V. If an application requires a
higher under-voltage lockout (UVLO) threshold,
use EN/SYNC to adjust the input voltage UVLO
by using two external resistors (see Figure 5).
For best results, set the UVLO falling threshold
MP1474S Rev.1.0
1/8/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
12
MP1474S – HIGH-EFFICIENCY, 2A, 16V, 500kHz SYNCHRONOUS STEP-DOWN CONVERTER
Over-Current Protection (OCP) and Hiccup
If both VIN and VEN/SYNC exceed their respective
thresholds, the chip starts up. The reference
block starts first, generating stable reference
voltage and currents, then the internal regulator
is enabled. The regulator provides a stable
supply for the remaining circuitries.
The MP1474S has a cycle-by-cycle over-
current limit when the inductor current peak
value exceeds the set current-limit threshold.
Meanwhile, the output voltage drops until VFB is
below the under-voltage (UV) threshold (50%
below the reference, typically). Once UV is
triggered, the MP1474S enters hiccup mode to
re-start the part periodically. This protection
mode is useful when the output is dead-shorted
to ground and greatly reduces the average
short-circuit current to alleviate thermal issues
and protect the regulator. The MP1474S exits
hiccup mode once the over-current condition is
removed.
Three events can shut down the chip: VEN/SYNC
low, VIN low, and thermal shutdown. During the
shutdown procedure, the signaling path is
blocked first to avoid any fault triggering. The
COMP voltage and the internal supply rail are
then pulled down. The floating driver is not
subject to this shutdown command.
Thermal Shutdown (TSD)
Thermal shutdown prevents the chip from
operating at exceedingly high temperatures.
When the die temperature exceeds 150°C, it
shuts down the whole chip. When the
temperature drops below its lower threshold,
(130°C, typically), the chip is enabled again.
Floating Driver and Bootstrap Charging
An external bootstrap capacitor powers the
floating power MOSFET driver. This floating
driver has its own UVLO protection. The UVLO
rising threshold is 2.2V with a hysteresis of
150mV. The bootstrap capacitor voltage is
regulated internally by VIN through D1, M1, R3,
C4, L1, and C2 (see Figure 6). If (VIN-VSW)
exceeds 5V, U1 regulates M1 to maintain a 5V
BST voltage across C4. It is recommended
strongly to place a 20ꢀ resistor between the
SW and BST cap to reduce SW spike voltage.
D1
VIN
M1
BST
U1
R3
5V
C4
VOUT
C2
L1
SW
Figure 6. Internal Bootstrap Charging Circuit
Start-Up and Shutdown
MP1474S Rev.1.0
1/8/2015
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13
MP1474S – HIGH-EFFICIENCY, 2A, 16V, 500kHz SYNCHRONOUS STEP-DOWN CONVERTER
APPLICATION INFORMATION
Choose
the
inductor-ripple
current
at
Setting the Output Voltage
approximately 30% of the maximum load
current. The maximum inductor peak current is
calculated by the following equation:
The external resistor divider sets the output
voltage (see “Typical Application” on page 1).
Choose R1 around 40.2kꢀ; R2 is then given by:
ΔIL
IL(MAX) = ILOAD
+
R1
2
R2 =
V
OUT
Use a larger inductor for improved efficiency
under light-load conditions (below 100mA).
− 1
0.807V
Selecting the Input Capacitor
The T-type network is highly recommended
when VOUT is low (see Figure 7).
The input current to the step-down converter is
discontinuous, therefore it requires a capacitor
to supply the AC current while maintaining the
DC input voltage. Use low ESR capacitors for
optimum performance. Use ceramic capacitors
with X5R or X7R dielectrics for best results
because of their low ESR and small
temperature coefficients. For most applications,
use a 22µF capacitor.
Figure 7. T-Type Network
Table 1 lists the recommended T-type resistor
values for common output voltages.
Since C1 absorbs the input-switching current, it
requires an adequate ripple-current rating. The
RMS current in the input capacitor is estimated
by:
Table 1. Resistor Selection for Common Output
Voltages(8)
VOUT (V) R1 (kΩ) R2 (kΩ) Rt (kΩ)
1.0
1.2
1.8
2.5
3.3
5
20.5
30.1
40.2
40.2
40.2
40.2
84.5
61.9
32.4
19.1
13
82
82
33
33
16
16
⎛
⎞
⎟
VOUT
VIN
VOUT
VIN
⎜
IC1 = ILOAD
×
× 1−
⎜
⎝
⎟
⎠
The worst case condition occurs at VIN = 2VOUT
,
where:
ILOAD
7.68
IC1
=
Notes:
2
8) The recommended parameters are based on a 500kHz
switching frequency; a different input voltage, output-inductor
value, and output-capacitor value may affect the selection of
R1, R2, and Rt. For additional component parameters, please
refer to “Typical Application Circuits” on pages 17 and 18.
For simplification, choose an input capacitor
that has a RMS current rating greater than half
of the maximum load current.
The input capacitor can be electrolytic, tantalum,
or ceramic. When using electrolytic or tantalum
Selecting the Inductor
For most applications, use a 1µH to 22µH
inductor with a DC current rating at least 25%
higher than the maximum load current. For
highest efficiency, use an inductor with a DC
resistance less than 15mꢀ. For most designs,
the inductance value is derived from the
following equation:
capacitors,
a
small, high-quality ceramic
capacitor (e.g. 0.1μF) should be placed as
close to the IC as possible. When using
ceramic capacitors, ensure that they have
enough capacitance to provide sufficient charge
in order to prevent excessive voltage ripple at
input. The input-voltage ripple caused by
capacitance can be estimated as:
VOUT ×(V − VOUT
)
IN
L1 =
V × ΔIL × fOSC
IN
Where ΔIL is the inductor-ripple current.
MP1474S Rev.1.0
1/8/2015
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© 2015 MPS. All Rights Reserved.
14
MP1474S – HIGH-EFFICIENCY, 2A, 16V, 500kHz SYNCHRONOUS STEP-DOWN CONVERTER
External Bootstrap Diode
⎛
⎞
⎟
⎠
ILOAD
VOUT
VOUT
ΔV
=
×
× 1−
⎜
IN
fS ×C1
V
IN
V
In particular conditions, BST voltage may
become insufficient (see equations below).
During these conditions, an external bootstrap
diode can enhance the efficiency of the
regulator and avoid insufficient BST voltage at
light-load PFM operation. Insufficient BST
voltage is more likely to happen during either of
following conditions:
⎝
IN
Selecting the Output Capacitor
The output capacitor (C2) maintains the DC
output voltage. Use ceramic, tantalum, or low
ESR electrolytic capacitors. For best results,
use low ESR capacitors to keep the output-
voltage ripple low. The output-voltage ripple is
estimated as:
z VIN is below 5V
⎛
⎞ ⎛
VOUT
⎞
⎟
⎠
VOUT
1
z VOUT is 5V or 3.3V; and Duty cycle is high:
ΔVOUT
=
× 1−
⎜
× R
⎟ ⎜
+
ESR
VOUT
fS ×L1
V
8× fS ×C2
⎝
IN ⎠ ⎝
D=
>65%
VIN
Where L1 is the inductor value, and RESR is the
equivalent series resistance (ESR) value of the
output capacitor.
If the BST voltage is insufficient, the output-
ripple voltage may become extremely large
during a light-load condition. If this occurs, add
an external BST diode from VCC to BST (see
Figure 8).
For ceramic capacitors, the capacitance
dominates the impedance at the switching
frequency, and the capacitance causes the
majority of the output-voltage ripple. For
simplification, the output-voltage ripple is
estimated as:
MP1474S
VOUT
8× fS2 ×L1 ×C2
⎛
VOUT
⎞
⎟
⎠
ΔVOUT
=
× 1−
⎜
V
⎝
IN
For tantalum or electrolytic capacitors, the ESR
dominates the impedance at the switching
frequency. For simplification, the output-ripple is
approximated as:
Figure 8. Optional External Bootstrap Diode
The recommended external BST diode is
IN4148, and the BST capacitor value is 0.1µF
to 1μF.
VOUT
VOUT
⎛
⎞
ΔVOUT
=
× 1−
×RESR
⎜
⎟
⎠
fS ×L1
V
IN
⎝
The characteristics of the output capacitor
affect the stability of the regulation system. The
MP1474S can be optimized for a wide range of
capacitance and ESR values.
MP1474S Rev.1.0
1/8/2015
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© 2015 MPS. All Rights Reserved.
15
MP1474S – HIGH-EFFICIENCY, 2A, 16V, 500kHz SYNCHRONOUS STEP-DOWN CONVERTER
PCB Layout Guidelines(9)
VOUT
Efficient PCB layout is critical to achieve stable
operation, especially for the placement of the
VCC capacitor and input capacitor. For best
results, refer to Figure 9 and the guidelines
below:
GND
VCC
EN/SYNC
BST
1. Use large ground plane to connect directly
to GND. If the bottom layer is ground plane,
add vias near GND.
SW
2. Place the VCC capacitor as close as
possible to VCC and GND. The trace
length of VCC to the VCC capacitor anode
to the VCC capacitor cathode to GND
should be as short as possible.
GND
3. Place the ceramic input capacitor close to
IN and GND. Keep the connection between
the input capacitor and IN as short and
wide as possible.
Bottom Layer
Figure 9. Recommended PCB Layout
4. Route SW and BST away from sensitive
analog areas (such as FB).
Design Example
Table 2 shows a design example following the
application guidelines for the specifications:
5. Place the T-type feedback resistor R6 close
to the chip to ensure the trace connected to
FB is as short as possible
Table 2. Design Example
Notes:
VIN
VOUT
IOUT
12V
3.3V
2A
9) The recommended layout is based on Figure 10 in the
“Typical Application circuit” section on page 17.
The detailed application schematic is shown in
Figure 11. The typical performance and circuit
waveforms have been shown in the “Typical
Performance Characteristics” section. For
additional device applications, please refer to
the related evaluation board datasheets.
Top Layer
MP1474S Rev.1.0
1/8/2015
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16
MP1474S – HIGH-EFFICIENCY, 2A, 16V, 500kHz SYNCHRONOUS STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS
R3
20
2
7
1
6
5
3
VIN
BST
SW
IN
C1A
0.1uF
25V
C1
22uF
25V
C4
0.1uF
MP1474S
L1
GND
GND
5.5uH
VOUT
5V/2A
C2A
VCC
VCC
PG
C5
0.1uF
C2
22uF
22uF
R5
100k
GND
GND
GND
PG
C3
15pF
R4
100k
R6
16k
8
EN/SYNC
FB
EN/SYNC
R1
40.2k
GND
GND
R2
7.68k
GND
Figure 10. 12VIN, 5V/2A Output
R3
20
2
5
VIN
BST
IN
C1A
0.1uF
25V
C1
22uF
25V
C4
0.1uF
MP1474S
L1
GND
GND
5.5uH
VOUT
3.3V/2A
C2A
7
3
VCC
PG
VCC
PG
SW
C5
0.1uF
C2
22uF
22uF
R5
100k
GND
GND
GND
1
6
C3
15pF
R4
100k
R6
16k
8
EN/SYNC
FB
EN/SYNC
R1
GND
GND
40.2k
R2
13k
GND
Figure 11. 12VIN, 3.3V/2A Output
R3
20
2
7
1
6
5
VIN
VCC
BST
IN
C1A
0.1uF
25V
C1
22uF
25V
C4
0.1uF
MP1474S
L1
GND
GND
4.7uH
VOUT
2.5V/2A
3
VCC
PG
SW
C5
0.1uF
C2
22uF
C2A
22uF
R5
100k
GND
GND
GND
PG
C3
15pF
R4
100k
R6
33k
8
EN/SYNC
FB
EN/SYNC
R1
40.2k
GND
GND
R2
19.1k
GND
Figure 12. 12VIN, 2.5V/2A Output
MP1474S Rev.1.0
1/8/2015
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17
MP1474S – HIGH-EFFICIENCY, 2A, 16V, 500kHz SYNCHRONOUS STEP-DOWN CONVERTER
R3
20
2
7
1
6
5
3
VIN
VCC
BST
SW
IN
C1A
0.1uF
25V
C1
22uF
25V
C4
0.1uF
MP1474S
L1
GND
GND
4.7uH
VOUT
1.8V/2A
C2A
VCC
PG
C5
0.1uF
C2
22uF
22uF
R5
100k
GND
GND
GND
PG
C3
15pF
R4
100k
R6
33k
8
EN/SYNC
FB
EN/SYNC
R1
40.2k
GND
GND
R2
32.4k
GND
Figure 13. 12VIN, 1.8V/2A Output
R3
20
2
5
VIN
VCC
BST
IN
C1A
0.1uF
25V
C1
22uF
25V
C4
0.1uF
MP1474S
L1
GND
GND
2.2uH
VOUT
1.2V/2A
7
1
6
3
VCC
PG
SW
C5
0.1uF
C2
22uF
C2A
22uF
R5
100k
GND
GND
GND
PG
C3
15pF
R4
100k
R6
82k
8
EN/SYNC
FB
EN/SYNC
R1
30.1k
GND
GND
R2
61.9k
GND
Figure 14. 12VIN, 1.2V/2A Output
R3
20
2
7
1
6
5
VIN
BST
IN
C1A
0.1uF
25V
C1
22uF
25V
C4
0.1uF
MP1474S
L1
GND
GND
2.2uH
VOUT
1V/2A
C2A
3
VCC
PG
VCC
PG
SW
C5
0.1uF
C2
22uF
22uF
R5
100k
GND
GND
GND
C3
15pF
R4
100k
R6
82k
8
EN/SYNC
FB
EN/SYNC
R1
20.5k
GND
GND
R2
84.5k
GND
Figure 15. 12VIN, 1V/2A Output
MP1474S Rev.1.0
1/8/2015
www.MonolithicPower.com
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18
MP1474S – HIGH-EFFICIENCY, 2A, 16V, 500kHz SYNCHRONOUS STEP-DOWN CONVERTER
PACKAGE INFORMATION
TSOT23-8
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP1474S Rev. 1.0
1/8/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
19
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