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PM908E625ACDWBR2 [MOTOROLA]

Microcontroller, FLASH, 8MHz, CMOS, PDSO54, SOIC-54;
PM908E625ACDWBR2
型号： PM908E625ACDWBR2
厂家： MOTOROLA    MOTOROLA
描述：

Microcontroller, FLASH, 8MHz, CMOS, PDSO54, SOIC-54

微控制器 光电二极管 外围集成电路
文件： 总40页 (文件大小：484K)
中文：  中文翻译
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Order this document from Analog Marketing: MM908E625/D  
Rev 2.0, 09/2003  
MOTOROLA  
SEMICONDUCTOR TECHNICAL DATA  
Preliminary Information  
908E625  
Integrated Quad Half H-Bridge with  
Power Supply, Embedded MCU, and  
LIN Serial Communication  
H-BRIDGE POWER SUPPLY  
WITH EMBEDDED MCU AND LIN  
The 908E625 is a highly integrated single-package solution that includes a  
high-performance HC08 microcontroller with a SMARTMOSTM analog control  
IC. The HC08 includes flash memory, a timer, enhanced serial  
communications interface (ESCI), an analog-to-digital converter (ADC), serial  
peripheral interface (SPI), and an internal clock generator module. The analog  
control die provides fully protected H-Bridge/high-side outputs, voltage  
regulator, watchdog, and local interconnect network (LIN) physical layer.  
The single-package solution, together with LIN, provides optimal  
application performance adjustments and space-saving PCB design. It is  
especially suited for the control of automotive mirror, door lock, and light-  
levelling applications.  
DWB SUFFIX  
CASE 1400-01  
Features  
54-TERMINAL SOICWB-EP  
• High-Performance M68HC08 Core  
• 16 K Bytes of On-Chip Flash Memory  
• 512 Bytes of RAM  
ORDERING INFORMATION  
Temperature  
• Two 16-Bit, 2-Channel Timers  
Package  
Device  
• 10-Bit Analog-to-Digital Converter (ADC)  
• Three 2-Terminal Hall-Effect Sensor Input Ports  
• One Analog Input with Switchable Current Source  
• Four Low RDS(ON) Half-Bridge Outputs  
Range (T )  
A
54 SOIC  
WB-EP  
PM908E625ACDWB/R2 -40°C to 85°C  
• One Low RDS(ON) High-Side Output  
• 16 Microcontroller I/Os  
908E625 Simplified Application Diagram  
908E625  
HB1  
LIN  
VREFH  
VDDA  
EVDD  
VDD  
4 Half-Bridge  
Outputs  
M
M
M
HB2  
HB3  
HB4  
VREFL  
VSSA  
EVSS  
VSS  
HS  
High-Side  
Output 2  
RxD  
PTE1/RxD  
RSTB  
Switched Internal  
VDD Output  
HVDD  
H1  
H2  
H3  
RSTB_A  
IRQB  
IRQB_A  
PTD1/TACH1  
FGEN  
SSB  
PTB1/AD1  
BEMF  
PTD0/TACH0  
Three 2-Terminal  
Hall-Effect  
Sensor Inputs  
Analog Input with  
Current Source  
PA1  
PTA0−4  
PTB3−7  
PTC2−4  
Microcontroller  
Ports  
This document contains information on a product under development.  
Motorola reserves the right to change or discontinue this product without notice.  
© Motorola, Inc. 2003  
G N  
G N  
GND  
GND  
V S  
VSUP3  
V S  
VSUP2  
V S  
VSUP1  
R S  
RSTB_A  
I
R Q  
IRQB_A  
B E M  
S S B  
BEMF  
F G  
FGEN  
SSB  
R x  
RxD  
P T  
PTE1/RxD  
P T  
PTB1/AD1  
P T  
PTD0/TACHO/BEMF  
P T  
PTD1/TACH1  
I R  
IRQB  
R S  
RSTB  
908E625  
2
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
1
PTB7/AD7/TBCH1  
PTB6/AD6/TBCH0  
PTC4/OSC1  
PTC3/OSC2  
PTC2/MCLK  
PTB5/AD5  
PTB4/AD4  
PTB3/AD3  
IRQB  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
PTA0/KBD0  
PTA1/KBD1  
PTA2/KBD2  
FLSVPP  
PTA3/KBD3  
PTA4/KBD4  
VREFH  
VDDA  
EVDD  
EVSS  
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
RSTB  
PTB1/AD1  
PTD0/TACH0/BEMF  
PTD1/TACH1  
NC  
VSSA  
VREFL  
PTE1/RxD  
RxD  
FGEN  
BEMF  
VSS  
PA1  
RSTB_A  
IRQB_A  
VDD  
H1  
SSB  
H2  
LIN  
H3  
NC  
HVDD  
NC  
NC  
HB1  
HB4  
VSUP1  
VSUP3  
GND2  
HB3  
GND1  
HB2  
VSUP2  
HS  
TERMINAL FUNCTION DESCRIPTION  
Terminal  
Terminal Name  
Die  
Description  
1
PTB7/AD7/  
TBCH1  
MCU  
Port B, Terminal 7 (shared with ADC and Timer Channel B)  
2
PTB6/AD6/  
TBCH0  
MCU  
Port B, Terminal 6 (shared with ADC and Timer Channel B)  
3
4
PTC4/OSC1  
PTC3/OSC2  
PTC2/MCLK  
PTB5/AD5  
PTB4/AD4  
PTB3/AD3  
IRQB  
MCU  
MCU  
MCU  
MCU  
MCU  
MCU  
MCU  
MCU  
MCU  
MCU  
Port C, Terminal 4  
Port C, Terminal 3  
5
Port C, Terminal 2  
6
Port B, Terminal 5 (shared with ADC)  
Port B, Terminal 4 (shared with ADC)  
Port B, Terminal 3 (shared with ADC)  
Interrupt Input Terminal  
7
8
9
10  
11  
12  
RSTB  
Reset Terminal  
PTB1/AD1  
Port B, Terminal 1 (shared with ADC)  
Port D, Terminal 0 (shared with ADC, Timer Channel A, and BEMF Counter)  
PTD0/TACH0/  
BEMF  
13  
PTD1/TACH1  
NC  
MCU  
–
Port D, Terminal 1 (shared with ADC and Timer Channel A)  
No Connected  
14, 21, 22, 33  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
908E625  
3
TERMINAL FUNCTION DESCRIPTION (continued)  
Terminal  
Terminal Name  
FGEN  
Die  
Description  
Current Limitation Frequency Input Terminal  
15  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
16  
BEMF  
Back Electromagnetic Force Output Terminal  
Reset Terminal  
17  
RSTB_A  
IRQB_A  
SSB  
18  
Interrupt Output Terminal  
19  
20  
SPI Port—Slave Select Terminal  
LIN Bus Line  
SIO  
23, 26, 29, 32  
HB1, HB2, HB3,  
HB4  
Half-Bridge Outputs 1 to 4 Terminals  
24, 27, 31  
VSUP1, VSUP2,  
VSUP3  
Analog  
Supply Voltage Terminals 1 to 3  
25, 30  
28  
GND1, GND2  
HS  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
Analog  
MCU  
Ground Terminals 1 and 2  
High-Side Output Terminal  
34  
HVDD  
Switchable 5.0 V Output  
35–37  
38  
H3, H2, H1  
VDD  
Hall-Effect Sensor Input Terminals 3 to 1  
Voltage Regulator Output Terminal  
Input Terminal (with Current Source)  
Voltage Regulator Ground Terminal  
LIN Receiver Output Terminal  
39  
PA1  
40  
VSS  
41  
RxD  
42  
PTE1/RxD  
VREFL, VREFH  
VSSA  
Port E, Terminal 1 (shared with SCI RX Line)  
ADC Supply Terminals  
43, 48  
44  
MCU  
MCU  
Supply Terminal  
45  
EVSS  
MCU  
Supply Terminal  
46  
EVDD  
MCU  
Supply Terminal  
47  
VDDA  
MCU  
Supply Terminal  
49  
PTA4/KBD4  
PTA3/KBD3  
DNC  
MCU  
Port A, Terminal 4 (shared with Keyboard Module)  
Port A, Terminal 3 (shared with Keyboard Module)  
FLSVPP Test Terminal  
50  
MCU  
51  
MCU  
52  
PTA2/KBD2  
PTA1/KBD1  
PTA0/KBD0  
MCU  
Port A, Terminal 2 (shared with Keyboard Module)  
Port A, Terminal 1 (shared with Keyboard Module)  
Port A, Terminal 0 (shared with Keyboard Module)  
53  
MCU  
54  
MCU  
908E625  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
4
MAXIMUM RATINGS  
All voltages are with respect to ground unless otherwise noted.  
Rating  
Symbol  
Value  
Unit  
ELECTRICAL RATINGS  
Supply Voltage  
V
V
-0.3 to 28  
-0.3 to 40  
-0.3 to 6.0  
SUP(ss)  
Analog Chip Supply Voltage under Normal Operation (Steady-State)  
Analog Chip Supply Voltage under Transient Conditions (Note 1)  
Microcontroller Chip Supply Voltage  
V
SUP(pk)  
VDD  
Input Terminal Voltage  
Analog Chip (Note 2)  
Microcontroller Chip  
V
V
-0.3 to 5.5  
(ANALOG)  
in  
V
-0.3 to V +0.3  
V
SS DD  
(MCU)  
in  
Maximum Microcontroller Current per Terminal  
All Terminals Except VDD/VSS/PTA0–PTA6/PTC0–PTC1  
Terminals PTA0–PTA6 and PTC0–PTC1  
mA  
I
±15  
±25  
(1)  
(2)  
pin  
I
pin  
Maximum Microcontroller VSS Output Current  
Maximum Microcontroller VDD Input Current  
I
100  
100  
mA  
mA  
V
MVSS  
MVDD  
I
LIN Supply Voltage (Note 3)  
Normal Operation (Steady-State)  
Transient Conditions (Note 1)  
V
-18 to 28  
40  
BUS(ss)  
VBUS(  
)
dynamic  
OUT(lim)  
Output Self-Limiting Current (Note 4)  
5.0  
A
V
I
ESD Voltage  
V
V
V
±2000/±4000  
±200  
ESD1  
ESD2  
ESD3  
Human Body Model (Microcontroller/SmartMOS) (Note 5)  
Machine Model (Note 6)  
Charge Device Model  
±500  
THERMAL RATINGS  
Storage Temperature  
T
-40 to 150  
+85  
°C  
°C  
STG  
Operating Case Temperature (Note 7)  
Operating Junction Temperature  
T
C
T
-40 to 125  
245  
°C  
J
Terminal Soldering Temperature (Note 8)  
T
°C  
SOLDER  
Thermal Resistance (Junction to Ambient)  
All Outputs ON (Note 9), (Note 11)  
°C/W  
R
24  
27  
θJA1  
Single Output ON (Note 10), (Note 11)  
R
JA2  
θ
Notes  
1. Transient capability for pulses with a time of t < 0.5 sec.  
2. Exceeding the limits on any parallel input, SSB, or Reset terminal may cause permanent damage to the devices.  
3. Exceeding the limits on the LIN terminal may cause permanent damage to the device.  
4. Overcurrent shutdown on HB1/HB2/HB3/HB4 and HS terminals.  
5. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).  
6. ESD2 testing is performed in accordance with the Machine Model (CZAP =200 pF, RZAP = 0 Ω).  
7. The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking.  
8. Terminal soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may  
cause malfunction or permanent damage to the device.  
9. All outputs ON and dissipating equal power.  
10. One output ON and dissipating power.  
11. Per JEDEC JESD51-2 at natural convection, still air condition; and 2s2p thermal test board per JEDEC JESD51-7 and JESD51-5 (thermal  
vias connected to top ground plane).  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
908E625  
5
 
 
 
 
 
 
 
 
 
 
 
STATIC ELECTRICAL CHARACTERISTICS  
All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for characteristics of the microcontroller  
chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted  
reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
SUPPLY VOLTAGE RANGE  
Nominal Operating Voltage  
V
8.0  
–
18  
V
SUP  
SUPPLY CURRENT RANGE  
STOP Mode (Note 12)  
I
–
–
60  
µA  
SUPSTOP  
V
= 12 V, Cyclic Wake-Up Disabled  
SUP  
DIGITAL INTERFACE RATINGS  
Output Terminals (RSTB, IRQ, BEMF)  
High-State Output Voltage (IOUT = 1.5 mA)  
Low-State Output Voltage (IOUT = - 250 µA)  
V
V
VOH  
VOL  
3.75  
–
–
–
–
0.9  
Input Terminals (RSTB, IRQ, FGEN, SSB)  
Input Logic Low Voltage  
VILL  
VILH  
–
3.5  
–
–
1.5  
–
Input Logic High Voltage  
Input Terminals (RSTB, IRQ, FGEN, SSB) - Input Logic Hysteresis  
VIHH  
IIN  
100  
–
550  
20  
800  
–
mV  
Input Terminals (RSTB, IRQ, FGEN, SSB) - Input Current (0 V < VIN < VDD  
)
µA  
Input Terminals (RSTB, IRQ, FGEN, SSB) - Input Capacitance (Note 13)  
CIN  
–
–
TBD  
60  
–
–
pF  
Input Terminals (RSTB, IRQ, FGEN, SSB) - Pull-up Resistor (IRQ, RSTB, SSB)  
R
kΩ  
Pullup  
SYSTEM RESETS AND INTERRUPTS  
High-Voltage Reset  
Threshold  
V
V
V
V
V
27  
–
30  
1.5  
33  
–
HVRON  
Hysteresis  
V
HVRH  
Low-Voltage Reset  
Threshold  
3.6  
4.0  
100  
4.5  
V
mV  
LVRON  
Hysteresis  
V
LVRH  
High-Voltage Interrupt  
Threshold  
V
17.5  
–
21  
1.0  
23  
–
HVION  
Hysteresis  
V
HVIH  
Low-Voltage Interrupt  
Threshold  
V
6.5  
–
–
0.4  
8.0  
–
LVION  
Hysteresis  
V
LVIH  
High-Temperature Reset (Note 14)  
Threshold  
°C  
T
–
5.0  
170  
–
–
–
RON  
Hysteresis  
T
IH  
Notes  
12. STOP mode current will increase if V  
exceeds 15 V.  
SUP  
13. This parameter is guaranteed by process monitoring but is not tested in production.  
14. High-Temperature Interrupt (HTI) threshold is linked to High-Temperature Reset (HTR) threshold (HTR = HTI + 10°C).  
908E625  
6
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
 
 
 
STATIC ELECTRICAL CHARACTERISTICS (continued)  
All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for characteristics of the microcontroller  
chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted  
reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
SYSTEM RESETS AND INTERRUPTS (continued)  
High-Temperature Interrupt  
Threshold  
°C  
T
–
5.0  
160  
–
–
–
ION  
Hysteresis  
T
IH  
VOLTAGE REGULATOR  
Normal Mode Output Voltage  
V
IOUT = 60 mA, 9.0 V < V  
< 16 V  
VDDRUN1  
VDDRUN2  
IOUTRUN  
VLR  
4.75  
4.5  
5.0  
5.0  
5.25  
5.5  
SUP  
IOUT = 60 mA, V  
< 9.0 V and V  
> 16 V  
SUP  
SUP  
Normal Mode Total Output Current  
Load Regulation  
60  
–
–
mA  
mA  
–
–
100  
IOUT = 60 mA, V  
= 9.0 V, TJ = 125°C  
SUP  
STOP Mode Output Voltage (Max. Output Current 100 µA)  
Low-Voltage Reset Threshold  
VDDSTOP  
VLVRON  
VLVRH  
4.5  
3.6  
50  
4.7  
4.0  
4.9  
4.5  
V
V
Low-Voltage Reset Hysteresis  
100  
150  
mV  
PHYSICAL LAYER  
Output Low Level  
V
V
V
LIN-LOW  
Tx Low, I  
= 40 mA  
–
–
1.4  
OUT  
Output High Level  
Tx High, I = 1.0 µA  
V
LIN-HIGH  
VSUP-1  
20  
–
30  
–
–
60  
–
OUT  
Pull-Up Resistor to VSUP  
Output Current Limit  
R
kΩ  
SLAVE  
I
50  
mA  
BLIM  
Leakage Current to GND  
I
µA  
LEAK1  
Recessive State (-0.5 V < VBUS < VSUP  
)
0
–
10  
Leakage Current to GND (VSUP Disconnected)  
µA  
I
I
I
-40  
–
–
–
-600  
25  
40  
–
–
Excluding Internal Pull-Up Resistor, VLIN Between -18 V and +18 V  
Including Internal Pull-Up Resistor, VLIN @ -18 V  
Including Internal Pull-Up Resistor, VLIN @ +18 V  
LEAK2  
LEAK3  
LEAK4  
LIN Receiver  
Recessive  
V
V
0.6 V  
BUS  
–
–
VSUP  
0.4 VBUS  
IH  
Dominant  
Threshold  
Input Hysteresis  
V
IL  
0
–
V
/2  
SUP  
–
V
–
ITH  
0.05 V  
0.1 VSUP  
SUP  
VIH  
LIN Wake-Up Threshold  
V
–
VSUP-3  
–
V
WTH  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
908E625  
7
STATIC ELECTRICAL CHARACTERISTICS (continued)  
All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for characteristics of the microcontroller  
chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted  
reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
HIGH-SIDE OUTPUT  
R
–
600  
700  
mΩ  
Switch On Resistance @ TJ = 25°C with ILOAD = 1.0 A  
DS(ON)-HS  
High-Side Overcurrent Shutdown  
High-Side Switching Frequency  
I
4.0  
–
–
–
6.5  
20  
A
HSOC  
f
kHz  
PWMHS  
HALF-BRIDGE OUTPUTS  
R
mΩ  
Switch On Resistance @ TJ = 25°C with ILOAD = 1.0 A  
DS(ON)HB  
–
–
425  
400  
500  
500  
High Side  
Low Side  
High-Side Overcurrent Shutdown  
Low-Side Overcurrent VDS Voltage  
High-Side Switching Frequency  
Low-Side Switching Frequency  
I
5.0  
–
–
8.0  
–
A
HBOC  
VOCDS  
3.6  
20  
25  
V
f
–
–
kHz  
kHz  
mA  
PWMHS  
f
–
–
PWMLS  
Low-Side Current Limitation  
I
35  
55  
75  
Current Limit 1 (CLS2 = 0, CLS1 = 1, CLS0 = 1)  
Current Limit 2 (CLS2 = 1, CLS1 = 0, CLS0 = 0)  
Current Limit 3 (CLS2 = 1, CLS1 = 0, CLS0 = 1)  
Current Limit 4 (CLS2 = 1, CLS1 = 1, CLS0 = 0)  
Current Limit 5 (CLS2 = 1, CLS1 = 1, CLS0 = 1)  
CL1  
I
210  
300  
450  
600  
260  
370  
550  
740  
310  
440  
650  
880  
CL2  
I
CL3  
I
CL4  
I
CL5  
Half-Bridge Output HIGH Threshold for BEMF Detection  
Half-Bridge Output LOW Threshold for BEMF Detection  
Hysteresis for BEMF Detection  
V
–
–
–
–
0
-10  
–
V
BEMFH  
V
-60  
60  
mV  
mV  
V/A  
BEMFL  
V
BEMFHY  
Low-Side Current-to-Voltage Ratio (V  
[V] / I [A])  
HB  
ADOUT  
RATIO  
7.0  
1.4  
10  
2.0  
13  
2.6  
H
CSA = 1  
CSA = 0  
RATIO  
L
SWITCHABLE VDD OUTPUT (HVDD  
)
Overcurrent Shutdown Threshold  
I
24  
4.85  
–
30  
36  
5.35  
15  
mA  
–
HVDDOCT  
VSUP DOWN-SCALER  
Voltage Ratio (RATIOVSUP = VSUP /VADOUT  
RATIOVSUP  
5.1  
HALL-EFFECT SENSOR INPUT TERMINAL  
Output Voltage  
V
I
V
V
HALL  
SUP  
Sense Current  
Threshold  
mA  
7.0  
–
8.8  
0.88  
10.6  
–
HSCT  
HSCH  
Hysteresis  
I
Output Current Limitation  
PHOC Flag Threshold  
–
–
–
100  
3.5  
0.5  
–
–
–
mA  
V
I
HL  
IPHOCT  
Drop-Out Voltage @ I  
= 15 mA  
V
V
LOAD  
PH-DO  
908E625  
8
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
STATIC ELECTRICAL CHARACTERISTICS (continued)  
All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for characteristics of the microcontroller  
chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical values noted  
reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
ANALOG INPUT  
Current Source PAx  
µA  
tCS1  
tCS2  
tCS3  
tCS4  
CSSEL1 = 0, CSSEL0 = 0  
CSSEL1 = 0, CSSEL0 = 1  
CSSEL1 = 1, CSSEL0 = 0  
CSSEL1 = 1, CSSEL0 = 1  
60  
70  
80  
180  
380  
625  
210  
420  
700  
240  
460  
775  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
908E625  
9
DYNAMIC ELECTRICAL CHARACTERISTICS  
All characteristics are for the analog chip only. Please refer to the specification for 68HC908EY16 for characteristics of the  
microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40°C ≤ TJ ≤ 125°C unless otherwise noted. Typical  
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
PHYSICAL LAYER  
Propagation Delay  
Tx Low to LIN Low  
Tx High to LIN High  
LIN Low to Rx Low  
LIN High to Rx High  
Bus Wake-Up to IRQ Low  
µs  
t
–
–
–
–
–
–
–
4.0  
4.0  
TBD  
4.0  
4.0  
6.0  
6.0  
–
TX-LIN-  
low  
t
TX-LIN-high  
t
LIN-Rx-low  
t
LIN-Rx-high  
t
PDWU  
Output Falling Edge Slew Rate  
80% to 20%  
SR  
V/µs  
V/µs  
F
-1.0  
-2.0  
-3.0  
Output Rising Edge Slew Rate  
SR  
R
20% to 80%, RBUS > 1.0 kΩ, CBUS < 10 nF  
1.0  
2.0  
–
3.0  
2.0  
Rise/Fall Slew Rate Symmetry  
SR  
-2.0  
µs  
S
HALL-EFFECT SENSOR INPUT PORT  
Dynamic Output Voltage Range  
VDR  
1.5  
–
–
–
–
V
Propagation Delay  
tPHPD  
1.0  
µs  
AUTONOMOUS WATCHDOG (AWD)  
AWD Oscillator Period  
tOSC  
–
40  
22  
–
µs  
AWD Period Low = 512 tOSC  
tAWDPH  
16  
28  
ms  
*
AWD Period High = 256 tOSC  
tAWDPL  
8.0  
11  
14  
ms  
*
908E625  
10  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
.
MICROCONTROLLER  
For a detailed microcontroller description, refer to the MC68HC908EY16 specification.  
Module  
Description  
Core  
Timer  
Flash  
RAM  
ADC  
SPI  
High-Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0 MHz  
2 x 16-Bit Timers with 2 Channels (TIM A and TIM B)  
16 K Bytes  
512 Bytes  
10-Bit Analog-to-Digital Converter  
SPI Module  
ESCI  
Standard SCI Module  
Bit-Time Measurement  
Arbitration  
Prescaler with Fine Baud-Rate Adjustment  
ICG  
Internal Clock Generation Module (25% Accuracy with Trim Capability to 2%)  
Special Counter for SmartMOS BEMF Output  
BEMF Counter  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
908E625  
11  
Timing Diagrams  
∆t Fall-time  
∆t Rise-time  
tLEAD  
tVALID  
tLAG  
SS  
0.8 VSUP  
0.8 VSUP  
∆V Fall  
∆V Rise  
SPSCK  
MISO  
0.2 VSUP  
0.2 VSUP  
Dominant State  
BIT 7  
BIT 7  
BIT 6  
BIT 5  
BIT 5  
BIT 2  
BIT 2  
BIT 1  
BIT 1  
BIT 0  
∆V Fall  
∆t Fall-time  
∆V Rise  
∆t Rise-time  
SRF  
=
SRR =  
MOSI  
Figure 4. LIN Slew Rate Description  
BIT 6  
BIT 0  
Figure 2. SPI Timing Diagram  
LIN  
Recessive State  
VSUP - 3V  
tTx-LIN-low  
tTx-LIN-high  
Dominant State  
Tx  
IRQ  
tPDWU  
LIN  
Recessive State  
0.4 VSUP  
0.9 VSUP  
Recessive State  
0.6 VSUP  
Figure 5. Wake-Up Terminal Wake-Up Timing  
0.1 VSUP  
Dominant State  
Rx  
tLIN-Rx-low  
tLIN-Rx-high  
Figure 3. LIN Timing Description  
908E625  
12  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
T = 25°C  
J
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
mere
3.0  
3.5  
4.0  
4.5  
5.0  
Amperes  
H-Bridge Low Side  
Figure 6. Free Wheel Diode Forward Voltage  
250  
200  
150  
100  
50  
T = 125°C  
A
T = 25°C  
A
T = -40°C  
A
0
0
55.0  
10  
15  
20  
25  
ILOAD (mA)  
Figure 7. Drop-Out Voltage on HVDD  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
908E625  
13  
SYSTEM/APPLICATION INFORMATION  
INTRODUCTION  
The 908E625 device was designed and developed as a  
outputs with one high-side switch. Other ports are also  
provided, which include Hall sensor input ports, analog input  
ports, a wake-up terminal, and a selectable HVDD terminal. An  
internal voltage regulator is provided on the SmartMOS IC chip,  
which provides power to the MCU chip.  
highly integrated and cost-effective solution for automotive and  
industrial applications. For automotive body electronics, the  
908E625 is well suited to perform complete mirror, door lock,  
and light-levelling control all via a 3-wire LIN bus.  
This device combines an HC08 MCU core with flash memory  
together with a SmartMOS IC chip. The SmartMOS IC chip  
combines power and control in one chip. Power switches are  
provided on the SmartMOS IC configured as half-bridge  
Also included in this device is a LIN physical layer, which  
communicates using a single wire. This enables this device to  
be compatible with 3-wire bus systems, where one wire is used  
for communication, one for battery, and the third for ground.  
FUNCTIONAL TERMINAL DESCRIPTION  
Power Supply Terminals (VSUP1, VSUP2, and  
VSUP3)  
Terminals are device power supply terminals. The nominal  
input voltage is designed for operation from 12 V systems.  
Owing to the low on-resistance and current requirements of the  
half-bridge driver outputs and high-side output driver, multiple  
terminals are provided.  
Hall-Effect Sensor Input Terminals (H1, H2, and H3)  
The Hall-effect sensor input terminals provide inputs for Hall-  
effect sensors and switches.  
Analog Input (PA1)  
This terminal is an analog input port with selectable source  
values.  
All VSUP terminals must be connected to get full chip  
functionality.  
Switchable VDD Output Terminal (HVDD)  
Terminal HVDD is a switchable VDD output for driving  
resistive loads requiring a regulated 5.0 V supply (e.g.,  
3-terminal Hall-effect sensors). The output is short-circuit  
protected.  
Power Ground Terminals (GND1 and GND2)  
GND1 and GND2 are device power ground connections.  
Owing to the low on-resistance and current requirements of the  
half-bridge driver outputs and high-side output driver, multiple  
terminals are provided.  
LIN Bus Terminal (LIN)  
This terminal represents the single-wire bus transmitter and  
receiver. It is suited for automotive bus systems and is based  
on the LIN Bus Specification.  
All GND terminals must be connected to get full chip  
functionality.  
Half-Bridge Output Terminals (HB1, HB2, HB3, and  
HB4)  
The 908E625 device includes power MOSFETs configured  
as four half-bridge driver outputs with a RDS(ON) of 500 mΩ.  
These outputs may be configured for stepper-motor drivers, DC  
motor drivers, or as high-side and low-side switches.  
Non-Power Ground Terminal (VSS)  
Ground terminal for the connection of all non-power ground  
connections (microcontroller and sensors).  
Note VSS, EVSS, VSSA, and VREFL must be connected  
together.  
These outputs are short-circuit and overtemperature  
protected, and they feature current recopy, current limitation,  
and BEMF generation. The protection is done on the high-side  
and low-side FETs (high-side with real current measurement  
and low-side with VDS monitoring), while current limitation and  
recopy are done on the low-side FETs.  
+5.0 V Supply Output Terminal (VDD)  
Voltage regulator output terminal. Terminal needed to place  
an external capacitor to stabilize the regulated output voltage.  
This terminal is not protected against shorts to GND. Therefore,  
it should not be used to supply loads others than the  
implemented microcontroller.  
High-Side Output Terminal (HS)  
This output is a low RDS(ON) high-side switch. The switch is  
protected against overtemperature and overcurrent. The output  
is capable of limiting the inrush current with an automatic PWM  
generation using the FGEN module.  
Note VDD, EVDD, VDDA, and VREFH must be connected  
together.  
908E625  
14  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
PTB0 is internally directly connected to terminal ADOUT.  
This input is used for all analog measurements done by the  
analog die (e.g., current recopy, VSUP, etc.).  
Slave Select (SSB)  
This is terminal is the SPI Slave Select terminal for the  
analog chip. All other SPI connections are done internally. SSB  
must be connected to PTB1 or any other logic I/O of the  
microcontroller.  
For details refer to the 68HC908EY16 specification.  
Port C I/O Terminals  
Interrupt Terminal (IRQB_A)  
IRQ_A is the interrupt output terminal of the analog die  
indicating errors or wake-up events. This terminal must be  
connected to the IRQB terminal of the MCU.  
PTC4/OSC1 and PTC0/MISO are special-function,  
bidirectional I/O port terminals. PTC3/OSC2 and PTC4/OSC1  
are shared with the on-chip oscillator circuit through  
configuration options.  
For details refer to the 68HC908EY16 specification.  
Depending on application requirements:  
• PTC3/OSC2 can be programmed to be OSC2.  
• PTC4/OSC1 can be programmed to be OSC1.  
• PTC2/MCLK is software selectable to be MCLK or bus  
clock out.  
Reset Terminal (RSTB_A)  
RSTB_A is the bidirectional reset terminal of the analog die.  
This terminal needs to be connected to the RSTB terminal of  
the MCU.  
BEMF Terminal  
PTC0 and PTC1 are not directly accessible in the multi-die  
approach. These terminals are internally connected to the  
MISO and MOSI SPI terminals of the analog die.  
This terminal gives the user information about back  
electromagnetic force (BEMF). This feature is mainly used in  
stepper motor applications for detecting a stalled motor. In  
order to evaluate this signal the terminal must be directly  
connected to terminal PTD0/TACH0/BEMF.  
Port D I/O Terminals (PTD1/TACH1 and PTD0/  
TACH0/BEMF)  
PTD1/TACH1 and PTD0/TACH0 are special-function,  
bidirectional I/O port terminals that can also be programmed to  
be timer terminals.  
FGEN Terminal  
Input terminal for the half-bridge current limitation and the HS  
inrush current limiter PWM frequency. This input is not a real  
PWM input terminal; it should just supply the period of the  
PWM. The duty cycle will be generate automatically.  
In stepper motor applications the PTD0 terminal should be  
connected to the BEMF output of the analog die in order to  
evaluate the BEMF signal without using a timer channel.  
Port A I/O Terminals  
PTD1 terminal is recommended to be used as an output  
terminal for generating the FGEN signal if required by the  
application.  
Port A input/output (I/O) terminals (PTA6/SS, PTA5/  
SPSCK, PTA4/KDB4, PTA3/KBD3, PTA2/KBD2, PTA1/  
KBD1, and PTA0/KBD0) are special-function, bidirectional I/O  
port terminals. PTA5 is shared with the serial peripheral  
interface (SPI). PTA4–PTA0 can be programmed to serve as  
keyboard interrupt terminals.  
Port E I/O Terminals (PTE1/RxD and PTE0/TxD)  
PTE1/RxD and PTE0/TxD are special-function, bidirectional  
I/O port terminals that can also be programmed to be enhanced  
serial communication.  
PTA5 is shared with the serial peripheral interface (SPI) but  
not directly accessible in the multichip approach. This terminal  
is internally directly connected to the SPI clock of the analog  
die.  
PTE0/TxD is internally connected to the TxD terminal of the  
analog die. The connection for the receiver functionality must  
be done externally.  
PTA6 is not accessible in the multi-die approach.  
For details refer to 68HC908EY16 Specification.  
External Reset Terminal (RSTB)  
A logic [0] on the RSTB terminal forces the MCU to a known  
startup state. RSTB is bidirectional, allowing a reset of the  
entire system. It is driven low when any internal reset source is  
asserted. This terminal contains an internal pull-up resistor that  
is always activated, even when the reset terminal is pulled low.  
Port B I/O Terminals  
PTB7/AD7/TBCH1, PTB6/AD6/TBCH0, and PTB5/AD5–  
PTB0/AD0 are special-function, bidirectional I/O port terminals  
that can also be used for ADC inputs. PTB7/AD7/TBCH1 and  
PTB6/AD6/TBCH0 are special function.  
For details refer to the 68HC908EY16 specification.  
PTB2 is not accessible in the multi-die approach.  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
908E625  
15  
External Interrupt Terminal (IRQB)  
IRQB is an asynchronous external interrupt terminal. This  
terminal contains an internal pull-up resistor that is always  
activated, even when the IRQB terminal is pulled low.  
Analog Power Supply/Reference Terminals (VDDA,  
VREFH, VSSA, and VREFL)  
VDDA and VSSA are the power supply terminals for the  
analog-to-digital converter (ADC). Decoupling of these  
terminals should be as per the digital supply.  
For details refer to the 68HC908EY16 specification.  
Note VREFH is the high reference supply for the ADC.  
VDDA should be tied to the same potential as VDD via separate  
traces. VREFL is the low reference supply for the ADC. VSSA  
should be tied to the same potential as VSS via separate traces.  
Power Supply Terminals (VDD and VSS)  
VDD and VSS are the power supply and ground terminals.  
The MCU operates from a single power supply.  
For details refer to the 68HC908EY16 specification.  
Fast signal transitions on MCU terminals place high, short-  
duration current demands on the power supply. To prevent  
noise problems, take special care to provide power supply  
bypassing at the MCU.  
For details refer to the 68HC908EY16 specification.  
ANALOG DIE DESCRIPTION  
High-Temperature Interrupt  
Interrupt Description  
The High-Temperature Interrupt (HTI) is generated by the  
on-chip temperature sensors. If the chip temperature is above  
the HTI threshold, the HTI flag will be set. In case the High-  
Temperature Interrupt is enabled, a interrupt will be initiated.  
The device has seven different interrupt sources. The  
interrupts can be disabled or enabled via the SPI. After RESET  
all interrupts are automatically disabled.  
Low-Voltage Interrupt  
During STOP mode the HTI circuitry is disabled.  
The Low-Voltage Interrupt (LVI) is related to the external  
supply voltage, VSUP. If this voltage falls below the LVI  
Autonomous Watchdog Interrupt (AWD)  
threshold, it will set the LVI flag. In case the low-voltage  
Refer to Autonomous Watchdog (AWD) on page 35.  
interrupt is enabled, an interrupt will be initiated.  
SIO Interrupt  
With LVI the H-Bridges (high-side FET only) and the Lamp  
driver are switched off. All other modules are not influenced by  
this interrupt.  
If the ISOIE bit is set, a falling edge on the SIO terminal will  
generate an interrupt. During STOP mode this interrupt will  
initiate a system wake-up.  
During STOP mode the LVI circuitry is disabled.  
Hall-Effect Sensor Input Terminal Interrupt  
High-Voltage Interrupt  
If the PHIE bit is set, the enabled Hall-effect sensor input  
terminals H0–H2 can generate an interrupt if a current above  
the threshold is detected. During STOP mode this interrupt,  
combined with the cyclic wake-up feature of the AWD, can  
wake up the system (refer to Hall-Effect Sensor Input Terminal  
section).  
The High-Voltage Interrupt (HVI) is related to the external  
supply voltage, VSUP. If this voltage rises above the HVI  
threshold it will set the HVI flag. In case the High-Voltage  
Interrupt is enabled, a interrupt will be initiated.  
With HVI the H-Bridges (high-side FET only) and the Lamp  
and the high-side driver are switched off. All other modules are  
not influenced by this interrupt.  
Overcurrent Interrupt  
During STOP mode the HVI circuitry is disabled.  
If an overcurrent condition on a half-bridge occurs, the high-  
side or the HVDD output is detected and the OCIE bit is set and  
an interrupt generated.  
908E625  
16  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
System Wake-Up  
Interrupt Flag Register  
System wake-up can be initiated by four sources:  
1. A falling edge on the SIO terminal.  
2. A wake-up signal from the AWD.  
Register Name and Address: IFR - $05  
Bit7  
6
PHF  
0
5
ISOF  
0
4
HTF  
0
3
LVF  
0
2
HVF  
0
1
Bit0  
0
Read  
Write  
Reset  
OCF  
3. Logic [1] at Hall-effect sensor input terminal during cyclic  
0
0
check via AWD.  
0
0
4. An LVR condition occurs.  
If one of these wake-up events occurs and the interrupt mask  
bit for this event is set, the interrupt will wake up the  
microcontroller as well as the main voltage regulator (MREG)  
(see Figure 8).  
PHF—Hall-Effect Sensor Input Terminal Flag Bit  
This read/write flag is set depending on run/STOP mode.  
RUN Mode Interrupt will generated when a state change on  
any enabled Hall-effect sensor input terminal is detected. Clear  
PHF by writing a logic [1] to PHF. Reset clears the PHF bit.  
Writing a logic [0] to PHF has no effect.  
Analog Die  
MCU  
• 1 = State change on the hallflags detected.  
• 0 = No state change on the hallflags detected.  
From Reset  
STOP Mode Interrupt will be generated when AWDCC is  
set and a current above threshold is detected on any enabled  
Hall-effect sensor input terminal. Clear PHF by writing a logic [1]  
to PHF. Reset clears the PHF bit. Writing a logic [0] to PHF has  
no effect.  
Initialize  
Operate  
• 1 = One or more of the selected Hall-effect sensor input  
terminals had been pulled high.  
• 0 = None of the selected Hall-effect sensor input terminals  
has been pulled high.  
SPI:  
GS =1  
(MREG* off)  
ISOF—ISO Flag Bit  
STOP MREG*  
This read/write flag is set on falling edge at the ISO9141 data  
line. Clear ISOF by writing a logic [1] to ISOF. Reset clears the  
ISOF bit. Writing a logic [0] to ISOF has no effect.  
Wait for action  
LIN  
AWD  
STOP  
• 1 = Falling edge on ISO9141 data line has occurred.  
• 0 = Falling edge on ISO9141 data line has not occurred  
since last clear.  
Hall-Effect Sensor  
HTF—High-Temperature Flag Bit  
IRQ  
Interrupt  
?
This read/write flag is set on high-temperature condition.  
Clear HTF by writing a logic [1] to HTF. If high-temperature  
condition is still present while writing a logical one to HTF, the  
writing has no effect. Therefore, a high-temperature interrupt  
cannot be lost due to inadvertent clearing of HTF. Reset clears  
the HTF bit. Writing a logic [0] to HTF has no effect.  
Assert IRQ  
SPI: Reason  
for interrupt  
Start  
MREG*  
• 1 = High-temperature condition has occurred.  
• 0 = High-temperature condition has not occurred.  
Operate  
*MREG = Main voltage regulator  
Figure 8. STOP Mode/Wake-Up Procedure  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
908E625  
17  
 
LVF—Low-Voltage Flag Bit  
Interrupt Mask Register (IMR)  
This read/write flag is set on low voltage condition. Clear  
LVF by writing a logic [1] to LVF. If low-voltage condition is still  
present while writing a logical one to LVF, the writing has no  
effect. Therefore, a low-voltage interrupt cannot be lost due to  
inadvertent clearing of LVF. Reset clears the LVF bit. Writing a  
logic [0] to LVF has no effect.  
Register Name and Address: IMR - $04  
Bit7  
6
5
4
3
LVIE  
0
2
HVIE  
0
1
OCIE  
0
Bit0  
0
Read  
Write  
Reset  
0
0
PHIE ISOIE HTIE  
0
0
0
0
• 1 = Low-voltage condition has occurred.  
• 0 = Low-voltage condition has not occurred.  
PHIE—Hall-Effect Sensor Input Terminal Interrupt Enable  
Bit  
HVF—High-Voltage Flag Bit  
This read/write bit enables CPU interrupts by the Hall-effect  
sensor input terminal flag, PHF. Reset clears the PHIE bit.  
This read/write flag is set on high-voltage condition. Clear  
HVF by writing a logic [1] to HVF. If high-voltage condition is still  
present while writing a logical one to HVF, the writing has no  
effect. Therefore, a high-voltage interrupt cannot be lost due to  
inadvertent clearing of HVF. Reset clears the HVF bit. Writing a  
logic [0] to HVF has no effect.  
• 1 = Interrupt requests from PHF flag enabled.  
• 0 = Interrupt requests from PHF flag disabled.  
ISOIE—ISO9141 Line Interrupt Enable Bit  
• 1 = High-voltage condition has occurred.  
• 0 = High-voltage condition has not occurred.  
This read/write bit enables CPU interrupts by the ISO flag,  
ISOF. Reset clears the ISOIE bit.  
• 1 = Interrupt requests from ISOF flag enabled.  
• 0 = Interrupt requests from ISOF flag disabled.  
OCF—Overcurrent Flag Bit  
This read-only flag is set on overcurrent condition. Reset  
clears the OCF bit. To clear this flag, write a logic [1] to the  
appropriate overcurrent flag in the SYSSTAT Register. See  
Figure 9, which shows the three signals triggering the OCF.  
HTIE—High-Temperature Interrupt Enable Bit  
This read/write bit enables CPU interrupts by the high-  
temperature flag, HTF. Reset clears the HTIE bit.  
• 1 = High-current condition has occurred.  
• 0 = High-current condition has not occurred.  
• 1 = Interrupt requests from HTF flag enabled.  
• 0 = Interrupt requests from HTF flag disabled.  
HVDD_OCF  
LVIE—Low-Voltage Interrupt Enable Bit  
HS_OCF  
HB_OCF  
OCF  
This read/write bit enables CPU interrupts by the low-  
voltage flag, LVF. Reset clears the LVIE bit.  
Figure 9. Principal Implementation for OCF  
• 1 = Interrupt requests from LVF flag enabled.  
• 0 = Interrupt requests from LVF flag disabled.  
HVIE—High-Voltage Interrupt Enable Bit  
This read/write bit enables CPU interrupts by the high-  
voltage flag, HVF. Reset clears the HVIE bit.  
• 1 = Interrupt requests from HVF flag enabled.  
• 0 = Interrupt requests from HVF flag disabled.  
OCIE—Overcurrent Interrupt Enable Bit  
This read/write bit enables CPU interrupts by overcurrent  
flag, OCF. Reset clears the OCIE bit.  
• 1 = Interrupt requests from OCF flag enabled.  
• 0 = Interrupt requests from OCF flag disabled.  
908E625  
18  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
 
Reset  
The 908E625 chip has four internal and one external reset  
sources, as shown in Figure 10.  
SPI REGISTERS  
AWDRE Flag  
HVRE Flag  
HTRE Flag  
AWD Reset Sensor  
VDD  
High Voltage  
Reset Sensor  
High-Temperature  
Reset Sensor  
RST  
MONO  
FLOP  
Low-Voltage Reset  
Figure 10. Internal Reset Routing  
Internal Sources  
External Sources  
Autonomous Watchdog  
Reset Terminal  
AWD modules generates RESET because of time-out  
(watchdog function).  
The microcontroller has the capability of resetting the  
SmartMOS device by pulling down the RESET terminal.  
High-Temperature Reset  
Reset Mask Register (RMR)  
To prevent a damage of the device, a RESET will be initiate  
if the temperature rises above a certain value. The reset is  
maskable with bit HTRE in the Reset Mask Register. After a  
reset the high-temperature reset is disabled.  
Register Name and Address: RMR - $06  
Bit7  
TTEST  
0
6
0
5
0
4
0
3
0
2
0
1
Bit0  
Read  
Write  
Reset  
HVRE HTRE  
Low-Voltage Reset  
0
0
0
0
0
0
0
The LVR is related to the internal VDD. In case the voltage  
falls below a certain threshold, it will pull down the RESET  
terminal.  
HVRE—High-Voltage Reset Enable Bit  
This read/write bit enables resets on high-voltage  
conditions. Reset clears the HVRE bit.  
High-Voltage Reset  
The HVR is related to the external VSUP voltage. In case the  
1 = High-voltage reset enabled.  
0 = High-voltage reset disabled.  
voltage is above a certain threshold, it will pull down the RESET  
terminal. The reset is maskable with bit HVRE in the Reset  
Mask Register. After a reset the high-voltage reset is disabled.  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
908E625  
19  
 
HTRE—High-Temperature Reset Enable Bit  
Serial Peripheral Interface (SPI)  
This read/write bit enables resets on high-temperature  
conditions. Reset clears the HTRE bit.  
The serial peripheral interface (SPI) creates the  
communication link between the microcontroller and the  
908E625.  
• 1 = High-temperature reset enabled.  
• 0 = High-temperature reset disabled.  
The interface consists of four terminals (see Figure 11):  
• MOSI—Master-Out Slave-In (Internal Pull-Down)  
• MISO—Master-In Slave-Out (Internal Pull-Down)  
• SPSCK—Serial Clock  
TTEST—High-Temperature Reset Test  
This read/write bit is for test purpose only. It decrease the  
overtemperature shutdown limit for final test. Reset clears the  
HTRE bit.  
•
SS—Slave Select (Internal Pull-Up)  
A complete data transfer via the SPI consist of 2 bytes. The  
master sends address and data, the slave system status, and  
data of the selected address.  
• 1 = Low-temperature threshold enabled.  
• 0 = High-temperature threshold disabled.  
SS  
Read/Write, Address, Parity  
Data (Register write)  
R/W A4  
A3  
A2  
A1  
A0  
P
X
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
MOSI  
System Status Register  
Data (Register read)  
S7  
S6  
S5  
S4  
S3  
S2  
S1  
S0  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
MISO  
SPSCK  
Rising edge of SPSCK  
Change MISO/MOSI  
Output  
Falling edge of SPSCK  
Sample MISO/MOSI  
Input  
Slave latch  
register address  
Slave latch  
data  
Figure 11. Principle SPI Protocol  
During the inactive phase of SS, the new data transfer will be  
prepared. The falling edge on the SS line indicates the start of  
a new data transfer and puts MISO in the low impedance mode.  
The first valid data are moved to MISO with the rising edge of  
SPSCK.  
Master Address Byte  
A4–A0  
Includes the address of the desired register.  
The MISO output will change data on a rising edge of  
SPSCK. The MOSI input will be sampled on a falling edge of  
SPSCK. The data transfer is only valid if exactly 16 sample  
clock edges are present in the active phase of SS.  
R/W  
Includes the information if it is a read or a write operation.  
• If R/W = 1, the second byte of master contains no valid  
information, slave just transmits back register data.  
• If R/W = 0, the master sends data to be written in the  
second byte, slave sends concurrently contents of  
selected register prior to write operation, write data is  
latched in the SmartMOS register on rising edge of SS.  
After a write operation, the transmitted data will be latched  
into the register by the rising edge of SS.  
Register read data is internally latched into the SPI at the  
time when the parity bit is transferred.  
SS high will force MISO to high impedance.  
908E625  
20  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
 
Parity P  
Slave Status Byte  
Completes the total number of 1 bits of (R/W,A[4:0]) to an  
This byte includes always the contents of the sYstem Status  
Register ($0c) independent if it is a write or read operation or  
which register was selected.  
even number; e.g., (R/W,A[4:0]) = 100001 -> P0 = 0.  
The parity bit is only evaluated during a write operation.  
Slave Data Byte  
Bit X  
This byte includes the contents of selected register, during  
write operation in includes the register content prior to write  
operation.  
Not used.  
Master Data Byte  
This byte includes data to be written or no valid data during  
a read operation.  
SPI Register Overview  
Table 1 summarizes the SPI Register addresses and the bit  
names of each register.  
Table 1. List of Registers  
Bit  
Addr  
$01  
$02  
$03  
$04  
$05  
$06  
$07  
Register Name  
R/W  
7
6
5
HB3_H  
0
4
HB3_L  
0
3
HB2_H  
0
2
1
0
R
W
R
H-Bridge Output  
(HBOUT)  
HB4_H  
HB4_L  
HB2_L  
HB1_H  
HB1_L  
H-Bridge Control  
(HBCTL)  
OFC_EN  
CSA  
SRS1  
PHIE  
CLS2  
0
CLS1  
0
CLS0  
W
R
0
0
0
GS  
0
System Control  
(SYSCTL)  
PSON  
SRS0  
ISOIE  
W
R
Interrupt Mask  
(IMR)  
0
0
HTIE  
LVIE  
HVIE  
OCIE  
OCF  
W
R
0
Interrupt Flag  
(IFR)  
PHF  
0
ISOF  
0
HTF  
0
LVF  
0
HVF  
0
W
R
Reset Mask  
(RMR)  
TTEST  
0
HVRE  
SS1  
HTRE  
SS0  
W
R
0
0
0
0
0
0
A/D Output  
(ADOUT)  
SS3  
0
SS2  
W
R
Hall-Effect Sensor Input  
Terminal Control  
(HACTL)  
0
0
$08  
$09  
H3EN  
H3F  
H2EN  
H2F  
H1EN  
H1F  
W
Hall-Effect Sensor Input  
Terminal Status  
(HASTAT)  
R
0
0
0
0
W
R
W
R
0
0
0
0
0
AWD Control  
(AWDCTL)  
$0a  
$0b  
$0c  
AWDRE  
CSSEL0  
AWDIE  
AWDCC  
AWDF  
AWDR  
AWDRST  
Power Output  
(POUT)  
CSSEL1  
CSEN1  
LVF  
CSEN0  
HVF  
HVDDON  
HB_OCF  
HS_ON  
HTF  
W
R
SICL  
System Status Register  
(SYSSTAT)  
HP_OCF  
HVDD_OCF HS_OCF  
W
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
908E625  
21  
 
Analog Multiplexer/ADOUT Terminal  
Analog Die I/Os  
LIN Physical Layer  
The ADOUT terminal is the analog output interface to the  
ADC of the MCU. To be able to have different sources for the  
MCU, an analog multiplexer is integrated. This multiplexer has  
nine different sources.  
This I/O provides a physical layer for full-/half duplex  
communication in automotive applications. The physical layer is  
designed to meet the LIN physical layer specification.  
Current Recopy  
Single-Wire Interface (SIO)  
The multiplexer is connected to the four low side current  
sense circuits of the half-bridges. This sense circuits offers a  
voltage proportional to the current through the low side  
transistor. The resolution is selectable between 5.0 V/2.5 A or  
5.0 V/500 mA. (Refer to Half-Bridge Current Recopy on page  
30.)  
The SIO terminal is the LIN interface, which is suited for  
automotive bus systems.  
The driver is a low-side transistor with a internal current  
limitation and a thermal shutdown. An internal pull-up resistor  
with a serial diode structure is integrated, so no external pull-up  
components are required for the application in a slave node.  
The fall time from dominate to recessive and the rise time from  
recessive to dominate is controlled. The symmetry between  
both slew rate controls is guaranteed.  
Analog Inputs  
Each analog input is directly connected to the analog  
multiplexer. It offers the possibility to read analog values from  
the periphery.  
The terminal offers high susceptibility immunity level from  
external disturbance in order to guarantee communication  
during external disturbance.  
Temperature Sensor  
The MC33980 includes a on-chip temperature sensor. This  
sensor offers a voltage which is proportional to the actual chip  
junction temperature.  
The LIN transmitter circuitry will be enabled by setting bit  
PSON in the System Control Register. If the transmitter work in  
the current limitation region, the SICL bit in the System Status  
Register is set. The software should switch off the transmitter  
owing to high power dissipation.  
VSUP Prescaler  
The VSUP prescaler offers a possibility to read or measure  
TxD Terminal  
the external supply voltage. The output of this voltage is VSUP  
/
RATIOVSUP  
.
This terminal is the MCU interface to control the state of the  
LIN transmitter. When TxD is low, LIN output is low. When TxD  
is high, LIN output transistor is turned off. The terminal has an  
internal pull-up current source in order to set the bus in  
recessive state in case the microcontroller could not control it  
during system power-up or power-down for instance.  
The different sources can be selected with the ADOUT  
Register.  
Analog Multiplexer Configuration Register (ADOUT)  
Register Name and Address: ADOUT - $07  
RxD Terminal  
Bit7  
0
6
0
5
0
4
0
3
SS3  
0
2
SS2  
0
1
SS1  
0
Bit0  
SS0  
0
This terminal is the MCU interface, which reports the state of  
the LIN bus voltage. LIN high is reported by a high level on RxD,  
LIN low reported by a low voltage on RxD.  
Read  
Write  
Reset  
0
0
0
0
STOP Mode/Wake-Up Feature  
During STOP mode operation the transmitter of the physical  
layer is disabled. The receiver terminal is still active to be able  
to detect wake-up events on the busline.  
SS3, SS2, SS1, and SS0—A/D Input Select Bits  
These read/write bits select the input to the ADC in the  
microcontroller according to Table 2, page 23. Reset clears  
SS3, SS2, SS1, and SS0 bits.  
If the SIO interrupt is enabled (SIOIE bit in the Interrupt Mask  
Register is set), a falling edge on the SIO line will cause an  
interrupt. This interrupt will switch on the main voltage regulator  
and generate a system wake-up.  
908E625  
22  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
Table 2. Analog Multiplexer Configuration Register  
The Port A provides one analog input used for reading  
switches or as analog inputs for potentiometers, NTC, etc.  
SS3  
0
SS2  
0
SS1  
0
SS0  
0
Channel  
The PA1 is an input terminal for reading analog values. The  
terminal is internally connected to the analog multiplexer. In  
addition the terminal has a switchable current source (see  
Figure 12).  
Current Recopy HB1  
Current Recopy HB2  
Current Recopy HB3  
Current Recopy HB4  
VSUP Prescaler  
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
Temperature  
Not Used  
PA1 Terminal  
Not Used  
Not Used  
Not Used  
Not Used  
Not Used  
Not Used  
Not Used  
Not Used  
Source Selection Bits  
SSx  
VDD  
3
Selectable  
Current  
Source  
CSSEL  
PSON  
CSEN  
Analog  
Multiplexer  
ADOUT  
PA1  
Analog Port PA1  
NTC  
Figure 12. Analog Input + Multiplexer  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
908E625  
23  
 
PORT A Current Source  
CSSEL0–CSSEL1—Current Source Select Bits  
PA1 provides a switchable current source, to be able to read  
in switches, NTC, etc., without the need of an additional supply  
line for the sensor. With this feature it is possible to read  
multiple switches on one input. The overall enable of this  
feature is done by setting the PSON bit in the System Control  
Register. The switch on of each individual current source is  
done by the CSEN bit in the Power Output Register. The value  
of the current source is selected by CSSELx.  
This read/write bit selects the current source values. Reset  
clears CSSEL0–CSSEL1 bits (refer to Table 4).  
Table 4. PA1 Current Source Level Selection Bits  
CSSEL1  
CSSEL0  
Current Source Enable (typ.)  
0
0
1
1
0
1
0
1
70 µA  
210 µA  
420 µA  
700 µA  
With the CSSELx bits, four different current source values  
can be selected: 60 µA, 180 µA, 360 µA, and 600 µA.  
This function ceases during STOP mode operation.  
Power Output Register (POUT)  
Hall-Effect Sensor Input Terminals  
Function  
Register Name and Address: IMR - $0b  
The Hall-effect sensor input terminals provide three inputs  
for two-terminal Hall-effect sensors to be able to detect stall and  
position or to read Hall-effect sensor contact switches. The Hall-  
effect sensor input terminals are not influenced by the PSON bit  
in the System Control Register.  
Bit7  
6
5
4
3
CSEN  
0
2
1
Bit0  
0
0
Read  
Write  
Reset  
Notes  
CSSEL CSSEL  
0
HVDDON HS_ON  
1
0
(Note 15)  
0
0
0
0
0
0
0
Each terminal of the Hall-effect sensor can be enabled by  
setting the HxEN bit in the Hall-Effect Sensor Input Terminal  
Control Register. If the terminals are enabled, the Hall-effect  
sensors are supplied with VSUP voltage and the sense circuitry  
is working. This sense circuitry monitors the current to VSS.  
The result of this sense operation is given by the HxF flags in  
the Hall-Effect Sensor Input Terminal Status Register.  
15. This bit must always be set to “0”.  
HVDDON—HVDD On Bit  
This read/write bit enables HVDD output. Reset clears  
HVDDON bit.  
The flag is high if the sensed current is higher than IREC. To  
prevent noise on this flag, a hysteresis is implemented on these  
terminals.  
• 1 = HVDD enabled.  
• 0 = HVDD disabled.  
HS_ON—Lamp Driver On Bit  
After switching on the Hall-effect sensor input terminals  
(HxEN = 1), the Hall-effect sensors need some time to stabilize  
the output. In RUN mode the software must take care to wait a  
few microseconds before sensing the hallflags.  
This read/write bit enables the Lamp driver. Reset clears  
HS_ON bit.  
• 1 = Lamp driver enabled.  
• 0 = Lamp driver disabled.  
The Hall-effect sensor input terminal is working in an  
dynamic output voltage range from VSUP to 1.5 V. Below 1.5 V  
the hallflags are not functional anymore. In case the output  
voltage is below a certain threshold, the Hall-Effect Sensor  
Input Terminal Overcurrent Flag (HP_OCF) in the System  
Status Register is set.  
CSEN—Current Source Enable Bits  
This read/write bit enables the current source for PA0–PA2.  
Reset clears CSENx bits (refer to Table 3).  
Figures 13 through 15, pp. 25–26, show the connections to  
the Hall-effect input sensors.  
Table 3. PA1 Current Source Enable Bit  
CSEN  
Current Source Enable  
Current Source Off  
0
1
PA1 Current Source Enabled  
908E625  
24  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
 
 
 
HxEN  
Two-Termnal Hall-Effect Sensor  
Sense  
Circuitry  
Hx  
HxF  
CGND  
V
Figure 13. Hall-Effect Sensor Input Terminal Connected to Two-Terminal Hall-Effect Sensor  
HxEN  
Rv  
Sense  
Circuitry  
Hx  
HxF  
CGND  
V
Figure 14. Hall-Effect Sensor Input Terminal Connected to Local Switch  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
908E625  
25  
Three-Terminal Hall-Effect Sensor  
Vs  
HxEN  
Sense  
Circuitry  
Hx  
Out  
HxF  
CGND  
GND  
V
Figure 15. Hall-Effect Sensor Input Terminal Connected to Three-Terminal Hall-Effect Sensor  
Cyclic Wake-Up  
Interrupts  
The Hall-effect sensor input terminal is interrupt capable.  
The Hall-effect sensor inputs can be used to wake up the  
system. This wake-up function will be provided by the cyclic  
check wake-up feature of the AWD (autonomous watchdog).  
How and when an interrupt occurs is dependent on the actual  
operating mode.  
If the cyclic check wake-up feature is enabled (AWDCC bit is  
set), the AWD will switch on the enabled Hall-effect sensor  
terminals periodically. To be sure that the Hall-effect sensor  
current after switch on is stabilized, the inputs are sensed after  
~32 µs. If a “1” is detected (IHall sensor > IREC) and the interrupt  
RUN Mode  
In RUN mode the Hall-effect sensor input terminal interrupt  
flag (PHF) will be set if a state change on the hallflags (HxF) is  
detected. The interrupt is maskable with the PHIE bit in the  
Interrupt Mask Register. Before enabling the interrupt, the flag  
should be cleared in order to prevent a wrong interrupt.  
mask bit PHIE is set, an interrupt will be performed. This will  
wake up the MCU and start the main voltage regulator.  
The wake-up function via this input is available when all three  
conditions exist:  
STOP Mode  
In STOP mode the Hall-effect sensor input terminals are  
disabled independent of the state of the HxEN flags.  
• The 2-terminal Hall-effect sensor input is enabled  
(HxEN = 1).  
• The cyclic wake-up of the AWD is enabled (AWDCC = 1)  
(see Figure 16, page 27).  
• The Hall-effect sensor input terminal interrupt is enabled  
(PHIE = 1).  
908E625  
26  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
SPI  
AWDCC = 1  
GS = 1  
SPI Command  
STOP  
MREG  
*
No  
AWD  
timer overflow ?  
STOP  
Yes  
Switch on selected  
Hall-effect sensor  
input terminal  
No  
IRQ ?  
Yes  
IRQ = 0  
Start MREG*  
SPI  
reason for wake-up  
Wait 32 µs  
Yes  
Hall-effect  
sensor = 1  
Operate  
Assert IRQ  
No  
*MREG = Main voltage regulator  
Figure 16. Hall-Effect Sensor Input Terminal Cyclic Check Wake-Up Feature  
Hall-Effect Sensor Input Terminal Control Register  
(HACTL)  
Hall-Effect Sensor Input Terminal Status Register  
(HASTAT)  
Register Name and Address: HACTL - $08  
Register Name and Address: HASTAT - $09  
Bit7  
6
0
5
0
4
0
3
0
2
1
Bit0  
Bit7  
6
0
5
0
4
0
3
0
2
1
Bit0  
H1F  
Read  
Write  
Reset  
Read  
Write  
Reset  
0
0
0
0
H3F  
H2F  
H3EN H2EN H1EN  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
H3EN, H2EN, and H1EN—Hall-Effect Sensor Input  
Terminal Enable Bits  
H3F, H2F, and H1F—Hall-Effect Sensor Input Terminal Flag  
Bits  
These read/write bits enable the Hall-effect sensor input  
terminals. Reset clears H3EN, H2EN, and H1EN bit.  
This read/write flag reflects the input Hx while the Hall-effect  
sensor input terminal Hx is enabled (HxEN = 1). Reset clears  
the HxF bit.  
• 1 = Hall-effect sensor input terminal Hx is switched on and  
sensed.  
• 0 = Hall-effect sensor input terminal Hx disabled.  
• 1 = Hall-effect sensor input terminal current above  
threshold.  
• 0 = Hall-effect sensor input terminal current below  
threshold.  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
908E625  
27  
Half-Bridges  
The output features:  
• Short circuit protection on high-side and low-side FETs  
(low side just via VDS monitoring).  
The outputs provide four low resistive half-bridge output  
stages. The half-bridges can be used in H-Bridge, high-side, or  
low-side configurations.  
• Current recopy feature (low side).  
• Overtemperature protection.  
• Overvoltage and undervoltage protection.  
• Current limitation feature (low side).  
Reset clears all bits in the H-Bridge Output Register owing to  
the fact that all half-bridge outputs are switched off.  
VSUP  
on/off  
High-Side Driver  
Charge Pump,  
Overtemperature Protection,  
Overcurrent Protection  
Status  
BEMF  
Control  
HBx  
on/off  
Low-Side Driver  
Current Recopy,  
Status  
Current Limitation,  
Overcurrent Protection via  
VDS Monitoring  
Current limit  
GND  
Figure 17. Half-Bridge Push-Pull Output Driver  
Half-Bridge Output Register (HBOUT)  
Half-Bridge Control  
Each output FET can be controlled individually. The general  
enable of the circuitry is done by setting PSON in the System  
Control Register. HBx_L and HBx_H form one half-bridge. It is  
not possible to switch on both FETs in one half-bridge at the  
same time.  
Register Name and Address: HBOUT - $01  
Bit7  
6
5
4
3
2
1
Bit0  
Read  
Write  
Reset  
HB4_H HB4_L HB3_H HB3_L HB2_H HB2_L HB!_H HB1_L  
In case both bits are set, the high-side transistor has a higher  
priority. To avoid cross conduction while switching the output  
transistors, a break before make circuit exists. The switch on of  
the high-side transistor is inhibited as long as the potential  
between gate and VSS is not below a certain threshold. The  
switch on of the low-side transistor is blocked as long as the  
potential between gate and source of the high-side transistor  
did not fall below a certain threshold.  
0
0
0
0
0
0
0
0
HBx_L—Low-Side On/Off Bits  
These read/write bits turn on the low-side FETs. Reset  
clears the HBx_L bits.  
• 1 = Low side is turned on for Output x.  
• 0 = Low side is turned off for Output x.  
908E625  
28  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
HBx_H—High-Side On/Off Bits  
frequency, whereas the duty cycle is controlled by the load  
characteristics.  
These read/write bits turn on the high-side FETs. Reset  
clears the HBx_H bits.  
The maximum input frequency for the FGEN and the PWM is  
~25 kHz.  
1 = High-side driver turned on for Output x.  
0 = High-side driver turned off for Output x.  
Functionality  
Half-Bridge Current Limitation  
Each low-side transistor will switch off if a current above the  
selected current limit was detected. The 908E625 offers five  
different current limits: 60 mA, 250 mA, 350 mA, 500 mA, and  
700 mA.  
Each low-side transistor offers a current limit or constant  
current feature. This features is realized by a pulse width  
modulation on the low-side transistors. The pulse width  
modulation on the outputs is controlled by the FGEN input and  
the load characteristic. The FGEN input provides the PWM  
The output transistor will switch on again if a rising edge on  
the FGEN input was detected (see Figure 18).  
H -B ridge lLowow-siSdeidFeEFTE T  
w ill be sw itched off if  
select current lim it is  
Coil Current  
.
reached  
H -B ridge lLooww-siSdeidFeEFTE T  
w ill be turned on w ith each  
rising edge of the FG E N  
.
input  
t (µs)  
Half-Bridge  
Low-Side Output  
t(µs)  
FGEN Input  
(Microcontroller PWM Signal)  
t (µs)  
Minimum 50 µs  
Figure 18. Current Limitation  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
908E625  
29  
 
Offset Chopping  
falling edge on the FGEN input. In stepper motor applications  
this feature allows the reduction of EMI due to a reduction of the  
di/dt (see Figure 19).  
If Bit OFC_EN in the H-Bridge Control Register is set, HB3  
and HB4 will switch on the low-side-FETs after detecting a  
Coil1Current  
Coil2 Current  
FGEN Input  
(Microcontroller  
PWM Signal)  
Current in  
VSUP Line  
Figure 19. Offset Chopping for Stepper Motor Control  
Half-Bridge Current Recopy  
Half-Bridge BEMF Generation  
Each low-side FET has an additional sense output to allow a  
current recopy feature. This sense source is internally  
connected to a shunt resistor. The drop voltage is amplified and  
switched to the Analog Multiplexer.  
The BEMF output is set to one if in any half-bridge a  
recirculation current is detected. This recirculation current will  
flow via the two free wheel diodes of the power transistors. The  
BEMF circuitry will detect that and generate a high on the BEMF  
output as long as a recirculation current is detected. This signal  
provides a flexible and reliable detection of stall in stepper  
motor applications. For this the BEMF circuitry will take  
advantage of the instability of the electrical and mechanical  
behavior of a stepper motor when blocked. In addition the signal  
can be used for open load detection (absence of this signal)  
(see Figure 20, page 31).  
The factor for the Current Sense amplification can be  
selected via bit CSA in the System Control Register.  
• CSA = 1: Low resolution selected (500 mA measurement  
range).  
• CSA = 0: High resolution selected (2.5 A measurement  
range).  
908E625  
30  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
 
Coil Current  
Voltage on  
1
1
BEMF signal  
Figure 20. BEMF Signal Generation  
Half-Bridge Overtemperature Protection  
The overvoltage/undervoltage status flags are cleared (and  
the outputs re-enabled) by writing a logic [1] to the LVF/HVF  
flags in the Interrupt Flag Register or by RESET. Clearing this  
flag is useless as long as a high- or low-voltage condition is  
present.  
The outputs provide an overtemperature pre-warning with  
the HTF in the Interrupt Status Register. In order to protected  
the outputs against overtemperature, the High-Temperature  
Reset has to be enabled. If this value is reached, the part will  
generate a reset and disable all power outputs.  
Half-Bridge Control Register (HBCTL)  
Half-Bridge Overcurrent Protection  
Register Name and Address: HBCTL - $02  
The half-bridges are protected against short to GND, VSUP,  
and load shorts. The high-side protection is done by a real  
current measurement, the low-side FET just by monitoring VDS  
voltage.  
Bit7  
6
CSA  
0
5
0
4
0
3
0
2
1
Bit0  
Read  
Write  
Reset  
OFC_  
EN  
CLS2 CLS1 CLS0  
In case a overcurrent on the high side is detected, the high-  
side FETs on all HB high-side FETs are switched off  
automatically. In case an overcurrent on the low side is  
detected all HB low-side FETs will be switched off  
automatically. In both cases the overcurrent status flag  
HB_OCF in the System Status Register is set.  
0
0
0
0
0
0
0
OFC_EN—H-Bridge Offset Chopping Enable Bit  
This read/write bit enables offset chopping. Reset clears the  
OFC_EN bit.  
• 1 = Offset chopping enabled.  
• 0 = Offset chopping disabled.  
The overcurrent status flag is cleared (and the outputs re-  
enabled) by writing a logic [1] to the HB_OCF flag in the System  
Status Register or by RESET.  
CSA—H-Bridges Current Sense Amplification Select Bit  
Half-Bridge Overvoltage/Undervoltage  
This read/write bit selects the current sense amplification of  
the H-Bridges. Reset clears the CSA bit.  
The half-bridge outputs are protected against undervoltage  
and overvoltage conditions. This protection is done by the low-  
and high-voltage interrupt circuitry. If one of these flags (LVF,  
HVF) is set, the outputs are automatically disabled.  
• 1 = Current sense amplification set for measuring 0.5 A.  
• 0 = Current sense amplification set for measuring 2.5 A.  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
908E625  
31  
CLS2, CLS1, and CLS0—H-Bridge Current Limitation  
Selection Bits  
High-Side Driver  
The high-side output is a low resistive high-side switch,  
targeted for driving lamps. The high side is protected against  
overtemperature. To limit the high inrush current of bulbs the  
overcurrent protection circuitry will be used to limit the current.  
The output is enable with bit PSON in the System Control  
Register and can be switched on/off with bit HS_ON in the  
Power Output Register. See Figure 21 for high-side switch  
circuitry and connection to external lamp.  
These read/write bits select the current limitation value  
according to Table 5. Reset clears the CLS2, CLS1, and CLS0  
bits.  
Table 5. H-Bridge Current Limitation Value Selection Bits  
CLS2  
CLS1  
CLS0  
Current Limit  
No Limit  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No Limit  
No Limit  
55 mA (typ)  
275 mA (typ)  
370 mA (typ)  
550 mA (typ)  
740 mA (typ)  
VSUP  
on/off  
High-Side Driver  
Status  
Charge Pump,  
Control  
Overcurrent Protection,  
Inrush Current Limiter  
Current  
Limit  
HS  
Figure 21. High-Side Circuitry  
High-Side Overcurrent Protection  
High-Side Overvoltage/Undervoltage Protection  
The output is protected against undervoltage/overvoltage  
conditions. This protection is done by the low- and high-voltage  
interrupt circuitry. If one of these flags (LVF, HVF) is set, the  
output is disabled.  
The high-side output is protected against overcurrent. In  
case the overcurrent limit is or was reached, the output will be  
automatically switched off and the overcurrent flag is set.  
Due to the high inrush current of bulbs, a special feature was  
implemented to avoid a overcurrent shutdown during this inrush  
current. If an PWM frequency will be supplied to the FGEN  
output during the switch on of a bulb the inrush current will be  
limited to the overcurrent shutdown limit. This means if the  
current reaches the overcurrent shutdown, the high side will be  
switched off, but each rising edge on the FGEN input will enable  
the driver again.  
The overvoltage/undervoltage status flags are cleared (and  
the output re-enabled) by writing a logic [1] to the LVF/HVF  
flags in the Interrupt Flag Register or by RESET. Clearing this  
flag is useless as long as a high- or low-voltage condition is  
present.  
High-Side Overtemperature Protection  
In order to be able to distinguish between a shutdown due to  
an inrush current or a real shutdown, the software has to check  
if the overcurrent status flag (HS_OCF) in the System Status  
Register is set beyond a certain period of time.  
The high-side output provides an overtemperature pre-  
warning with the HTF in the Interrupt Status Register. In order  
to protected the output against overtemperature the High-  
Temperature Reset has to be enabled. If this value is reached,  
the part will generate a reset and disable all power outputs.  
908E625  
32  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
 
 
The overcurrent status flag is cleared by writing a logic [1] to  
the HS_OCF in the System Status Register (see Figure 22).  
High-Side  
Current  
High-Side Overcurrent Shutdown Threshold  
t
FGEN Input  
(Microcontroller  
PWM Signal)  
t
Figure 22. Inrush Current Limit on High-Side Output  
System Control Register (SYSCTL)  
Switchable VDD Outputs  
The HVDD terminal is a switchable VDD output terminal. It  
can be used for driving external circuitry which requires a VDD  
voltage. The output is enable with bit PSON in the System  
Control Register and can be switched on/off with bit HVDD_ON  
in the Power Output Register. Low- or high-voltage conditions  
(LVI/HVI) will have no influence on this circuitry.  
Register Name and Address: SYSCTL - $03  
Bit7  
6
5
4
0
3
0
2
0
1
0
Bit0  
0
Read  
Write  
Reset  
PSON SRS1 SRS0  
GS  
0
0
0
0
0
0
0
0
HVDD Overtemperature Protection  
The overtemperature protection is enabled if the high-  
temperature reset is enabled.  
PSON—Power Stages On Bit  
This read/write bit enables the power stages (half-bridges,  
high side, LIN transmitter, Port A Current Sources, and HVDD  
output). Reset clears the PSON bit.  
HVDD Overcurrent Protection  
The HVDD output is protected against overcurrent. In case  
the overcurrent limit is or was reached, the output will be  
automatically switched off and the HVDD overcurrent flag in the  
System Status Register is set.  
• 1 = Power stages enabled.  
• 0 = Power stages disabled.  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
908E625  
33  
 
SRS0–SRS1—LIN Slew Rate Selection Bits  
HVDD_OCF—HVDD Output Overcurrent Flag Bit  
This read/write bits enables the user to select the  
appropriate LIN slew rate for different baud rate configurations  
as shown in Table 6.  
This read/write flag is set on overcurrent condition at HVDD  
terminal. Clear HVDD_OCF and enable the output by writing a  
logic [1] to the HVDD_OCF Flag. Reset clears the HVDD_OCF  
bit. Writing a logic [0] to HVDD_OCF has no effect.  
Table 6. LIN Slew Rate Selection Bits  
• 1 = Overcurrent condition on VDD has occurred.  
• 0 = No overcurrent condition on VDD has occurred.  
SRS1  
SRS0  
Current Source Enable  
Initial SR  
0
0
1
1
0
1
0
0
HS_OCF—High-Side Overcurrent Flag Bit  
0.5 x initial SR  
16 x initial SR  
8 x initial SR  
This read/write flag is set on overcurrent condition at high-  
side driver. Clear HS_OCF and enable HS Driver by writing a  
logic [1] to HS_OCF. Reset clears the HS_OCF bit. Writing a  
logic [0] to HS_OCF has no effect.  
• 1 = Overcurrent condition on high-side drivers has  
GS—Go to STOP Mode Bit  
occurred.  
This read/write bit instructs the chip to power down and go  
into STOP mode. Reset or CPU interrupt requests clears the  
GS bit.  
• 0 = No overcurrent condition on high-side drivers has  
occurred.  
• 1 = Power down and go to STOP mode.  
• 0 = Not in STOP mode.  
LVF—H-Bridge Low-Voltage Bit  
This read only bit is a copy of the LVF bit in the Interrupt Flag  
Register.  
System Control Register (SYSSTAT)  
• 1 = Low-voltage condition on H-Bridges.  
• 0 = No low-voltage condition on H-Bridges.  
Register Name and Address: SYSSTAT - $0c  
Bit7  
6
5
4
3
2
1
Bit0  
HTF  
HVF—H-Bridge High-Voltage Sensor Bit  
Read  
Write  
Reset  
SICL  
LVF  
HVF  
HP_  
OCF  
HVDD  
_OCF  
HS_  
OCF  
HB_  
OCF  
This read only bit is a copy of the HVF bit in the Interrupt Flag  
Register.  
0
0
0
0
0
0
0
0
• 1 = High-voltage condition on H-Bridges.  
• 0 = No high-voltage condition on H-Bridges.  
HP_OCF—Hall-Effect Sensor Input Terminal Overcurrent  
Flag Bit  
HB_OCF—H-Bridge Overcurrent Flag Bit  
This read/write flag is set on overcurrent condition at one of  
the Hall-effect sensor input terminals. Clear HP_OCF and  
enable the output by writing a logic [1] to the HP_OCF Flag.  
Reset clears the HP_OCF bit. Writing a logic [0] to HP_OCF  
has no effect.  
This read/ write flag is set on overcurrent condition at the H-  
Bridges. Clear HB_OCF and enable Half-Bridge driver by  
writing a logic [1] to HB_OCF. Reset clears the HB_OCF bit.  
Writing a logic [0] to HB_OCF has no effect.  
• 1 = Overcurrent condition on H-Bridges has occurred.  
• 0 = No overcurrent condition on H-Bridges has occurred.  
• 1 = Overcurrent condition on Hall-effect sensor input  
terminal has occurred.  
• 0 = No overcurrent condition on Hall-effect sensor input  
terminal has occurred.  
HTF—Overtemperature Status Bit  
This read only bit is a copy of the HTF bit in the Interrupt Flag  
Register.  
SICL — Serial Input Current Limitation Bit  
• 1 = Overtemperature condition on H-Bridges.  
• 0 = No overtemperature condition on H-Bridges.  
This read only bit is set if the ISO9141 transmitter operates  
in current limitation region. Due to excessive power dissipation  
in the transmitter, software is advised to turn the transmitter off  
immediately.  
• 1 = Transmitter operating in current limitation region.  
• 0 = Transmitter not operating in current limitation region.  
908E625  
34  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
 
AWDRE—Autonomous Watchdog Reset Enable Bit  
Autonomous Watchdog (AWD)  
This read/write bit enables resets on AWD time-outs. RST  
will only be asserted when the device is in RUN mode. AWDRE  
is one-time setable after each reset. Reset clears the AWDRE  
bit.  
The Autonomous Watchdog module comprises three  
functions:  
• Periodic interrupt function  
• Watchdog function for the CPU in RUN mode  
• Cyclic wake-up function  
• 1 = Autonomous watchdog enabled.  
• 0 = Autonomous watchdog disabled.  
The AWD is enabled if AWDIE or AWDRE or AWDCC in the  
AWDCTL Register is set. If these bits are cleared, the AWD  
oscillator is disabled and the watchdog is switched off.  
AWDIE—Autonomous Watchdog Interrupt Enable Bit  
This read/write bit enables CPU interrupts by the  
Autonomous Watchdog time-out flag, AWFD. IRQ will only be  
asserted when the device is in STOP mode. Reset clears the  
AWDIE bit.  
Periodic Interrupt  
The periodic interrupt is available in STOP mode. It will be  
enabled by setting the AWDIE bit in the AWDCTL Register. If  
AWDIE is set, the AWD will wake up the system after a fixed  
period of time. This time period can be selected with bit AWDR  
in the AWD Control Register.  
• 1 = CPU interrupt requests from AWDF enabled.  
• 0 = CPU interrupt requests from AWDF disabled.  
AWDCC—Autonomous Watchdog Cyclic Check  
Watchdog  
This read/write bit enables the cyclic check of the two-  
terminal Hall-effect sensor and the analog inputs. Reset clears  
the AWDCC bit.  
The watchdog function is only available in RUN mode. On  
setting the AWDRE bit, the watchdog functionality in RUN mode  
is activated. Once this function is enabled, it is not possible to  
disable it via software.  
• 1 = Cyclic check of the Hall-effect sensor and analog port.  
• 0 = No cyclic check of the Hall-effect sensor and analog  
port.  
If the timer reaches end value and AWDRE is set, a system  
reset will be initiated. Operations of the watchdog function are  
ceased in STOP mode. Normal operation will be continued  
when the system is back to RUN mode.  
AWDF—Autonomous Watchdog Time-Out Flag Bit  
This read/write flag is set when the Autonomous Watchdog  
has timed out. Clear AWDF by writing a logic [1] to AWDF.  
Clearing AWDF also resets the AWD counter and starts a new  
time-out period. Reset clears the AWDF bit. Writing a logic [0]  
to AWDF has no effect.  
To prevent a watchdog reset the watchdog time-out counter  
has to be reset before it reaches the end value. This is done by  
a write to the AWDRST bit in the AWDCTL Register.  
Cyclic Wake-Up  
• 1 = AWD has timed out.  
• 0 = AWD has not yet timed out.  
The cyclic wake-up feature is available in STOP mode. If this  
feature is enabled, the selected Hall-effect sensor input  
terminals are switched on and sensed. If a “1” is detected on  
one of these inputs and the interrupt for the Hall-effect sensors  
is enabled, a system wake-up will be performed. (Switch on  
main voltage regulator and assert IRQ to the microcontroller).  
AWDR—Autonomous Watchdog Rate Bit  
This read/write bit select the clock rate of the Autonomous  
Watchdog. Reset clears the AWDR bit.  
• 1 = Fast rate selected (10 ms).  
• 0 = Slow rate selected (20 ms).  
Autonomous Watchdog Control Register (AWDCTL)  
Voltage Regulator  
Register Name and Address: AWDCTL - $0b  
The 908E625 chip contains a low-power, low-drop voltage  
regulator to provide internal power and external power for the  
MCU. The on-chip regulator consist of two elements, the main  
regulator and the low-voltage reset circuit.  
Bit7  
0
6
0
5
4
3
2
1
AWDF  
0
Bit0  
AWDR  
0
Read  
Write  
Reset  
AWDRE AWDIE AWDCC  
AWDRST  
0
0
0
0
0
0
The VDD regulator accepts a unregulated input supply and  
provides a regulated VDD supply to all digital sections of the  
device. The output of the regulator is also connected to the VDD  
AWDRST—Autonomous Watchdog Reset Bit  
terminal to provide the 5.0 V to the microcontroller.  
This write only bit resets the Autonomous Watchdog time-out  
period. AWDRST always reads zero. Reset clears AWDRST  
bit.  
RUN Mode  
During RUN mode the main voltage regulator is on. It will  
provide a regulated supply to all digital sections.  
• 1 = Reset AWD and restart time-out period.  
• 0 = No effect.  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
908E625  
35  
STOP Mode  
regulator has a very limited output current capability. The output  
voltage will be lower as the output voltage of the main voltage  
regulator.  
During STOP mode, the STOP mode regulator will take care  
of suppling a regulated output voltage. The STOP mode  
PACKAGE THERMAL PERFORMANCE  
Figure 23 shows a thermal response curve for a package  
mounted onto a thermally enhanced PCB.  
Note PCB board is a multi-layer with two inner copper  
planes (2s2p). The board conforms to JEDEC EIA/JESD 51-5  
and JESD51-7. Substrate thickness is 1.60 mm. Top and  
bottom copper trace layers are 0.7 mm thick, with two inner  
copper planes of 0.35 mm thickness. Thermal vias have  
0.35 mm thick plating.  
30  
25  
20  
15  
10  
5
5.0  
0
0.00001 0.0001 0.001  
0.01  
0.1  
11.0  
10  
100  
1000  
10000  
Time (s)  
]  
Figure 23. Thermal Response of H-Bridge Driver with Package Soldered to a JEDEC PCB Board  
908E625  
36  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
 
PACKAGE DIMENSIONS  
DWB SUFFIX  
54-TERMINAL SOIC WIDE BODY EXPOSED PAD  
PLASTIC PACKAGE  
CASE 1400-01  
ISSUE B  
10.3  
5
C
9
7.6  
7.4  
2.65  
2.35  
B
NOTES:  
1. ALL DIMENSIONS ARE IN MILLIMETERS.  
2. DIMENSIONING AND TOLERANCING PER ASME  
Y14.5M, 1994.  
3. DATUMSBANDCTOBEDETERMINEDATTHEPLANE  
WHERE THE BOTTOM OF THE LEADS EXIT THE  
PLASTIC BODY.  
52X  
1
54  
0.65  
4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH,  
PROTRUSION OR GATE BURRS. MOLD FLASH,  
PROTRUSION OR GATEBURRS SHALLNOT EXCEED  
0.15MMPERSIDE.THISDIMENSIONISDETERMINED  
AT THE PLANE WHERE THE BOTTOM OF THE LEADS  
EXIT THE PLASTIC BODY.  
PIN 1 INDEX  
5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD  
FLASH OR PROTRUSIONS. INTERLEAD FLASH AND  
PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER  
SIDE. THIS DIMENSION IS DETERMINED AT THE  
PLANE WHERE THE BOTTOM OF THE LEADS EXIT  
THE PLASTIC BODY.  
4
9
18.0  
17.8  
C
L
6. THIS DIMENSION DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION  
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED  
0.46 MM. DAMBAR CANNOT BE LOCATED ON THE  
LOWER RADIUS OR THE FOOT. MINIMUM SPACE  
BETWEEN PROTRUSION AND ADJACENT LEAD  
SHALL NOT LESS THAN 0.07 MM.  
B
B
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.  
8. THESE DIMENSIONS APPLY TO THE FLAT SECTION  
OF THE LEAD BETWEEN 0.1 MM AND 0.3 MM FROM  
THE LEAD TIP.  
9. THE PACKAGE TOP MAY BE SMALLER THAN THE  
PACKAGE BOTTOM. THIS DIMENSION IS  
27  
28  
SEATING  
DETERMINED AT THE OUTERMOST EXTREMES OF  
THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH,  
TIE BAR BURRS, GATE BURRS AND INTER-LEAD  
FLASH, BUT INCLUDING ANY MISMATCH BETWEEN  
THE TOP AND BOTTOM OF THE PLASTIC BODY.  
A
54X  
PLANE  
5.15  
2X 27 TIPS  
0.10  
A
0.3  
A B C  
A
R0.08 MIN  
0.25  
°
MIN  
0
C
C
GAUGE PLANE  
(1.43)  
A
0.1  
0.0  
0.9  
0.5  
°
°
8
0
10.9  
9.7  
0.30 A B C  
SECTION B-B  
(0.29)  
BASE METAL  
0.30  
0.25  
(0.25)  
5.3  
4.8  
0.38  
0.22  
0.30 A B C  
PLATING  
6
M
0.13  
A
B C  
8
SECTION A-A  
ROTATED 90 CLOCKWISE  
°
VIEW C-C  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
908E625  
37  
NOTES  
908E625  
38  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
NOTES  
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA  
908E625  
39  
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee  
regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product  
or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do  
vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer  
application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not  
designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or  
sustain life, or for any other appl ication in which the failure of the Motorola product could create a situation where personal injury or death may occur.  
Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its  
officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees  
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that  
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Opportunity/Affirmative Action Employer.  
MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their  
respective owners.  
© Motorola, Inc. 2003  
HOW TO REACH US:  
USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution: P.O. Box 5405, Denver, Colorado 80217.  
1-303-675-2140 or 1-800-441-2447  
JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan.  
81-3-3440-3569  
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tao Po, N.T.,  
Hong Kong. 852-26668334  
TECHNICAL INFORMATION CENTER: 1-800-521-6274  
MM908E625/D  

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