MPC2106ASG66 [MOTOROLA]
512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms; 512KB和1MB BurstRAM二级缓存模块用于PowerPC准备/ CHRP平台
| 型号： | MPC2106ASG66 |
| 厂家： | 
MOTOROLA |
| 描述： | 512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| 文件： | 总20页 (文件大小：249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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by MPC2105A/D
SEMICONDUCTOR TECHNICAL DATA
512KB and 1MB BurstRAM
Secondary Cache Modules for
PowerPC PReP/CHRP Platforms
The MPC2105A/B and the MPC2106A/B are designed to provide burstable, high
performance L2 cache for the PowerPC 60x microprocessor family in conformance
with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware
Reference Platform (CHRP) specifications.
MPC2105A
MPC2106A
MPC2105B
MPC2106B
The MPC2105A/B and MPC2106A/B utilize synchronous BurstRAMs. The
modules are configured as 64K x 72, and 128K x 72 bits in a 178 (89 x 2) pin DIMM
format. The MPC2105A/B uses four of the 3 V 64K x 18; the MPC2106A/B uses eight
of the 3 V 64K x 18. For tag bits, a 5 V cache tag RAM configured as 16K x 12 for tag
field plus 16K x 2 for valid and dirty status bits is used.
178–LEAD CARD EDGE
TOP VIEW
MPC2105A/B CASE 1132A–01
MPC2106A/B CASE 1132–01
Bursts can be initiated with the ADS signal. Subsequent burst addresses are
generated internal to the BurstRAM by the CNTEN signal.
Write cycles are internally self timed and are initiated by the rising edge of the clock
(CLKx) inputs. Eight write enables are provided for byte write control.
Presence detect pins are available for auto configuration of the cache control.
The module family pinout will support 5 V and 3.3 V components for a clear path
to lower voltage and power savings. Both power supplies must be connected.
All of these cache modules are plug and pin compatible with each other.
1
•
•
•
•
•
PowerPC–style Burst Counter on Chip
Flow–Through Data I/O
Plug and Pin Compatibility
Multiple Clock Pins for Reduced Loading
20 Ω Series Resistors on DL and DH Pins for Noise
Reduction (MPC2105A/6A)
24
25
•
•
•
•
•
All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible
Three State Outputs
Byte Write Capability
Fast Module Clock Rates: Up to 66 MHz
Fast SRAM Access Times: 10 ns for Tag RAM Match
9 ns for Data RAM
47
48
•
•
•
•
Decoupling Capacitors for Each Fast Static RAM
High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes
178 Pin Card Edge Module
Burndy Connector, Part Number: ELF178KSC–3Z50
80
BurstRAM is a trademark of Motorola.
The PowerPC name is a trademark of IBM Corp., used under license therefrom.
REV 1
12/19/96
Motorola, Inc. 1996
MPC2105A/B BLOCK DIAGRAM
V
SS
A13 – A28
’244
BA13 – BA28
69F618ATQ
SA
SBA
DQA
SBB
DQB
K
CWE0
DH0 – DH7 + DP0
CWE1
ADS0
CNTEN0
CG0
ADSC
ADV
G
DH8 – DH15 + DP1
CLK0
SE1
69F618ATQ
SRAM TIE OFF
SBA
DQA
SBB
DQB
K
CWE2
DH16 – DH23 + DP2
CWE3
SA
V
DD
ADSC
ADV
G
DH24 – DH31 + DP3
CLK0
SE1
SE2
SGW
ADSP
SW
ZZ
69F618ATQ
SA
CWE4
DL0 – DL7 + DP4
CWE5
SBA
DQA
SBB
DQB
K
ADSC
ADV
G
DL8 – DL15 + DP5
CLK1
SE1
69F618ATQ
SA
SBA
DQA
SBB
DQB
K
CWE6
DL16 – DL23 + DP6
CWE7
ADSC
ADV
G
DL24 – DL31 + DP7
CLK1
SE1
A0
= NC
CLK3
CLK4
ALE
ADS1
CNTEN1 = NC
= NC
= NC
= NC
= NC
TAG: 16K x 12 + V + D
A0 – A13
TAG0 –11
A13 – A26
A1 – A12
TT1, WTD, E1
V
V
SS
SFUNC, SG
TAH, TAG, TAD
E2, PWRDN
RESET
SW
TCLR
TWE
CG1
= NC
= NC
= NC
via 100
Ω
CC
ADDR0
ADDR1
PD3
TW
V
CLK2
MATCH
DIRTYOUT
VALIDIN
DIRTYIN
TG
V
K
CCQ
DD
J3
J2
J1
MATCH
TA, VALIDQ
NC
WTQ
DIRTYQ
VALIDD
PD2
PD1
PD0
V
V
CC
CC
DIRTYD
TG
J0
Note: BA28 is tied to SA0 on SRAM;
BA27 is tied to SA1 on SRAM;
STANDBY is tied to SE3 on SRAM.
MPC2105A•MPC2106A•MPC2105B•MPC2106B
MOTOROLA FAST SRAM
2
MPC2106A/B BLOCK DIAGRAM
A13 – A28
A12
BA13 – BA28
BA12
’244
69F618ATQ
69F618ATQ
SA
SA
CWE0
DH0 – DH7 + DP0
CWE1
DH8 – DH15 + DP1
CLK0
SBA
DQA
SBB
DQB
K
SBB
DQB
SBA
DQA
K
ADS0
CNTEN0
CG0
ADS1
ADSC
ADV
G
ADSC
ADV
G
CNTEN1
CG1
SE1
SE2
69F618ATQ
69F618ATQ
SBA
DQA
SBB
DQB
K
SBB
DQB
SBA
DQA
K
CWE2
DH16 – DH23 + DP2
CWE3
DH24 – DH31 + DP3
CLK1
SA
SA
ADSC
ADV
G
ADSC
ADV
G
SE1
SE2
69F618ATQ
69F618ATQ
CWE4
DL0 – DL7 + DP4
CWE5
SA
SA
SBA
DQA
SBB
DQB
K
SBB
DQB
SBA
DQA
K
ADSC
ADV
G
ADSC
ADV
G
DL8 – DL15 + DP5
CLK3
SE1
SE2
69F618ATQ
69F618ATQ
SA
SA
SBA
DQA
SBB
DQB
K
SBB
DQB
SBA
DQA
K
CWE6
DL16 – DL23 + DP6
CWE7
ADSC
ADV
G
ADSC
ADV
G
DL24 – DL31 + DP7
CLK4
SE1
SE2
BANK A: SE2 TIED TO.
BANK B: SE1 TIED TO. V
SS
V
VIA 100 Ω.
DD
SRAM TIE OFF
V
DD
TAG: 16K x 12 + V + D
V
V
V
CC
CC
SS
A0 – A13
TAG0 –11
A13 – A26
A0 – A11
TT1, WTD
SFUNC, SG
TAH, TAG, TAD
PWRDN
RESET
SW
TW
TCLR
TWE
SGW
SW
ZZ
V
via 100 Ω
CC
ADSP
V
CLK2
MATCH
DIRTYOUT
VALIDIN
DIRTYIN
TG
V
K
CCQ
DD
MATCH
TA, VALIDQ
NC
WTQ
DIRTYQ
VALIDD
DIRTYD
TG
ALE
= NC
= NC
= NC
E1
E2
A12
ADDR0
ADDR1
PD3
V
CC
E1
E2
V
SS
A12
J3
J2
J1
J0
PD2
PD1
PD0
Note: BA28 is tied to SA0 on SRAM;
BA27 is tied to SA1 on SRAM;
STANDBY is tied to SE3 on SRAM.
MPC2105A•MPC2106A•MPC2105B•MPC2106B
MOTOROLA FAST SRAM
3
PIN ASSIGNMENT 178–LEAD DIMM
Pin
1
Name
Pin Name
Pin
53
54
55
56
57
58
59
60
61
62
Name
DL1
Pin
79
80
81
82
83
84
85
86
87
88
Name
Pin
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
Name
DH14
DH13
Pin
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
Name
DL17
CWE6
DL15
DL13
Pin
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
Name
A22
V
SS
27
DH0
DP0
V
SS
2
PD0/IDSCLK 28
DL0
A7
A5
A3
A0
A20
3
PD2
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
V
V
SS
V
CC
V
SS
SS
4
DH30
DH28
DH26
DH24
CLK1
CLK2
DH10
DH8
A18
A16
A15
A14
5
V
SS
V
SS
V
SS
6
DL28
DL26
DL24
DP7
DP4
CG0
CG1
V
CC
CWE1
DH6
DL10
DL8
7
TCLR
8
V
DD
MATCH
TG
V
DD
CWE5
DL6
V
DD
9
DP3
V
DH4
A10
DD
ADDR0
63 RESERVED 89
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
DH22
DH20
DH19
V
CC
DIRTYIN
V
SS
V
DD
A8
A6
DL22
DL20
DL18
DL16
V
V
CLK0
DL5
DL2
SS
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
ADS0
ADS1
A28
90
V
SS
V
SS
SS
V
SS
91 PD1/IDSDATA
DH1
CWE0
DL31
DL30
V
SS
A4
A2
A1
DH17
DP2
92
93
PD3
CLK3
V
SS
A26
DH31
DH29
DH27
DH25
V
SS
DH15
DH12
DP6
DL14
DL12
DL11
A25
94
CLK4
172 BURSTMODE
A23
95
V
SS
V
SS
173
174
175
176
177
V
CC
V
CC
V
SS
96
DL29
DL27
DL25
CWE4
ALE
VALIDIN
TWE
DH11
DH9
DP1
DH7
A21
A19
A17
A13
97
V
DD
V
SS
98
CWE3
DH23
DH21
DH18
V
DD
STANDBY
DIRTYOUT
DL9
DP5
DL7
DL4
99
V
CC
ADDR1
100
101
102
103
104
CWE7
DL23
DL21
DL19
152 RESERVED 178
V
SS
V
DD
V
DD
153
154
155
156
CNTEN0
CNTEN1
A27
DH5
DH3
DH2
A12
V
SS
V
DD
A11
A9
DH16
26
DL3
CWE2
V
SS
A24
NOTE: V
and V
must be connected on all modules.
DD
CC
TOP VIEW
90
1
113
114
24
25
136
137
47
48
89
178
MPC2105A•MPC2106A•MPC2105B•MPC2106B
MOTOROLA FAST SRAM
4
PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
Address Inputs – (MSB:0, LSB:28).
66, 67, 68, 69, 71, 72, 73, 74,
76, 77, 78, 80, 81, 82, 83,
155, 156, 157, 158, 160, 161,
162, 163, 165, 166, 167, 169,
170, 171
A0 – A28
Input
62
151
ADDR0
ADDR1
Input
Input
Input
Least significant address bit when asynchronous Data RAMs are used.
Next to least significant address bit when asynchronous Data RAMs are used.
64, 65
ADS0, ADS1
Data RAM Address Strobe – For MPC2105A/B use ADS0 only. For
MPC2106A/B use ADS0, ADS1.
149
172
ALE
Input
Input
Input
Data RAM Address Latch Enable – Use for asynchronous Data RAM only.
Burstmode. 0 = Linear, 1 = Interleaved.
BURSTMODE
59, 60
CG0,
CG1
Data RAM Output Enables – For MPC2105A/B use CG0 only. For
MPC2106A/B use CG0, CG1.
30, 56, 115, 144, 146
153, 154
CLK0 – CLK4
Input
Input
Input
I/O
Clock Inputs – CLK2 is for Tag RAM, CLK0, 1, 3, and 4 are for Data RAMs only.
For MPC2106A/B use all the clocks. For MPC2105A/B use CLK0 – CLK2 only.
CNTEN0,
CNTEN1
Data RAM Count Enables – For MPC2105A/B use CNTEN0 only. For
MPC2106A/B use CNTEN0, CNTEN1.
98, 104, 110, 118,
126, 132, 138, 148
CWE0 – CWE7
Data RAM Write Enables – (MSB:0, LSB:7).
4, 5, 6, 7, 10, 11, 12, 14, 16,
17, 19, 20, 22, 24, 25, 26, 27,
93, 94, 95, 96, 99, 100, 101,
103, 105, 106, 108, 109, 111,
113, 117
DH0 – DH31
High Data Bus – (MSB:0, LSB:31).
88
DIRTYIN
DIRTYOUT
DL0 – DL31
Input
Dirty input bit.
177
Output Dirty output bit.
32, 33, 34, 37, 38, 39, 40, 43,
44, 45, 47, 49, 50, 52, 53, 54,
119, 120, 122, 123, 124, 127,
128, 129, 131, 133, 134, 136,
137, 139, 141, 142
I/O
Low Data Bus – (MSB:0, LSB:31).
9, 15, 21, 28, 35, 42, 48, 58
DP0 – DP7
MATCH
I/O
Data Parity Bits – (MSB:0, LSB:7)
86
Output Tag RAM active high match indication.
2
PD0/IDSCLK
PD1/IDSDATA
PD2, PD3
RESERVED
STANDBY
TCLR
Input
I/O
Presence detect bit 0/EEPROM serial clock. (EEPROM option only).
Presence detect bit 1/EEPROM serial data. (EEPROM option only).
91
3, 92
Output Presence detect bits.
Reserved pin.
63, 152
176
Input
Input
Input
Input
Input
Input
Input
Standby pin. Reduces standby power consumption.
85
Tag RAM clear.
87
TG
Tag RAM output enable.
175
174
TWE
Tag RAM write enable.
VALIDIN
Tag RAM valid bit.
18, 36, 84, 107, 125, 173
V
+ 5 V power supply. Must be connected.
+ 3.3 V power supply. Must be connected.
CC
DD
8, 23, 51, 61, 75, 97, 112,
140, 150, 164
V
1, 13, 29, 31, 41, 46, 55, 57,
70, 79, 89, 90, 102, 114,
116, 121, 130, 135, 143,
145, 147, 159, 168, 178
V
SS
Input
Ground.
MPC2105A•MPC2106A•MPC2105B•MPC2106B
MOTOROLA FAST SRAM
5
DATA RAM MCM69F618A SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)
STANDBY
ADSx
CNTENx
CWEx
CLKx
L–H
L–H
L–H
L–H
L–H
L–H
L–H
Address Used
N/A
Operation
H
L
L
L
X
X
X
L
X
L
Deselected
External Address
External Address
Next Address
Next Address
Current Address
Current Address
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Suspend Burst
Read Cycle, Suspend Burst
L
L
H
L
X
X
X
H
H
H
H
L
H
L
H
H
X
H
NOTES:
1. X means Don’t Care.
2. All inputs except CG must meet set–up and hold times for the low–to–high transition of clock (CLK0 – CLK4).
3. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation
Read
CG
L
I/O Status
Data Out (DQ0 – DQ8)
High–Z
Read
H
Write
X
High–Z — Data In
High–Z
Deselected
X
NOTES:
1. X means Don’t Care.
2. Forawriteoperationfollowingareadoperation, CGmustbehighbeforetheinputdata
required set–up time and held high through the input data hold time.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V
SS
= 0 V)
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
Rating
Power Supply Voltage
Voltage Relative to V
Symbol
Value
Unit
V
CC
– 0.5 to + 7.0
V
V , V
in out
– 0.5 to V
CC
+ 0.5
V
SS
Output Current (per I/O)
Data RAM
Tag
I
± 30
± 20
mA
out
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will
ensure the output devices are in High–Z at
power up.
Power Dissipation
MPC2105A/B
MPC2106A/B
P
4.6
9.2
W
D
Temperature Under Bias
Operating Temperature
Storage Temperature
T
bias
– 10 to + 85
0 to +70
°C
°C
°C
T
A
T
stg
– 55 to + 125
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
MPC2105A•MPC2106A•MPC2105B•MPC2106B
MOTOROLA FAST SRAM
6
DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 5%, V
= 3.3 V ± 10%, T = 0 to + 70°C, Unless Otherwise Noted)
DD A
CC
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to V
Parameter
= 0 V)
SS
Symbol
Min
Max
Unit
Supply Voltage (Operating Voltage Range)
V
CC
V
DD
4.75
3.00
5.25
3.60
V
Input High Voltage
Input Low Voltage
V
2.2
V
DD
+ 0.3**
V
V
IH
V
– 0.5*
0.8
IL
*V (min) = – 0.5 V dc; V (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
IL IL
**V (max) = V
+ 0.3 V dc; V (max) = V
+ 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
IH IH
DD
DD
DC CHARACTERISTICS
Parameter
Input Leakage Current (All Inputs, V = 0 to V
Symbol
Min
Max
Unit
)
Data RAM
Tag
I
lkg(I)
—
± 1.0
± 5.0
µA
in
DD
Output Leakage Current (CG = V , V
IH out
= 0 to V
)
Data RAM
Tag
I
—
± 1.0
± 5.0
µA
DD
lkg(O)
TTL Output Low Voltage (I
= + 8.0 mA)
V
—
0.4
—
V
V
OL
OL
TTL Output High Voltage (I
= – 4.0 mA)
V
OH
2.4
OH
POWER SUPPLY CURRENTS
Parameter
= 0 mA, All Inputs = V and V
= 0.0 V and V ≥ 3.0 V, Cycle Time ≥ 20 ns)
IH
Symbol
Max
Unit
AC Supply Current (CG = V , E = V , I
IH IL out
IL
,
MPC2105A/B
MPC2106A/B
I
900
1800
mA
IL
IH
DDA
V
MPC2105A/B
MPC2106A/B
I
320
640
mA
mA
mA
CCA
AC Standby Current (E = V , I
= 0 mA, All Inputs = V or V
IL
MPC2105A/B
MPC2106A/B
I
(V
)
)
440
880
IH out
IH
SB1 DD
V
IL
= 0.0 V and V ≥ 3.0 V, Cycle Time ≥ 20 ns)
IH
MPC2105A/B
MPC2106A/B
I
(V
320
640
SB1 CC
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T = 25°C, Periodically Sampled Rather Than 100% Tested)
A
Parameter
Symbol
Typ
Max
Unit
Input Capacitance
(A13 – A28)
(Data RAM Control Pins)
(CLK0 – CLK4)
C
—
16
8
15
20
10
5
pF
in
(Tag Control Pins)
—
Tag Output Capacitance
(MATCH, DIRTYOUT)
(DH0 – DH31, DL0 – DL31)
(A0 – A11)
C
out
C
I/O
C
I/O
—
6
7
8
7
pF
pF
pF
Data RAM Input/Output Capacitance
Tag Input/Output Capacitance
—
MPC2105A•MPC2106A•MPC2105B•MPC2106B
MOTOROLA FAST SRAM
7
DATA RAMs AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 5%, V
= 3.3 V ± 10% T = 0 to + 70°C, Unless Otherwise Noted)
DD A
CC
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . See Figure 1a Unless Otherwise Noted
SYNCHRONOUS DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)
MPC2105A/B
MPC2106A/B
Parameter
Symbol
Min
Max
—
9
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Cycle Time
t
15
—
—
6
KHKH
Clock Access Time
t
4
KHQV
Output Enable to Output Valid
Clock High to Output Active
Clock High to Output Change
Output Enable to Output Active
Output Disable to Q High–Z
Clock High to Q High–Z
Clock High Pulse Width
Clock Low Pulse Width
Setup Time
t
5
GLQV
t
t
—
—
—
6
KHQX1
KHQX2
3
t
0
GLQX
GHQZ
t
2
t
—
5
6
KHQZ
t
—
—
—
—
KHKL
KLKH
AVKH
t
5
Address
t
7.5
2.5
5, 6
5
Setup Times:
Address Status
Data In
Write
Address Advance
Chip Enable
t
t
SVKH
DVKH
t
WVKH
t
BAVVKH
t
EVKH
Hold Times:
Address
Address Status
Data In
Write
Address Advance
Chip Enable
t
0.5
—
ns
5
KHAX
t
KHTSX
t
KHDX
t
KHWX
t
KHBAX
t
KHEX
NOTES:
1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW.
2. All read and write cycle timings are referenced from CLK or CG.
3. CG is a don’t care when UW or LW is sampled low.
4. Maximum access times are guaranteed for all possible PowerPC external bus cycles.
5. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of CLK whenever TSP or
TSC is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of
CLK when the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when TSP or TSC is low) to remain
enabled.
6. 5 ns of setup delay is incurred in address buffers.
MPC2105A•MPC2106A•MPC2105B•MPC2106B
MOTOROLA FAST SRAM
8
SYNCHRONOUS DATA RAM READ CYCLE
t
KHKH
CLK1, CLK0
t
t
KHKL
KLKH
ADS0
t
t
KHTSX
TSVKH
t
t
KHAX
AVKH
A(12, 13 – 26)
(See Note 1)
A1
A2
CWE0 –
CWE7
t
KHWX
t
WVKH
t
t
KHEX
EVKH
STANDBY
t
t
KHBAX
BAVKH
CNTEN0
t
KHQV
t
GLQV
CG
t
GLQX
t
t
t
KHQV
KHQZ
GHQZ
t
KHQX1
t
KHQX2
DATA OUT
NOTES:
Q (A2)
Q (A2 + 1)
Q (A2 + 2)
Q (A2 + 3)
Q (A1)
READ
BURST READ
1. Cache addresses used are: 13 – 26 for MPC2105A/B; and 12 – 26 for MPC2106A/B.
2. Q1 (A2) represents the first ouput from the external address A2; Q2 (A2) represents the next output data in the burst sequence with
A2 as the base address.
MPC2105A•MPC2106A•MPC2105B•MPC2106B
MOTOROLA FAST SRAM
9
SYNCHRONOUS DATA RAM WRITE CYCLE
t
KHKH
CLK1, CLK0
t
t
KHKL
KLKH
t
t
t
SVKH
KHTSX
ADS0
t
AVKH
t
KHAX
t
AVKH
KHAX
A1
A2
A(12, 13 – 26)
CWE0 – CWE7
t
t
KHWX
WVKH
t
t
KHEX
EVKH
STANDBY
CNTEN0
t
t
KHBAX
BAVKH
t
t
DVKH
KHDX
DATA IN
D (A2)
D (A2 + 1)
D (A2 + 2)
D (A2 + 3)
D (A1)
SINGLE WRITE
BURST WRITE
NOTES:
1. Cache addresses used are: 13 – 26 for MPC2105A/B; and 12 – 26 for MPC2106A/B.
2. CG0 = V
IH
MPC2105A•MPC2106A•MPC2105B•MPC2106B
MOTOROLA FAST SRAM
10
TAG RAM
RESET FUNCTION TRUTH TABLE (See Notes 1 and 2)
TCLR
CLK
L – H
L – H
TWE
H
TAG0 – TAG11
High–Z
DIRTYOUT
MATCH
(3)
Operation
Reset Status
Not Allowed
POWER
Active
—
(3)
L
L
L
L
L
—
—
—
NOTES:
1. H = V , L = V , X = don‘t care, — = undefined.
IH
IL
2. TG is X for this table.
3. These are output states.
READ FUNCTION TRUTH TABLE (See Notes 1, 2, and 3)
TG
L
TWE
H
CLK
X
TAG0 – TAG11
VALIDIN
DIRTYIN
DIRTYOUT
MATCH
Operation
D
—
—
—
—
D
D
out
Read Tag I/O
out
out
H
X
X
High–Z
—
—
Tag I/O Disable
WRITE FUNCTION TRUTH TABLE (See Notes 1 and 2)
TG
TWE
CLK
L – H
L – H
TAG0 – TAG11
VALIDIN
DIRTYIN
DIRTYOUT
MATCH
Operation
Write Tag I/O
Not Allowed
H
L
L
D
—
—
—
—
—
—
L
in
L
—
—
NOTES:
1. H = V , L = V , X = don‘t care, — = undefined.
IH IL
2. This table applies when RESET and PWRDN are high.
3. D in this case is the same as D . The input data is written through to the outputs during the write operation.
out
in
MATCH FUNCTION TRUTH TABLE (See Notes 1 through 4)
(4)
(4)
TG
X
TWE
X
TAG0 – TAG11
VALIDIN
DIRTYIN
MATCH
Operation
—
—
—
—
—
D
Selected
out
L
L
H
D
Read Tag I/O
out
H
L
D
D
D
in
L
L
Write Tag I/O, Status Bits
Invalid Data – Dedicated Status Bits
Match – Dedicated Status Bits
in
in
H
H
TAG
TAG
L
—
in
in
H
H
H
—
H
NOTES:
1. H = V , L = V , X = don‘t care, — = undefined.
IH IL
2. M = high if TAG equals the memory contents at the address; M = low if TAG does not equal the contents at that address.
in
in
3. PWRDN and RESET are high for this table. GS and CLK are X.
4. This column represents the stored memory cell data for the given status bit at the selected address.
MPC2105A•MPC2106A•MPC2105B•MPC2106B
11
MOTOROLA FAST SRAM
TAG RAM AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 5%, T = 0 to + 70°C, Unless Otherwise Noted)
CC
A
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . Figure 1a Unless Otherwise Noted
TAG RAM READ CYCLE (See Notes 1 through 4)
Tag RAM
Parameter
Clock Access Time
Symbol
Min
—
—
0
Max
10
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
t
KHQV
t
Output Enable to Output Valid
Output Enable to Output Active
Output Disable to Q High–Z
GLQV
t
—
6
GLQX
t
1
GHQZ
t
3
—
10
—
12
Status Bit Hold from Address Change
Address Access Time Status Bits
Tag Bit Hold from Address Change
Address Access Time Tag Bits
AXSX
t
—
3
AVSV
t
AVQX
t
—
AVQV
NOTES:
1. Setup and hold times, W (write) refers to TWE.
2. A read cycle is defined by TWE high. A write cycle is defined by TWE low.
3. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles.
4. Tag reads are asynchronous.
TAG RAM WRITE CYCLE (See Notes 1 through 4)
Tag RAM
Parameter
Symbol
Min
15
Max
—
Unit
ns
t
Cycle Time
KHKH
t
4.5
4.5
1.5
—
ns
Clock High Pulse Width
Clock Low Pulse Width
Clock High to Output Active
Setup Times
KHKL
t
—
ns
KLKH
t
—
ns
KHQX
t
Address
Write
3
—
—
ns
ns
AVKH
t
WVKH
t
Hold Times
Address
Write
1.5
KHAX
t
KHWX
t
0
—
9
ns
ns
Status Output Hold
KHSX
t
—
Clock High to Status Bits Valid
NOTES:
KHSV
1. Setup and hold times, W (write) refers to TWE.
2. A read cycle is defined by TWE high. A write cycle is defined by TWE low.
3. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles.
4. Tag writes are synchronous.
MPC2105A•MPC2106A•MPC2105B•MPC2106B
MOTOROLA FAST SRAM
12
MPC2105A•MPC2106A•MPC2105B•MPC2106B
MOTOROLA FAST SRAM
13
TAG RAM MATCH CYCLE
Tag RAM
Parameter
Symbol
Min
—
—
—
2
Max
7
Unit
ns
t
Clock High Write to MATCH Invalid
Clock High Read to MATCH Valid
Address Valid to MATCH Valid
MATCH Valid Hold from Address Change
TG Low to MATCH Invalid
KHML
t
10
10
—
7
ns
KHMV
t
ns
AVMV
t
ns
AXMX
t
—
—
ns
GLML
t
8
ns
TG High to MATCH Valid
GHMX
TAG RAM RESET (TCLR) CYCLE
Tag RAM
Parameter
TCLR Setup Time
Symbol
Min
4
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
STC
t
1
—
TCLR Hold Time
HTC
t
—
2
60
Status Bit Reset Time
SRST
t
—
Status Bit Hold from TCLR Low
TCLR Low to MATCH Invalid
TCLR High to MATCH Valid
TCLR Low to TAG High–Z
TCLR High to TAG Active
STANDBY Setup to TCLR Low
TCLR High to TWE Low
SHRS
t
—
—
—
—
30
80
10
RSML
t
100
10
RSMV
t
RSQZ
t
100
—
RSQX
t
PDSR
t
—
RHWX
TIMING LIMITS
+5 V
The table of timing values shows either a
minimum or a maximum limit for each param-
eter. Input requirements are specified from
the external system point of view. Thus, ad-
dress setup time is shown as a minimum
since the system must supply at least that
much time. On the other hand, responses
from the memory are specified from the de-
vice point of view. Thus, the access time is
shown as a maximum since the device never
provides data later than that time.
480
Ω
Z
= 50 Ω
0
OUTPUT
OUTPUT
255
50
Ω
Ω
5 pF
V
= 1.5 V
L
(a)
(b)
Figure 1. Test Loads
MPC2105A•MPC2106A•MPC2105B•MPC2106B
MOTOROLA FAST SRAM
14
MPC2105A•MPC2106A•MPC2105B•MPC2106B
MOTOROLA FAST SRAM
15
TAG RAM TCLR FUNCTION
CLK
t
t
HTC
STC
TCLR
t
SRST
t
SHRS
DIRTYOUT
t
t
RHWX
WVKH
TWE
t
RSMV
MATCH
VALID
t
RSQZ*
t
RSQX
A0 – A11
* Transition is measured plus or minus 200 mV from steady state.
MPC2105A•MPC2106A•MPC2105B•MPC2106B
MOTOROLA FAST SRAM
16
ORDERING INFORMATION
(Order by Full Part Number)
MPC
210xx
XX XX
Speed (66 = 66 MHz)
Motorola Memory Prefix
Part Number
Package (SG = Gold Pad SIMM)
Full Part Numbers — MPC2105ASG66
MPC2106ASG66
MPC2105A = 512KB, synchronous, series resistors
MPC2106A = 1MB, synchronous, series resistors
MPC2105B = 512KB, synchronous
MPC2105BSG66
MPC2106BSG66
MPC2106B = 1MB, synchronous
MPC2105A•MPC2106A•MPC2105B•MPC2106B
MOTOROLA FAST SRAM
17
PACKAGE DIMENSIONS
178 LEAD CARD EDGE
MPC2105A/B
CASE 1132A–01
D
M
L
0.006
B
C
A
2X D1
C
E
L
COMPONENT
AREA
A
A5
NOTE 4
2X A1
1
24 25
47 48
89
E1
R
D6
R
NOTE 5
A
E2
B
VIEW A
D5
M
0.016
D7
VIEW A
NOTES 3 AND 6
M
L
0.006
C
B
A
C
D4
D3
2X D2
SIDE VIEW
FRONT VIEW
NOTES:
90
178
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN INCHES.
3. CARD THICKNESS APPLIES ACROSS TABS AND
INCLUDES PLATING AND/OR METALLIZATION.
4. DIMENSIONS E AND A5 DEFINE A
DOUBLE–SIDED MODULE.
COMPONENT
AREA
5. DIMENSION E1 DEFINES OPTIONAL
SINGLE–SIDED MODULE.
6. STRAIGHTNESS CALLOUT APPLIES TO TAB
AREA ONLY.
BACK VIEW
INCHES
DIM
A
MIN
1.190
0.545
0.095
–––
0.195
0.195
0.039
5.055
0.100
0.190
1.255
3.405
1.250 BSC
0.072
0.075
0.050 BSC
0.075 BSC
–––
–––
MAX
1.210
–––
–––
0.010
–––
C
L
A1
A2
A3
A4
A5
b
–––
0.043
5.065
–––
–––
1.265
3.410
1
47
48
D
A4
D1
D2
D3
D4
D5
D6
D7
e
e1
E
E1
E2
A2
A3
178X b
0.076
0.081
e1
L
L
4X
0.006
C B A
86X
e
0.210
0.140
0.070
VIEW A
0.055
MPC2105A•MPC2106A•MPC2105B•MPC2106B
MOTOROLA FAST SRAM
18
178 LEAD CARD EDGE
MPC2106A/B
CASE 1132–01
D
M
L
0.006
B
C
A
E
C
2X D1
A
L
COMPONENT
AREA
A5
NOTE 4
2X A1
1
24 25
47 48
89
E1
R
D6
R
NOTE 5
A
E2
B
VIEW A
D5
M
0.016
D7
VIEW A
NOTES 3 AND 6
M
L
0.006
C
B
A
C
D4
D3
2X D2
SIDE VIEW
FRONT VIEW
NOTES:
90
178
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN INCHES.
3. CARD THICKNESS APPLIES ACROSS TABS AND
INCLUDES PLATING AND/OR METALLIZATION.
4. DIMENSIONS E AND A5 DEFINE A
DOUBLE–SIDED MODULE.
COMPONENT
AREA
5. DIMENSION E1 DEFINES OPTIONAL
SINGLE–SIDED MODULE.
6. STRAIGHTNESS CALLOUT APPLIES TO TAB
AREA ONLY.
BACK VIEW
INCHES
DIM
A
MIN
MAX
1.410
–––
–––
0.010
–––
1.390
0.545
0.095
–––
0.195
0.195
0.039
5.055
0.100
0.190
1.255
3.405
1.250 BSC
0.072
0.075
0.050 BSC
0.075 BSC
–––
–––
C
L
A1
A2
A3
A4
A5
b
–––
0.043
5.065
–––
–––
1.265
3.410
1
47
48
D
A4
D1
D2
D3
D4
D5
D6
D7
e
e1
E
E1
E2
A2
A3
178X b
0.076
0.081
e1
L
L
4X
0.006
C B A
e
86X
0.210
0.140
0.070
VIEW A
0.055
MPC2105A•MPC2106A•MPC2105B•MPC2106B
MOTOROLA FAST SRAM
19
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
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How to reach us:
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MPC2105A/D
◊
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