MPC2106SG66 [MOTOROLA]
256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms; 256KB和512KB BurstRAM二级缓存模块用于PowerPC准备/ CHRP平台
| 型号： | MPC2106SG66 |
| 厂家： | 
MOTOROLA |
| 描述： | 256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms |
| 文件： | 总24页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document
by MPC2104/D
SEMICONDUCTOR TECHNICAL DATA
MPC2104
Advance Information
MPC2105
MPC2106
MPC2107
256KB and 512KB BurstRAM
Secondary Cache Modules for
PowerPC PReP/CHRP Platforms
The MPC2104/5/6/7 are designed to provide burstable, high performance L2
cache for the PowerPC 60x microprocessor family in conformance with the
PowerPC Reference Platform (PReP) and the PowerPC Common Hardware
Reference Platform (CHRP) specifications. These products utilize synchronous or
asynchronous data RAMs.
The MPC2104, MPC2105, and MPC2106 utilize synchronous BurstRAMs.
The modules are configured as 32K x 72, 64K x 72, and 128K x 72 bits in a 182
(91 x 2) pin DIMM format. The MPC2104 uses four of Motorola’s 5 V 32K x 18;
the MPC2105 uses four of the 5 V 64K x 18; the MPC2106 uses eight of the
5 V 64K x 18. For tag bits, a 5 V cache tag RAM configured as 16K x 12 for tag field
plus 16K x 2 for valid and dirty status bits is used.
Bursts can be initiated with the ADS signal. Subsequent burst addresses are
generated internal to the BurstRAM by the CNTEN signal.
Write cycles are internally self timed and are initiated by the rising edge of the
clock (CLKx) inputs. Eight write enables are provided for byte write control.
The MPC2107 utilizes asynchronous data RAMs. The module is configured as
32K x 64 in the same 182 pin DIMM format. Again, 5 V cache tag RAMs configured
as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits are used. Burst
capability is provided in that two burst addresses bypass the address latch.
Presence detect pins are available for auto configuration of the cache con-
trol. A serial EEPROM is optional to provide more in–depth description of the
cachemodule. This EEPROMwillbeavailableonfuturerevisionsofthemodule
family.
The module family pinout will support 5 V and 3.3 V components for a clear
path to lower voltage and power savings. Both power supplies must be connected.
All of these cache modules are plug and pin compatible with each other.
•
•
•
•
•
•
•
•
•
PowerPC–style Burst Counter on Chip (MPC2104/5/6)
Flow–Through Data I/O (MPC2104/5/6)
Plug and Pin Compatibility of entire Module Family
Multiple Clock Pins for Reduced Loading
All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible (MPC2104/5/6)
Three State Outputs
Byte Write Capability
Fast Module Clock Rates: Up to 66 MHz
Fast SRAM Access Times: 10 ns for Tag RAM Match
9 ns for Data RAM (MPC2104/5/6)
15 ns for Data RAM (MPC2107)
•
•
•
•
Decoupling Capacitors for Each Fast Static RAM
High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes
182 Pin Card Edge Module
Burndy Connector, Part Number: ELF182JSC–3Z50
BurstRAM is a trademark of Motorola.
PowerPC is a trademark of International Business Machines Corp.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
11/8/95
Motorola, Inc. 1995
V
92
93
94
1
2
3
V
SS
SS
PD1/IDSDATA
PD3
PD0/IDSCLK
PD2
PIN ASSIGNMENT
182–LEAD DIMM
DH31
DH29
95
96
4
5
DH30
DH28
TOP VIEW – CASE TBD
DH27
DH25
97
98
6
7
DH26
DH24
V
3
99
8
9
V
3
CC
CC
DP3
CWE3
DH23
DH21
DH18
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
DH22
DH20
DH19
V
DH17
DP2
DH15
DH12
V
DH11
DH9
DP1
DH7
V
SS
SS
DH16
CWE2
DH14
DH13
V
DH10
DH8
CWE1
DH6
V
5
5
CC
CC
3
DH4
V
3
CC
CC
DH5
DH3
DH2
DH0
DP0
V
CLK1
VSS
DL28
DL26
DL24
DP7
V
SS
CLK0
V
SS
DH1
CWE0
DL31
SS
DL30
V
SS
DL29
DL27
DL25
V
5
V
5
CC
CC
CWE7
DL23
DL21
DL19
DL22
DL20
DL18
DL16
V
DP6
V
SS
SS
DL17
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
DL14
DL12
DL11
CWE6
DL15
DL13
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
V
V
DL10
DL8
SS
SS
DL9
DP5
DL7
DL4
CWE5
DL6
V
3
V
3
DL5
DL2
CC
CC
DL3
DL1
DL0
V
CLK3
SS
V
CLK2
SS
V
CLK4
SS
V
DP4
SS
V
SS
COE0
COE1
CWE4
ALE
V
3
V
3
CC
CC
ADDR0
RESERVED
ADS0
ADDR1
RESERVED
CNTEN0
ADS1
CNTEN1
V
V
5
5
V
V
5
5
CC
CC
CC
CC
A28
A26
A25
A23
A27
A24
A22
A20
V
V
A18
SS
SS
A21
A19
A17
A13
A16
A15
A14
V
3
V
3
A10
A8
CC
CC
A12
A11
A9
A6
V
V
SS
SS
A7
A5
A3
A0
A4
A2
A1
BURSTMODE
V
TCLR
5
V
5
CC
CC
NOTES:
VALIDIN
TWE
MATCH
TOE
DIRTYIN
1. V 5 and V 3 must be connected on all modules.
CC CC
STANDBY
DIRTYOUT
V
V
SS
SS
MPC2104•MPC2105•MPC2106•MPC2107
MOTOROLA FAST SRAM
2
MPC2104/MPC2105 BLOCK DIAGRAM
MCM67Mx18
A28
A27
A0
CLK3
CLK4
ALE
ADS1
CNTEN1 = NC
COE1
ADDR0
ADDR1
PD2
= NC
= NC
= NC
= NC
CLK0
K
DQ0 – DQ8
DQ9 – DQ17
LW
A1
DH0 – DH7 + DP0
DH8 – DH15 + DP1
CWE0
A14 – A26
A13
A2 – A14
A15
’244
ADS0
TSC
BAA
G
= NC
= NC
= NC
= NC
CWE1
UW
CNTEN0
COE0
STANDBY
E
PD3
V
5 via 100 Ω
TSP
CC
J4
MCM67Mx18
A0
A1
CLK0
K
DQ0 – DQ8
DQ9 – DQ17
LW
DH16 – DH23 + DP2
DH24 – DH31 + DP3
CWE2
A2 – A14
A15
TSC
BAA
G
CWE3
UW
X24C00
(OPTIONAL)
PD0/IDSCLK PD1/IDSDATA
E
SCL
SDA
J2
TSP
J3
MCM67Mx18
A0
A1
CLK1
K
DQ0 – DQ8
DQ9 – DQ17
LW
DL0 – DL7 + DP4
DL8 – DL15 + DP5
CWE4
A2 – A14
A15
TSC
BAA
G
CWE5
UW
E
TSP
MCM67Mx18
A0
A1
CLK1
K
DQ0 – DQ8
DQ9 – DQ17
LW
DL16 – DL23 + DP6
DL24 – DL31 + DP7
CWE6
A2 – A14
A15
TSC
BAA
G
CWE7
UW
256KB
512KB
EEPROM EEPROM
E
256KB
no stuff
no stuff
no stuff
no stuff
512KB
0 Ω
no stuff
no stuff
no stuff
no stuff
TSP
J5
J4
J3
J2
J1
J0
no stuff
0
0
0
Ω
Ω
Ω
0
0
0
0
Ω
Ω
Ω
Ω
no stuff
no stuff
0
Ω
TAG: 16K x 12 + V + D
no stuff
0
Ω
no stuff
0 Ω
J1
J0
A13
TT1, WTD, E1
V
SS
A14 – A26
A2 – A12
A0 – A12
TDQ0 – TDQ10
TDQ11
SFUNC, SG
TAG, TAD, E2
TAH, PWRDN
MATCH
V
5 via 100 Ω
CC
J5
A1
TCLR
TWE
RESET
MATCH
SW
TW
DIRTYQ
DIRTYOUT
V
V
3
CCQ
CC
CLK2
VALIDIN
DIRTYIN
K
VALIDQ
WTQ
NC
NC
VALIDD
DIRTYD
TG
TOE
Note: MPC2104 utilizes 32K x 18 BurstRAMs. MPC2105 utilizes 64K x 18 BurstRAMs.
MPC2104•MPC2105•MPC2106•MPC2107
MOTOROLA FAST SRAM
3
MPC2106 BLOCK DIAGRAM
64K X 18 BURST
A13 – A28
’244
PAL
A0 – A15
TSC
BAA
CLK0
K
DQ0 – DQ8
DQ9 – DQ17
LW
ADS0
CNTEN0
COE0
DH0 – DH7 + DP0
DH8 – DH15 + DP1
CWE0
G
X24C00
PA12
(OPTIONAL)
CWE1
A12
UW
E
PD0/IDSCLK PD1/IDSDATA
J0
SCL
SDA
STANDBY
64K X 18 BURST
PA12L
CLK1
K
A0 – A15
DH16 – DH23 + DP2
DH24 – DH31 + DP3
CWE2
TSC
BAA
G
DQ0 – DQ8
DQ9 – DQ17
LW
CWE3
E
UW
TAG: 16K x 12 + V + D
14
A13 – A26
A0 – A11
A0 – A13
TT1, WTD
SFUNC, SG
TAH, TAG, TAD
V
V
SS
64K X 18 BURST
TDQ0 – TDQ11
RESET
SW
TW
K
5
CC
A0 – A15
TCLR
CLK3
K
DQ0 – DQ8
DQ9 – DQ17
LW
via 100
Ω
DL0 – DL7 + DP4
TSC
BAA
G
PWRDN
MATCH
DIRTYQ
TWE
MATCH
DIRTYOUT
DL8 – DL15 + DP5
CWE4
CLK2
VALIDIN
DIRTYIN
TOE
VALIDD
DIRTYD
TG
CWE5
E
UW
V
V
3
CCQ
CC
TA, VALIDQ
NC
NC
64K X 18 BURST
A0 – A15
WTQ
A12
V
E1
E2
CLK4
K
DL16 – DL23 + DP6
DL24 – DL31 + DP7
CWE6
DD
DQ0 – DQ8
DQ9 – DQ17
LW
TSC
BAA
G
CWE7
UW
E
TAG: 16K x 12 + V + D
A13 – A26
A0 – A11
A0 – A13
TDQ0 – TDQ11
RESET
TT1, WTD
V
SS
64K X 18 BURST
SFUNC, SG
TAH, TAG, TAD
PWRDN
V
5
CC
via 100
TCLR
CLK0
K
A0 – A15
Ω
DH0 – DH7 + DP0
DH8 – DH15 + DP1
CWE0
SW
DQ0 – DQ8
DQ9 – DQ17
LW
ADS1
CNTEN1
COE1
TWE
TSC
BAA
G
MATCH
DIRTYQ
MATCH
DIRTYOUT
TW
K
VALIDD
CLK2
VALIDIN
DIRTYIN
TOE
CWE1
UW
V
3
E
V
CC
CCQ
DIRTYD
TG
NC
NC
TA, VALIDQ
WTQ
64K X 18 BURST
V
A12
E1
E2
CLK1
SS
A0 – A15
K
DQ0 – DQ8
DQ9 – DQ17
LW
DH16 – DH23 + DP2
DH24 – DH31 + DP3
CWE2
TSC
BAA
G
CWE3
E
UW
ALE
= NC
64K X 18 BURST
ADDR0
ADDR1
PD2
= NC
= NC
= NC
A0 – A15
CLK3
K
DQ0 – DQ8
DQ9 – DQ17
LW
DL0 – DL7 + DP4
DL8 – DL15 + DP5
CWE4
TSC
BAA
G
PD3
J1
CWE5
E
UW
64K X 18 BURST
A0 – A15
CLK4
K
DL16 – DL23 + DP6
DL24 – DL31 + DP7
CWE6
DQ0 – DQ8
DQ9 – DQ17
LW
TSC
BAA
G
1M
EEPROM 1M
no stuff
no stuff
J1
J0
0
0
Ω
Ω
CWE7
UW
E
Note: All 64K X 18 TSP signals are tied to V
via a 100 Ω resistor. Edge connector A28 connects to the 64K x 18 A0; edge
CC
connector A27 connects to the 64K x 18 A1.
MPC2104•MPC2105•MPC2106•MPC2107
MOTOROLA FAST SRAM
4
MPC2107 BLOCK DIAGRAM
MCM6206
ADDR0
ADDR1
A0
A1
A14 – A26
’373
A2 – A14
DH0 – DH7
CWE0
DQ0 – DQ7
W
ALE
COE0
X24C00
(OPTIONAL)
G
E
PD0/IDSCLK PD1/IDSDATA
STANDBY
SCL
SDA
J2
MCM6206
A0
A1
J3
A2 – A14
DH8 – DH15
CWE1
DQ0 – DQ7
W
G
E
MCM6206
A0
A1
A2 – A14
DH16 – DH23
CWE2
DQ0 – DQ7
W
G
E
TAG: 16K x 12 + V + D
V
A13
MCM6206
SS
13
A0
A1
A14 – A26
A2 – A13
A0 – A12
TDQ0 – TDQ11
RESET
SW
TT1, WTD, E1
V
SS
SFUNC, SG
TAH, TAG, TAD
E2, PWRDN
MATCH
V
5
CC
via 100
A2 – A14
TCLR
TWE
DH24 – DH31
CWE3
Ω
DQ0 – DQ7
W
MATCH
G
E
TW
CLK2
VALIDIN
DIRTYIN
TOE
DIRTYQ
DIRTYOUT
K
VALIDD
DIRTYD
TG
V
3
V
CC
CCQ
MCM6206
NC
TA, VALIDQ
A0
A1
WTQ
NC
A2 – A14
DL0 – DL7
CWE4
DQ0 – DQ7
W
G
E
COE1
MCM6206
CLK0, 1, 3, 4
ADS0, ADS1
= NC
= NC
A0
A1
CNTEN0, CNTEN1 = NC
A2 – A14
A27, A28
DP0 – DP7
BURSTMODE
PD2
= NC
= NC
= NC
DL8 – DL15
CWE5
DQ0 – DQ7
W
G
E
PD3
= NC
MCM6206
J1
A0
A1
A2 – A14
DL16 – DL23
CWE6
DQ0 – DQ7
W
G
E
256KB
EEPROM 256KB
no stuff
no stuff
J3
J2
J1
0
0
0
Ω
Ω
Ω
MCM6206
A0
A1
no stuff
A2 – A14
DL24 – DL31
CWE7
DQ0 – DQ7
W
G
E
MPC2104•MPC2105•MPC2106•MPC2107
MOTOROLA FAST SRAM
5
PIN DESCRIPTIONS
Pin Locations
Symbol
Type
Description
Address Inputs – (MSB:0, LSB:28)
68, 69, 70, 71, 73, 74, 75, 76,
78, 79, 80, 82, 83, 84, 85,
159, 160, 161, 162, 164, 165,
166, 167, 169, 170, 171, 173,
174, 175
A0 – A28
Input
62
153
ADDR0
ADDR1
Input
Input
Input
Least significant address bit when asynchronous Data RAMs are used.
Next to least significant address bit when asynchronous Data RAMs are used.
30, 56, 117, 146, 148
CLK0 – CLK4
Clock Inputs – CLK2 is for Tag RAM, CLK0, 1, 3, and 4 are for Data RAMs only.
For MPC2106 use all the clocks. For MPC2104 or MPC2105 use CLK0–CLK2
only. For MPC2107 use CLK2 only.
4, 5, 6, 7, 10, 11, 12, 14, 16,
17, 19, 20, 22, 24, 25, 26, 27,
95, 96, 97, 98, 101, 102, 103,
105, 107, 108, 110, 111, 113,
115, 119
DH0 – DH31
DL0 – DL31
I/O
I/O
I/O
High Data Bus – (MSB:0, LSB:31)
Low Data Bus – (MSB:0, LSB:31)
Data Parity Bits – (MSB:0, LSB:7)
32, 33, 34, 37, 38, 39, 40, 43,
44, 45, 47, 49, 50, 52, 53, 54,
121, 122, 124, 125, 126, 129,
130, 131, 133, 135, 136, 138,
139, 141, 143, 144
9, 15, 21, 28, 35, 42, 48, 58
DP0 – DP7
PD2, PD3
3, 94
2
Output Presence detect bits.
PD0/IDSCLK
PD1/IDSDATA
ADS0, ADS1
Input
I/O
Presence detect bit 0/EEPROM serial clock. (EEPROM option only.)
93
Presence detect bit 1/EEPROM serial data. (EEPROM option only.)
64, 65
Input
Data RAM Address Strobe – For MPC2104 or MPC2105 use ADS0 only. For
MPC2106 use ADS0, ADS1.
151
ALE
Input
Input
Data RAM Address Latch Enable – Use for asynchronous Data RAM only.
155, 156
CNTEN0,
CNTEN1
Data RAM Count Enables – For MPC2104 or MPC2105 use CNTEN0 only. For
MPC2106 use CNTEN0, CNTEN1.
59, 60
COE0,
COE1
Input
Input
Input
Data RAM Output Enables – For MPC2104 or MPC2105 use COE0 only. For
all others use COE0, COE1.
100, 106, 112, 120,
128, 134, 140, 150
CWE0 – CWE7
Data RAM Write Enables – (MSB:0, LSB:7)
87
TCLR
MATCH
Tag RAM clear.
88
178
Output Tag RAM active high match indication.
VALIDIN
TWE
Input
Input
Input
Input
Tag RAM valid bit.
Tag RAM write enable.
Tag RAM output enable.
Dirty input bit.
179
89
TOE
90
DIRTYIN
DIRTYOUT
STANDBY
RESERVED
181
Output Dirty output bit.
180
Input
Standby pin. Reduces standby power consumption.
176, 63, 154
Reserved pin.
8, 23, 51, 61, 77, 99, 114,
142, 152, 168
V
3
Input
Input
Input
+ 3.3 V power supply. Must be connected.
CC
18, 36, 66, 67, 86, 109, 127,
157, 158, 177
V
CC
5
+ 5 V power supply. Must be connected.
Ground
1, 13, 29, 31, 41, 46, 55, 57,
72, 81, 91, 92, 104, 116,
118, 123, 132, 137, 145,
147, 149, 163, 172, 182
V
SS
176
BURSTMODE
Input
Burstmode. 0 = Linear, 1 = Interleaved.
MPC2104•MPC2105•MPC2106•MPC2107
MOTOROLA FAST SRAM
6
DATA RAM MCM67M518, MCM67M618 SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)
STANDBY
ADS0
CNTEN0
CWEx
CLKx
L–H
L–H
L–H
L–H
L–H
L–H
L–H
Address Used
N/A
Operation
H
L
L
L
X
X
X
L
X
L
Deselected
External Address
External Address
Next Address
Next Address
Current Address
Current Address
Write Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Suspend Burst
Read Cycle, Suspend Burst
L
L
H
L
X
X
X
H
H
H
H
L
H
L
H
H
X
H
NOTES:
1. X means Don’t Care.
2. All inputs except COE must meet set–up and hold times for the low–to–high transition of clock (CLK0 – CLK4).
3. Wait states are inserted by suspending burst.
ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
Operation
Read
COE
L
I/O Status
Data Out (DQ0 – DQ8)
High–Z
Read
H
Write
X
High–Z — Data In
High–Z
Deselected
X
NOTES:
1. X means Don’t Care.
2. For a write operation following a read operation, COE must be high before the input
data required set–up time and held high through the input data hold time.
DATA RAM MCM6206 ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)
STANDBY
COE0, COE1
CWE0 – CWE7
Operation
Deselected
Output Disabled
Read
I/O Status
High–Z
H
L
L
L
X
H
L
X
H
H
L
High–Z
Data Out
High–Z
X
Write
NOTES:
1. X means Don’t Care.
2. For a write operation following a read operation, COE0, and COE1 must be high before the input data required set–up time, and held high
through the input data hold time.
ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V
SS
= 0 V)
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
Rating
Power Supply Voltage
Voltage Relative to V
Symbol
Value
Unit
V
CC
– 0.5 to + 7.0
V
V , V
in out
– 0.5 to V
CC
+ 0.5
V
SS
Output Current (per I/O)
Data RAM
Tag
I
± 30
± 20
mA
out
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will
ensure the output devices are in High–Z at
power up.
Power Dissipation
P
8.1
W
°C
°C
°C
D
Temperature Under Bias
Operating Temperature
Storage Temperature
T
bias
– 10 to + 85
0 to +70
T
A
T
stg
– 55 to + 125
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
MPC2104•MPC2105•MPC2106•MPC2107
MOTOROLA FAST SRAM
7
DC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 5%, T = 0 to + 70°C, Unless Otherwise Noted)
CC
A
RECOMMENDED OPERATING CONDITIONS (Voltages referenced to V
= 0 V)
SS
Parameter
Supply Voltage (Operating Voltage Range)
Input High Voltage
Symbol
Min
4.75
2.2
Max
Unit
V
V
CC
5.25
V
IH
V
+ 0.3**
V
CC
Input Low Voltage
V
IL
– 0.5*
0.8
V
*V (min) = – 0.5 V dc; V (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
IL IL
**V (max) = V
+ 0.3 V dc; V (max) = V
+ 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
IH IH
CC
CC
DC CHARACTERISTICS
Parameter
Input Leakage Current (All Inputs, V = 0 to V
Symbol
Min
Max
Unit
)
Data RAM
Tag
I
lkg(I)
—
± 1.0
± 5.0
µA
in
CC
Output Leakage Current (COE = V , V
IH out
= 0 to V
)
Data RAM
Tag
I
—
± 1.0
± 5.0
µA
CC
lkg(O)
TTL Output Low Voltage (I
= + 8.0 mA)
V
—
0.4
—
V
V
OL
OL
TTL Output High Voltage (I
= – 4.0 mA)
V
OH
2.4
OH
POWER SUPPLY CURRENTS
Parameter
= 0 mA, All Inputs = V and V
= 0.0 V and V ≥ 3.0 V, Cycle Time ≥ 20 ns)
IH
Symbol
Max
Unit
AC Supply Current (COE = V , E = V , I
IH IL out
IL
,
I
CCA
mA
IL
IH
V
MPC2104
MPC2105
MPC2106
MPC2107
1480
1420
2840
1400
AC Standby Current (E = V , I
= 0 mA, All Inputs = V or V
IL
,
I
SB1
mA
IH out
IH
V
IL
= 0.0 V and V ≥ 3.0 V, Cycle Time ≥ 20 ns)
MPC2104
MPC2105
MPC2106
MPC2107
620
700
1400
960
IH
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T = 25°C, Periodically Sampled Rather Than 100% Tested)
A
Parameter
Symbol
Typ
Max
Unit
Input Capacitance
(A13 – A28)
(Data RAM Control Pins)
(CLK0 – CLK4)
C
—
16
8
15
20
10
5
pF
in
(Tag Control Pins)
—
Tag Output Capacitance
(MATCH, DIRTYOUT)
(DH0 – DH31, DL0 – DL31)
(A0 – A11)
C
out
C
I/O
C
I/O
—
6
7
8
7
pF
pF
pF
Data RAM Input/Output Capacitance
Tag Input/Output Capacitance
—
MPC2104•MPC2105•MPC2106•MPC2107
MOTOROLA FAST SRAM
8
DATA RAMs AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 5% T = 0 to + 70°C, Unless Otherwise Noted)
CC
A
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted
SYNCHRONOUS DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 7)
MPC2104
MPC2105
MPC2106
Parameter
Symbol
Min
15
—
—
6
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Cycle Time
t
—
9
KHKH
Clock Access Time
t
4
KHQV
Output Enable to Output Valid
Clock High to Output Active
Clock High to Output Change
Output Enable to Output Active
Output Disable to Q High–Z
Clock High to Q High–Z
Clock High Pulse Width
Clock Low Pulse Width
Setup Time
t
5
GLQV
t
t
—
—
—
6
KHQX1
KHQX2
3
t
0
GLQX
t
2
GHQZ
t
—
5
6
KHQZ
t
—
—
—
—
KHKL
KLKH
AVKH
t
5
Address
t
7.5
2.5
5, 6
5
Setup Times:
Address Status
Data In
Write
Address Advance
Chip Enable
t
t
SVKH
DVKH
t
WVKH
t
BAVVKH
t
EVKH
Hold Times:
Address
Address Status
Data In
Write
Address Advance
Chip Enable
t
0.5
—
ns
5
KHAX
t
KHTSX
t
KHDX
t
KHWX
t
KHBAX
t
KHEX
NOTES:
1. In setup and hold times, W (write) refers to either one or both byte write enables LW and UW.
2. All read and write cycle timings are referenced from CLK or COE.
3. COE is a don’t care when UW or LW is sampled low.
4. Maximum access times are guaranteed for all possible PowerPC external bus cycles.
5. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of CLK whenever TSP or
TSC is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of
CLK when the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when TSP or TSC is low) to remain
enabled.
6. 5 ns of set–up delay is incurred in address buffers.
7. Applies to MPC2104, MPC2105, and MPC2106.
MPC2104•MPC2105•MPC2106•MPC2107
MOTOROLA FAST SRAM
9
SYNCHRONOUS DATA RAM READ CYCLE
t
KHKH
CLK1,
CLK0
t
t
KHKL
KLKH
ADS0
t
t
KHTSX
TSVKH
t
AVKH
t
KHAX
A(12, 13,
14 – 26)
A1
A2
(See Note 1)
CWE0 –
CWE7
t
KHWX
t
WVKH
t
EVKH
t
KHEX
STANDBY
t
t
KHBAX
BAVKH
CNTEN0
COE
t
KHQV
t
GLQV
t
GLQX
t
t
t
KHQV
KHQZ
GHQZ
t
KHQX1
t
KHQX2
DATA OUT
NOTES:
Q (A2)
Q (A2 + 1)
Q (A2 + 2)
Q (A2 + 3)
Q (A1)
READ
BURST READ
1. Cache addresses used are: 14 – 26 for MPC2104 and MPC2107; 13 – 26 for MPC2105; and 12 – 26 for MPC2106.
2. Q1 (A2) represents the first ouput from the external address A2; Q2 (A2) represents the next output data in the burst sequence with
A2 as the base address.
MPC2104•MPC2105•MPC2106•MPC2107
MOTOROLA FAST SRAM
10
SYNCHRONOUS DATA RAM WRITE CYCLE
t
KHKH
CLK1,
CLK0
t
t
KHKL
KLKH
t
t
t
t
SVKH
KHTSX
ADS0
t
AVKH
t
KHAX
AVKH
KHAX
A(12, 13,
14 – 26)
A1
A2
t
t
KHWX
WVKH
CWE0 –
CWE7
t
t
KHEX
EVKH
STANDBY
CNTEN0
t
t
t
BAVKH
KHBAX
t
DVKH
KHDX
DATA IN
D (A2)
D (A2 + 1)
D (A2 + 2)
D (A2 + 3)
D (A1)
SINGLE WRITE
BURST WRITE
NOTES:
1. Cache addresses used are: 14 – 26 for MPC2104 and MPC2107; 13 – 26 for MPC2105; and 12 – 26 for MPC2106.
2. COE0 = V
IH
MPC2104•MPC2105•MPC2106•MPC2107
MOTOROLA FAST SRAM
11
AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 5% T = 0 to + 70°C, Unless Otherwise Noted)
CC
A
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . See Figure 1A Unless Otherwise Noted
ASYNCHRONOUS DATA RAMs READ CYCLE TIMING (See Notes 1 and 8)
MPC2107–15
Parameter
Symbol
Min
Max
—
15
15
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Cycle Time
t
15
—
—
—
4
2
AVAV
Address Access Time
t
AVQV
Enable Access Time
t
3
ELQV
GLQV
AXQX
Output Enable Access Time
Output Hold from Address Change
Enable Low to Output Active
Enable High to Output High–Z
Output Enable Low to Output Active
Output Enable High to Output High–Z
Power Up Time
t
t
—
—
8
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
t
4
ELQX
EHQZ
GLQX
GHQZ
t
t
0
0
—
7
t
0
t
t
0
—
15
ELICCH
EHICCL
Power Down Time
—
NOTES:
1. W is high for read cycle.
2. All timings are referenced from the last valid address to the first transitioning address.
3. Addresses valid prior to or coincident with E going low.
4. Atanygivenvoltageandtemperature,t
and from device to device.
(max)islessthant
EHQZ
(min),andt
ELQX
(max)islessthant
GHQZ
(min),bothforagivendevice
GLQX
5. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B.
6. This parameter is sampled and not 100% tested.
7. Device is continuously selected (E = V , COE0 = V ).
IL IL
8. Applies to MPC2107.
MPC2104•MPC2105•MPC2106•MPC2107
MOTOROLA FAST SRAM
12
ASYNCHRONOUS READ CYCLE 1 (See Note 7)
t
AVAV
A (ADDRESS)
Q (DATA OUT)
t
AXQX
PREVIOUS DATA VALID
DATA VALID
t
AVQV
ASYNCHRONOUS READ CYCLE 2 (See Note 3)
t
AVAV
A (ADDRESS)
t
AVQV
t
ELQV
E (CHIP ENABLE)
t
EHQZ
t
ELQX
G (OUTPUT ENABLE)
t
t
GHQZ
GLQV
t
GLQX
HIGH–Z
HIGH–Z
Q (DATA OUT)
DATA VALID
t
ELICCH
t
EHICCL
V
SUPPLY
CC
CURRENT
MPC2104•MPC2105•MPC2106•MPC2107
MOTOROLA FAST SRAM
13
ASYNCHRONOUS DATA RAMs WRITE CYCLE 1 (See Notes 1 and 2)
MPC2107–15
Parameter
Symbol
Min
Max
—
Unit
ns
Notes
Write Cycle Time
t
15
0
3
AVAV
Address Set–up Time
Address Valid to End of Write
Write Pulse Width
t
—
ns
AVWL
t
12
12
—
ns
AVWH
t
—
ns
WLWH
t
WLEH
Write Pulse Width, G High
t
t
10
—
ns
4
WLWH
WLEH
DVWH
WHDX
Data Valid to End of Write
Data Hold Time
t
t
7
0
0
5
0
—
—
7
ns
ns
ns
ns
ns
Write Low to Output High–Z
Write High to Output Active
Write Recovery Time
NOTES:
t
5,6,7
5,6,7
WLQZ
WHQX
t
—
—
t
WHAX
1. A write occurs during the overlap of E low and W low.
2. If E goes low coincident with or after W goes low, the output will remain in a high impedance state.
3. All timings are referenced from the last valid address to the first transitioning address.
4. If E ≥ V , the output will remain in a high impedance state.
IH
5. At any given voltage and temperature, t
(max) is less than t
(min), both for a given device and from device to device.
WHQX
WLQZ
6. Transition is measured ±500 mV from steady–state voltage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
ASYNCHRONOUS WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)
t
AVAV
A (ADDRESS)
t
t
WHAX
AVWH
E (CHIP ENABLE)
t
WLEH
t
WLWH
W (WRITE ENABLE)
t
t
t
WHDX
DVWH
AVWL
D (DATA IN)
DATA VALID
HIGH–Z
t
WLQZ
HIGH–Z
Q (DATA OUT)
t
WHQX
MPC2104•MPC2105•MPC2106•MPC2107
MOTOROLA FAST SRAM
14
ASYNCHRONOUS DATA RAMs WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)
MPC2107–15
Parameter
Symbol
Min
Max
—
Unit
ns
Notes
Write Cycle Time
t
15
0
0
AVAV
Address Setup Time
Address Valid to End of Write
Enable to End of Write
t
—
ns
AVEL
t
12
10
—
ns
AVEH
t
—
ns
3, 4
ELEH
t
ELWH
Data Valid to End of Write
Data Hold Time
t
7
0
0
—
—
—
ns
ns
ns
DVEH
EHDX
t
Write Recovery Time
NOTES:
t
EHAX
1. A write occurs during the overlap of E low and W low.
2. All timings are referenced from the last valid address to the first transitioning address.
3. If E goes low coincident with or after W goes low, the output will remain in a high impedance state.
4. If E goes high coincident with or before W goes high, the output will remain in a high impedance state.
ASYNCHRONOUS WRITE CYCLE 2 (E Controlled, See Note 1)
t
AVAV
A (ADDRESS)
t
AVEH
E (CHIP ENABLE)
t
t
ELEH
ELWH
t
t
EHAX
AVEL
t
WLEH
W (WRITE ENABLE)
t
t
EHDX
DVEH
D (DATA IN)
DATA VALID
HIGH–Z
Q (DATA OUT)
MPC2104•MPC2105•MPC2106•MPC2107
MOTOROLA FAST SRAM
15
TAG RAM
RESET FUNCTION TRUTH TABLE (See Notes 1 and 2)
TCLR
CLK
L – H
L – H
TWE
H
TAG
High–Z
—
VLD
out
DTY
out
WT
MATCH
(3)
TA
High–Z
—
Operation
Reset Status
Not Allowed
POWER
Active
—
out
(3)
L
(3)
L
(3)
L
L
L
L
L
—
—
—
—
NOTES:
1. H = V , L = V , X = don‘t care, — = unrelated.
IH IL
2. TOE is X for this table.
READ FUNCTION TRUTH TABLE (See Notes 1, 2, and 3)
TOE
L
TWE
H
CLK
X
TAG
VLD
DTY
WT
in
VLD
out
DTY
out
WT
out
MATCH
Operation
in
in
D
—
—
—
—
—
—
—
D
Read Tag I/O
OUT
OUT
—
H
X
X
High–Z
—
—
—
—
—
Tag I/O Disable
WRITE FUNCTION TRUTH TABLE (See Notes 1 and 2)
TOE
TWE
CLK
L – H
L – H
TAG
VLD
—
DTY
—
WT
in
VLD
out
DTY
WT
MATCH
Operation
Write Tag I/O
Not Allowed
in
in
out
out
H
L
L
D
—
—
D
D
D
L
IN
OUT
—
OUT
—
OUT
—
L
—
—
—
—
NOTES:
1. H = V , L = V , X = don‘t care, — = unrelated.
IH IL
2. This table applies when RESET and PWRDN are high.
3. D in this case is the same as D . The input data is written through to the outputs during the write operation.
OUT
IN
MATCH FUNCTION TRUTH TABLE (See Notes 1 through 4)
(4)
VLD
(4)
DTY
(4)
WT
TOE
X
TWE
X
TAG
MATCH
Operation
—
—
—
—
—
—
D
Selected
OUT
L
L
H
D
—
Read Tag I/O
OUT
H
L
D
D
D
D
IN
L
L
Write Tag I/O, Status Bits
Invalid Data – Dedicated Status Bits
Match – Dedicated Status Bits
IN
IN
IN
H
H
TAG
TAG
L
—
—
—
—
IN
IN
H
H
H
M
NOTES:
1. H = V , L = V , X = don‘t care, — = unrelated.
IH IL
2. M = high if TAG equals the memory contents at the address; M = low if TAG does not equal the ocntents at that address.
IN
IN
3. PWRDN and RESET are high for this table. OES and CLK are X.
4. This column represents the stored memory cell data for the given status bit at the selected address.
MPC2104•MPC2105•MPC2106•MPC2107
MOTOROLA FAST SRAM
16
TAG RAM AC OPERATING CONDITIONS AND CHARACTERISTICS
(V
= 5.0 V ± 5%, T = 0 to + 70°C, Unless Otherwise Noted)
CC
A
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Measurement Reference Level . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . Figure 1A Unless Otherwise Noted
TAG RAM READ CYCLE (See Notes 1 through 4)
Tag RAM
Parameter
Clock Access Time
Symbol
Min
—
—
0
Max
10
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes
t
KHQV
Output Enable to Output Valid
Output Enable to Output Active
Output Disable to Q High–Z
t
t
GLQV
GLQX
GHQZ
—
6
t
1
Status Bit Hold from Address Change
Address Access Time Status Bits
Tag Bit Hold from Address Change
Address Access Time Tag Bits
t
3
—
10
—
12
AXSX
t
—
3
AVSV
AVQX
AVQV
t
t
—
NOTES:
1. Set–up and hold times, W (write) referes to TWE.
2. A read cycle is defined by TWE high. A write cycle is defined by TWE low.
3. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles.
4. Tag reads are asynchronous.
TAG RAM WRITE CYCLE (See Notes 1 through 4)
Tag RAM
Parameter
Symbol
Min
15
Max
—
Unit
ns
Notes
Cycle Time
t
KHKH
Clock High Pulse Width
Clock Low Pulse Width
Clock High to Output Active
Set–up Times
t
4.5
4.5
1.5
3
—
ns
KHKL
KLKH
KHQX
t
—
ns
t
—
ns
t
Address
Write
—
ns
AVKH
t
WVKH
t
Hold Times
Address
Write
1.5
—
ns
KHAX
t
KHWX
Status Output Hold
Clock High to Status Bits Valid
NOTES:
t
0
—
9
ns
ns
KHSX
t
—
KHSV
1. Set–up and hold times, W (write) referes to TWE.
2. A read cycle is defined by TWE high. A write cycle is defined by TWE low.
3. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles.
4. Tag writes are synchronous.
MPC2104•MPC2105•MPC2106•MPC2107
MOTOROLA FAST SRAM
17
MPC2104•MPC2105•MPC2106•MPC2107
MOTOROLA FAST SRAM
18
TAG RAM MATCH CYCLE
Tag RAM
Min
Parameter
Symbol
Max
7
Unit
ns
Notes
Clock High Write to MATCH Invalid
Clock High Read to MATCH Valid
Address Valid to MATCH Valid
MATCH Valid Hold from Address Change
TOE Low to MATCH Invalid
t
—
—
—
2
KHML
t
10
10
—
7
ns
KHMV
t
ns
AVMV
t
ns
AXMX
t
—
—
ns
GLML
TOE High to MATCH Valid
t
8
ns
GHMX
TAG RAM RESET (TCLR) CYCLE
Tag RAM
Parameter
TCLR Set–up Time
Symbol
Min
4
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
t
STC
TCLR Hold Time
t
1
—
HTC
Status Bit Reset Time
t
—
2
60
SRST
SHRS
RSML
RSMV
Status Bit Hold from TCLR Low
TCLR Low to MATCH Invalid
TCLR High to MATCH Valid
TCLR Low to TAG High–Z
TCLR High to TAG Active
STANDBY Set–up to TCLR Low
TCLR High to TWE Low
t
t
—
—
—
—
—
30
80
10
t
100
10
t
RSQZ
RSQX
t
100
—
t
PDSR
t
—
RHWX
TIMING LIMITS
The table of timing values shows either a
AC TEST LOADS
minimum or a maximum limit for each param-
eter. Input requirements are specified from
the external system point of view. Thus, ad-
dress setup time is shown as a minimum
since the system must supply at least that
much time (even though most devices do not
requireit). Ontheotherhand, responsesfrom
the memory are specified from the device
point of view. Thus, the access time is shown
as a maximum since the device never pro-
vides data later than that time.
+5 V
480
Ω
Z
= 50 Ω
0
OUTPUT
OUTPUT
50
Ω
255
Ω
5 pF
V
= 1.5 V
L
Figure 1A
Figure 1B
MPC2104•MPC2105•MPC2106•MPC2107
MOTOROLA FAST SRAM
19
MPC2104•MPC2105•MPC2106•MPC2107
MOTOROLA FAST SRAM
20
TAG RAM TCLR FUNCTION
CLK
t
t
STC
HTC
TCLR
t
SRST
t
SHRS
DIRTYOUT
t
t
RHWX
WVKH
TWE
t
RSMV
MATCH
VALID
t
RSQZ*
t
RSQX
A0 – A11
* Transition is measured plus or minus 200 mV from steady state.
MPC2104•MPC2105•MPC2106•MPC2107
MOTOROLA FAST SRAM
21
ORDERING INFORMATION
(Order by Full Part Number)
MPC
210x
XX
XX
Speed (66 = 66 MHz, synchronous)
(15 = 15 ns asynchronous)
Motorola Memory Prefix
Part Number
Package (SG = Gold Pad SIMM)
Full Part Numbers — MPC2104SG66
MPC2105SG66
MPC2104 = 256KB, synchronous
MPC2105 = 512KB, synchronous
MPC2106 = 1MB, synchronous
MPC2107 = 256KB, asynchronous
MPC2106SG66
MPC2107SG15
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
andspecificallydisclaimsanyandallliability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
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against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
MPC2104•MPC2105•MPC2106•MPC2107
MOTOROLA FAST SRAM
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MPC2104•MPC2105•MPC2106•MPC2107
MOTOROLA FAST SRAM
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How to reach us:
USA / EUROPE: Motorola Literature Distribution;
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,
6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315
MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE (602) 244–6609
INTERNET: http://Design–NET.com
HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MPC2104/D
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