MC88915TFN70 [MOTOROLA]
LOW SKEW CMOS PLL CLOCK DRIVER; 低偏移的CMOS PLL时钟驱动器
| 型号： | MC88915TFN70 |
| 厂家： | 
MOTOROLA |
| 描述： | LOW SKEW CMOS PLL CLOCK DRIVER |
| 文件： | 总20页 (文件大小：220K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
The MC88915T Clock Driver utilizes phase–locked loop technology to
lock its low skew outputs’ frequency and phase onto an input reference
clock. It is designed to provide clock distribution for high performance
PC’s and workstations. For a 3.3V version, see the MC88LV915T data
sheet.
The PLL allows the high current, low skew outputs to lock onto a single
clock input and distribute it with essentially zero delay to multiple
components on a board. The PLL also allows the MC88915T to multiply a
low frequency input clock and distribute it locally at a higher (2X) system
frequency. Multiple 88915’s can lock onto a single reference clock, which
is ideal for applications when a central system clock must be distributed
synchronously to multiple boards (see Figure 7).
LOW SKEW CMOS
PLL CLOCK DRIVER
Five “Q” outputs (Q0–Q4) are provided with less than 500 ps skew between their rising edges. The Q5 output is inverted (180°
phase shift) from the “Q” outputs. The 2X_Q output runs at twice the “Q” output frequency, while the Q/2 runs at 1/2 the “Q”
frequency.
The VCO is designed to run optimally between 20 MHz and the 2X_Q F
max
specification. The wiring diagrams in Figure 5 detail
the different feedback configurations which create specific input/output frequency relationships. Possible frequency ratios of the
“Q” outputs to the SYNC input are 2:1, 1:1, and 1:2.
The FREQ_SEL pin provides one bit programmable divide–by in the feedback path of the PLL. It selects between divide–by–1
and divide–by–2 of the VCO before its signal reaches the internal clock distribution section of the chip (see the block diagram on
page 2). In most applications FREQ_SEL should be held high (÷1). If a low frequency reference clock input is used, holding
FREQ_SEL low (÷2) will allow the VCO to run in its optimal range (>20MHz and >40MHz for the TFN133 version).
Innormalphase–lockedoperationthePLL_ENpinisheldhigh. PullingthePLL_ENpinlowdisablestheVCOandputsthe88915
in a static “test mode”. In this mode there is no frequency limitation on the input clock, which is necessary for a low frequency board
test environment. The second SYNC input can be used as a test clock input to further simplify board–level testing (see detailed
description on page 11).
Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0–Q4, Q5 and Q/2 into a high impedance state (3–state). After the
OE/RST pin goes back high Q0–Q4, Q5 and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNC
input. Assuming PLL_EN is low, the outputs will remain reset until the 88915 sees a SYNC input pulse.
A lock indicator output (LOCK) will go high when the loop is in steady–state phase and frequency lock. The LOCK output will go
low if phase–lock is lost or when the PLL_EN pin is low. The LOCK output will go high no later than 10ms after the 88915 sees a
SYNC signal and full 5V V
.
CC
Features
• Five Outputs (Q0–Q4) with Output–Output Skew < 500 ps each being phase and frequency locked to the SYNC input
• The phase variation from part–to–part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the t
PD
specification, which defines the part–to–part skew)
• Input/Output phase–locked frequency ratios of 1:2, 1:1, and 2:1 are available
• Input frequency range from 5MHz – 2X_Q FMAX spec. (10MHz – 2X_Q FMAX for the TFN133 version)
• Additional outputs available at 2X and +2 the system “Q” frequency. Also a Q (180° phase shift) output available
• All outputs have ±36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs
are TTL–level compatible. ±88mA I /I specifications guarantee 50Ω transmission line switching on the incident edge
OL OH
• Test Mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes.
All outputs can go into high impedance (3–state) for board test purposes
• Lock Indicator (LOCK) accuracy indicates a phase–locked state
Yield Surface Modeling and YSM are trademarks of Motorola, Inc.
1/97
REV 4
Motorola, Inc. 1997
MC88915TFN55/70/100/133/160
Pinout: 28–Lead PLCC (Top View)
OE/RST
V
Q5
2
GND Q4
V
2X_Q
26
CC
CC
4
3
1
28
27
FEEDBACK
REF_SEL
SYNC[0]
5
25
Q/2
GND
Q3
6
24
23
22
21
20
19
7
V
(AN)
RC1
8
V
CC
CC
9
Q2
GND(AN)
SYNC[1]
10
11
GND
LOCK
12
13
14
15
V
16
17
18
PLL_EN
GND Q0
Q1 GND
FREQ_SEL
CC
FN SUFFIX
PLASTIC PLCC
CASE 776–02
PIN SUMMARY
Pin Name
Num
I/O
Function
1
1
1
1
1
1
5
1
1
1
1
1
1
11
SYNC[0]
SYNC[1]
REF_SEL
FREQ_SEL
FEEDBACK
RC1
Q(0–4)
Q5
2x_Q
Q/2
LOCK
OE/RST
PLL_EN
Input
Input
Input
Input
Input
Reference clock input
Reference clock input
Chooses reference between sync[0] & Sync[1]
Doubles VCO Internal Frequency (low)
Feedback input to phase detector
Input for external RC network
Clock output (locked to sync)
Inverse of clock output
2 x clock output (Q) frequency (synchronous)
Clock output(Q) frequency ÷ 2 (synchronous)
Indicates phase lock has been achieved (high when locked)
Output Enable/Asynchronous reset (active low)
Disables phase–lock for low freq. testing
Power and ground pins (note pins 8, 10 are
“analog” supply pins for internal PLL only)
Input
Output
Output
Output
Output
Output
Input
Input
V
,GND
CC
MOTOROLA
2
TIMING SOLUTIONS
BR1333 — Rev 6
MC88915TFN55/70/100/133/160
LOCK
FEEDBACK
SYNC (0)
VOLTAGE
CONTROLLED
OSCILLATOR
0
1
PHASE/FREQ.
DETECTOR
CHARGE PUMP/LOOP
FILTER
M
U
X
SYNC (1)
EXTERNAL REC NETWORK
(RC1 Pin)
REF_SEL
2x_Q
Q0
0
1
PLL_EN
MUX
D
Q
Q
(
÷
1)
2)
CP
1
R
R
R
M
U
X
(÷
DIVIDE
BY TWO
0
Q1
Q2
Q3
D
Q
CP
FREQ_SEL
OE/RST
D
Q
Q
CP
D
CP
R
R
R
Q4
Q5
D
Q
Q
Q
CP
D
CP
Q/2
D
CP
R
MC88915T Block Diagram (All Versions)
3
MOTOROLA
MC88915TFN55/70/100/133/160
MC88915TFN55 and MC88915TFN70
SYNC INPUT TIMING REQUIREMENTS
Minimum
Symbol
Parameter
TFN70
TFN55
—
Maximum
Unit
t
t
,SYNC Inputs Rise/Fall Time, SYNC Inputs
—
3.0
ns
RISE/FALL
From 0.8 to 2.0V
1
1
2
200
, SYNC Inputs
Input Clock Period SYNC Inputs
Input Duty Cycle SYNC Inputs
28.5
36.0
ns
CYCLE
Duty Cycle SYNC Inputs
1. These t
50% ±25%
minimum values are valid when ‘Q’ output is fed back and connected to the FEEDBACK pin. This is the configuration shown
CYCLE
in Figure 5b.
2. Information in Table 1 and in Note 3 of the AC specification notes describe this specification and its limits depending on what output is fed back,
and if FREQ_SEL is high or low.
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND) T =–40° C to +85° C for 55MHz Version; T =0° C to +70° C for 70MHz Version; V
= 5.0 V ± 5%
A
A
CC
V
CC
V
Symbol
Parameter
Test Conditions
Target Limit
Unit
V
IH
Minimum High–Level Input
Voltage
V
out
= 0.1 V or V
– 0.1 V
4.75
5.25
2.0
2.0
V
CC
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
4.75
5.25
0.8
0.8
V
V
V
IL
out
CC
V
OH
Minimum High–Level Output
Voltage
V
= V or V
IH IL
4.75
5.25
4.01
4.51
in
1
= –36 mA
I
OH
V
OL
Maximum Low–Level Output
Voltage
V
= V or V
IH IL
4.75
5.25
0.44
0.44
in
1
= 36 mA
I
OL
I
Maximum Input Leakage Current
V = V
or GND
– 2.1 V
5.25
5.25
5.25
5.25
5.25
±1.0
µA
mA
mA
mA
mA
in
I
CC
CC
2
I
Maximum I /Input
CC
V = V
I
CCT
OLD
2.0
3
I
Minimum Dynamic Output Current
V
= 1.0V Max
= 3.85V Min
88
–88
1.0
OLD
OHD
I
V
OHD
I
Maximum Quiescent Supply
Current (per Package)
V = V
I
or GND
CC
CC
4
I
Maximum 3–State Leakage Current
V = V or V ;V = V or GND
IH IL CC
5.25
±50
µA
OZ
OL
I
O
1. I
and I
OH
are 12mA and –12mA respectively for the LOCK output.
2. The PLL_EN input pin is not guaranteed to meet this specification.
3. Maximum test duration is 2.0ms, one output loaded at a time.
4. Specification value for I
is preliminary, will be finalized upon ‘MC’ status.
OZ
CAPACITANCE AND POWER SPECIFICATIONS
Symbol
Parameter
Typical Values
Unit
Conditions
C
Input Capacitance
4.5
40
pF
pF
V
V
V
= 5.0 V
= 5.0 V
= 5.0 V
IN
CC
CC
CC
C
Power Dissipation Capacitance
PD
PD
Power Dissipation @ 50MHz with 50Ω Thevenin Termination
23mW/Output
184mW/Device
mW
1
T = 25°C
PD
Power Dissipation @ 50MHz with 50Ω Parallel Termination to GND
57mW/Output
456mW/Device
mW
V
= 5.0 V
T = 25° C
2
CC
NOTE: PD and PD mW/Output numbers are for a ‘Q’ output.
1
2
FREQUENCY SPECIFICATIONS (T =–40° C to +85° C, V
= 5.0 V ±5%)
CC
A
Guaranteed Minimum
TFN70 TFN55
70 55
35 27.5
Symbol
Parameter
Unit
1
f
Maximum Operating Frequency (2X_Q Output)
MHz
MHz
max
Maximum Operating Frequency (Q0–Q4,Q5 Output)
1. Maximum Operating Frequency is guaranteed with the part in a phase–locked condition, and all outputs loaded with 50Ω terminated to V /2.
CC
MOTOROLA
4
TIMING SOLUTIONS
BR1333 — Rev 6
MC88915TFN55/70/100/133/160
MC88915TFN55 and MC88915TFN70 (continued)
AC CHARACTERISTICS (T =–40° C to +85° C, V
= 5.0V ±5%, Load = 50Ω Terminated to V /2)
CC CC
A
Symbol
Parameter
Min
Max
Unit
Condition
t
Rise/Fall Time, All Outputs
1.0
2.5
ns
Into a 50Ω Load
RISE/FALL
Outputs
(Between 0.2V
and 0.8V
)
CC
Terminated to V /2
CC
CC
1
t
Rise/Fall Time Into a 20pF Load, With
Termination Specified in Note
0.5
1.6
ns
ns
ns
t
t
: 0.8V – 2.0V
: 2.0V – 0.8V
RISE/FALL
2X_Q Output
RISE
FALL
2
1
2
2
2
2
t
Output Pulse Width: Q0, Q1, Q2, Q3,
Q4, Q5, Q/2 @ V /2
CC
0.5t
– 0.5
– 0.5
0.5t
0.5t
0.5t
0.5t
+ 0.5
+ 0.5
Into a 50Ω Load
Terminated to V /2
PULSE WIDTH
(Q0–Q4, Q5, Q/2)
CYCLE
CYCLE
CC
1
t
Output Pulse Width:
2X_Q @ 1.5V
66MHz 0.5t
50MHz
40MHz
Must Use Termination
Specified in Note 2
PULSE WIDTH
(2X_Q Output)
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
0.5t
0.5t
– 1.0
– 1.5
+ 1.0
+ 1.5
1
2
2
t
Output Pulse Width:
50–65MHz 0.5t
– 1.0
0.5t
0.5t
0.5t
+ 1.0
ns
ns
Into a 50Ω Load
PULSE WIDTH
(2X_Q Output)
CYCLE
CYCLE
2X_Q @ V /2
40–49MHz
66–70MHz
0.5t
0.5t
– 1.5
– 0.5
+ 1.5
+ 0.5
Terminated to V /2
CC
CYCLE
CYCLE
CYCLE
CYCLE
CC
1,3
t
SYNC Input to Feedback Delay
(Measured at SYNC0 or 1 and
FEEDBACK Input Pins)
See Note 4 and
Figure 2 for Detailed
Explanation
(With 1MΩ from RC1 to An V
)
PD
SYNC Feedback
CC
–0.40
(With 1MΩ from RC1 to An GND)
–1.05
+1.25
—
+3.25
500
1,4
t
Output–to–Output Skew Between Out-
puts Q0–Q4, Q/2 (Rising Edges Only)
ps
ps
ps
ms
All Outputs Into a
Matched 50Ω Load
SKEWr
(Rising) See Note
5
Terminated to V /2
CC
1,4
t
Output–to–Output Skew Between Out-
puts Q0–Q4 (Falling Edges Only)
—
—
500
750
10
All Outputs Into a
Matched 50Ω Load
SKEWf
(Falling)
Terminated to V /2
CC
1,4
SKEWall
t
Output–to–Output Skew 2X_Q, Q/2,
Q0–Q4 Rising, Q5 Falling
All Outputs Into a
Matched 50Ω Load
Terminated to V /2
CC
5
t
Time Required to Acquire Phase–Lock
From Time SYNC Input Signal is
Received
1.0
Also Time to LOCK
Indicator High
LOCK
6
t
t
Output Enable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
3.0
3.0
14
14
ns
ns
Measured With the
PLL_EN Pin Low
PZL
6
PHZ PLZ
,t
Output Disable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
Measured With the
PLL_EN Pin Low
1. These specifications are not tested, they are guaranteed by statistcal characterization. See AC specification Note 1.
2. T
3. The T
in this spec is 1/Frequency at which the particular output is running.
specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
CYCLE
PD
4. Under equally loaded conditions and at a fixed temperature and voltage.
5. With V fully powered–on, and an output properly connected to the FEEDBACK pin. t
maximum is with C1 = 0.1µF, t minimum is
LOCK
CC
with C1 = 0.01µF.
6. The t , t , t
LOCK
minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is
PZL PHZ PLZ
reached.
5
MOTOROLA
MC88915TFN55/70/100/133/160
MC88915TFN100
SYNC INPUT TIMING REQUIREMENTS
Symbol
Parameter
Minimum
Maximum
Unit
t
,SYNC Inputs Rise/Fall Time, SYNC Inputs From 0.8 to 2.0V
—
3.0
ns
RISE/FALL
1
2
t
, SYNC Inputs
Input Clock Period SYNC Inputs
Input Duty Cycle SYNC Inputs
20.0
200
ns
CYCLE
Duty Cycle SYNC Inputs
1. These t
50% ±25%
minimum values are valid when ‘Q’ output is fed back and connected to the FEEDBACK pin. This is the configuration shown
CYCLE
in Figure 5b.
2. Information in Table 1 and in Note 3 of the AC specification notes describe this specification and its limits depending on what output is fed back,
and if FREQ_SEL is high or low.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) T =–40° C to +85° C, V
= 5.0 V ± 5%
A
CC
V
CC
V
Symbol
Parameter
Test Conditions
Target Limit
Unit
V
IH
Minimum High–Level Input
Voltage
V
out
= 0.1 V or V
– 0.1 V
4.75
5.25
2.0
2.0
V
CC
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
4.75
5.25
0.8
0.8
V
V
V
IL
out
CC
V
OH
Minimum High–Level Output
Voltage
V
= V or V
IH IL
4.75
5.25
4.01
4.51
in
1
= –36 mA
I
OH
V
OL
Maximum Low–Level Output
Voltage
V
= V or V
IH IL
4.75
5.25
0.44
0.44
in
1
= 36 mA
I
OL
I
Maximum Input Leakage Current
V = V
or GND
– 2.1 V
5.25
5.25
5.25
5.25
5.25
±1.0
µA
mA
mA
mA
mA
in
I
CC
CC
2
I
Maximum I /Input
CC
V = V
I
CCT
OLD
2.0
3
I
Minimum Dynamic Output Current
V
OLD
V
OHD
= 1.0V Max
= 3.85V Min
88
–88
1.0
I
OHD
I
Maximum Quiescent Supply
Current (per Package)
V = V
I
or GND
CC
CC
4
I
Maximum 3–State Leakage Current
V = V or V ;V = V or GND
IH IL CC
5.25
±50
µA
OZ
I
O
1. I
and I
OH
are 12mA and –12mA respectively for the LOCK output.
OL
2. The PLL_EN input pin is not guaranteed to meet this specification.
3. Maximum test duration is 2.0ms, one output loaded at a time.
4. Specification value for I
is preliminary, will be finalized upon ‘MC’ status.
OZ
CAPACITANCE AND POWER SPECIFICATIONS
Symbol
Parameter
Typical Values
Unit
Conditions
C
Input Capacitance
4.5
40
pF
pF
V
V
V
= 5.0 V
= 5.0 V
= 5.0 V
IN
CC
CC
CC
C
Power Dissipation Capacitance
PD
PD
Power Dissipation @ 50MHz with 50Ω Thevenin Termination
23mW/Output
184mW/Device
mW
1
T = 25°C
PD
Power Dissipation @ 50MHz with 50Ω Parallel Termination to GND
57mW/Output
456mW/Device
mW
V
= 5.0 V
T = 25° C
2
CC
NOTE: PD and PD mW/Output numbers are for a ‘Q’ output.
1
2
FREQUENCY SPECIFICATIONS (T =–40° C to +85° C, V
= 5.0 V ±5%)
CC
A
Guaranteed Minimum
Symbol
Parameter
TFN100
100
Unit
1
f
Maximum Operating Frequency (2X_Q Output)
MHz
MHz
max
Maximum Operating Frequency (Q0–Q4,Q5 Output)
50
1. Maximum Operating Frequency is guaranteed with the part in a phase–locked condition, and all outputs loaded with 50Ω terminated to V /2.
CC
MOTOROLA
6
TIMING SOLUTIONS
BR1333 — Rev 6
MC88915TFN55/70/100/133/160
MC88915TFN100 (continued)
AC CHARACTERISTICS (T =–40° C to +85° C, V
= 5.0V ±5%, Load = 50Ω Terminated to V /2)
CC CC
A
Symbol
Parameter
Min
Max
Unit
Condition
t
Rise/Fall Time, All Outputs
1.0
2.5
ns
Into a 50Ω Load
RISE/FALL
Outputs
(Between 0.2V
and 0.8V
)
CC
Terminated to V /2
CC
CC
1
t
Rise/Fall Time Into a 20pF Load, With
Termination Specified in Note
0.5
1.6
ns
ns
ns
ns
t
t
: 0.8V – 2.0V
: 2.0V – 0.8V
RISE/FALL
2X_Q Output
RISE
FALL
2
1
2
2
2
2
2
2
t
Output Pulse Width: Q0, Q1, Q2, Q3,
Q4, Q5, Q/2 @ V /2
CC
0.5t
0.5t
– 0.5
– 0.5
– 1.5
0.5t
0.5t
0.5t
+ 0.5
+ 0.5
+ 1.5
Into a 50Ω Load
Terminated to V /2
PULSE WIDTH
(Q0–Q4, Q5, Q/2)
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CC
1
1
t
Output Pulse Width:
2X_Q @ 1.5V
Must Use Termination
Specified in Note 2
PULSE WIDTH
(2X_Q Output)
t
Output Pulse Width:
40–49MHz 0.5t
Into a 50Ω Load
Terminated to V /2
PULSE WIDTH
(2X_Q Output)
2X_Q @ V /2
50–65MHz
66–100MHz
0.5t
– 1.0
– 0.5
0.5t
0.5t
+ 1.0
+ 0.5
CC
CYCLE
0.5t
CYCLE
CYCLE
CYCLE
CC
1,3
t
SYNC Input to Feedback Delay
(Measured at SYNC0 or 1 and
FEEDBACK Input Pins)
ns
See Note 4 and
Figure 2 for Detailed
Explanation
(With 1MΩ from RC1 to An V
)
PD
SYNC Feedback
CC
–0.30
(With 1MΩ from RC1 to An GND)
–1.05
+1.25
—
+3.25
500
1,4
t
Output–to–Output Skew Between Out-
puts Q0–Q4, Q/2 (Rising Edges Only)
ps
ps
ps
ms
All Outputs Into a
Matched 50Ω Load
SKEWr
(Rising) See Note
5
Terminated to V /2
CC
1,4
t
Output–to–Output Skew Between Out-
puts Q0–Q4 (Falling Edges Only)
—
—
500
750
10
All Outputs Into a
Matched 50Ω Load
SKEWf
(Falling)
Terminated to V /2
CC
1,4
SKEWall
t
t
Output–to–Output Skew 2X_Q, Q/2,
Q0–Q4 Rising, Q5 Falling
All Outputs Into a
Matched 50Ω Load
Terminated to V /2
CC
5
Time Required to Acquire Phase–Lock
From Time SYNC Input Signal is
Received
1.0
Also Time to LOCK
Indicator High
LOCK
6
t
t
Output Enable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
3.0
3.0
14
14
ns
ns
Measured With the
PLL_EN Pin Low
PZL
6
PHZ PLZ
,t
Output Disable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
Measured With the
PLL_EN Pin Low
1. These specifications are not tested, they are guaranteed by statistcal characterization. See AC specification Note 1.
2. T
3. The T
in this spec is 1/Frequency at which the particular output is running.
specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
CYCLE
PD
4. Under equally loaded conditions and at a fixed temperature and voltage.
5. With V fully powered–on, and an output properly connected to the FEEDBACK pin. t
maximum is with C1 = 0.1µF, t minimum is
LOCK
CC
with C1 = 0.01µF.
6. The t , t , t
LOCK
minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is
PZL PHZ PLZ
reached.
7
MOTOROLA
MC88915TFN55/70/100/133/160
MC88915TFN133
SYNC INPUT TIMING REQUIREMENTS
Symbol
Parameter
Minimum
Maximum
Unit
t
,SYNC Inputs Rise/Fall Time, SYNC Inputs From 0.8 to 2.0V
—
3.0
ns
RISE/FALL
1
2
t
, SYNC Inputs
Input Clock Period SYNC Inputs
Input Duty Cycle SYNC Inputs
15.0
100
ns
CYCLE
Duty Cycle SYNC Inputs
1. These t
50% ±25%
minimum values are valid when ‘Q’ output is fed back and connected to the FEEDBACK pin. This is the configuration shown
CYCLE
in Figure 5b.
2. Information in Table 1 and in Note 3 of the AC specification notes describe this specification and its limits depending on what output is fed back,
and if FREQ_SEL is high or low.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) T =–40° C to +85° C, V
= 5.0 V ± 5%
A
CC
V
CC
V
Symbol
Parameter
Test Conditions
Target Limit
Unit
V
IH
Minimum High–Level Input
Voltage
V
out
= 0.1 V or V
– 0.1 V
4.75
5.25
2.0
2.0
V
CC
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
4.75
5.25
0.8
0.8
V
V
V
IL
out
CC
V
OH
Minimum High–Level Output
Voltage
V
= V or V
IH IL
4.75
5.25
4.01
4.51
in
1
= –36 mA
I
OH
V
OL
Maximum Low–Level Output
Voltage
V
= V or V
IH IL
4.75
5.25
0.44
0.44
in
1
= 36 mA
I
OL
I
Maximum Input Leakage Current
V = V
or GND
– 2.1 V
5.25
5.25
5.25
5.25
5.25
±1.0
µA
mA
mA
mA
mA
in
I
CC
CC
2
I
Maximum I /Input
CC
V = V
I
CCT
OLD
2.0
3
I
Minimum Dynamic Output Current
V
OLD
V
OHD
= 1.0V Max
= 3.85V Min
88
–88
1.0
I
OHD
I
Maximum Quiescent Supply
Current (per Package)
V = V
I
or GND
CC
CC
4
I
Maximum 3–State Leakage Current
V = V or V ;V = V or GND
IH IL CC
5.25
±50
µA
OZ
I
O
1. I
and I
OH
are 12mA and –12mA respectively for the LOCK output.
OL
2. The PLL_EN input pin is not guaranteed to meet this specification.
3. Maximum test duration is 2.0ms, one output loaded at a time.
4. Specification value for I
is preliminary, will be finalized upon ‘MC’ status.
OZ
CAPACITANCE AND POWER SPECIFICATIONS
Symbol
Parameter
Typical Values
Unit
Conditions
C
Input Capacitance
4.5
40
pF
pF
V
V
V
= 5.0 V
= 5.0 V
= 5.0 V
IN
CC
CC
CC
C
Power Dissipation Capacitance
PD
PD
Power Dissipation @ 50MHz with 50Ω Thevenin Termination
23mW/Output
184mW/Device
mW
1
T = 25°C
PD
Power Dissipation @ 50MHz with 50Ω Parallel Termination to GND
57mW/Output
456mW/Device
mW
V
= 5.0 V
T = 25° C
2
CC
NOTE: PD and PD mW/Output numbers are for a ‘Q’ output.
1
2
FREQUENCY SPECIFICATIONS (T =–40° C to +85° C, V
= 5.0 V ±5%)
CC
A
Guaranteed Minimum
Symbol
Parameter
TFN133
133
Unit
1
f
Maximum Operating Frequency (2X_Q Output)
MHz
MHz
max
Maximum Operating Frequency (Q0–Q4,Q5 Output)
66
1. Maximum Operating Frequency is guaranteed with the part in a phase–locked condition, and all outputs loaded with 50Ω terminated to V /2.
CC
MOTOROLA
8
TIMING SOLUTIONS
BR1333 — Rev 6
MC88915TFN55/70/100/133/160
MC88915TFN133 (continued)
AC CHARACTERISTICS (T =–40° C to +85° C, V
= 5.0V ±5%, Load = 50Ω Terminated to V /2)
CC CC
A
Symbol
Parameter
Min
Max
Unit
Condition
t
Rise/Fall Time, All Outputs
1.0
2.5
ns
Into a 50Ω Load
RISE/FALL
Outputs
(Between 0.2V
and 0.8V
)
CC
Terminated to V /2
CC
CC
1
t
Rise/Fall Time Into a 20pF Load, With
Termination Specified in Note
0.5
1.6
ns
ns
ns
ns
t
t
: 0.8V – 2.0V
: 2.0V – 0.8V
RISE/FALL
2X_Q Output
RISE
FALL
2
1
2
2
2
2
t
Output Pulse Width: Q0, Q1, Q2, Q3,
Q4, Q5, Q/2 @ V /2
CC
0.5t
– 0.5
– 0.5
0.5t
0.5t
+ 0.5
+ 0.5
Into a 50Ω Load
Terminated to V /2
PULSE WIDTH
(Q0–Q4, Q5, Q/2)
CYCLE
CYCLE
CC
1
1
t
Output Pulse Width:
2X_Q @ 1.5V
66–133MHz 0.5t
40–65MHz
Must Use Termination
Specified in Note 2
PULSE WIDTH
(2X_Q Output)
CYCLE
CYCLE
CYCLE
CYCLE
0.5t
– 0.9
0.5t
+ 0.9
2
2
t
Output Pulse Width:
66–133MHz 0.5t
– 0.5
0.5t + 0.5
CYCLE
0.5t
CYCLE
Into a 50Ω Load
Terminated to V /2
PULSE WIDTH
(2X_Q Output)
CYCLE
CYCLE
2X_Q @ V /2
40–65MHz
0.5t
– 0.9
+ 0.9
CC
CC
1,3
t
SYNC Input to Feedback Delay
(Measured at SYNC0 or 1 and
FEEDBACK Input Pins)
ns
See Note 4 and
Figure 2 for Detailed
Explanation
(With 1MΩ from RC1 to An V
)
PD
SYNC Feedback
CC
–1.05
–0.25
(With 1MΩ from RC1 to An GND)
+1.25
—
+3.25
500
1,4
t
Output–to–Output Skew Between Out-
puts Q0–Q4, Q/2 (Rising Edges Only)
ps
ps
ps
ms
All Outputs Into a
Matched 50Ω Load
SKEWr
(Rising) See Note
5
Terminated to V /2
CC
1,4
t
Output–to–Output Skew Between Out-
puts Q0–Q4 (Falling Edges Only)
—
—
500
750
10
All Outputs Into a
Matched 50Ω Load
SKEWf
(Falling)
Terminated to V /2
CC
1,4
SKEWall
t
Output–to–Output Skew 2X_Q, Q/2,
Q0–Q4 Rising, Q5 Falling
All Outputs Into a
Matched 50Ω Load
Terminated to V /2
CC
5
t
Time Required to Acquire Phase–Lock
From Time SYNC Input Signal is
Received
1.0
Also Time to LOCK
Indicator High
LOCK
6
t
t
Output Enable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
3.0
3.0
14
14
ns
ns
Measured With the
PLL_EN Pin Low
PZL
6
PHZ PLZ
,t
Output Disable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
Measured With the
PLL_EN Pin Low
1. These specifications are not tested, they are guaranteed by statistcal characterization. See AC specification Note 1.
2. T
3. The T
in this spec is 1/Frequency at which the particular output is running.
specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
CYCLE
PD
4. Under equally loaded conditions and at a fixed temperature and voltage.
5. With V fully powered–on, and an output properly connected to the FEEDBACK pin. t
maximum is with C1 = 0.1µF, t minimum is
LOCK
CC
with C1 = 0.01µF.
6. The t , t , t
LOCK
minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is
PZL PHZ PLZ
reached.
9
MOTOROLA
MC88915TFN55/70/100/133/160
MC88915TFN160
SYNC INPUT TIMING REQUIREMENTS
Symbol
Parameter
Minimum
Maximum
Unit
t
,SYNC Inputs Rise/Fall Time, SYNC Inputs From 0.8 to 2.0V
—
3.0
ns
RISE/FALL
t
, SYNC Inputs
Input Clock Period SYNC Inputs
Input Duty Cycle SYNC Inputs
12.5
100
ns
CYCLE
Duty Cycle SYNC Inputs
1. These t
50% ±25%
minimum values are valid when ‘Q’ output is fed back and connected to the FEEDBACK pin. This is the configuration shown
CYCLE
in Figure 5b.
2. Information in Table 1 and in Note 3 of the AC specification notes describe this specification and its limits depending on what output is fed back,
and if FREQ_SEL is high or low.
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND) T =0° C to +70° C, V
= 5.0 V ± 5%
CC
A
V
CC
V
Symbol
Parameter
Test Conditions
Target Limit
Unit
V
IH
Minimum High–Level Input
Voltage
V
out
= 0.1 V or V
– 0.1 V
4.75
5.25
2.0
2.0
V
CC
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
4.75
5.25
0.8
0.8
V
V
V
IL
out
CC
V
OH
Minimum High–Level Output
Voltage
V
= V or V
IH IL
4.75
5.25
4.01
4.51
in
1
= –36 mA
I
OH
V
OL
Maximum Low–Level Output
Voltage
V
= V or V
IH IL
4.75
5.25
0.44
0.44
in
1
= 36 mA
I
OL
I
Maximum Input Leakage Current
V = V
or GND
– 2.1 V
5.25
5.25
5.25
5.25
5.25
±1.0
µA
mA
mA
mA
mA
in
I
CC
CC
2
I
Maximum I /Input
CC
V = V
I
CCT
OLD
2.0
3
I
Minimum Dynamic Output Current
V
OLD
V
OHD
= 1.0V Max
= 3.85V Min
88
–88
1.0
I
OHD
I
Maximum Quiescent Supply
Current (per Package)
V = V
I
or GND
CC
CC
4
I
Maximum 3–State Leakage Current
V = V or V ;V = V or GND
IH IL CC
5.25
±50
µA
OZ
I
O
1. I
and I
OH
are 12mA and –12mA respectively for the LOCK output.
OL
2. The PLL_EN input pin is not guaranteed to meet this specification.
3. Maximum test duration is 2.0ms, one output loaded at a time.
4. Specification value for I
is preliminary, will be finalized upon ‘MC’ status.
OZ
CAPACITANCE AND POWER SPECIFICATIONS
Symbol
Parameter
Typical Values
Unit
Conditions
C
Input Capacitance
4.5
40
pF
pF
V
V
V
= 5.0 V
= 5.0 V
= 5.0 V
IN
CC
CC
CC
C
Power Dissipation Capacitance
PD
PD
Power Dissipation @ 50MHz with 50Ω Thevenin Termination
15mW/Output
120mW/Device
mW
1
T = 25°C
PD
Power Dissipation @ 50MHz with 50Ω Parallel Termination to GND
57mW/Output
456mW/Device
mW
V
= 5.0 V
T = 25° C
2
CC
NOTE: PD and PD mW/Output numbers are for a ‘Q’ output.
1
2
FREQUENCY SPECIFICATIONS (T =0° C to +70° C, V
= 5.0 V ±5%)
CC
A
Guaranteed Minimum
Symbol
Parameter
Maximum Operating Frequency (2X_Q Output)
Maximum Operating Frequency (Q0–Q4,Q5 Output)
TFN160
160
Unit
1
f
MHz
MHz
max
80
1. Maximum Operating Frequency is guaranteed with the part in a phase–locked condition, and all outputs loaded with 50Ω terminated to V /2.
CC
MOTOROLA
10
TIMING SOLUTIONS
BR1333 — Rev 6
MC88915TFN55/70/100/133/160
MC88915TFN160 (continued)
AC CHARACTERISTICS (T =0° C to +70° C, V
= 5.0V ±5%, Load = 50Ω Terminated to V /2)
CC
A
CC
Symbol
Parameter
Min
Max
Unit
Condition
t
Rise/Fall Time, All Outputs
1.0
2.5
ns
Into a 50Ω Load
RISE/FALL
Outputs
(Between 0.2V
and 0.8V
)
Terminated to V /2
CC
CC
CC
t
Rise/Fall Time
0.5
1.6
ns
ns
ns
t
t
: 0.8V – 2.0V
: 2.0V – 0.8V
RISE/FALL
2X_Q Output
RISE
FALL
2
2
t
Output Pulse Width: Q0, Q1, Q2, Q3,
Q4, Q5, Q/2 @ V /2
0.5t
– 0.5
0.5t
+ 0.5
Into a 50Ω Load
Terminated to V /2
PULSE WIDTH
(Q0–Q4, Q5, Q/2)
CYCLE
CYCLE
CC
CC
t
Output Pulse Width:
80MHz
100MHz
133MHz
160MHz
0.5t
0.5t
0.5t
– 0.7
– 0.5
– 0.5
0.5t
0.5t
0.5t
+ 0.7
+ 0.5
+ 0.5
PULSE WIDTH
(2X_Q Output)
CYCLE
CYCLE
CYCLE
TBD
CYCLE
CYCLE
CYCLE
TBD
2X_Q @ V
CC
1
t
SYNC Input to Feedback Delay
(Measured at SYNC0 or 1 and
FEEDBACK Input Pins)
ns
See Note 2 and
Figure 2 for Detailed
Explanation
(With 1MΩ from RC1 to An V
)
PD
SYNC Feedback
CC
133MHz
160MHz
–1.05
–0.9
–0.25
–0.10
t
Cycle–to–Cycle Variation
133MHz
160MHz
t
t
– 300ps
– 300ps
t
t
+ 300ps
+ 300ps
CYCLE
(2x_Q Output)
CYCLE
CYCLE
CYCLE
CYCLE
3
t
Output–to–Output Skew Between Out-
—
500
ps
ps
ps
ms
All Outputs Into a
Matched 50Ω Load
SKEWr
(Rising) See Note 4 puts Q0–Q4, Q/2 (Rising Edges Only)
Terminated to V /2
CC
3
t
Output–to–Output Skew Between Out-
puts Q0–Q4 (Falling Edges Only)
—
—
500
750
10
All Outputs Into a
Matched 50Ω Load
SKEWf
(Falling)
Terminated to V /2
CC
3
t
Output–to–Output Skew 2X_Q, Q/2,
Q0–Q4 Rising, Q5 Falling
All Outputs Into a
Matched 50Ω Load
SKEWall
Terminated to V /2
CC
4
t
Time Required to Acquire Phase–Lock
From Time SYNC Input Signal is
Received
1.0
Also Time to LOCK
Indicator High
LOCK
5
t
t
Output Enable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
3.0
3.0
14
14
ns
ns
Measured With the
PLL_EN Pin Low
PZL
5
,t
PHZ PLZ
Output Disable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
Measured With the
PLL_EN Pin Low
1. T
CYCLE
in this spec is 1/Frequency at which the particular output is running.
specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
2. The T
PD
3. Under equally loaded conditions and at a fixed temperature and voltage.
4. With V fully powered–on, and an output properly connected to the FEEDBACK pin. t
maximum is with C1 = 0.1µF, t minimum is
LOCK LOCK
minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is
CC
with C1 = 0.01µF.
5. The t , t , t
PZL PHZ PLZ
reached.
11
MOTOROLA
MC88915TFN55/70/100/133/160
Applications Information for All Versions
General AC Specification Notes
2. These two specs (t
RlSE/FALL
and t
Width 2X_Q
PULSE
output) guarantee that the MC88915T meets the 40MHz
and 33MHz MC68040 P–Clock input specification (at
80MHz and 66MHz, respectively). For these two specs to
be guaranteed by Motorola, the termination scheme
shown below in Figure 1 must be used.
1. Several specifications can only be measured when the
MC88915TFN55, 70 and 100 are in phase–locked
operation. It is not possible to have the part in phase–lock
on ATE (automated test equipment). Statistical
characterization techniques were used to guarantee
those specifications which cannot be measured on the
ATE. MC88915TFN55, 70 and 100 units were fabricated
with key transistor properties intentionally varied to
create a 14 cell designed experimental matrix. IC
performancewas characterized over a range of transistor
properties (represented by the 14 cells) in excess of the
expected process variation of the wafer fabrication area,
to set performance limits of ATE testable specifications
within those which are to be guaranteed by statistical
characterization. In this way all units passing the ATE test
will meet or exceed the non–tested specifications limits.
3. The wiring Diagrams and explanations in Figure 5
demonstratethe input and output frequencyrelationships
for three possible feedback configurations. The allowable
SYNC input range for each case is also indicated. There
are two allowable SYNC frequency ranges, depending
whether FREQ_SEL is high or low. Although not shown, it
is possible to feed back the Q5 output, thus creating a
180° phase shift between the SYNC input and the “Q”
outputs. Table 1 below summarizes the allowable SYNC
frequency range for each possible configuration.
Z
O
(CLOCK TRACE)
R
s
88915
2X_Q
Output
68040
P–Clock
Input
R
p
R = Z – 7
Ω
s
o
R = 1.5 Z
p
o
Figure 1. MC68040 P–Clock Input Termination Scheme
FREQ_SEL
Level
Feedback
Output
Allowable SYNC Input
Frequency Range (MHZ)
Corresponding VCO
Frequency Range
Phase Relationships
of the “Q” Outputs
to Rising SYNC Edge
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
Q/2
5 to (2X_Q FMAX Spec)/4
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
0°
0°
Any “Q” (Q0–Q4) 10 to (2X_Q FMAX Spec)/2
Q5
2X_Q
Q/2
10 to (2X_Q FMAX Spec)/2
20 to (2X_Q FMAX Spec)
180°
0°
2.5 to (2X_Q FMAX Spec)/8 20 to (2X_Q FMAX Spec)
0°
Any “Q” (Q0–Q4) 5 to (2X_Q FMAX Spec)/4
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAXSpec)
20 to (2X_Q FMAXSpec)
0°
Q5
5 to (2X_Q FMAX Spec)/4
10 to (2X_Q FMAX Spec)/2
180°
0°
2X_Q
Table 1. Allowable SYNC Input Frequency Ranges for Different Feedback Configurations.
4. A 1MΩ resistor tied to either Analog V
or Analog GND
the 14 lots described in note 1 while the part was in
phase–lockedoperation. Theactualmeasurementswere
made with a 10MHz SYNC input (1.0ns edge rate from
0.8V – 2.0V) with the Q/2 output fed back. The phase
measurements were made at 1.5V. The Q/2 output was
CC
as shown in Figure 2 is required to ensure no jitter is
present on the MC88915T outputs. This technique
causes a phase offset between the SYNC input and the
output connected to the FEEDBACK input, measured at
the input pins. The t
varies with process, temperature, and voltage. The specs
were arrived at by measuring the phase relationship for
spec describes how this offset
terminatedattheFEEDBACKinputwith100ΩtoV
100Ω to ground.
and
PD
CC
MOTOROLA
12
TIMING SOLUTIONS
BR1333 — Rev 6
MC88915TFN55/70/100/133/160
ANALOG VCC
RC1
EXTERNAL LOOP FILTER
330
1M
Ω
RC1
R2
REFERENCE
RESISTOR
Ω
R2
C1
330
Ω
1M
Ω
REFERENCE
RESISTOR
0.1
µ
F
0.1µF
C1
ANALOG GND
ANALOG GND
With the 1M
measured at the input pins is:
Ω
resistor tied in this fashion, the t specification
PD
With the 1M
measured at the input pins is:
Ω
resistor tied in this fashion, the t specification
PD
t
= 2.25ns
±
1.0ns
t
= –0.775ns ± 0.275ns
PD
PD
3.0V
3.0V
SYNC INPUT
SYNC INPUT
–0.775ns OFFSET
2.25ns OFFSET
5.0V
5.0V
FEEDBACK OUTPUT
FEEDBACK OUTPUT
Figure 2. Depiction of the Fixed SYNC to Feedback Offset (tPD) Which is
Present When a 1MΩ Resistor is Tied to VCC or Ground
5.Thet
specificationguaranteesthattherisingedges
distributionof these outputs are provided in table 2. When
taking the skew data, Q0 was used as a reference, so all
measurements are relative to thisoutput. Theinformation
in Table 2 is derived from measurements taken from the
14 process lots described in Note 1, over the temperature
and voltage range.
SKEWr
of outputs Q/2, Q0, Q1, Q2, Q3, and Q4 will always fall
within a 500ps window within one part. However, if the
relative position of each output within this window is not
specified, the 500 ps window must be added to each side
of the tPD specification limits to calculate the total
part–to–part skew. For this reason the absolute
–
(ps)
+
(ps)
Output
Q0
0
0
Q1
–72
–44
–40
–274
–16
–633
40
Q2
276
255
–34
250
–35
Q3
Q4
Q/2
2X_Q
Table 2. Relative Positions of Outputs Q/2, Q0–Q4, 2X_Q, Within the 500ps t
SKEWr
Spec Window
13
MOTOROLA
MC88915TFN55/70/100/133/160
6. Calculation of Total Output–to–Skew between
[–1.05ns – 0.32ns] = –1.37ns is the lower t limit, and
PD
multiple parts (Part–to–Part skew)
[–0.5ns + 0.32ns] = –0.18ns is the upper limit. Therefore
the worst case skew of output Q2 between any number of
parts is |(–1.37) – (–0.18)| = 1.19ns. Q2 has the worst
case skew distribution of any output, so 1.2ns is the
absolute worst case output–to–output skew between
multiple parts.
By combining the t
specification and the information in
PD
Note 5, the worst case output–to–output skew between
multiple 88915’s connected in parallel can be calculated.
This calculation assumes that all parts have a common
SYNC input clock with equal delay of that input signal to
each part. This skew value is valid at the 88915 output
pins only (equally loaded), it does not include PCB trace
delays due to varying loads.
7. Note 4 explains that the t
PD
specification was measured
and is guaranteed for the configuration of the Q/2 output
connected to the FEEDBACK pin and the SYNC input
running at 10MHz. The fixed offset (t ) as described
PD
With a 1MΩ resistor tied to analog V
as shown in note
above has some dependence on the input frequency and
at what frequency the VCO is running. The graphs of
Figure 3 demonstrate this dependence.
CC
spec. limits between SYNC and the Q/2 output
4, the t
PD
(connected to the FEEDBACK pin) are –1.05ns and
–0.5ns. To calculate the skew of any given output
between two or more parts, the absolute value of the
distribution of that output given in table 2 must be
The data presented in Figure 3 is from devices
representing process extremes, and the measurements
subtracted and added to the lower and upper t
limits respectively. For output Q2, [276 – (–44)] = 320ps is
the absolute value of the distribution. Therefore
spec
were also taken at the voltage extremes (V = 5.25V
PD
CC
and 4.75V). Therefore the data in Figure 3 is a realistic
representation of the variation of t
.
PD
–0.50
–0.5
–0.75
–1.0
tPD
tPD
SYNC to
FEEDBACK
(ns)
SYNC to
FEEDBACK
(ns)
–1.00
–1.25
–1.50
–1.5
–2.0
2.5
5.0
7.5
10.0
12.5
15.0
17.5
2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5
SYNC INPUT FREQUENCY (MHz)
SYNC INPUT FREQUENCY (MHz)
Figure 3a.
Figure 3b.
t
versus Frequency Variation for Q/2 Output Fed
t
versus Frequency Variation for Q4 Output Fed
PD
PD
Back, Including Process and Voltage Variation @ 25
°
C
Back, Including Process and Voltage Variation @ 25
°
C
(With 1M
Ω
Resistor Tied to Analog VCC)
(With 1M
Ω
Resistor Tied to Analog V
)
CC
3.5
3.0
2.5
2.0
1.5
1.0
0.5
3.5
3.0
2.5
tPD
SYNC to
FEEDBACK
(ns)
tPD
SYNC to
FEEDBACK
(ns)
2.0
1.5
1.0
0.5
2.5
5.0
7.5
10.0
12.5
15.0
17.5
0
5
10
15
20
25
SYNC INPUT FREQUENCY (MHz)
SYNC INPUT FREQUENCY (MHz)
Figure 3c.
Figure 3d.
t
versus Frequency Variation for Q/2 Output Fed
t
versus Frequency Variation for Q4 Output Fed
PD
Back, Including Process and Voltage Variation @ 25
(With 1M Resistor Tied to Analog GND)
PD
°
C
Back, Including Process and Voltage Variation @ 25
°
C
Ω
(With 1MΩ Resistor Tied to Analog GND)
MOTOROLA
14
TIMING SOLUTIONS
BR1333 — Rev 6
MC88915TFN55/70/100/133/160
8. The lock indicator pin (LOCK) will reliably indicate a
phase–locked condition at SYNC input frequencies down
to 10MHz. At frequencies below 10MHz, the frequency of
correction pulses going into the phase detector form the
SYNC andFEEDBACKpinsmaynotbesufficienttoallow
the lock indicator circuitry to accurately predict a
phase–locked conditition. The MC88915T is guaranteed
to provide stable phase–locked operation down to the
appropriate minimum input frequency given in Table 1,
even though the LOCK pin may be LOW at frequencies
below 10MHZ. The exact minimum frequency where the
lock indicator functionality can be guaranteed will be
available when the MC88915T reaches ‘MC’ status.
SYNC INPUT
(SYNC[1] or
SYNC[0])
t
SYNC INPUT
CYCLE
t
PD
FEEDBACK
INPUT
Q/2 OUTPUT
t
t
t
SKEWf
SKEWf
SKEWr
t
SKEWR
t
SKEWALL
Q0 – Q4
OUTPUTS
t
CYCLE “Q” OUTPUTS
Q5 OUTPUT
2X_Q OUTPUT
Figure 4. Output/Input Switching Waveforms and Timing Diagrams
(These waveforms represent the hook–up configuration of Figure 5a on page 16)
Timing Notes:
• The MC88915T aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does
not require a 50% duty cycle.
• All skew specs are measured between the V /2 crossing point of the appropriate output edges.All skews
CC
are specified as ‘windows’, not as a ± deviation around a center point.
• If a “Q” output is connected to the FEEDBACK input (this situation is not shown), the “Q” output frequency
would match the SYNC input frequency, the 2X_Q output would run at twice the SYNC frequency, and the
Q/2 output would run at half the SYNC frequency.
15
MOTOROLA
MC88915TFN55/70/100/133/160
100MHz SIGNAL
25MHz FEEDBACK SIGNAL
HIGH
1:2 Input to “Q” Output Frequency Relationship
In this application, the Q/2 output is connected to
the FEEDBACK input. The internal PLL will line up
the positive edges of Q/2 and SYNC, thus the Q/2
frequency will equal the SYNC frequency. The “Q”
outputs (Q0–Q4, Q5) will always run at 2X the Q/2
frequency, and the 2X_Q output will run at 4X the
Q/2 frequency.
RST
Q4
2X_Q
Q5
FEEDBACK
REF_SEL
SYNC[0]
Q/2
Q3
Q2
LOW
25MHz INPUT
CRYSTAL
OSCILLATOR
MC88915T
50MHz
“Q”
CLOCK
OUTPUTS
ANALOG V
CC
EXTERNAL
LOOP
RC1
FILTER
ANALOG GND
Allowable Input Frequency Range:
PLL_EN
FQ_SEL
HIGH
Q0
Q1
5MHz to (2X_Q FMAX Spec)/4 (for FREQ_SEL HIGH)
2.5MHz to (2X_Q FMAX Spec)/8 (for FREQ_SEL LOW)
Note: If the OE/RST input is active, a pull–up or pull–down re-
sistor isn’t necessary at the FEEDBACK pin so it won’t when
the fed back output goes into 3–state.
HIGH
Figure 5a. Wiring Diagram and Frequency Relationships With Q/2 Output Feed Back
100MHz SIGNAL
50MHz FEEDBACK SIGNAL
HIGH
1:1 Input to “Q” Output Frequency Relationship
RST
Q5
Q4
2X_Q
25MHz
SIGNAL
FEEDBACK
REF_SEL
SYNC[0]
Q/2
Q3
Q2
In this application, the Q4 output is connected to
the FEEDBACK input. The internal PLL will line up
the positive edges of Q4 and SYNC, thus the Q4
frequency (and the rest of the “Q” outputs) will
equal the SYNC frequency. The Q/2 output will al-
LOW
50MHZ INPUT
CRYSTAL
50MHz
“Q”
CLOCK
MC88915T
OSCILLATOR
ANALOG V
CC
EXTERNAL
LOOP
FILTER
RC1
OUTPUTS ways run at 1/2 the “Q” frequency, and the 2X_Q
output will run at 2X the “Q” frequency.
ANALOG GND
PLL_EN
FQ_SEL
HIGH
Q0
Q1
Allowable Input Frequency Range:
10MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL HIGH)
5MHz to (2X_Q FMAX Spec)/4 (for FREQ_SEL LOW)
HIGH
Figure 5b. Wiring Diagram and Frequency Relationships With Q4 Output Feed Back
100MHz FEEDBACK SIGNAL
HIGH
RST
Q4
2X_Q
Q/2
Q5
2:1 Input to “Q” Output Frequency Relationship
25MHz
SIGNAL
FEEDBACK
REF_SEL
SYNC[0]
LOW
In this application, the 2X_Q output is connected
to the FEEDBACK input. The internal PLL will line
up the positive edges of 2X_Q and SYNC, thus the
2X_Q frequency will equal the SYNC frequency.
The Q/2 output will always run at 1/4 the 2X_Q fre-
quency, and the “Q” outputs will run at 1/2 the
2X_Q frequency.
100MHz INPUT
MC88915T
CRYSTAL
Q3
Q2
50MHz
“Q”
CLOCK
OUTPUTS
OSCILLATOR
ANALOG V
CC
EXTERNAL
LOOP
FILTER
RC1
ANALOG GND
PLL_EN
Q1
FQ_SEL
HIGH
Q0
Allowable Input Frequency Range:
HIGH
20MHz to (2X_Q FMAX Spec) (for FREQ_SEL HIGH)
10MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL LOW)
Figure 5c. Wiring Diagram and Frequency Relationships with 2X_Q Output Feed Back
MOTOROLA
16
TIMING SOLUTIONS
BR1333 — Rev 6
MC88915TFN55/70/100/133/160
BOARD V
CC
47Ω
8
9
ANALOG V
CC
1MΩ
330
Ω
ANALOG LOOP FILTER/VCO
SECTION OF THE MC88915T
28–PIN PLCC PACKAGE (NOT
DRAWN TO SCALE)
0.1
µ
F HIGH
FREQ
10
µF LOW
RC1
FREQ BYPASS
BYPASS
0.1µF (LOOP
FILTER CAP)
10 ANALOG GND
47Ω
A SEPARATE ANALOG POWER SUPPLY IS NOT NECESSARY AND
SHOULDNOTBEUSED. FOLLOWINGTHESEPRESCRIBEDGUIDELINES
IS ALL THAT IS NECESSARY TO USE THE MC88915T IN A NORMAL
DIGITAL ENVIRONMENT.
BOARD GND
Figure 6. Recommended Loop Filter and Analog Isolation Scheme for the MC88915T
Notes Concerning Loop Filter and Board Layout Issues
1. Figure 6 shows a loop filter and analog isolation scheme
purpose of the bypass filtering scheme shown in Figure 6
which will be effective in most applications. The following
guidelines should be followed to ensure stable and
jitter–free operation:
is to give the 88915T additional protection from the power
supply and ground plane transients that can occur in a
high frequency, high speed digital system.
1a.All loop filter and analog isolation components should be
tied as close to the package as possible. Stray current
passing through the parasitics of long traces can cause
undesirable voltage transients at the RC1 pin.
1c.There are no special requirements set forth for the loop
filter resistors (1MΩ and 330Ω). The loop filter capacitor
(0.1µF) can be a ceramic chip capacitior, the same as a
standard bypass capacitor.
1b.The 47Ω resistors, the 10µF low frequency bypass
capacitor, andthe0.1µF high frequency bypass capacitor
form a wide bandwidth filter that will minimize the
88915T’s sensitivity to voltage transients from the system
1d.The 1M reference resistor injects current into the internal
charge pump of the PLL, causing a fixed offset between
the outputs and the SYNC input. This also prevents
excessive jitter caused by inherent PLL dead–band. If the
VCO (2X_Q output) is running above 40MHz, the 1MΩ
resistor provides the correct amount of current injection
into the charge pump (2–3µA). For the TFN55, 70 or 100,
if the VCO is running below 40MHz, a 1.5MΩ reference
resistor should be used (instead of 1MΩ).
digital V
supply and ground planes. This filter will
CC
typically ensure that a 100mV step deviation on the digital
supply will cause no more than a 100pS phase
V
CC
deviation on the 88915T outputs. A 250mV step deviation
on V using the recommended filter values should
CC
cause no more than a 250pS phase deviation; if a 25µF
bypass capacitor is used (instead of 10µF) a 250mV V
CC
2. In addition to the bypass capacitors used in the analog
step should cause no more than a 100pS phase
deviation.
filter of Figure 6, there should be a 0.1µF bypass
capacitorbetweeneachoftheother(digital)fourV
pins
CC
and the board ground plane. This will reduce output
switching noise caused by the 88915T outputs, in
addition to reducing potential for noise in the ‘analog’
section of the chip. These bypass capacitors should also
be tied as close to the 88915T package as possible.
If good bypass techniques are used on a board design
near components which may cause digital V
and
step deviations
CC
ground noise, the above described V
should not occur at the 88915T’s digital V
CC
supply. The
CC
17
MOTOROLA
MC88915TFN55/70/100/133/160
CPU
CMMU
CPU
CMMU
CMMU
CARD
MC88915T
PLL
2f
CLOCK
@ f
CMMU
CMMU
SYSTEM
CLOCK
SOURCE
CPU
CMMU
CMMU
CARD
CMMU
CPU
MC88915T
PLL
2f
DISTRIBUTE
CLOCK @ f
CMMU
CMMU
CLOCK @ 2f
AT POINT OF USE
MC88915T
PLL
MEMORY
CONTROL
2f
MEMORY
CARDS
CLOCK @ 2f
AT POINT OF USE
Figure 7. Representation of a Potential Multi–Processing Application Utilizing the MC88915T
for Frequency Multiplication and Low Board–to–Board Skew
MC88915T System Level Testing Functionality
3–state functionality has been added to the 100MHz version of the MC88915T to ease system board testing. Bringing the
OE/RST pin low will put all outputs (except for LOCK) into the high impedance state. As long as the PLL_EN pin is low, the
Q0–Q4, Q5, and the Q/2 outputs will remain reset in the low state after the OE/RST until a falling SYNC edge is seen. The 2X_Q
output will be the inverse of the SYNC signal in this mode. If the 3–state functionality will be used, a pull–up or pull–down resistor
must be tied to the FEEDBACK input pin to prevent it from floating when the fedback output goes into high impedance.
With the PLL_EN pin low the selected SYNC signal is gated directly into the internal clock distribution network, bypassing
and disabling the VCO. In this mode the outputs are directly driven by the SYNC input (per the block diagram). This mode can
also be used for low frequency board testing.
Note: If the outputs are put into 3–state during normal PLL operation, the loop will be broken and phase–lock will be lost. It will
take a maximum of 10mS (tLOCK spec) to regain phase–lock after the OE/RST pin goes back high.
MOTOROLA
18
TIMING SOLUTIONS
BR1333 — Rev 6
MC88915TFN55/70/100/133/160
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
ISSUE D
M
S
S
0.007 (0.180)
T
L–M
N
B
Y BRK
D
–N–
M
S
S
0.007 (0.180)
T
L–M
N
U
Z
–M–
–L–
W
D
S
S
S
0.010 (0.250)
T
L–M
N
X
G1
V
28
1
VIEW D–D
M
S
S
S
A
0.007 (0.180)
0.007 (0.180)
T
L–M
L–M
N
M
S
S
0.007 (0.180)
T
L–M
N
H
Z
M
S
T
N
R
K1
C
E
0.004 (0.100)
SEATING
PLANE
G
K
–T–
VIEW S
J
M
S
S
0.007 (0.180)
T
L–M
N
F
G1
S
S
S
0.010 (0.250)
T
L–M
N
VIEW S
NOTES:
INCHES
MILLIMETERS
1. DATUMS –L–, –M–, AND –N– DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM –T–, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
MIN
MAX
0.495
0.495
0.180
0.110
0.019
MIN
12.32
12.32
4.20
MAX
12.57
12.57
4.57
0.485
0.485
0.165
0.090
0.013
2.29
2.79
0.33
0.48
0.050 BSC
1.27 BSC
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
0.026
0.020
0.025
0.450
0.450
0.042
0.042
0.042
–––
0.032
–––
–––
0.456
0.456
0.048
0.048
0.056
0.020
10
0.66
0.51
0.64
11.43
11.43
1.07
1.07
1.07
–––
0.81
–––
–––
11.58
11.58
1.21
1.21
1.42
0.50
10
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
2
2
0.410
0.040
0.430
–––
10.42
1.02
10.92
–––
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
19
MOTOROLA
MC88915TFN55/70/100/133/160
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
P.O. Box 5405; Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
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51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MC88915T/D
◊
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