MC88916DW80R2 [IDT]
PLL Based Clock Driver, 88916 Series, 5 True Output(s), 1 Inverted Output(s), CMOS, PDSO20, PLASTIC, SOIC-20;
| 型号： | MC88916DW80R2 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PLL Based Clock Driver, 88916 Series, 5 True Output(s), 1 Inverted Output(s), CMOS, PDSO20, PLASTIC, SOIC-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总9页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document
from Logic Marketing
SEMICONDUCTOR TECHNICAL DATA
The MC88916 Clock Driver utilizes phase–locked loop technology to
lock its low skew outputs’ frequency and phase onto an input reference
clock. It is designed to provide clock distribution for CISC microprocessor
or single processor RISC systems. The RST_IN/RST_OUT(LOCK) pins
provide a processor reset function designed specifically for the
MC68/EC/LC030/040 microprocessor family. The 88916 comes in two
speed grades: 70 and 80MHz. These frequencies correspond to the
2X_Q maximum output frequency. The two grades should be ordered as
the MC88916DW70 and MC88916DW80, respectively.
LOW SKEW CMOS PLL
CLOCK DRIVER WITH
PROCESSOR RESET
• Provides Performance Required to Drive 68030 Microprocessor Family
as well as the 33 and 40MHz 68040 Microprocessors
• Three Outputs (Q0–Q2) With Output–Output Skew <500ps and Six
Outputs Total (Q0–Q2, Q3, 2X_Q,) With <1ns Skew Each Being Phase
and Frequency Locked to the SYNC Input
20
• The Phase Variation From Part–to–Part Between SYNC and the ‘Q’
1
Outputs Is Less Than 600ps (Derived From the T
Specification,
PD
Which Defines the Part–to–Part Skew)
• SYNC Input Frequency Range From 5MHZ to 2X_Q F
/4
Max
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
• Additional Outputs Available at 2X and ÷2 the System ‘Q’ Frequency.
Also a Q (180° Phase Shift) Output Available.
• All Outputs Have ±36mA Drive (Equal High and Low) CMOS Levels.
Can Drive Either CMOS or TTL Inputs. All Inputs Are TTL–Level
Compatible
• Test Mode Pin (PLL_EN) Provided for Low Frequency Testing
The PLL allows the high current, low skew outputs to lock onto a single clock input and distribute it with essentially zero delay
to multiple locations on a board. The PLL also allows the MC88916 to multiply a low frequency input clock and distribute it locally
at a higher (2X) system frequency.
Three ‘Q’ outputs (Q0–Q2) are provided with less than 500ps skew between their rising edges. The Q3 output is inverted (180°
phase shift) from the ‘Q’ outputs. A 2X_Q output runs at twice the ‘Q’ output frequency. The 2X_Q output does not meet the
stringent duty cycle requirement of the 20 and 25Mhz 68040 microprocessor PCLK input. The 88920 has been designed
specifically to provide the 68040 PCLK and BCLK inputs for the low frequency 68040 microprocessor. 68040 designers should
refer to the 88920 data sheet for more details. For the 33 and 40MHz 68040, the 2X_Q output will meet the duty cycle
requirements of the PCLK input. The Q/2 output runs at 1/2 the ‘Q’ frequency. This output is fed back internally, providing a fixed
2X multiplication from the ‘Q’ outputs to the SYNC input. Since the feedback is done internally (no external feedback pin is
provided) the input/output frequency relationships are fixed.
In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the
88916 in a static ‘test mode’. In this mode there is no frequency limitation on the input clock, which is necessary for a low
frequency board test environment.
The RST_OUT(LOCK) pin doubles as a phase–lock indicator. When the RST_IN pin is held high, the open drain RST_OUT
pin will be pulled actively low until phase–lock is achieved. When phase–lock occurs, the RST_OUT(LOCK) is released and a
pull–up resistor will pull the signal high. To give a processor reset signal, the RST_IN pin is toggled low, and the
RST_OUT(LOCK) pin will stay low for 1024 cycles of the ‘Q’ output frequency after the RST_IN pin is brought back high.
Description of the RST_IN/RST_OUT(LOCK) Functionality
The RST_IN and RST_OUT(LOCK) pins provide a 68030/040 processor reset function, with the RST_OUT pin also acting as
a lock indicator. If the RST_IN pin is held high during system power–up, the RST_OUT pin will be in the low state until steady
state phase/frequency lock to the input reference is achieved. 1024 ‘Q’ output cycles after phase–lock is achieved the
RST_OUT(LOCK) pin will go into a high impedance state, allowing it to be pulled high by an external pull–up resistor (see the
AC/DC specs for the characteristics of the RST_OUT(LOCK) pin). If the RST_IN pin is held low during power–up, the
RST_OUT(LOCK) pin will remain low.
11/93
REV 2
1
Motorola, Inc. 1995
MC88916
1
20
Q3
CC
GND
2
3
19
18
17
16
15
14
13
12
11
V
2X_Q
Q/2
MR
4
RST_IN
V
CC
5
V
(AN)
RC1
Q2
CC
6
GND
7
GND(AN)
SYNC
GND
RST_OUT(LOCK)
PLL_EN
8
9
Q1
10
Q0
V
CC
Pinout: 20–Lead Wide SOIC Package (Top View)
Description of the RST_IN/RST_OUT(LOCK) Functionality (continued)
After the system start–up is complete and the 88916 is
phase–locked to the SYNC input signal (RST_OUT high), the
processor reset functionality can be utilized. When the
RST_IN pin is toggled low (min. pulse width=10nS),
RST_OUT(LOCK) will go to the low state and remain there
for 1024 cycles of the ‘Q’ output frequency (512 SYNC
cycles). During the time in which the RST_OUT(LOCK) is
actively pulled low, all the 88916 clock outputs will continue
operating correctly and in a locked condition to the SYNC
input (clock signals to the 68030/040 family of processors
must continue while the processor is in reset). A propagation
delay after the 1024th cycle RST_OUT(LOCK) goes back to
the high impedance state to be pulled high by the resistor.
phase–lock to the reference source, some constraints must
be placed on the power supply ramp rate to make sure the
RST_OUT(LOCK) signal holds the processor in reset during
system start–up (power–up). With the recommended loop
filter values (see Figure 7) the lock time is approximately
10ms. The phase–lock loop will begin attempting to lock to a
reference source (if it is present) when VCC reaches 2V. If
the V
ramp rate is significantly slower than 10ms, then the
CC
PLL could lock to the reference source, causing
RST_OUT(LOCK) to go high before the 88916 and 68030
processor is fully powered up, violating the processor reset
specification. Therefore, if it is necessary for the RST_IN pin
to be held high during power–up, the V
ramp rate must be
CC
less than 10mS for proper 68030/040 reset operation.
This ramp rate restriction can be ignored if the RST_IN pin
can be held low during system start–up (which holds
RST_OUT low). The RST_OUT(LOCK) pin will then be
pulled back high 1024 cycles after the RST_IN pin goes high.
Power Supply Ramp Rate Restriction for Correct 68030
Processor Reset Operation During System Start–up
Because the RST_OUT(LOCK) pin is an indicator of
CAPACITANCE AND POWER SPECIFICATIONS
Symbol
Parameter
Input Capacitance
Value Typ
Unit
pF
Test Conditions
C
C
4.5
40
V
CC
V
CC
V
CC
= 5.0V
= 5.0V
= 5.0V
IN
PD
Power Dissipation Capacitance
pF
PD
Power Dissipation at 33MHz With 50Ω
Thevenin Termination
15mW/Output
90mW/Device
mW
1
T = 25°C
PD
Power Dissipation at 33MHz With 50Ω
Parallel Termination to GND
37.5mW/Output
225mW/Device
mW
V = 5.0V
CC
T = 25°C
2
MOTOROLA
2
MC88916
MAXIMUM RATINGS*
Symbol
Parameter
DC Supply Voltage Referenced to GND
Limits
Unit
V
V
V
, AV
CC
–0.5 to 7.0
CC
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, Per Pin
–0.5 to V
+0.5
V
in
CC
CC
V
out
–0.5 to V
+0.5
V
I
I
I
±20
mA
mA
mA
°C
in
DC Output Sink/Source Current, Per Pin
±50
±50
out
CC
DC V
or GND Current Per Output Pin
CC
T
stg
Storage Temperature
–65 to +150
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Limits
Unit
V
V
V
Supply Voltage
5.0 ±10%
CC
DC Input Voltage
0 to V
0 to V
V
in
CC
CC
V
out
DC Output Voltage
V
T
Ambient Operating Temperature
Static Discharge Voltage
–40 to 85
> 1500
°C
V
A
ESD
DC CHARACTERISTICS (T = –40°C to +85°C; V
= 5.0V ± 5%)
A
CC
Symbol
Parameter
V
CC
Guaranteed Limits
Unit
Condition
V
IH
Minimum High Level Input Voltage
4.75
5.25
2.0
2.0
V
V
= 0.1V or
OUT
V
CC
– 0.1V
V
Minimum Low Level Input Voltage
Minimum High Level Output Voltage
4.75
5.25
0.8
0.8
V
V
V
= 0.1V or
OUT
IL
V
CC
– 0.1V
V
OH
4.75
5.25
4.01
4.51
V
= V or V
IH IL
IN
I
OH
–36mA
–36mA
V
Minimum Low Level Output Voltage
Maximum Input Leakage Current
4.75
5.25
0.44
0.44
V
V
= V or V
IH
OL
IN
IL
1
I
OH
+36mA
+36mA
I
I
I
I
5.25
5.25
5.25
5.25
5.25
±1.0
µA
mA
mA
mA
µA
V = V , GND
I
IN
CC
2
Maximum I /Input
CC
2.0
V = V
I
– 2.1V
CCT
OLD
OHD
CC
3
Minimum Dynamic Output Current
88
V
OLD
V
OHD
= 1.0V Max
= 3.85 Min
–88
750
I
Maximum Quiescent Supply Current
is +12mA for the RST_OUT output.
V = V , GND
I CC
CC
1. I
OL
2. The PLL_EN input pin is not guaranteed to meet this specification.
3. Maximum test duration 2.0ms, one output loaded at a time.
3
MOTOROLA
MC88916
RST_OUT
LOCK INDICATOR AND
RESET_OUT 1024 CYCLE
COUNT CIRCUITRY
2X_Q
Q0
RST_IN
SYNC
D
D
D
D
D
Q
Q
CH
PUMP
PFD
VCO
R
R
R
R
R
Q
Q
Q1
Q2
Q3
Q/2
PLL_EN
0
1
Q
Q
Q
Q
POWER–ON
RESET
Q
Q
MR
Figure 1. MC88916 Logic Block Diagram
SYNC INPUT TIMING REQUIREMENTS
Symbol
Parameter
Minimum
Maximum
Unit
t
Rise/Fall Time, SYNC Input
RISE/FALL
SYNC Input
—
5.0
ns
From 0.8V to 2.0V
Input Clock Period
SYNC Input
‘DW70
57
‘DW80
50
t
,
CYCLE
200
ns
SYNC Input
Duty Cycle
Duty Cycle, SYNC Input
50% ± 25%
FREQUENCY SPECIFICATIONS (T = –40°C to +85°C; V
= 5.0V ± 5%)
CC
A
Guaranteed Minimum
MC88916DW70 MC88916DW80
70 80
35 40
Symbol
Fmax (2X_Q)
Fmax (‘Q’)
Parameter
Maximum Operating Frequency, 2X_Q Output
Maximum Operating Frequency, Q0–Q2, Q3 Outputs
Unit
MHz
MHz
1. Maximum Operating Frequency is guaranteed with the 88916 in a phase–locked condition, and all outputs loaded at 50Ω terminated to V /2.
CC
MOTOROLA
4
MC88916
AC CHARACTERISTICS (T = –40°C to +85°C; V
= 5.0V ± 5%)
CC
A
Symbol
Parameter
Mimimum
Maximum
Unit
Condition
1
t
Rise/Fall Time, All Outputs into a 50Ω
Load
0.3
1.6
ns
t
t
– 0.8V to 2.0V
– 2.0V to 0.8V
RISE/FALL
RISE
FALL
All Outputs
1
t
Rise/Fall Time into a 20pF Load, With
Termination Specified in AppNote 3
0.5
1.6
ns
ns
ns
t
t
– 0.8V to 2.0V
– 2.0V to 0.8V
RISE/FALL
2X_Q Output
RISE
FALL
1
t
Output Pulse Width
0.5t
– 0.5
0.5t
+ 0.5
50Ω Load Terminated to
V /2 (See App Note 3)
pulse width(a)
(Q0, Q1, Q2, Q3)
cycle
cycle
Q0, Q1, Q2, Q3 at V /2
CC
CC
50Ω Load Terminated to
V /2 (See App Note 3)
CC
1
5
5
5
5
t
Output Pulse Width
40–49MHz 0.5t
50–65MHz 0.5t
66–80MHz
– 1.5
– 1.0
0.5t
0.5t
0.5t
+ 1.5
+ 1.0
pulse width(b)
(2X_Q Output)
cycle
cycle
cycle
cycle
cycle
cycle
2X_Q at V /2
CC
0.5t
– 0.5
+ 0.5
1,4
t
SYNC Input to Q/2 Output Delay
(Measured at SYNC and Q/2 Pins)
–0.75
–0.15
ns
ns
ps
With 1MΩ From RC1
to An V
(See Application Note 2)
PD
SYNC – Q/2
CC
7
7
+1.25
—
+3.25
500
With 1MΩ From RC1
to An GND
(See Application Note 2)
1,2
1,2
t
Output–to–Output Skew
Between Outputs Q0–Q2, Q/2
(Rising Edge Only)
Into a 50Ω Load
SKEWr
(Rising)
Terminated to V /2
CC
(See Timing Diagram in
Figure 6)
t
Output–to–Output Skew
Between Outputs Q0–Q2
(Falling Edge Only)
—
—
1.0
1.0
ns
ns
Into a 50Ω Load
SKEWf
(Falling)
Terminated to V /2
CC
(See Timing Diagram in
Figure 6)
1,2
t
Output–to–Output Skew
2X_Q, Q/2, Q0–Q2 Rising
Q3 Falling
Into a 50Ω Load
SKEWall
Terminated to V /2
CC
(See Timing Diagram in
Figure 6)
3
t
t
Phase–Lock Acquisition Time,
All Outputs to SYNC Input
1
10
ms
ns
LOCK
MR – Q
Propagation Delay,
MR to Any Output (High–Low)
1.5
13.5
Into a 50Ω Load
PHL
Terminated to V /2
CC
(See Timing Diagram in
Figure 6)
t
, MR to
Reset Recovery Time rising MR edge
to falling SYNC edge
9
—
ns
REC
6
SYNC
6
t
t
t
, MR LOW
Minimum Pulse Width, MR input Low
Minimum Pulse Width, RST_IN Low
5
—
—
ns
ns
ns
W
, RST_IN LOW
10
1.5
When in Phase–Lock
W
Output Enable Time
RST_IN Low to RST_OUT Low
16.5
See Application
Note 5
PZL
t
Output Enable Time
RST_IN High to RST_OUT High Z
1016 ‘Q’ Cycles
(508 Q/2 Cycles) (512 Q/2 Cycles)
1024 ‘Q’ Cycles
ns
See Application
Note 5
PLZ
1. These specifications are not tested, they are guaranteed by statistical characterization. See Application Note 1 for a discussion of this
methodology.
2. Under equally loaded conditions and at a fixed temperature and voltage.
3. With V
fully powered–on: t
Max is with C1 = 0.1µF; t
Min is with C1 = 0.01µF.
CC
CLOCK
LOCK
4. See Application Note 4 for the distribution in time of each output referenced to SYNC.
5. Limits do not meet requirements of the 68040 microprocessor. Refer to the 88920 for a low frequency 68040 clock driver.
6. Specification is valid only when the PLL_EN pin is low.
7. This is a typical specification only, worst case guarantees are not provided.
5
MOTOROLA
MC88916
Application Notes
1. Several specifications can only be measured when the
MC88916 is in phase–locked operation. It is not possible
to have the part in phase–lock on ATE (automated test
equipment). Statistical characterization techniques were
used to guarantee those specifications which cannot be
measured on the ATE. MC88916 units were fabricated
with key transistor properties intentionally varied to create
a 14 cell designed experimental matrix. IC performance
was characterized over a range of transistor properties
(represented by the 14 cells) in excess of the expected
process variation of the wafer fabrication area. IC
performance to each specification and fab variation were
used to set performance limits of ATE testable
specifications within those which are to be guaranteed by
statistical characterization. In this way, all units passing
the ATE test will meet or exceed the non–tested
specifications limits.
3. The pulse width spec for the Q and 2Q_X outputs is
referenced to a V /2 threshold. To translate this down to
CC
a 1.5V reference with the same pulse width tolerance, the
termination scheme pictured in Figure 3 must be used.
This termination scheme is required to drive the PCLK
input of the 68040 microprocessor with the 88916 outputs.
4. The t
spec (SYNC to Q/2) guarantees how close the
PD
Q/2 output will be locked to the reference input connected
to the SYNC input (including temperature and voltage
variation). This also tells what the skew from the Q/2
output on one part connected to a given reference input, to
the Q/2 output on one or more parts connected to that
reference input (assuming equal delay from the reference
input to the SYNC input of each part). Therefore the t
PD
spec is equivalent to a part–to–part specification.
However, to correctly predict the skew from a given output
on one part to any other output on one or more other parts,
the distribution of each output in relation to the SYNC
input must be known. This distribution for the MC88916 is
provided in Table 1.
2. A 1MΩ resistor tied to either Analog V
or Analog GND,
CC
as shown in Figure 2, is required to ensure no jitter is
present on the MC88916 outputs. This technique causes
a phase offset between the SYNC input and the Q0
TABLE 1. Distribution of Each Output versus SYNC
output, measured at the pins. The t
spec describes how
PD
this offset varies with process, temperature, and voltage.
The specs were arrived at by measuring the phase
relationship for the 14 lots described in note 1 while the
part was in phase–locked operation. The actual
measurements were made with a 10MHz SYNC input
(1.0ns edge rate from 0.8V to 2.0V). The phase
measurements were made at 1.5V. See Figure 2 for a
graphical description.
Output
–(ps)
+(ps)
2X_Q
Q0
Q1
Q2
Q3
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Q/2
RC1
ANALOG V
CC
RC1
EXTERNAL
LOOP FILTER
1M
330
Ω
REFERENCE
RESISTOR
R2
C1
330
Ω
R2
C1
1M
0.1µF
REFERENCE
RESISTOR
0.1µF
ANALOG GND
ANALOG GND
WITH THE 1MΩ RESISTOR TIED IN THIS FASHION THE T
WITH THE 1M
Ω
RESISTOR TIED IN THIS FASHION THE T
SPECIFICATION, MEASURED AT THE INPUT PINS IS:
PD
PD
SPECIFICATION, MEASURED AT THE INPUT PINS IS:
t
= 2.25ns
±
1.0ns (TYPICAL VALUES)
3V
t
= –0.80ns 0.30ns
±
PD
PD
3V
–0.8ns
OFFSET
SYNC INPUT
Q0 OUTPUT
SYNC INPUT
Q0 OUTPUT
2.25ns
OFFSET
5V
5V
Figure 2. Depiction of the Fixed SYNC to Q0 Offset (t ) Which Is Present
PD
or Ground
When a 1MΩ Resistor Is Tied to V
CC
MOTOROLA
6
MC88916
Zo (CLOCK
TRACE)
68040
PCLK
CLOCK
INPUT
88916
2X_Q
OUTPUT
Rs
R
P
Rs = Zo – 7
Ω
R
= 1.5Zo
P
Figure 3. MC68040 PCLK Input Termination Scheme
16.5MHz
CRYSTAL
2X_Q
66MHz PCLK OUTPUT
RST_OUT PIN
V
CC
SYNC
OSCILLATOR
Q0
Q1
Q2
1K
33MHz
B–CLOCK
AND SYSTEM
OUTPUTS
INTERNAL
LOGIC
MR
C
L
PLL_EN
RST_IN
Q3
Q/2
RST_OUT
ANALOG GND
Figure 4. RST_OUT Test Circuit
Figure 5. Logical Representation of the MC88916 With
Input/Output Frequency Relationships
SYNC Input
t
SYNC Input
CYCLE
t
t
t
t
t
SKEWr
SKEWall
SKEWf
SKEWr
SKEWf
Q0–Q2 Outputs
Q3 Output
t
‘Q’ Outputs
CYCLE
2X_Q Output
Q/2 Output
Figure 6. Output/Input Switching Waveforms and Timing Relationships
Timing Notes
1. The MC88916 aligns rising edges of the outputs and the SYNC input, therefore the SYNC input does not require a 50%
duty cycle.
2. All skew specs are measured between the V /2 crossing point of the appropriate output edges. All skews are specified as
CC
‘windows’, not as a ± deviation around a center point.
7
MOTOROLA
MC88916
The t
spec includes the full temperature range from 0°C
to 70°C and the full V range from 4.75V to 5.25V. If the
5. The RST_OUT pin is an open drain N–Channel output.
Therefore an external pull–up resistor must be provide to
pull up the RST_OUT pin when it goes into the high
impedance state (after the MC88916 is phase–locked to
the reference input with RST_IN held high or 1024 ‘Q’
cycles after the RST_IN pin goes high when the part is
PD
CC
in a given system are less than the
∆T and ∆V
specification limits, the t
CC
spec window will be reduced.
is given by the
PD
window for a given ∆T and ∆V
The t
PD
following regression formula:
CC
locked). In the t
and t
specifications, a 1KΩ resistor
PLZ
is used as a pull–up as shown in Figure 4.
PZL
TBD
Notes Concerning Loop Filter and Board Layout Issues
1. Figure 7 shows a loop filter and analog isolation scheme
is to give the 88916 additional protection from the power
supply and ground plane transients that can occur in a
high frequency, high speed digital system.
which will be effective in most applications. The following
guidelines should be followed to ensure stable and
jitter–free operation:
1c. There are no special requirements set forth for the loop
filter resistors (1M and 330Ω). The loop filter capacitor
(0.1uF) can be a ceramic chip capacitor, the same as a
standard bypass capacitor.
1a. All loop filter and analog isolation components should be
tied as close to the package as possible. Stray current
passing through the parasitics of long traces can cause
undesirable voltage transients at the RC1 pin.
1d. The 1M reference resistor injects current into the internal
charge pump of the PLL, causing a fixed offset between
the outputs and the SYNC input. This also prevents
excessive jitter caused by inherent PLL dead–band. If the
VCO (2X_Q output) is running above 40MHz, the 1M
resistor provides the correct amount of current injection
into the charge pump (2–3µA). If the VCO is running
below 40MHz, a 1.5MΩ reference resistor should be
used.
1b. The 47Ω resistors, the 10µF low frequency bypass
capacitor, and the 0.1µF high frequency bypass capacitor
form a wide bandwidth filter that will make the 88916 PLL
insensitive to voltage transients from the system digital
V
supply and ground planes. This filter will typically
CC
ensure that a 100mV step deviation on the digital V
CC
supply will cause no more than a 100ps phase deviation
on the 88916 outputs. A 250mV step deviation on V
CC
using the recommended filter values will cause no more
than a 250ps phase deviation; if a 25µF bypass capacitor
2. In addition to the bypass capacitors used in the analog
is used (instead of 10µF) a 250mV V
CC
more than a 100ps phase deviation.
step will cause no
filter of Figure 7, there should be a 0.1µF bypass
capacitor between each of the other (digital) four V
CC
If good bypass techniques are used on a board design
near components which may cause digital V and
pins and the board ground plane. This will reduce output
switching noise caused by the 88916 outputs, in addition
to reducing potential for noise in the ‘analog’ section of
the chip. These bypass capacitors should also be tied as
close to the 88916 package as possible.
CC
step deviations
ground noise, the above described V
should not occur at the 88916’s digital V
CC
supply. The
purpose of the bypass filtering scheme shown in Figure 7
CC
BOARD V
CC
47Ω
5
ANALOG V
CC
1MΩ
330
Ω
ANALOG LOOP FILTER/VCO
SECTION OF THE MC88916
20–PIN SOIC PACKAGE (NOT
DRAWN TO SCALE)
10µF LOW
0.1µF HIGH
6
7
RC1
FREQ BIAS
FREQ BIAS
0.1µF (LOOP
FILTER CAP)
ANALOG GND
47Ω
A SEPARATE ANALOG POWER SUPPLY IS NOT NECESSARY AND
SHOULD NOT BE USED. FOLLOWING THESE PRESCRIBED GUIDE-
LINESIS ALL THAT IS NECESSARY TO USE THE MC88916 IN A NORMAL
DIGITAL ENVIRONMENT.
BOARD GND
Figure 7. Recommended Loop Filter and Analog Isolation Scheme for the MC88916
MOTOROLA
8
MC88916
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
–A
–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
20
11
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
–B
–
P 10 PL
M
M
0.010 (0.25)
B
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
1
10
D 20 PL
J
MILLIMETERS
INCHES
M
S
S
0.010 (0.25)
T
A
B
DIM
A
B
C
D
MIN
12.65
7.40
2.35
0.35
0.50
MAX
12.95
7.60
2.65
0.49
0.90
MIN
MAX
0.510
0.299
0.104
0.019
0.035
0.499
0.292
0.093
0.014
0.020
F
F
R X 45°
G
J
K
1.27 BSC
0.050 BSC
0.25
0.10
0.32
0.25
0.010
0.004
0.012
0.009
C
M
P
R
0
°
7
°
0
°
7°
0.415
0.029
10.05
0.25
10.55
0.75
0.395
0.010
–T
M
–
SEATING
PLANE
K
G 18 PL
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
andspecificallydisclaimsanyandallliability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintendedor unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us:
USA/EUROPE: Motorola Literature Distribution;
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447
6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315
HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
CODELINE
MC88916/D
◊
相关型号：
MC88920DWR2
88920 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO20, PLASTIC, SOIC-20
MOTOROLA
MC88920DWR2
PLL Based Clock Driver, 88920 Series, 5 True Output(s), 1 Inverted Output(s), CMOS, PDSO20, PLASTIC, SOIC-20
IDT
MC88921DWR2
88921 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20, PLASTIC, SOIC-20
MOTOROLA
©2020 ICPDF网 联系我们和版权申明