MC88921 [MOTOROLA]
LOW SKEW CMOS PLL CLOCK DRIVER With Power-Down/ Power-Up Feature; 低偏移CMOS PLL时钟驱动器具有掉电/启动功能
| 型号： | MC88921 |
| 厂家： | 
MOTOROLA |
| 描述： | LOW SKEW CMOS PLL CLOCK DRIVER With Power-Down/ Power-Up Feature |
| 文件： | 总10页 (文件大小：110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SEMICONDUCTOR TECHNICAL DATA
The MC88921 Clock Driver utilizes phase–locked loop technology to
lock its low skew outputs’ frequency and phase onto an input reference
clock. It is designed to provide clock distribution for CISC microprocessor
or single processor RISC systems.
LOW SKEW CMOS PLL
CLOCK DRIVER
With Power–Down/
Power–Up Feature
The PLL allows the high current, low skew outputs to lock onto a single
clock input and distribute it with essentially zero delay to multiple
locations on a board. The PLL also allows the MC88921 to multiply a low
frequency input clock and distribute it locally at a higher (2X) system
frequency.
• 2X_Q Output Meets All Requirements of the 20, 25 and 33MHz 68040
Microprocessor PCLK Input Specifications
• 60 and 66MHz Output to Drive the Pentium Microprocessor
• Four Outputs (Q0–Q3) With Output–Output Skew <500ps and Six
Outputs Total (Q0–Q3, 2X_Q) With <1ns Skew Each Being Phase and
Frequency Locked to the SYNC Input
20
• The Phase Variation From Part–to–Part Between SYNC and the ‘Q’
1
Outputs Is Less Than 600ps (Derived From the T
Which Defines the Part–to–Part Skew)
Specification,
PD
• SYNC Input Frequency Range From 5MHZ to 2X_Q F
/4
Max
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
• Additional Outputs Available at 2X the System ‘Q’ Frequency
• All Outputs Have ±36mA Drive (Equal High and Low) CMOS Levels.
Can Drive Either CMOS or TTL Inputs. All Inputs Are TTL–Level
Compatible
• Test Mode Pin (PLL_EN) Provided for Low Frequency Testing
• Special Power–Down Mode With 2X_Q, Q0, and Q1 Being Reset (With
MR), and Other Outputs Remain Running. 2X_Q, Q0 and Q1 Are
Guaranteed to Be in Lock 3 Clock Cycles After MR Is Negated
Four ‘Q’ outputs (Q0–Q3) are provided with less than 500ps skew between their rising edges. A 2X_Q output runs at twice the
‘Q’ output frequency. The 2X_Q output is ideal for 68040 systems which require a 2X processor clock input. The 2X_Q output
meets the tight duty cycle spec of the 20, 25 and 33MHz 68040. The 66MHz 2X_Q output can also be used for driving the clock
input of the Pentium Microprocessor while providing multiple 33MHz outputs to drive the support and bus logic. The FBSEL pin
allows the user to internally feedback either the Q or the Q/2 frequency providing a 1x or 2x multiplication factor of the reference
input.
In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the
88921 in a static ‘test mode’. In this mode there is no frequency limitation on the input clock, which is necessary for a low
frequency board test environment.
A lock indicator output (LOCK) will go HIGH when the loop is in steady state phase and frequency lock. The output will go LOW
if phase–lock is lost or when the PLL_EN pin is LOW. The lock output will go HIGH no later than 10ms after the 88921 sees a sync
signal and full 5.0V V
.
CC
Pentium is a trademark of the Intel Corporation.
8/95
REV 2
1
Motorola, Inc. 1995
MC88921
1
20
Q3
CC
GND
2
3
19
18
17
16
15
14
13
12
11
V
2X_Q
Q/2
MR
Power–Down Mode Functionality
The MC88921 has a special feature
designed in to allow the processor clock
inputs to be reset for total processor
power–down, and then to return to
phase–lockedoperationveryquicklywhen
the processor is powered–up again.
The MR pin resets outputs 2X_Q, Q0
and Q1 only leaving the other outputs
operationalfor other system activity. When
MR is negated, all outputs will beoperating
normally within 3 clock cycles.
4
PLL_EN
V
CC
5
V
(AN)
RC1
Q2
CC
6
GND
LOCK
FBSEL
Q1
7
GND(AN)
SYNC
GND
8
9
10
Q0
V
CC
Pinout: 20–Lead Wide SOIC Package (Top View)
CAPACITANCE AND POWER SPECIFICATIONS
Symbol
Parameter
Input Capacitance
Value Typ
Unit
pF
Test Conditions
C
C
4.5
40
V
CC
V
CC
V
CC
= 5.0V
= 5.0V
= 5.0V
IN
PD
Power Dissipation Capacitance
pF
PD
Power Dissipation at 33MHz With 50Ω
Thevenin Termination
15mW/Output
90mW/Device
mW
1
T = 25°C
PD
Power Dissipation at 33MHz With 50Ω
Parallel Termination to GND
37.5mW/Output
225mW/Device
mW
V = 5.0V
CC
T = 25°C
2
MAXIMUM RATINGS*
Symbol
Parameter
DC Supply Voltage Referenced to GND
Limits
Unit
V
V
V
, AV
CC
–0.5 to 7.0
CC
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, Per Pin
–0.5 to V
+0.5
V
in
CC
CC
V
out
–0.5 to V
+0.5
V
I
I
I
±20
mA
mA
mA
°C
in
DC Output Sink/Source Current, Per Pin
±50
±50
out
CC
DC V
or GND Current Per Output Pin
CC
T
stg
Storage Temperature
–65 to +150
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the
Recommended Operating Conditions.
MOTOROLA
2
MC88921
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Limits
Unit
V
V
Supply Voltage
5.0 ±10%
CC
in
V
DC Input Voltage
0 to V
0 to V
V
CC
CC
V
out
DC Output Voltage
V
T
Ambient Operating Temperature
Static Discharge Voltage
0 to 70
> 1500
°C
V
A
ESD
DC CHARACTERISTICS (T = –40°C to 85°C; V
= 5.0V ± 5%)
CC
A
Symbol
Parameter
V
Guaranteed Limits
Unit
Condition
= 0.1V or
OUT
CC
V
IH
Minimum High Level Input Voltage
4.75
5.25
2.0
2.0
V
V
V
– 0.1V
CC
V
Minimum Low Level Input Voltage
Minimum High Level Output Voltage
4.75
5.25
0.8
0.8
V
V
V
= 0.1V or
OUT
IL
V
CC
– 0.1V
V
OH
4.75
5.25
4.01
4.51
V
= V or V
IH IL
IN
I
OH
–36mA
–36mA
V
Minimum Low Level Output Voltage
Maximum Input Leakage Current
4.75
5.25
0.44
0.44
V
V
= V or V
IH
OL
IN
IL
1
I
OH
+36mA
+36mA
I
I
I
I
5.25
5.25
5.25
5.25
5.25
±1.0
µA
mA
mA
mA
µA
V = V , GND
I
IN
CC
2
Maximum I /Input
CC
2.0
V = V
I
– 2.1V
CCT
OLD
OHD
CC
3
Minimum Dynamic Output Current
88
V
OLD
V
OHD
= 1.0V Max
= 3.85 Min
–88
750
I
Maximum Quiescent Supply Current
V = V , GND
I CC
CC
1. I
2.
is +12mA for the LOCK output.
OL
The PLL_EN input pin is not guaranteed to meet this specification.
3. Maximum test duration 2.0ms, one output loaded at a time.
SYNC INPUT TIMING REQUIREMENTS
Symbol
Parameter
Minimum
Maximum
Unit
t
Rise/Fall Time, SYNC Input
From 0.8V to 2.0V
RISE/FALL
SYNC Input
—
5.0
ns
t
,
Input Clock Period
SYNC Input
1
CYCLE
200
ns
f
4
SYNC Input
2X_Q
Duty Cycle
Duty Cycle, SYNC Input
50% ± 25%
3
MOTOROLA
MC88921
LOCK
2X_Q
LOCK INDICATOR
RC1
D
D
D
D
Q
Q
Q
Q0
Q1
Q2
SYNC1
R
R
R
R
CH
PUMP
PFD
VCO
PLL_EN
0
1
POWER–ON
RESET
÷
2
Q
Q
“Dummy” Flip–Flop to Maintain
Phase–Locked Operation
MR
D
D
Q
Q
Q3
R
R
Q/2
FBSEL
0
1
Figure 1. MC88921 Logic Block Diagram
FREQUENCY SPECIFICATIONS (T = –40°C to 85°C; V = 5.0V ± 5%)
A
CC
Symbol
Fmax (2X_Q)
Fmax (‘Q’)
Parameter
Guaranteed Minimum
Unit
Maximum Operating Frequency, 2X_Q Output
66
33
MHz
MHz
Maximum Operating Frequency,
Q0–Q3 Outputs
1. Maximum Operating Frequency is guaranteed with the 88921 in a phase–locked condition, and all outputs loaded at 50pF.
MOTOROLA
4
MC88921
AC CHARACTERISTICS (T = –40°C to 85°C; V
= 5.0V ± 5%)
CC
A
Symbol
Parameter
Minimum
Maximum
Unit
Condition
1
t
Rise/Fall Time, All Outputs into 50Ω
Load
0.3
1.6
ns
t
t
– 0.8V to 2.0V
– 2.0V to 0.8V
RISE/FALL
RISE
FALL
All Outputs
1
t
Rise/Fall Time into a 20pF Load, With
Termination Specified in AppNote 3
0.5
1.6
ns
ns
t
t
– 0.8V to 2.0V
– 2.0V to 0.8V
RISE/FALL
2X_Q Output
RISE
FALL
1
5
5
5
5
t
Output Pulse Width
0.5t
0.5t
– 0.5
0.5t
+ 0.5
50Ω Load Terminated to
V /2 (See Application
CC
Note 3)
pulse width(a)
(Q0, Q1, Q2, Q3)
cycle
cycle
Q0, Q1, Q2, Q3 at V /2
CC
1
t
Output Pulse Width
– 0.5
0.5t
+ 0.5
ns
ns
ns
ps
50Ω Load Terminated to
V
Note 3)
pulse width(b)
(2X_Q Output)
cycle
cycle
2X_Q at V /2
/2 (See Application
CC
CC
1,4
t
SYNC Input to Q Output Delay
(Measured at SYNC and Q/2 Pins)
–0.75
–0.15
With 1MΩ From RC1
to An V
(See Application Note 2)
PD
SYNC – Q/2
CC
7
7
+1.25
—
+3.25
500
With 1MΩ From RC1
to An GND
(See Application Note 2)
1,2
1,2
t
Output–to–Output Skew
Between Outputs Q0–Q3
(Rising Edge Only)
Into a 50Ω Load
Terminated to V /2
(See Timing Diagram in
Figure 6)
SKEWr
(Rising)
CC
t
Output–to–Output Skew
Between Outputs Q0–Q3
(Falling Edge Only)
—
—
1.0
1.0
ns
ns
Into a 50Ω Load
Terminated to V /2
(See Timing Diagram in
Figure 6)
SKEWf
(Falling)
CC
1,2
t
Output–to–Output Skew
2X_Q, Q0–Q3 Rising
Into a 50Ω Load
Terminated to V /2
(See Timing Diagram in
Figure 6)
SKEWall
CC
3
t
t
t
Phase–Lock Acquisition Time,
All Outputs to SYNC Input
1
1.5
9
10
13.5
—
ms
ns
ns
ns
ns
LOCK
MR – Q
Propagation Delay,
MR to Any Output (High–Low)
Into a 50Ω Load
PHL
Terminated to V /2
CC
, MR to
6
Reset Recovery Time rising MR edge
to falling SYNC edge
REC
SYNC
t
, MR to
REC
Normal Operation
Recovery Time for Outputs 2X_Q, Q0,
Q1 to Return to Normal PLL Operation
—
5
3 Clock Cycles
(Q Frequency)
6
t
W
, MR LOW
Minimum Pulse Width, MR input Low
—
1. These specifications are not tested, they are guaranteed by statistical characterization. See Application Note 1 for a discussion of this
methodology.
2. Under equally loaded conditions and at a fixed temperature and voltage.
3. With V
fully powered–on: t
Max is with C1 = 0.1µF; t
Min is with C1 = 0.01µF.
CC
CLOCK
LOCK
4. See Application Note 4 for the distribution in time of each output referenced to SYNC.
5. Refer to Application Note 3 to translate signals to a 1.5V threshold.
6. Specification is valid only when the PLL_EN pin is low.
7. This is a typical specification only, worst case guarantees are not provided.
5
MOTOROLA
MC88921
Application Notes
1. Several specifications can only be measured when the
MC88921 is in phase–locked operation. It is not possible
to have the part in phase–lock on ATE (automated test
equipment). Statistical characterization techniques were
used to guarantee those specifications which cannot be
measured on the ATE. MC88921 units were fabricated
with key transistor properties intentionally varied to create
a 14 cell designed experimental matrix. IC performance
was characterized over a range of transistor properties
(represented by the 14 cells) in excess of the expected
process variation of the wafer fabrication area.
these two specs to be guaranteed by Motorola, the
termination scheme shown in Figure 3 must be used. For
applications which require 1.5V thresholds, but do not
require a tight duty cycle the R resistor can be ignored.
P
4. The t
spec (SYNC to Q/2) guarantees how close the
PD
Q/2 output will be locked to the reference input connected
to the SYNC input (including temperature and voltage
variation). This also tells what the skew from the Q/2
output on one part connected to a given reference input, to
the Q/2 output on one or more parts connected to that
reference input (assuming equal delay from the reference
input to the SYNC input of each part). Therefore the t
2. A 1MΩ resistor tied to either Analog V
or Analog GND,
PD
CC
spec is equivalent to a part–to–part specification.
However, to correctly predict the skew from a given output
on one part to any other output on one or more other parts,
the distribution of each output in relation to the SYNC
input must be known. This distribution for the MC88921 is
provided in Table 1.
as shown in Figure 2, is required to ensure no jitter is
present on the MC88921 outputs. This technique causes
a phase offset between the SYNC input and the Q0
output, measured at the pins. The t
spec describes how
PD
this offset varies with process, temperature, and voltage.
The specs were arrived at by measuring the phase
relationship for the 14 lots described in note 1 while the
part was in phase–locked operation. The actual
measurements were made with a 10MHz SYNC input
(1.0ns edge rate from 0.8V to 2.0V). The phase
measurements were made at 1.5V. See Figure 2 for a
graphical description.
TABLE 1. Distribution of Each Output versus SYNC
Output
–(ps)
+(ps)
2X_Q
Q0
Q1
Q2
Q3
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
3. Two specs (t
and t
Width 2X_Q output,
PULSE
RISE/FALL
see AC Specifications) guarantee that the MC88921
meets the 20MHz, 25MHz and 33MHz 68040 P–Clock
input specification (at 40MHz, 50MHz, and 66MHz). For
Q/2
RC1
ANALOG V
CC
RC1
EXTERNAL
LOOP FILTER
1M
330
Ω
REFERENCE
RESISTOR
R2
C1
330
Ω
R2
C1
1M
0.1µF
REFERENCE
RESISTOR
0.1µF
ANALOG GND
ANALOG GND
WITH THE 1MΩ RESISTOR TIED IN THIS FASHION THE T
WITH THE 1M
Ω
RESISTOR TIED IN THIS FASHION THE T
SPECIFICATION, MEASURED AT THE INPUT PINS IS:
PD
PD
SPECIFICATION, MEASURED AT THE INPUT PINS IS:
t
= 2.25ns
±
1.0ns (TYPICAL VALUES)
3V
t
= –0.80ns 0.30ns
±
PD
PD
3V
–0.8ns
OFFSET
SYNC INPUT
Q0 OUTPUT
SYNC INPUT
Q0 OUTPUT
2.25ns
OFFSET
5V
5V
Figure 2. Depiction of the Fixed SYNC to Q0 Offset (t ) Which Is Present
PD
or Ground
When a 1MΩ Resistor Is Tied to V
CC
MOTOROLA
6
MC88921
Zo (CLOCK
TRACE)
88921
2X_Q
OUTPUT
68040
P–CLOC
K
Rs
R
P
INPUT
Rs = Zo – 7
Ω
R
= 1.5Zo
P
Figure 3. MC68040 P–Clock Input Termination Scheme
16.5MHz
CRYSTAL
2X_Q
66MHz P–CLOCK OUT-
PUT
SYNC
OSCILLATOR
Q0
Q1
Q2
Q3
33MHz
B–CLOCK
AND SYSTEM
OUTPUTS
MR
PLL_EN
Figure 4. Logical Representation of the MC88921 With Input/Output Frequency Relationships
SYNC Input
t
SYNC Input
CYCLE
t
t
t
t
t
SKEWr
SKEWall
SKEWf
SKEWr
SKEWf
Q0–Q3 Outputs
2X_Q Output
Figure 5. Output/Input Switching Waveforms and Timing Relationships
Timing Notes
1. The MC88921 aligns rising edges of the outputs and the SYNC input, therefore the SYNC input does not require a 50%
duty cycle.
2. All skew specs are measured between the V /2 crossing point of the appropriate output edges. All skews are specified as
CC
‘windows’, not as a ± deviation around a center point.
7
MOTOROLA
MC88921
The t
spec includes the full temperature range from 0°C
to 70°C and the full V range from 4.75V to 5.25V. If the
The t
window for a given ∆T and ∆V
is given by the
CC
PD
PD
following regression formula:
CC
is a given system are less than the
∆T and ∆V
CC
specification limits, the t
spec window will be reduced.
TBD
PD
Notes Concerning Loop Filter and Board Layout Issues
1. Figure 7 shows a loop filter and analog isolation scheme
which will be effective in most applications. The following
guidelines should be followed to ensure stable and
jitter–free operation:
purpose of the bypass filtering scheme shown in Figure 7
is to give the 88921 additional protection from the power
supply and ground plane transients that can occur in a
high frequency, high speed digital system.
1a. All loop filter and analog isolation components should be
tied as close to the package as possible. Stray current
passing through the parasitics of long traces can cause
undesirable voltage transients at the RC1 pin.
1c. There are no special requirements set forth for the loop
filter resistors (1M and 330Ω). The loop filter capacitor
(0.1uF) can be a ceramic chip capacitor, the same as a
standard bypass capacitor.
1b. The 47Ω resistors, the 10µF low frequency bypass
capacitor, and the 0.1µF high frequency bypass capacitor
form a wide bandwidth filter that will make the 88921 PLL
insensitive to voltage transients from the system digital
1d. The 1M reference resistor injects current into the internal
charge pump of the PLL, causing a fixed offset between
the outputs and the SYNC input. This also prevents
excessive jitter caused by inherent PLL dead–band. If the
VCO (2X_Q output) is running above 40MHz, the 1M
resistor provides the correct amount of current injection
into the charge pump (2–3µA).
V
supply and ground planes. This filter will typically
CC
ensure that a 100mV step deviation on the digital V
CC
supply will cause no more than a 100ps phase deviation
on the 88921 outputs. A 250mV step deviation on V
CC
using the recommended filter values will cause no more
2. In addition to the bypass capacitors used in the analog
than a 250ps phase deviation; if a 25µF bypass capacitor
filter of Figure 7, there should be a 0.1µF bypass
is used (instead of 10µF) a 250mV V
CC
more than a 100ps phase deviation.
step will cause no
capacitor between each of the other (digital) four V
CC
pins and the board ground plane. This will reduce output
switching noise caused by the 88921 outputs, in addition
to reducing potential for noise in the ‘analog’ section of
the chip. These bypass capacitors should also be tied as
close to the 88921 package as possible.
If good bypass techniques are used on a board design
near components which may cause digital V and
CC
step deviations
ground noise, the above described V
should not occur at the 88921’s digital V
CC
supply. The
CC
BOARD V
CC
47Ω
5
ANALOG V
CC
1MΩ
330
Ω
ANALOG LOOP FILTER/VCO
SECTION OF THE MC88921
20–PIN SOIC PACKAGE (NOT
DRAWN TO SCALE)
10µF LOW
0.1µF HIGH
6
7
RC1
FREQ BIAS
FREQ BIAS
0.1µF (LOOP
FILTER CAP)
ANALOG GND
47Ω
A SEPARATE ANALOG POWER SUPPLY IS NOT NECESSARY AND
SHOULD NOT BE USED. FOLLOWING THESE PRESCRIBED GUIDE-
LINESIS ALL THAT IS NECESSARY TO USE THE MC88921 IN A NORMAL
DIGITAL ENVIRONMENT.
BOARD GND
Figure 6. Recommended Loop Filter and Analog Isolation Scheme for the MC88921
MOTOROLA
8
MC88921
Pentium
Microprocessor
ASIC
ASIC
66MHz
33MHz
16.5MHz
X–TAL
OSCILLATOR
2X_Q
PCLK
SYNC
Q1
Q2
Q3
MEMORY MODULE
Figure 7. Typical MC88921/Pentium Microprocessor System Configuration
9
MOTOROLA
MC88921
OUTLINE DIMENSIONS
DW SUFFIX
SOIC PACKAGE
CASE 751D-03
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
-A-
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. 751D-01, AND -02 OBSOLETE, NEW STANDARD
751D-03.
20
1
11
10
M
M
-B-
P
0.25 (0.010)
B
10 PL
MILLIMETERS
INCHES
DIM
MIN
12.65
7.40
2.35
0.35
0.50
1.27 BSC
0.25
0.10
MAX
12.95
7.60
2.65
0.49
0.90
MIN
MAX
G
R X 45°
A
B
C
D
F
G
J
K
M
P
R
0.499
0.292
0.093
0.014
0.020
0.050 BSC
0.010
0.004
0.510
0.299
0.104
0.019
0.035
C
-T-
SEATING
PLANE
M
J
0.32
0.25
0.012
0.009
7°
0.415
0.029
F
K
D 20 PL
0°
7°
0
°
M
S
S
A
0.25 (0.010)
T
B
10.05
0.25
10.55
0.75
0.395
0.010
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
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INTERNET: http://Design–NET.com
HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
CODELINE
MC88921/D
◊
相关型号：
MC88921DWR2
88921 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20, PLASTIC, SOIC-20
MOTOROLA
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