MC88915TFN160R2 [MOTOROLA]
PLL Based Clock Driver, 88915 Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28, PLASTIC, LCC-28;
| 型号： | MC88915TFN160R2 |
| 厂家： | 
MOTOROLA |
| 描述： | PLL Based Clock Driver, 88915 Series, 7 True Output(s), 1 Inverted Output(s), CMOS, PQCC28, PLASTIC, LCC-28 |
| 文件： | 总21页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M OT O R OL A
SEMICONDUCTOR TECHNICAL DATA
Order Number: MC88915T/D
Rev 5, 08/2001
M
M
C
C
8
8
8
8
8
8
8
8
8
8
9
9
9
9
9
1
1
1
1
1
5
5
5
5
5
T
T
T
T
T
F
F
F
F
F
N
N
N
N
N
1
1
1
5
7
0
3
6
5
0
0
3
0
L
C
o
w
c
S
k
D
e
r
w
v
C
M
O
S
P L L
3 - S ta t e
M
C
l
o
k
i
e
r
s
,
55, 70, 100, 133 and 160MHz Versions
M
M
C
C
The MC88915T Clock Driver utilizes phase–locked loop technology to
lock its low skew outputs’ frequency and phase onto an input reference
clock. It is designed to provide clock distribution for high performance PC’s
and workstations. For a 3.3V version, see the MC88LV915T data sheet.
The PLL allows the high current, low skew outputs to lock onto a single
clock input and distribute it with essentially zero delay to multiple
components on a board. The PLL also allows the MC88915T to multiply a
low frequency input clock and distribute it locally at a higher (2X) system
frequency. Multiple 88915’s can lock onto a single reference clock, which is
ideal for applications when a central system clock must be distributed
synchronously to multiple boards (see Figure 7).
LOW SKEW CMOS
PLL CLOCK DRIVER
Five “Q” outputs (Q0–Q4) are provided with less than 500 ps skew between their rising edges. The Q5 output is inverted (180°
phase shift) from the “Q” outputs. The 2X_Q output runs at twice the “Q” output frequency, while the Q/2 runs at 1/2 the “Q”
frequency.
The VCO is designed to run optimally between 20 MHz and the 2X_Q Fmax specification. The wiring diagrams in Figure 5 detail
the different feedback configurations which create specific input/output frequency relationships. Possible frequency ratios of the
“Q” outputs to the SYNC input are 2:1, 1:1, and 1:2.
The FREQ_SEL pin provides one bit programmable divide–by in the feedback path of the PLL. It selects between divide–by–1
and divide–by–2 of the VCO before its signal reaches the internal clock distribution section of the chip (see the block diagram on
page 2). In most applications FREQ_SEL should be held high (÷1). If a low frequency reference clock input is used, holding
FREQ_SEL low (÷2) will allow the VCO to run in its optimal range (>20MHz and >40MHz for the TFN133 version).
In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the
88915 in a static “test mode”. In this mode there is no frequency limitation on the input clock, which is necessary for a low frequency
board test environment. The second SYNC input can be used as a test clock input to further simplify board–level testing (see
detailed description on page 11).
Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0–Q4, Q5 and Q/2 into a high impedance state (3–state). After the
OE/RST pin goes back high Q0–Q4, Q5 and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNC
input. Assuming PLL_EN is low, the outputs will remain reset until the 88915 sees a SYNC input pulse.
A lock indicator output (LOCK) will go high when the loop is in steady–state phase and frequency lock. The LOCK output will go
low if phase–lock is lost or when the PLL_EN pin is low. The LOCK output will go high no later than 10ms after the 88915 sees a
SYNC signal and full 5V VCC
.
Features
•
Five Outputs (Q0–Q4) with Output–Output Skew < 500 ps each being phase and frequency locked to the SYNC input
•
The phase variation from part–to–part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPD
specification, which defines the part–to–part skew)
•
•
•
•
Input/Output phase–locked frequency ratios of 1:2, 1:1, and 2:1 are available
Input frequency range from 5MHz – 2X_Q FMAX spec. (10MHz – 2X_Q FMAX for the TFN133 version)
Additional outputs available at 2X and +2 the system “Q” frequency. Also a Q (180° phase shift) output available
All outputs have ±36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs are
TTL–level compatible. ±88mA IOL/IOH specifications guarantee 50Ω transmission line switching on the incident edge
Test Mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes.
All outputs can go into high impedance (3–state) for board test purposes
•
•
Lock Indicator (LOCK) accuracy indicates a phase–locked state
Yield Surface Modeling and YSM are trademarks of Motorola, Inc.
Motorola, Inc. 2001
t
Pinout: 28–Lead PLCC (Top View)
O
E
/
R
S
T
V
C
Q
5
G
N
D
Q
4
V
C C
2
X
_
Q
C
4
3
2
1
2
8
2
7
2 6
F
E
E
D
B
A
C
K
5
2
5
4
3
2
1
0
9
Q
G
Q
/
2
RE F_ SE L
6
7
8
9
1
2
2
2
2
2
1
N
3
D
S YN C[ 0]
V
(
A
N
)
V
C C
C
C
R
C
1
Q
G
2
G
N
D
(
A
N
)
0
N
D
S
Y
N
C
[
1
]
11
L O CK
1
2
1
3
1
4
1
5
1
6
1
7
1 8
G
FR EQ _S EL
N
D
Q
0
V
C
Q
1
G
N
D
P
L
L
_
E
N
C
FN SUFFIX
PLASTIC PLCC
CASE 776–02
PIN SUMMARY
P
i
n
N
a
m
e
N
u
m
I
/O
F
u
n
c
t
i
o
n
1
1
1
1
1
1
5
1
1
1
1
1
1
S YN C [ 0 ]
S YN C [ 1 ]
R E F_ S EL
F R EQ _ SE L
F E ED B AC K
R C 1
Q (0 - 4 )
Q 5
2 x _Q
I n pu t
I n pu t
I n pu t
I n pu t
I n pu t
I n pu t
O ut p u t
O ut p u t
O ut p u t
O ut p u t
O ut p u t
I n pu t
R e f e re n c e c l o c k i n p u t
R e f e re n c e c l o c k i n p u t
C h o os e s r e f e re n c e b e t w ee n s y n c [ 0]
D o u bl e s V C O I n t e rn a l F r e q ue n c y ( l o w )
F e e d ba c k i n p u t t o p h a s e d e t e ct o r
I n p u t f o r e x t e rn a l R C n e t w or k
C l o c k o u t p ut ( l o c ke d t o s y n c )
I n v e rs e o f c l o c k o u t p ut
&
S
y
n
c
[
1
]
2
x
c
l
o
c
k
o
u
t
p
u
t
(
Q
)
f
r
e
q
u
e
n
c
y
(
s
y
n
c
h
r
o
n
o
u
s
)
Q
/
2
C
l
o
c
k
o
u
t
p
u
t
(
Q
)
f
r
e
q
u
e
÷
n
c
y
2
(
s
y
n
c
h
r
o
n
o
u
s
)
L OC K
O E/ R ST
P LL _ E N
I n d i ca t e s p h a s e l o c k h a s b e e n a c h i ev e d ( h i g h w h e n l o c k ed )
O u t p ut E n a bl e / A s y n c hr o n o u s r e s e t ( a c t i ve l o w )
D i s a bl e s p h a s e- l o c k f o r l o w f r e q . t e s t i ng
I n pu t
11
V
, G ND
C C
P o w e r a n d g r o un d p i n s ( n o t e p i n s 8 , 1 0 a r e
a n al o g " s u p p ly p i n s f o r i n t e rn a l P L L o n l y )
2
MOTOROLA
L
O
C
K
FEED BAC K
S
S
Y
N
N
C
C
(
(
0
1
)
)
V
O
L
T
A
G
E
0
1
P HA SE/ FR EQ .
C
H
A
R
G
E
F
P UMP / L O OP
I LTE R
C
O
N
T
R
O
L
L
E
D
M
U
X
D
E
T
E
C
T
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L
L
ATO
R
Y
E
X
T
ER
N
A
L
R
1
E C
P in )
N
E
T
W
O
R
K
(
R
C
R E F_ SEL
2
x
_
Q
0
1
P
L
L
_
E
N
M
U
X
Q
Q
Q
Q
Q
Q
Q
0
D
Q
Q
(
÷
1
2
)
)
C
P
1
R
R
R
R
R
R
R
M
U
X
(
÷
D
I
V
I
D
T
E
W
0
B
Y
O
1
2
3
4
5
D
Q
Q
Q
Q
Q
Q
C
P
F
R
E
Q
_
S
E
L
O
E
/
R
S
T
D
C
P
D
C
P
D
C
P
D
C
P
/
2
D
C
P
Figure 1. MC88915T Block Diagram (All Versions)
3
MOTOROLA
MC88915TFN55 and MC88915TFN70
SYNC INPUT TIMING REQUIREMENTS
Minimum
Symbol
,SYNC Inputs
Parameter
Rise/Fall Time, SYNC Inputs
TFN70
TFN55
—
Maximum
Unit
t
t
—
3.0
ns
RISE/FALL
From 0.8 to 2.0V
1
1
2
, SYNC Inputs
Input Clock Period SYNC Inputs
Input Duty Cycle SYNC Inputs
28.5
36.0
200
ns
CYCLE
Duty Cycle SYNC Inputs
1. These t
50% ±25%
minimum values are valid when ‘Q’ output is fed back and connected to the FEEDBACK pin. This is the configuration shown in
CYCLE
Figure 5b.
2. Information in Table 1 and in Note 3 of the AC specification notes describe this specification and its limits depending on what output is fed back,
and if FREQ_SEL is high or low.
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND) T =–40° C to +85° C for 55MHz Version; T =0° C to +70° C for 70MHz Version; V = 5.0 V ± 5%
A
A
CC
V
CC
V
Symbol
Parameter
Test Conditions
Target Limit
Unit
V
IH
Minimum High–Level Input
Voltage
V
out
= 0.1 V or V – 0.1 V
4.75
5.25
2.0
2.0
V
CC
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V – 0.1 V
4.75
5.25
0.8
0.8
V
V
V
IL
out
CC
V
OH
Minimum High–Level Output
Voltage
V
in
= V or V
IL
4.75
5.25
4.01
4.51
IH
1
I
= –36 mA
OH
V
I
Maximum Low–Level Output
Voltage
V
in
= V or V
IL
4.75
5.25
0.44
0.44
OL
IH
1
I
OL
= 36 mA
Maximum Input Leakage Current
V = V or GND
I
5.25
5.25
5.25
5.25
5.25
±1.0
µA
mA
mA
mA
mA
in
CC
2
I
Maximum I /Input
V = V – 2.1 V
I
CCT
OLD
CC
CC
2.0
3
I
Minimum Dynamic Output Current
V
= 1.0V Max
88
–88
1.0
OLD
OHD
I
V
= 3.85V Min
OHD
I
Maximum Quiescent Supply
Current (per Package)
V = V or GND
I CC
CC
4
I
Maximum 3–State Leakage Current
V = V or V ;V = V or GND
5.25
±50
µA
OZ
I
IH
IL
O
CC
1. I and I are 12mA and –12mA respectively for the LOCK output.
OL
OH
2. The PLL_EN input pin is not guaranteed to meet this specification.
3. Maximum test duration is 2.0ms, one output loaded at a time.
4. Specification value for I is preliminary, will be finalized upon ‘MC’ status.
OZ
CAPACITANCE AND POWER SPECIFICATIONS
Symbol
Parameter
Typical Values
Unit
pF
Conditions
C
Input Capacitance
Power Dissipation Capacitance
Power Dissipation @ 50MHz with 50Ω Thevenin Termination
4.5
40
V
CC
V
CC
V
CC
= 5.0 V
IN
C
pF
= 5.0 V
= 5.0 V
PD
PD
23mW/Output
184mW/Device
mW
1
T = 25°C
PD
Power Dissipation @ 50MHz with 50Ω Parallel Termination to GND
57mW/Output
456mW/Device
mW
V
= 5.0 V
2
CC
T = 25° C
NOTE: PD and PD mW/Output numbers are for a ‘Q’ output.
1
2
4
MOTOROLA
MC88915TFN55 and MC88915TFN70 (continued)
FREQUENCY SPECIFICATIONS (T =–40° C to +85° C, V = 5.0 V ±5%)
A
CC
Guaranteed Minimum
TFN70 TFN55
70 55
35 27.5
Symbol
Parameter
Maximum Operating Frequency (2X_Q Output)
Maximum Operating Frequency (Q0–Q4,Q5 Output)
Unit
MHz
MHz
1
f
max
1. Maximum Operating Frequency is guaranteed with the part in a phase–locked condition, and all outputs loaded with 50Ω terminated to V /2.
CC
AC CHARACTERISTICS (T =–40° C to +85° C, V = 5.0V ±5%, Load = 50Ω Terminated to V /2)
A
CC
CC
Symbol
Parameter
Min
Max
Unit
Condition
t
Rise/Fall Time, All Outputs
1.0
2.5
ns
Into a 50Ω Load
RISE/FALL
Outputs
(Between 0.2V and 0.8V
)
Terminated to V /2
CC
CC
CC
1
t
Rise/Fall Time Into a 20pF Load, With Ter-
mination Specified in Note
0.5
1.6
ns
ns
ns
t
t
: 0.8V – 2.0V
: 2.0V – 0.8V
RISE/FALL
RISE
FALL
2
2X_Q Output
1
2
2
2
2
t
Output Pulse Width: Q0, Q1, Q2, Q3, Q4,
0.5t
0.5t
0.5t
0.5t
– 0.5
– 0.5
0.5t
0.5t
0.5t
0.5t
+ 0.5
Into a 50Ω Load
Terminated to V /2
PULSE WIDTH
(Q0–Q4, Q5, Q/2)
CYCLE
CYCLE
Q5, Q/2 @ V /2
CC
CC
1
t
Output Pulse Width:
2X_Q @ 1.5V
66MHz
50MHz
40MHz
+ 0.5
Must Use Termination
Specified in Note 2
PULSE WIDTH
(2X_Q Output)
CYCLE
CYCLE
– 1.0
– 1.5
+ 1.0
+ 1.5
CYCLE
CYCLE
CYCLE
CYCLE
1
2
2
t
Output Pulse Width:
50–65MHz
40–49MHz
66–70MHz
0.5t
0.5t
0.5t
– 1.0
– 1.5
– 0.5
0.5t
0.5t
0.5t
+ 1.0
+ 1.5
+ 0.5
ns
ns
Into a 50Ω Load
PULSE WIDTH
CYCLE
CYCLE
(2X_Q Output)
2X_Q @ V /2
Terminated to V /2
CC
CYCLE
CYCLE
CYCLE
CYCLE
CC
1,3
t
SYNC Input to Feedback Delay
(Measured at SYNC0 or 1 and
FEEDBACK Input Pins)
See Note 4 and
Figure 2 for Detailed
Explanation
(With 1MΩ from RC1 to An V
)
PD
CC
SYNC Feedback
–1.05
–0.40
(With 1MΩ from RC1 to An GND)
+1.25
—
+3.25
500
1,4
t
Output–to–Output Skew Between Outputs
Q0–Q4, Q/2 (Rising Edges Only)
ps
ps
ps
ms
All Outputs Into a
Matched 50Ω Load
SKEWr
5
(Rising) See Note
Terminated to V /2
CC
1,4
t
Output–to–Output Skew Between Outputs
Q0–Q4 (Falling Edges Only)
—
—
500
750
10
All Outputs Into a
Matched 50Ω Load
SKEWf
(Falling)
Terminated to V /2
CC
1,4
t
Output–to–Output Skew 2X_Q, Q/2,
Q0–Q4 Rising, Q5 Falling
All Outputs Into a
Matched 50Ω Load
SKEWall
Terminated to V /2
CC
5
t
Time Required to Acquire Phase–Lock
From Time SYNC Input Signal is
Received
1.0
Also Time to LOCK
Indicator High
LOCK
6
t
t
Output Enable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
3.0
3.0
14
14
ns
ns
Measured With the
PLL_EN Pin Low
PZL
6
,t
Output Disable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
Measured With the
PLL_EN Pin Low
PHZ PLZ
1. These specifications are not tested, they are guaranteed by statistcal characterization. See AC specification Note 1.
2. T in this spec is 1/Frequency at which the particular output is running.
CYCLE
3. The T specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
PD
4. Under equally loaded conditions and at a fixed temperature and voltage.
5. With V fully powered–on, and an output properly connected to the FEEDBACK pin. t
maximum is with C1 = 0.1µF, t
minimum is with
CC
LOCK
LOCK
C1 = 0.01µF.
6. The t , t
, t
minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is reached.
PZL PHZ PLZ
5
MOTOROLA
MC88915TFN100
SYNC INPUT TIMING REQUIREMENTS
Symbol
Parameter
Minimum
Maximum
Unit
t
t
,SYNC Inputs
Rise/Fall Time, SYNC Inputs From 0.8 to 2.0V
—
3.0
ns
RISE/FALL
1
2
, SYNC Inputs
Input Clock Period SYNC Inputs
Input Duty Cycle SYNC Inputs
20.0
200
ns
CYCLE
Duty Cycle SYNC Inputs
1. These t
50% ±25%
minimum values are valid when ‘Q’ output is fed back and connected to the FEEDBACK pin. This is the configuration shown in
CYCLE
Figure 5b.
2. Information in Table 1 and in Note 3 of the AC specification notes describe this specification and its limits depending on what output is fed back,
and if FREQ_SEL is high or low.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) T =–40° C to +85° C, V = 5.0 V ± 5%
A
CC
V
CC
V
Symbol
Parameter
Test Conditions
Target Limit
Unit
V
IH
Minimum High–Level Input
Voltage
V
out
= 0.1 V or V – 0.1 V
4.75
5.25
2.0
2.0
V
CC
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V – 0.1 V
4.75
5.25
0.8
0.8
V
V
V
IL
out
CC
V
OH
Minimum High–Level Output
Voltage
V
in
= V or V
IL
4.75
5.25
4.01
4.51
IH
1
I
= –36 mA
OH
V
OL
Maximum Low–Level Output
Voltage
V
in
= V or V
IL
4.75
5.25
0.44
0.44
IH
1
I
OL
= 36 mA
I
Maximum Input Leakage Current
V = V or GND
5.25
5.25
5.25
5.25
5.25
±1.0
µA
mA
mA
mA
mA
in
I
CC
2
I
I
Maximum I /Input
V = V – 2.1 V
CCT
CC
I
CC
2.0
3
Minimum Dynamic Output Current
V
= 1.0V Max
88
–88
1.0
OLD
OLD
OHD
I
V
= 3.85V Min
OHD
I
Maximum Quiescent Supply
Current (per Package)
V = V or GND
I CC
CC
4
I
Maximum 3–State Leakage Current
V = V or V ;V = V or GND
5.25
±50
µA
OZ
I
IH
IL
O
CC
1. I and I are 12mA and –12mA respectively for the LOCK output.
OL
OH
2. The PLL_EN input pin is not guaranteed to meet this specification.
3. Maximum test duration is 2.0ms, one output loaded at a time.
4. Specification value for I is preliminary, will be finalized upon ‘MC’ status.
OZ
CAPACITANCE AND POWER SPECIFICATIONS
Symbol
Parameter
Typical Values
Unit
pF
Conditions
C
Input Capacitance
Power Dissipation Capacitance
Power Dissipation @ 50MHz with 50Ω Thevenin Termination
4.5
40
V
CC
V
CC
V
CC
= 5.0 V
IN
C
pF
= 5.0 V
= 5.0 V
PD
PD
23mW/Output
184mW/Device
mW
1
T = 25°C
PD
Power Dissipation @ 50MHz with 50Ω Parallel Termination to GND
57mW/Output
456mW/Device
mW
V
= 5.0 V
2
CC
T = 25° C
NOTE: PD and PD mW/Output numbers are for a ‘Q’ output.
1
2
FREQUENCY SPECIFICATIONS (T =–40° C to +85° C, V = 5.0 V ±5%)
A
CC
Guaranteed Minimum
Symbol
Parameter
Maximum Operating Frequency (2X_Q Output)
Maximum Operating Frequency (Q0–Q4,Q5 Output)
TFN100
100
Unit
1
f
MHz
MHz
max
50
1. Maximum Operating Frequency is guaranteed with the part in a phase–locked condition, and all outputs loaded with 50Ω terminated to V /2.
CC
6
MOTOROLA
MC88915TFN100 (continued)
AC CHARACTERISTICS (T =–40° C to +85° C, V = 5.0V ±5%, Load = 50Ω Terminated to V /2)
A
CC
CC
Symbol
Parameter
Min
Max
Unit
Condition
t
Rise/Fall Time, All Outputs
1.0
2.5
ns
Into a 50Ω Load
RISE/FALL
Outputs
(Between 0.2V and 0.8V
)
Terminated to V /2
CC
CC
CC
1
t
Rise/Fall Time Into a 20pF Load, With Ter-
mination Specified in Note
0.5
1.6
ns
ns
ns
ns
t
t
: 0.8V – 2.0V
: 2.0V – 0.8V
RISE/FALL
RISE
FALL
2
2X_Q Output
1
2
2
2
2
2
2
t
Output Pulse Width: Q0, Q1, Q2, Q3, Q4,
0.5t
0.5t
0.5t
– 0.5
– 0.5
– 1.5
0.5t
0.5t
0.5t
+ 0.5
Into a 50Ω Load
Terminated to V /2
PULSE WIDTH
(Q0–Q4, Q5, Q/2)
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
Q5, Q/2 @ V /2
CC
CC
1
t
Output Pulse Width:
2X_Q @ 1.5V
+ 0.5
Must Use Termination
Specified in Note 2
PULSE WIDTH
(2X_Q Output)
1
t
Output Pulse Width:
40–49MHz
50–65MHz
66–100MHz
+ 1.5
Into a 50Ω Load
Terminated to V /2
PULSE WIDTH
(2X_Q Output)
2X_Q @ V /2
0.5t
0.5t
– 1.0
– 0.5
0.5t
0.5t
+ 1.0
+ 0.5
CC
CYCLE
CYCLE
CYCLE
CYCLE
CC
1,3
t
SYNC Input to Feedback Delay
(Measured at SYNC0 or 1 and
FEEDBACK Input Pins)
ns
See Note 4 and
Figure 2 for Detailed
Explanation
(With 1MΩ from RC1 to An V
)
PD
CC
SYNC Feedback
–1.05
–0.30
(With 1MΩ from RC1 to An GND)
+1.25
—
+3.25
500
1,4
t
Output–to–Output Skew Between Outputs
Q0–Q4, Q/2 (Rising Edges Only)
ps
ps
ps
ms
All Outputs Into a
Matched 50Ω Load
SKEWr
5
(Rising) See Note
Terminated to V /2
CC
1,4
t
Output–to–Output Skew Between Outputs
Q0–Q4 (Falling Edges Only)
—
—
500
750
10
All Outputs Into a
Matched 50Ω Load
SKEWf
(Falling)
Terminated to V /2
CC
1,4
t
Output–to–Output Skew 2X_Q, Q/2,
Q0–Q4 Rising, Q5 Falling
All Outputs Into a
Matched 50Ω Load
SKEWall
Terminated to V /2
CC
5
t
Time Required to Acquire Phase–Lock
From Time SYNC Input Signal is
Received
1.0
Also Time to LOCK
Indicator High
LOCK
6
t
t
Output Enable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
3.0
3.0
14
14
ns
ns
Measured With the
PLL_EN Pin Low
PZL
6
,t
Output Disable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
Measured With the
PLL_EN Pin Low
PHZ PLZ
1. These specifications are not tested, they are guaranteed by statistcal characterization. See AC specification Note 1.
2. T in this spec is 1/Frequency at which the particular output is running.
CYCLE
3. The T specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
PD
4. Under equally loaded conditions and at a fixed temperature and voltage.
5. With V fully powered–on, and an output properly connected to the FEEDBACK pin. t
maximum is with C1 = 0.1µF, t
minimum is with
CC
LOCK
LOCK
C1 = 0.01µF.
6. The t , t
, t
minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is reached.
PZL PHZ PLZ
7
MOTOROLA
MC88915TFN133
SYNC INPUT TIMING REQUIREMENTS
Symbol
Parameter
Minimum
Maximum
Unit
t
t
,SYNC Inputs
Rise/Fall Time, SYNC Inputs From 0.8 to 2.0V
—
3.0
ns
RISE/FALL
1
2
, SYNC Inputs
Input Clock Period SYNC Inputs
Input Duty Cycle SYNC Inputs
15.0
100
ns
CYCLE
Duty Cycle SYNC Inputs
1. These t
50% ±25%
minimum values are valid when ‘Q’ output is fed back and connected to the FEEDBACK pin. This is the configuration shown in
CYCLE
Figure 5b.
2. Information in Table 1 and in Note 3 of the AC specification notes describe this specification and its limits depending on what output is fed back,
and if FREQ_SEL is high or low.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) T =–40° C to +85° C, V = 5.0 V ± 5%
A
CC
V
CC
V
Symbol
Parameter
Test Conditions
Target Limit
Unit
V
IH
Minimum High–Level Input
Voltage
V
out
= 0.1 V or V – 0.1 V
4.75
5.25
2.0
2.0
V
CC
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V – 0.1 V
4.75
5.25
0.8
0.8
V
V
V
IL
out
CC
V
OH
Minimum High–Level Output
Voltage
V
in
= V or V
IL
4.75
5.25
4.01
4.51
IH
1
I
= –36 mA
OH
V
OL
Maximum Low–Level Output
Voltage
V
in
= V or V
IL
4.75
5.25
0.44
0.44
IH
1
I
OL
= 36 mA
I
Maximum Input Leakage Current
V = V or GND
5.25
5.25
5.25
5.25
5.25
±1.0
µA
mA
mA
mA
mA
in
I
CC
2
I
I
Maximum I /Input
V = V – 2.1 V
CCT
CC
I
CC
2.0
3
Minimum Dynamic Output Current
V
= 1.0V Max
88
–88
1.0
OLD
OLD
OHD
I
V
= 3.85V Min
OHD
I
Maximum Quiescent Supply
Current (per Package)
V = V or GND
I CC
CC
4
I
Maximum 3–State Leakage Current
V = V or V ;V = V or GND
5.25
±50
µA
OZ
I
IH
IL
O
CC
1. I and I are 12mA and –12mA respectively for the LOCK output.
OL
OH
2. The PLL_EN input pin is not guaranteed to meet this specification.
3. Maximum test duration is 2.0ms, one output loaded at a time.
4. Specification value for I is preliminary, will be finalized upon ‘MC’ status.
OZ
CAPACITANCE AND POWER SPECIFICATIONS
Symbol
Parameter
Typical Values
Unit
pF
Conditions
C
Input Capacitance
Power Dissipation Capacitance
Power Dissipation @ 50MHz with 50Ω Thevenin Termination
4.5
40
V
CC
V
CC
V
CC
= 5.0 V
IN
C
pF
= 5.0 V
= 5.0 V
PD
PD
23mW/Output
184mW/Device
mW
1
T = 25°C
PD
Power Dissipation @ 50MHz with 50Ω Parallel Termination to GND
57mW/Output
456mW/Device
mW
V
= 5.0 V
2
CC
T = 25° C
NOTE: PD and PD mW/Output numbers are for a ‘Q’ output.
1
2
FREQUENCY SPECIFICATIONS (T =–40° C to +85° C, V = 5.0 V ±5%)
A
CC
Guaranteed Minimum
Symbol
Parameter
Maximum Operating Frequency (2X_Q Output)
Maximum Operating Frequency (Q0–Q4,Q5 Output)
TFN133
133
Unit
1
f
MHz
MHz
max
66
1. Maximum Operating Frequency is guaranteed with the part in a phase–locked condition, and all outputs loaded with 50Ω terminated to V /2.
CC
8
MOTOROLA
MC88915TFN133 (continued)
AC CHARACTERISTICS (T =–40° C to +85° C, V = 5.0V ±5%, Load = 50Ω Terminated to V /2)
A
CC
CC
Symbol
Parameter
Min
Max
Unit
Condition
t
Rise/Fall Time, All Outputs
1.0
2.5
ns
Into a 50Ω Load
RISE/FALL
Outputs
(Between 0.2V and 0.8V
)
Terminated to V /2
CC
CC
CC
1
t
Rise/Fall Time Into a 20pF Load, With Ter-
mination Specified in Note
0.5
1.6
ns
ns
ns
ns
t
t
: 0.8V – 2.0V
: 2.0V – 0.8V
RISE/FALL
RISE
FALL
2
2X_Q Output
1
2
2
2
2
t
Output Pulse Width: Q0, Q1, Q2, Q3, Q4,
0.5t
0.5t
– 0.5
– 0.5
0.5t
0.5t
+ 0.5
Into a 50Ω Load
Terminated to V /2
PULSE WIDTH
(Q0–Q4, Q5, Q/2)
CYCLE
CYCLE
Q5, Q/2 @ V /2
CC
CC
1
t
Output Pulse Width:
2X_Q @ 1.5V
66–133MHz
40–65MHz
+ 0.5
+ 0.9
Must Use Termination
Specified in Note 2
PULSE WIDTH
(2X_Q Output)
CYCLE
CYCLE
0.5t
– 0.9
0.5t
CYCLE
CYCLE
1
2
2
t
Output Pulse Width:
66–133MHz
40–65MHz
0.5t
0.5t
– 0.5
– 0.9
0.5t
0.5t
+ 0.5
+ 0.9
Into a 50Ω Load
Terminated to V /2
PULSE WIDTH
(2X_Q Output)
CYCLE
CYCLE
2X_Q @ V /2
CC
CYCLE
CYCLE
CC
1,3
t
SYNC Input to Feedback Delay
(Measured at SYNC0 or 1 and
FEEDBACK Input Pins)
ns
See Note 4 and
Figure 2 for Detailed
Explanation
(With 1MΩ from RC1 to An V
)
PD
CC
SYNC Feedback
–1.05
–0.25
(With 1MΩ from RC1 to An GND)
+1.25
—
+3.25
500
1,4
t
Output–to–Output Skew Between Outputs
Q0–Q4, Q/2 (Rising Edges Only)
ps
ps
ps
ms
All Outputs Into a
Matched 50Ω Load
SKEWr
5
(Rising) See Note
Terminated to V /2
CC
1,4
t
Output–to–Output Skew Between Outputs
Q0–Q4 (Falling Edges Only)
—
—
500
750
10
All Outputs Into a
Matched 50Ω Load
SKEWf
(Falling)
Terminated to V /2
CC
1,4
t
Output–to–Output Skew 2X_Q, Q/2,
Q0–Q4 Rising, Q5 Falling
All Outputs Into a
Matched 50Ω Load
SKEWall
Terminated to V /2
CC
5
t
Time Required to Acquire Phase–Lock
From Time SYNC Input Signal is
Received
1.0
Also Time to LOCK
Indicator High
LOCK
6
t
t
Output Enable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
3.0
3.0
14
14
ns
ns
Measured With the
PLL_EN Pin Low
PZL
6
,t
Output Disable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
Measured With the
PLL_EN Pin Low
PHZ PLZ
1. These specifications are not tested, they are guaranteed by statistcal characterization. See AC specification Note 1.
2. T in this spec is 1/Frequency at which the particular output is running.
CYCLE
3. The T specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
PD
4. Under equally loaded conditions and at a fixed temperature and voltage.
5. With V fully powered–on, and an output properly connected to the FEEDBACK pin. t
maximum is with C1 = 0.1µF, t
minimum is with
CC
LOCK
LOCK
C1 = 0.01µF.
6. The t , t
, t
minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is reached.
PZL PHZ PLZ
9
MOTOROLA
MC88915TFN160
SYNC INPUT TIMING REQUIREMENTS
Symbol
Parameter
Minimum
Maximum
Unit
t ,SYNC Inputs
RISE/FALL
Rise/Fall Time, SYNC Inputs From 0.8 to 2.0V
—
3.0
ns
t
, SYNC Inputs
Input Clock Period SYNC Inputs
Input Duty Cycle SYNC Inputs
12.5
100
ns
CYCLE
Duty Cycle SYNC Inputs
1. These t
50% ±25%
minimum values are valid when ‘Q’ output is fed back and connected to the FEEDBACK pin. This is the configuration shown in
CYCLE
Figure 5b.
2. Information in Table 1 and in Note 3 of the AC specification notes describe this specification and its limits depending on what output is fed back,
and if FREQ_SEL is high or low.
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) T =0° C to +70° C, V = 5.0 V ± 5%
A
CC
V
CC
V
Symbol
Parameter
Test Conditions
Target Limit
Unit
V
IH
Minimum High–Level Input
Voltage
V
out
= 0.1 V or V – 0.1 V
4.75
5.25
2.0
2.0
V
CC
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V – 0.1 V
4.75
5.25
0.8
0.8
V
V
V
IL
out
CC
V
OH
Minimum High–Level Output
Voltage
V
in
= V or V
IL
4.75
5.25
4.01
4.51
IH
1
I
= –36 mA
OH
V
I
Maximum Low–Level Output
Voltage
V
in
= V or V
IL
4.75
5.25
0.44
0.44
OL
IH
1
I
OL
= 36 mA
Maximum Input Leakage Current
V = V or GND
I
5.25
5.25
5.25
5.25
5.25
±1.0
µA
mA
mA
mA
mA
in
CC
2
I
I
Maximum I /Input
V = V – 2.1 V
I
CCT
OLD
CC
CC
2.0
3
Minimum Dynamic Output Current
V
OLD
V
OHD
= 1.0V Max
88
–88
1.0
I
= 3.85V Min
OHD
I
Maximum Quiescent Supply
Current (per Package)
V = V or GND
I CC
CC
4
I
Maximum 3–State Leakage Current
V = V or V ;V = V or GND
5.25
±50
µA
OZ
I
IH
IL
O
CC
1. I and I are 12mA and –12mA respectively for the LOCK output.
OL
OH
2. The PLL_EN input pin is not guaranteed to meet this specification.
3. Maximum test duration is 2.0ms, one output loaded at a time.
4. Specification value for I is preliminary, will be finalized upon ‘MC’ status.
OZ
CAPACITANCE AND POWER SPECIFICATIONS
Symbol
Parameter
Typical Values
Unit
pF
Conditions
C
Input Capacitance
Power Dissipation Capacitance
Power Dissipation @ 50MHz with 50Ω Thevenin Termination
4.5
40
V
CC
V
CC
V
CC
= 5.0 V
IN
C
pF
= 5.0 V
= 5.0 V
PD
PD
15mW/Output
120mW/Device
mW
1
T = 25°C
PD
Power Dissipation @ 50MHz with 50Ω Parallel Termination to GND
57mW/Output
456mW/Device
mW
V
= 5.0 V
2
CC
T = 25° C
NOTE: PD and PD mW/Output numbers are for a ‘Q’ output.
1
2
FREQUENCY SPECIFICATIONS (T =0° C to +70° C, V = 5.0 V ±5%)
A
CC
Guaranteed Minimum
Symbol
Parameter
TFN160
160
Unit
1
f
Maximum Operating Frequency (2X_Q Output)
MHz
MHz
max
Maximum Operating Frequency (Q0–Q4,Q5 Output)
80
1. Maximum Operating Frequency is guaranteed with the part in a phase–locked condition, and all outputs loaded with 50Ω terminated to V /2.
CC
10
MOTOROLA
MC88915TFN160 (continued)
AC CHARACTERISTICS (T =0° C to +70° C, V = 5.0V ±5%, Load = 50Ω Terminated to V /2)
A
CC
CC
Symbol
Parameter
Min
Max
Unit
Condition
t
Rise/Fall Time, All Outputs
1.0
2.5
ns
Into a 50Ω Load
RISE/FALL
Outputs
(Between 0.2V and 0.8V
)
Terminated to V /2
CC
CC
CC
t
Rise/Fall Time
0.5
1.6
ns
ns
ns
t
t
: 0.8V – 2.0V
: 2.0V – 0.8V
RISE/FALL
RISE
FALL
2X_Q Output
2
2
t
Output Pulse Width: Q0, Q1, Q2, Q3, Q4,
0.5t
– 0.5
0.5t
+ 0.5
Into a 50Ω Load
Terminated to V /2
PULSE WIDTH
CYCLE
CYCLE
(Q0–Q4, Q5, Q/2)
Q5, Q/2 @ V /2
CC
CC
t
Output Pulse Width:
2X_Q @ V
CC
80MHz
100MHz
133MHz
160MHz
0.5t
0.5t
0.5t
– 0.7
– 0.5
– 0.5
0.5t
0.5t
0.5t
+ 0.7
+ 0.5
+ 0.5
PULSE WIDTH
CYCLE
CYCLE
CYCLE
CYCLE
(2X_Q Output)
CYCLE
TBD
CYCLE
TBD
1
t
SYNC Feedback
SYNC Input to Feedback Delay
(Measured at SYNC0 or 1 and
FEEDBACK Input Pins)
ns
See Note 2 and
Figure 2 for Detailed
Explanation
(With 1MΩ from RC1 to An V
)
PD
CC
133MHz
160MHz
–1.05
–0.9
–0.25
–0.10
t
Cycle–to–Cycle Variation
133MHz
160MHz
t
t
– 300ps
– 300ps
t
t
+ 300ps
+ 300ps
CYCLE
CYCLE
CYCLE
CYCLE
CYCLE
(2x_Q Output)
3
t
Output–to–Output Skew Between Outputs
—
500
ps
ps
ps
ms
All Outputs Into a
Matched 50Ω Load
SKEWr
(Rising) See Note 4 Q0–Q4, Q/2 (Rising Edges Only)
Terminated to V /2
CC
3
t
Output–to–Output Skew Between Outputs
Q0–Q4 (Falling Edges Only)
—
—
500
750
10
All Outputs Into a
Matched 50Ω Load
SKEWf
(Falling)
Terminated to V /2
CC
3
t
Output–to–Output Skew 2X_Q, Q/2,
Q0–Q4 Rising, Q5 Falling
All Outputs Into a
Matched 50Ω Load
SKEWall
Terminated to V /2
CC
4
t
Time Required to Acquire Phase–Lock
From Time SYNC Input Signal is
Received
1.0
Also Time to LOCK
Indicator High
LOCK
5
t
t
Output Enable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
3.0
3.0
14
14
ns
ns
Measured With the
PLL_EN Pin Low
PZL
5
,t
Output Disable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
Measured With the
PLL_EN Pin Low
PHZ PLZ
1. T
in this spec is 1/Frequency at which the particular output is running.
CYCLE
2. The T specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
PD
3. Under equally loaded conditions and at a fixed temperature and voltage.
4. With V fully powered–on, and an output properly connected to the FEEDBACK pin. t
maximum is with C1 = 0.1µF, t
minimum is with
CC
LOCK
LOCK
C1 = 0.01µF.
5. The t , t
, t
minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is reached.
PZL PHZ PLZ
11
MOTOROLA
Applications Information for All Versions
General AC Specification Notes
2. These two specs (tRlSE/FALL and tPULSE Width 2X_Q
output) guarantee that the MC88915T meets the 40MHz
and 33MHz MC68040 P–Clock input specification (at
80MHz and 66MHz, respectively). For these two specs to
be guaranteed by Motorola, the termination scheme
shown below in Figure 1 must be used.
1. Several specifications can only be measured when the
MC88915TFN55, 70 and 100 are in phase–locked
operation. It is not possible to have the part in phase–lock
on ATE (automated test equipment). Statistical
characterization techniques were used to guarantee those
specifications which cannot be measured on the ATE.
MC88915TFN55, 70 and 100 units were fabricated with
key transistor properties intentionally varied to create a 14
cell designed experimental matrix. IC performance was
characterized over a range of transistor properties
(represented by the 14 cells) in excess of the expected
process variation of the wafer fabrication area, to set
performance limits of ATE testable specifications within
those which are to be guaranteed by statistical
characterization. In this way all units passing the ATE test
will meet or exceed the non–tested specifications limits.
3. The wiring Diagrams and explanations in Figure 5
demonstrate the input and output frequency relationships
for three possible feedback configurations. The allowable
SYNC input range for each case is also indicated. There
are two allowable SYNC frequency ranges, depending
whether FREQ_SEL is high or low. Although not shown, it
is possible to feed back the Q5 output, thus creating a 180°
phase shift between the SYNC input and the “Q” outputs.
Table 1 below summarizes the allowable SYNC frequency
range for each possible configuration.
Z (C LO CK T RA C E )
O
R
s
8
8
9
1
5
6
80
4
0
2
O
X
_
p
Q
P
-
C
p
l
u
o
c
t
k
u
t
u
t
I
n
R
p
R = Z- Ω7
s
o
Rp = 1.5 Zo
Figure 1. MC68040 P–Clock Input Termination Scheme
Table 1. Allowable SYNC Input Frequency Ranges for Different Feedback Configurations.
FREQ_SEL
Level
Feedback
Output
Allowable SYNC Input
Frequency Range (MHZ)
Corresponding VCO
Frequency Range
Phase Relationships
of the “Q” Outputs
to Rising SYNC Edge
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
Q/2
5 to (2X_Q FMAX Spec)/4
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAX Spec)
0°
0°
Any “Q” (Q0–Q4) 10 to (2X_Q FMAX Spec)/2
Q5
2X_Q
Q/2
10 to (2X_Q FMAX Spec)/2
20 to (2X_Q FMAX Spec)
180°
0°
2.5 to (2X_Q FMAX Spec)/8 20 to (2X_Q FMAX Spec)
0°
Any “Q” (Q0–Q4) 5 to (2X_Q FMAX Spec)/4
20 to (2X_Q FMAX Spec)
20 to (2X_Q FMAXSpec)
20 to (2X_Q FMAXSpec)
0°
Q5
5 to (2X_Q FMAX Spec)/4
10 to (2X_Q FMAX Spec)/2
180°
0°
2X_Q
4. A 1MΩ resistor tied to either Analog VCC or Analog GND as
shown in Figure 2 is required to ensure no jitter is present
on the MC88915T outputs. This technique causes a phase
offset between the SYNC input and the output connected
to the FEEDBACK input, measured at the input pins. The
tPD spec describes how this offset varies with process,
temperature, and voltage. The specs were arrived at by
measuring the phase relationship for the 14 lots described
in note 1 while the part was in phase–locked operation.
The actual measurements were made with a 10MHz
SYNC input (1.0ns edge rate from 0.8V – 2.0V) with the
Q/2 output fed back. The phase measurements were
made at 1.5V. The Q/2 output was terminated at the
FEEDBACK input with 100Ω to VCC and 100Ω to ground.
12
MOTOROLA
A N A LO G V C C
R C 1
EX T ER NA L LO O P F I LT E R
Ω1M
R E F ER E N C E
R E S I STO R
R C 1
R 2
3 30 Ω
R 2
C 1
3 3 0 Ω
0 . 1 µF
1 M Ω
RE F E R E N C E
R E S I STO R
0 . 1 µF
C 1
A N AL O G G N D
A N A LO G G N D
W i t h t h e Ω1 M r e s i st o r t i e d i n t h i s f a s h iosnp,e c i ftichaet io nt
m e a s ur e d a t t h e i n p u t p i n s i s :
Wi t h t he Ω1M r e si s t o r t i ed i n t h is f a sh i osnp,ec i fti chaet i o nt
m ea su re d at t h e i n pu t p i ns i s :
P D
P D
t
P D
=
2 . 2±5 n s 1 . 0n s
t
P D
=
- 0 . 7 7±5 n s 0 . 2 7 5n s
3 . 0V
3 . 0 V
SY N C I N PU T
S Y N C I N P U T
- 0 . 7 75 n s O FF SE T
2 . 25 n s O F FS E T
5 . 0 V
5
.
0
V
F E E D BA C K O U T P UT
F
E
E
D
B
A
C
K
O
U
T
P
U
T
Figure 2. Depiction of the Fixed SYNC to Feedback Offset (tPD)
Which is Present When a 1MΩ Resistor is Tied to VCC or Ground
5. The tSKEWr specification guarantees that the rising edges
of outputs Q/2, Q0, Q1, Q2, Q3, and Q4 will always fall
within a 500ps window within one part. However, if the
relative position of each output within this window is not
specified, the 500 ps window must be added to each side
of the tPD specification limits to calculate the total
part–to–part skew. For this reason the absolute
distribution of these outputs are provided in table 2. When
taking the skew data, Q0 was used as a reference, so all
measurements are relative to this output. The information
in Table 2 is derived from measurements taken from the 14
process lots described in Note 1, over the temperature and
voltage range.
Table 2. Relative Positions of Outputs Q/2, Q0–Q4, 2X_Q,
Within the 500ps tSKEWr Spec Window
–
(ps)
+
(ps)
Output
Q0
0
0
Q1
–72
–44
–40
–274
–16
–633
40
Q2
276
255
–34
250
–35
Q3
Q4
Q/2
2X_Q
13
MOTOROLA
6. Calculation of Total Output–to–Skew between multiple
the lower tPD limit, and [–0.5ns + 0.32ns] = –0.18ns is the
upper limit. Therefore the worst case skew of output Q2
between any number of parts is |(–1.37) – (–0.18)| =
1.19ns. Q2 has the worst case skew distribution of any
output, so 1.2ns is the absolute worst case
output–to–output skew between multiple parts.
parts (Part–to–Part skew)
By combining the tPD specification and the information in
Note 5, the worst case output–to–output skew between
multiple 88915’s connected in parallel can be calculated.
This calculation assumes that all parts have a common
SYNC input clock with equal delay of that input signal to
each part. This skew value is valid at the 88915 output pins
only (equally loaded), it does not include PCB trace delays
due to varying loads.
7. Note 4 explains that the tPD specification was measured
and is guaranteed for the configuration of the Q/2 output
connected to the FEEDBACK pin and the SYNC input
running at 10MHz. The fixed offset (tPD) as described
above has some dependence on the input frequency and
at what frequency the VCO is running. The graphs of
Figure 3 demonstrate this dependence.
With a 1MΩ resistor tied to analog VCC as shown in note
4, the tPD spec. limits between SYNC and the Q/2 output
(connected to the FEEDBACK pin) are –1.05ns and
–0.5ns. To calculate the skew of any given output between
two or more parts, the absolute value of the distribution of
that output given in table 2 must be subtracted and added
to the lower and upper tPD spec limits respectively. For
output Q2, [276 – (–44)] = 320ps is the absolute value of
the distribution. Therefore [–1.05ns – 0.32ns] = –1.37ns is
The data presented in Figure 3 is from devices
representing process extremes, and the measurements
were also taken at the voltage extremes (VCC = 5.25V and
4.75V). Therefore the data in Figure 3 is a realistic
representation of the variation of tPD
.
14
MOTOROLA
-
0
.
5
0
-
-
0
.
.
5
0
-
-
-
-
0
.
.
.
.
7
0
2
5
5
0
5
0
1
t
P
D
tPD
C
F EED B A C K
S
Y
N
C
FE E DBAC K
t o
S
Y
N
to
1
1
1
( ns)
(n s )
-
1.
5
0
-
2
.
2
.
5
5
.
0
7
.
5
1
0
.0
1
2
.5
1
5.
0
1
7
.
5
2
.5
5
.0
7
.
5
1
0.
0
1
2
.
5
1
5.
0
1
7.
5
2
0
.
0
2
2.
5
2
5.
0
2
7.
5
S
YN
C
I
N
P
U
T
F
R
EQ
U
E
N
C
Y
(
M
H
z
)
S
Y
N
C
I
N
P
U
T
F
R
E
Q
U
E
N
C
Y
( MHz)
F i g ur e 3 a.
F i g u r e 3 b .
t
v er s u s F r eq u e n cy Va r ia t i o n fo r Q / 2 O u tp u t Fte d v e r s us F r e q u en c y Va r i a ti o n fo r Q 4 O ut put Fe d
P D
PD
B ac k, I n cl u d i n g P r oc e s s a n d Vo l t a g e Va r i a°tCi o n @ B a2c5k, I n c l u di n g P r o c es s a n d Vo l ta g e Va r i a°tCio n
@
2 5
( W it h 1ΩM R e si s t or Ti e d t o A n a)l o g ( Wit h 1ΩM R e s i st o r Ti e d to A n a)l o g
V
V
CC
CC
3
3
2
2
.
.
.
.
5
0
5
0
3
3
2
.5
.0
.5
.0
t PD
C
tPD
C
F EED B A C K
S
Y
N
t
o
S
Y
N
to
FE E DBAC K
( ns)
2
(n s )
1
1
.
5
0
1
1
.
5
0
.
.
0 .5
0 .5
2
.
5
5
.
0
7
.
5
1
0
.0
1
2
.5
1
5
.
0
1
7
.
5
0
5
1
0
1
5
2
0
2
5
S
Y
N
C
I
N
P
U
T
F
R
E
Q
U
E
N
C
Y
(
M
H
z
)
S
Y
N
C
I
N
P
U
T
F
R
E
Q
U
E
N
C
Y
(
M
H
z
)
F
i
g
u
r
e
3
c
.
F
i
g
u
r
e
3
d
.
t
v er s u s F r eq u e n cy Va r ia t i o n fo r Q / 2 O u tp u t Fte d v e r s us F r e q u en c y Va r i a ti o n fo r Q 4 O ut put Fe d
P D
P
D
B
a
c
k
,
I
n
c
l
u
d
i
n
g
P
r
o
c
e
s
s
a
n
d
V
o
l
t
a
g
e
V
a
r
i
a
°
t
C
i
o
n
@
B
a
2
c
5
k
,
I
n
c
l
u
d
i
n
g
P
r
o
c
e
s
s
a
n
d
V
o
l
t
a
g
e
V
a
r
i
a
°
t
C
i
o
n
@
2 5
( W it h 1ΩM R e si s t or Ti e d t o A n a l og G N D ) ( Wit h 1ΩM R e s i st o r Ti e d to A n a l og G N D )
8. The lock indicator pin (LOCK) will reliably indicate a
phase–locked condition at SYNC input frequencies down
to 10MHz. At frequencies below 10MHz, the frequency of
correction pulses going into the phase detector form the
SYNC and FEEDBACK pins may not be sufficient to allow
the lock indicator circuitry to accurately predict a
phase–locked conditition. The MC88915T is guaranteed
to provide stable phase–locked operation down to the
appropriate minimum input frequency given in Table 1,
even though the LOCK pin may be LOW at frequencies
below 10MHZ. The exact minimum frequency where the
lock indicator functionality can be guaranteed will be
available when the MC88915T reaches ‘MC’ status.
15
MOTOROLA
S
(
Y
N
C
C
I
]
N
PU T
o r
S 1
SYN C [0 ])
Y
N
[
t
S
Y
N
C
I NP UT
C Y C L E
t
P
D
FEED BAC K
IN PU T
Q
/
2
OU TPU T
t
S
t
S
t
S K E
K
E
W
f
K
E
Wr
W f
t
S K E W R
t
S K E WA L L
Q
O
0
U
- Q 4
T PU T S
t
C Y C L E Q " O U T P U T S
Q
5
OU TPU T
2
X
_Q
OU TPU T
Figure 4. Output/Input Switching Waveforms and Timing Diagrams
(These waveforms represent the hook–up configuration of Figure 5a on page 17)
Timing Notes:
• The MC88915T aligns rising edges of the FEEDBACK input and SYNC input, therefore the SYNC input does
not require a 50% duty cycle.
• All skew specs are measured between the VCC/2 crossing point of the appropriate output edges.All skews
are specified as ‘windows’, not as a ± deviation around a center point.
• If a “Q” output is connected to the FEEDBACK input (this situation is not shown), the “Q” output frequency
would match the SYNC input frequency, the 2X_Q output would run at twice the SYNC frequency, and the
Q/2 output would run at half the SYNC frequency.
16
MOTOROLA
1 0 0 M Hz S I G N A L
2 5M H z F E ED B AC K S I GN AL
H I GH
1 :2 I n p u t to Q " O u tp u t F r e qu e nc y R e l a ti on s hi p
I n t h i s a p p l ic a t i o n , t h e Q / 2 o u t p u t is c o n n e c t e d t o
t h e F E E D BA C K i n p u t. T h e i n te r n a l PL L w il l li n e u p
t h e p o s i t iv e e d g es o f Q / 2 a n d SY N C , t h u s t h e Q / 2
f r e q ue n c y w i l l e q u al t h e S Y N C f r e q u e n c y. Th e Q "
o u t p ut s ( Q 0 -Q 4 , ) Q 5w i l l a l w a ys r u n a t 2 X t h e Q / 2
f r e q ue n c y, a n d t h e 2 X _ Q o u t pu t w il l r u n a t 4 X t h e
Q / 2 f r e q ue n c y.
R S T
Q 4
2X _ Q
Q 5
F E ED B AC K
R EF _ S EL
S YN C [ 0 ]
Q / 2
Q 3
Q 2
LOW
2 5 MH z IN P UT
CR YS TAL
OS CI L L ATO R
M C 88 9 1 5T
5 0 M H z
Q "
C L O CK
O U T PU T S
A NA L O G
V
C C
EX TER N AL
L O OP
FI LTE R
R C 1
A NA L O G G N D
A l l o w ab l e I n p u t F r e q ue n c y R a n g e:
P LL _ E N
F Q _S E L
H I GH
Q 0
Q 1
5 M H z to (2 X _ Q F M A X S p( feocr) / 4 F R E Q_ S E L H I G H )
2 . 5 M Hz to (2 X _ Q F M A X (Sf opre c)F/ 8R E Q _S E L L O W)
N o t e : I f t h e/ R SOTE i n p u t i s a c t i v e,
a
p u ll - u p o r p u ll - d o w n r e Ć
H I G H
s i s t o r i s n ' t n e c e ss a r y a t t h e F E E D BA C K p in s o it w o n ' t w h e
t h e f e d b a c k o u t p ut g o e s i n t o 3 - s t at e .
Figure 5a. Wiring Diagram and Frequency Relationships With Q/2 Output Feed Back
1 0 0 M Hz S I G N A L
5 0M H z F E ED B AC K S I GN A L
H I GH
1 :1 I n p u t to Q " O u tp u t F r eq ue n c y R e l a ti on s hi p
R
S
T
Q
5
Q 4
2X _ Q
2 5 M H z
S I G N AL
F E ED B AC K
R EF _ S EL
S YN C [ 0 ]
Q / 2
Q 3
Q 2
I n t h i s a p p l ic a t i o n , t h e Q 4 ou t p u t is c o n n e c t e d t o
t h e F E E D BA C K i n p u t. T h e i n t e r n a l PL L w il l li n e u p
t h e p o s i t iv e e d g es o f Q 4 a n d SY N C , t h u s t h e Q 4
f r e q ue n c y ( a n d t h e r e s t o f t h e Q " o u t p u t s ) w il l
LOW
5
0
M
H
Z
I
N
P
U
T
C RY STAL
OS CI L L ATO R
5 0 M H z
Q "
M C 88 9 1 5T
A NA L O G
R C 1
V
C
C
EX TER N AL
L O OP
FI LTE R
C L O CK e q u al t h e S Y N C f r e q ue n c y. T h e Q / 2 o u t p u t w il l a lĆ
O U T PU T S w a y s r u n a t 1 / 2 t h e Q " f r e q u e n c y, a n d t h e 2 X_ Q
o u t p ut w i l l r u n a t 2 X t h e Q " f r e q u e n c y.
A NA L O G G N D
P LL _E N
Q 1
F Q _S E L
H I GH
Q 0
A l l o w ab l e I n p u t F r e q u en c y R a n g e:
1 0 M H z to (2 X _ Q F M A X (Sf opre c)F/ 2R E Q_ S EL H I G H )
5 M H z to (2 X _ Q F M A X (Sf opre c)F/ 4R E Q_ S E L L O W)
H
I
G
H
Figure 5b. Wiring Diagram and Frequency Relationships With Q4 Output Feed Back
1 00 M H z F E ED B AC K S I GN A L
H I GH
2 :1 I n p u t to Q " O u tp u t F r eq ue n c y R e l a ti on s hi p
R S T
Q 4
2 X _ Q
Q / 2
Q 5
I n t h i s a p p l ic a t i o n , t h e 2 X _ Q o u t p u t is c o n n e c t e d
t o t h e F E E D BA C K i n p u t. T h e in t e r n a l PL L w il l li n e
u p t h e p o s i t iv e e d g es o f 2 X _Q a n d SY N C , t h u s t h e
2 X _ Q f r e q ue n c y w i l l e q u al t h e SY N C f r e q u e n c y.
T h e Q / 2 o u t p ut w i l l a l w a ys ru n a t 1 / 4 t h e 2 X_ Q f r
q u e nc y, a n d t h e Q " o u t p ut s w il l r u n a t 1 / 2 t h e
2 X _ Q f r e q ue n c y.
2 5 M H z
S I G N AL
F E ED B AC K
R EF _ S EL
S YN C [ 0 ]
A NA L O G
LOW
1 0 0 MH z IN P U T
M
C
8
8
9
1
5
T
C RY STAL
OS CI L L ATO R
Q 3
Q 2
5 0 M H z
Q "
C L O CK
O U T PU T S
V
C
C
EX TER N AL
L O OP
FI LTE R
R C 1
A NA L O G G N D
A l l o w ab l e I n p u t F r e q u en c y R a n g e:
P LL _ E N
Q 1
F Q _S E L
H I GH
Q
0
2 0 M H z to (2 X _ Q F M A X ( f oSr p e cF)R E Q _S E L H I G H )
1 0 M H z to (2 X _ Q F M A X S p( feocr) / 2 F R E Q _ SE L L O W)
H I G H
Figure 5c. Wiring Diagram and Frequency Relationships with 2X_Q Output Feed Back
17
MOTOROLA
B
O
A
R
D
V
C C
4
7
Ω
8
9
A
N
A
LO
G
V
C C
1
M
Ω
3
3
0
Ω
A
S
N
A
L
O
G
N
L
O
O
F
O
P
F
E
I LTE R/ V CO
C
0
.
1
µ
F
H
I
FR E
G
Q
H
1
0µ
F LO W
B YPA SS
E
C
T
I
O
T
H
M
8
8
9
1
5
T
T
R
C
1
F
R
EQ
2 8- P I N P LC C PA CK A GE (N O
D
B YPA SS
0
.1µ
F
(
L
O
O
CA P )
P
R
A
W
N
T
O
S
C
A
L
E
)
F
I
L
T
E
R
1
0
A
N
A
L
O
G
G
N
D
4
7Ω
A
S E PA RATE A NA LO G P O WE R S UP P LY I S NO T N EC ESS ARY AN D
S HO UL D NO T B E US E D. FO L LO W I NG THE S E P RE SC RI BE D G U ID EL IN ES
B
O
A
R
D
G
N
D
I S A LL THAT I S NE CE S S ARY TO US E THE MC 8 89 1 5 T IN
DI G I TA L E NV I RO NME NT.
A
N O RMA
Figure 6. Recommended Loop Filter and Analog Isolation Scheme for the MC88915T
Notes Concerning Loop Filter and Board Layout Issues
1. Figure 6 shows a loop filter and analog isolation scheme
88915T additional protection from the power supply and
ground plane transients that can occur in a high frequency,
high speed digital system.
which will be effective in most applications. The following
guidelines should be followed to ensure stable and
jitter–free operation:
1c.There are no special requirements set forth for the loop
filter resistors (1MΩ and 330Ω). The loop filter capacitor
(0.1µF) can be a ceramic chip capacitior, the same as a
standard bypass capacitor.
1a.All loop filter and analog isolation components should be
tied as close to the package as possible. Stray current
passing through the parasitics of long traces can cause
undesirable voltage transients at the RC1 pin.
1d.The 1M reference resistor injects current into the internal
charge pump of the PLL, causing a fixed offset between
the outputs and the SYNC input. This also prevents
excessive jitter caused by inherent PLL dead–band. If the
VCO (2X_Q output) is running above 40MHz, the 1MΩ
resistor provides the correct amount of current injection
into the charge pump (2–3µA). For the TFN55, 70 or 100,
if the VCO is running below 40MHz, a 1.5MΩ reference
resistor should be used (instead of 1MΩ).
1b.The 47Ω resistors, the 10µF low frequency bypass
capacitor, and the 0.1µF high frequency bypass capacitor
form a wide bandwidth filter that will minimize the 88915T’s
sensitivity to voltage transients from the system digital VCC
supply and ground planes. This filter will typically ensure
that a 100mV step deviation on the digital VCC supply will
cause no more than a 100pS phase deviation on the
88915T outputs. A 250mV step deviation on VCC using the
recommended filter values should cause no more than a
250pS phase deviation; if a 25µF bypass capacitor is used
(instead of 10µF) a 250mV VCC step should cause no more
than a 100pS phase deviation.
2. In addition to the bypass capacitors used in the analog filter
of Figure 6, there should be a 0.1µF bypass capacitor
between each of the other (digital) four VCC pins and the
board ground plane. This will reduce output switching
noise caused by the 88915T outputs, in addition to
reducing potential for noise in the ‘analog’ section of the
chip. These bypass capacitors should also be tied as close
to the 88915T package as possible.
If good bypass techniques are used on a board design
near components which may cause digital VCC and ground
noise, the above described VCC step deviations should not
occur at the 88915T’s digital VCC supply. The purpose of
the bypass filtering scheme shown in Figure 6 is to give the
18
MOTOROLA
C
C
P
A
U
R
C
M
M
U
C
C
M
M
M
M
U
U
D
MC 88 9 15 T
P
LL
C
L
O
CK
2
f
CP U
@
f
C
M
M
U
CM MU
S YS TEM
C LO CK
S OU RC E
C
C
P
A
U
R
C
C
M
M
M
M
U
U
D
C
M MU
M
C
8
8
L
9 15 T
P
L
CP U
2
f
D
IS
T
R
IB
UT
E
C
L
O
CK
@
f
C
M
M
U
CM MU
C
L
O
CK
@
2
f
AT
P
OI
N
T
O
F
U SE
MC 88 9 15 T
P LL
M
E
M
O
R
R
O
Y
L
2
f
C
O
N
T
M
E
M
O
CA RD S
R
Y
C
L
O
C
K
@
2 f
AT
P
O
I
N
T
O
F
U
S
E
Figure 7. Representation of a Potential Multi–Processing Application Utilizing the MC88915T
for Frequency Multiplication and Low Board–to–Board Skew
MC88915T System Level Testing Functionality
3–state functionality has been added to the 100MHz version of the MC88915T to ease system board testing. Bringing the
OE/RST pin low will put all outputs (except for LOCK) into the high impedance state. As long as the PLL_EN pin is low, the
Q0–Q4, Q5, and the Q/2 outputs will remain reset in the low state after the OE/RST until a falling SYNC edge is seen. The 2X_Q
output will be the inverse of the SYNC signal in this mode. If the 3–state functionality will be used, a pull–up or pull–down resistor
must be tied to the FEEDBACK input pin to prevent it from floating when the fedback output goes into high impedance.
With the PLL_EN pin low the selected SYNC signal is gated directly into the internal clock distribution network, bypassing
and disabling the VCO. In this mode the outputs are directly driven by the SYNC input (per the block diagram). This mode can
also be used for low frequency board testing.
Note: If the outputs are put into 3–state during normal PLL operation, the loop will be broken and phase–lock will be lost. It will
take a maximum of 10mS (tLOCK spec) to regain phase–lock after the OE/RST pin goes back high.
19
MOTOROLA
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
ISSUE D
M
ꢀ
S
S
0
.
0
0
7
ꢀ(
0.
1
8
0)
ꢀ
T
L
-
M
ꢀ
N
B
Y BRK
D
–N–
M
ꢀ
S
S
N
0
.
00
7ꢀ
(
0
.
1
8
0)
ꢀ
T
L
-
M
ꢀ
U
Z
–M–
–L–
W
D
S
S
S
N
0
.
0
1
0ꢀ
(
0
.
2
5
0)
ꢀ
T
L
-M
ꢀ
X
G1
V
28
1
VIEW D–D
M
S
S
S
A
0
.
0
0
7
ꢀ
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20
MOTOROLA
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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◊
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