MC74HC4353 [MOTOROLA]
Analog Multiplexers/Demultiplexers with Address Latch; 模拟多路复用器/多路解复用器与地址锁存
| 型号： | MC74HC4353 |
| 厂家： | 
MOTOROLA |
| 描述： | Analog Multiplexers/Demultiplexers with Address Latch |
| 文件： | 总13页 (文件大小：480K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
High–Performance Silicon–Gate CMOS
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
The MC54/74HC4351, and MC54/74HC4353 utilize silicon–gate CMOS
technology to achieve fast propagation delays, low ON resistances, and low
OFF leakage currents. These analog multiplexers/demultiplexers control
analog voltages that may vary across the complete power supply range
20
20
1
(from V
to V ).
CC
EE
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
The Channel–Select inputs determine which one of the Analog Inputs/
Outputs is to be connected, by means of an analog switch, to the Common
Output/Input. The data at the Channel–Select inputs may be latched by
using the active–low Latch Enable pin. When Latch Enable is high, the latch
is transparent. When either Enable 1 (active low) or Enable 2 (active high) is
inactive, all analog switches are turned off.
1
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
20
1
The Channel–Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with LSTTL
outputs.
ORDERING INFORMATION
These devices have been designed so that the ON resistance (R ) is
on
of metal–gate CMOS analog
MC54HCXXXXJ
MC74HCXXXXN
MC74HCXXXXDW
Ceramic
Plastic
SOIC
more linear over input voltage than R
switches.
on
For multiplexers/demultiplexers without latches, see the HC4051,
HC4052, and HC4053.
•
•
•
•
•
•
•
•
Fast Switching and Propagation Speeds
Low Crosstalk Between Switches
Diode Protection on All Inputs/Outputs
PIN ASSIGNMENT
MC54/74HC4351
Analog Power Supply Range (V
CC
– V ) = 2.0 to 12.0 V
EE
X4
1
20
V
CC
Digital (Control) Power Supply Range (V
Improved Linearity and Lower ON Resistance than Metal–Gate Types
Low Noise
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: HC4351 — 222 FETs or 55.5 Equivalent Gates
HC4353 — 186 FETs or 46.5 Equivalent Gates
– GND) = 2.0 to 6.0 V
CC
X6
NC
X
2
3
4
19
18
17
X2
X1
X0
X7
X5
5
6
7
16
15
14
X3
A
•
ENABLE 1
ENABLE 2
NC
8
13
12
11
B
C
V
9
EE
GND
LATCH
ENABLE
10
NC = NO CONNECTION
10/95
Motorola, Inc. 1995
REV 6
MC54/74HC4351 MC54/74HC4353
LOGIC DIAGRAM
MC54/74HC4351
Single–Pole, 8–Position Plus Common Off and Address Latch
17
18
19
X0
X1
X2
X3
X4
X5
X6
X7
FUNCTION TABLE
MC54/74HC4351
Control Inputs
Enable Select
16
1
ANALOG
INPUTS/OUTPUTS
MULTIPLEXER/
DEMULTIPLEXER
ON
COMMON
OUTPUT/INPUT
4
X
Channel
(LE = H)*
6
1
2
C
B
A
2
L
L
L
L
L
L
L
L
H
X
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
X
X
X0
X1
X2
X3
X4
X5
X6
X7
None
5
L
H
H
H
H
X
X
15
L
A
B
C
CHANNEL
ADDRESS
LATCH
CHANNEL–SELECT
INPUTS
H
H
X
X
13
12
PIN 20 = V
PIN 9 = V
PIN 10 = GND
CC
EE
None
11
7
LATCH ENABLE
PINS 3, 14 = NC
X = don’t care
SWITCH
ENABLES
ENABLE 1
ENABLE 2
* When Latch Enable is low, the Channel
Selection is latched and the Channel
Address Latch does not change states.
8
BLOCK DIAGRAM
MC54/74HC4353
Triple Single–Pole, Double–Position Plus Common Off and Address Latch
PIN ASSIGNMENT
16
17
X0
X1
18
X
X SWITCH
Y SWITCH
Z SWITCH
Y1
1
20
V
CC
Y0
NC
Z1
2
3
4
19
18
17
Y
X
2
1
COMMON
OUTPUT/INPUT
Y0
Y1
19
5
Y
Z
X1
6
4
Z0
Z1
Z
Z0
X0
A
5
16
15
14
13
12
11
6
ENABLE 1
ENABLE 2
7
NC
B
15
13
12
A
CHANNEL
ADDRESS
LATCH
8
CHANNEL–SELECT
INPUTS
B
C
PIN 20 = V
PIN 9 = V
PIN 10 = GND
CC
EE
V
9
C
EE
GND
LATCH
ENABLE
10
11
7
LATCH ENABLE
PINS 3, 14 = NC
SWITCH
NC = NO CONNECTION
ENABLE 1
ENABLE 2
8
ENABLES
FUNCTION TABLE
NOTE:
Control Inputs
On
Channel
(LE = H)*
This device allows independent control of each switch. Channel–Select
Input A controls the X Switch, Input B controls the Y Switch, and Input C
controls the Z Switch.
Enable
Select
B
1
2
C
A
L
L
L
L
L
L
L
L
H
X
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
X
X
Z0
Z0
Z0
Z0
Z1
Z1
Z1
Z1
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
None
None
X0
X1
X0
X1
X0
X1
X0
X1
L
H
H
H
H
X
X
L
H
H
X
X
X = Don’t Care
* When Latch Enable is low, the Channel Selection
is latched and the Channel Address Latch does not
change states.
MOTOROLA
2
MC54/74HC4351 MC54/74HC4353
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
CC
Positive DC Supply Voltage
(Ref. to GND)
(Ref. to V
– 0.5 to + 7.0
– 0.5 to 14.0
V
)
EE
V
EE
Negative DC Supply Voltage (Ref. to GND)
Analog Input Voltage
– 7.0 to + 0.5
V
V
V
IS
V
– 0.5
EE
to V
+ 0.5
CC
cuit. For proper operation, V and
in
V
DC Input Voltage (Ref. to GND)
DC Current Into or Out of Any Pin
– 1.5 to V
+ 1.5
V
in
CC
± 25
V
out
should be constrained to the
ranges indicated in the Recom-
mended Operating Conditions.
I
mA
mW
P
D
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
750
500
Unused digital input pins must be
tied to an appropriate logic voltage
level (e.g., either GND or V ).
CC
T
stg
Storage Temperature
– 65 to + 150
C
C
Unused Analog I/O pins may be left
open or terminated. See Applica-
tions Information.
T
L
Lead Temperature, 1 mm from Case for
10 Seconds
(Plastic DIP or SOIC Package)
(Ceramic DIP)
260
300
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
Ceramic DIP: – 10 mW/ C from 100 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Positive DC Supply Voltage
Min
Max
Unit
V
CC
(Ref. to GND)
(Ref. to V
2.0
2.0
6.0
12.0
V
)
EE
V
Negative DC Supply Voltage
(Ref. to GND) – 6.0 GND
V
V
EE
V
Analog Input Voltage
V
V
IS
EE
CC
CC
V
Digital Input Voltage (Ref. to GND)
Static or Dynamic Voltage Across Switch
Operating Temperature, All Package Types
GND
—
V
V
in
V
IO
*
1.2
V
T
– 55 + 125
C
ns
A
t , t
r f
Input Rise and Fall Time,
Channel Select or Enable
Inputs (Figure 9a)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
* For voltage drops across the switch greater than 1.2 V (switch on), excessive V
current may
CC
and switch input components.
be drawn; i.e., the current out of the switch may contain both V
CC
The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) V
= GND, Except Where Noted
Guaranteed Limit
– 55 to
EE
V
CC
V
Symbol
Parameter
Test Conditions
= Per Spec
25 C
Unit
85 C
125 C
V
IH
Minimum High–Level Input
Voltage, Channel–Select or
Enable Inputs
R
R
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
on
on
V
IL
Maximum Low–Level Input
Voltage, Channel–Select or
Enable Inputs
= Per Spec
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
I
Maximum Input Leakage
Current, Channel–Select or
Enable Inputs
V
V
= V
or GND,
6.0
± 0.1
± 1.0
± 1.0
µA
µA
in
in
CC
= – 6.0 V
EE
I
Maximum Quiescent Supply
Current (per Package)
Channel Select = V
Enables = V
or GND
or GND
CC
CC
CC
or GND
V
V
= V
= 0 V
V
EE
V
EE
= GND
= – 6.0
6.0
6.0
2
8
20
80
40
160
IS
IO
CC
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
3
MOTOROLA
MC54/74HC4351 MC54/74HC4353
DC ELECTRICAL CHARACTERISTICS Analog Section
Guaranteed Limit
– 55 to
V
CC
V
V
EE
V
Symbol
Parameter
Test Conditions
25 C
Unit
85 C
125 C
R
Maximum “ON” Resistance
Ω
V
V
= V or V
4.5
4.5
6.0
0.0
– 4.5
– 6.0
190
120
100
240
150
125
280
170
140
on
in
IS
IL IH
= V to V
CC EE
I
S
2.0 mA (Figures 1, 2)
V
V
= V or V
4.5
4.5
6.0
0.0
– 4.5
– 6.0
150
100
80
190
125
100
230
140
115
in
IS
IL IH
= V or V
CC EE
(Endpoints)
I
S
2.0 mA (Figures 1, 2)
∆R
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
V
V
= V or V
IL
CC
2.0 mA
4.5
4.5
6.0
0.0
– 4.5
– 6.0
30
12
10
35
15
12
40
18
14
Ω
on
in
IS
IH
= 1/2 (V
– V
)
EE
I
S
I
off
µA
Maximum Off–Channel Leakage
Current, Any One Channel
V
V
= V or V
IL
6.0
– 6.0
0.1
0.5
1.0
in
IH
= V
– V
IO
CC EE
Switch Off (Figure 3)
V
V
= V or V
IL IH
Maximum Off–Channel Leakage
Current, Common Channel
HC4351
in
= V
– V
IO
CC EE
Switch Off (Figure 4)
6.0
6.0
– 6.0
– 6.0
0.2
0.1
2.0
1.0
4.0
2.0
HC4353
I
on
V
= V or V
µA
Maximum On–Channel Leakage
Current, Channel to Channel
HC4351
in IL IH
Switch to Switch = V
(Figure 5)
– V
EE
CC
6.0
6.0
– 6.0
– 6.0
0.2
0.1
2.0
1.0
4.0
2.0
HC4353
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
V
Symbol
Parameter
25 C
Unit
85 C
125 C
t
t
t
t
,
Maximum Propagation Delay, Channel–Select to Analog Output
(Figure 9)
2.0
4.5
6.0
370
74
63
465
93
79
550
110
94
ns
PLH
t
PHL
,
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
ns
ns
ns
PLH
t
PHL
,
Maximum Propagation Delay, Latch Enable to Analog Output
(Figure 12)
2.0
4.5
6.0
325
65
55
410
82
70
485
97
82
PLH
t
PHL
,
Maximum Propagation Delay, Enable 1 or 2 to Analog Output
(Figure 11)
2.0
4.5
6.0
290
58
49
365
73
62
435
87
74
PLZ
t
PHZ
t
t
,
Maximum Propagation Delay, Enable 1 or 2 to Analog Output
(Figure 11)
2.0
4.5
6.0
345
69
59
435
87
74
515
103
87
PZL
PZH
C
Maximum Input Capacitance
—
—
—
10
35
10
35
10
35
pF
pF
in
C
Enable 1 = V , Enable 2 = V
IH
Maximum Capacitance Analog I/O
l/O
IL
Common O/I: HC4351
HC4353
130
50
130
50
130
50
Feedthrough
—
1.0
1.0
1.0
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
CC
= 5.0 V
C
Power Dissipation Capacitance (Per Package) (Figure 14)*
pF
45 (HC4351)
45 (HC4353)
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
Motorola High–Speed CMOS Data Book (DL129/D).
V
f + I
V . For load considerations, see Chapter 2 of the
CC CC
PD CC
MOTOROLA
4
MC54/74HC4351 MC54/74HC4353
TIMING REQUIREMENTS (Input t = t = 6 ns)
r
f
Guaranteed Limit
V
CC
V
– 55 to
25 C
Symbol
Parameter
Unit
85 C
125 C
t
su
Minimum Setup Time, Channel–Select to Latch Enable
(Figure 12)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
t
Minimum Hold Time, Latch Enable to Channel Select
(Figure 12)
2.0
4.5
6.0
0
0
0
0
0
0
0
0
0
ns
ns
ns
h
t
w
Minimum Pulse Width, Latch Enable
(Figure 12)
2.0
4.5
6.0
80
16
14
100
20
17
120
24
20
t , t
r f
Maximum Input Rise and Fall Times, Channel–Select, Latch Enable,
and Enables 1 and 2
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0.0 V)
Limit*
V
CC
V
V
EE
V
25 C
54/74HC
Symbol
Parameter
Test Condition
= 1 MHz Sine Wave
Unit
BW
Maximum On–Channel Bandwidth or
Minimum Frequency Response
(Figure 6)
f
MHz
in
Adjust f Voltage to Obtain 0 dBm at V
51 52 53
in
OS
80 95 120
80 95 120
80 95 120
Increase f Frequency Until dB Meter
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
in
Reads – 3 dB
R
= 50 Ω, C = 10 pF
L
L
—
Off–Channel Feedthrough Isolation
(Figure 7)
dB
f
Sine Wave
in
Adjust f Voltage to Obtain 0 dBm at V
in IS
f
= 10 kHz, R = 600 Ω, C = 50 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
– 50
– 50
– 50
in
L
L
f
in
= 1.0 MHz, R = 50 Ω, C = 10 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
– 40
– 40
– 40
L
L
—
Feedthrough Noise, Channel Select
Input to Common O/I
(Figure 8)
mV
PP
V
1 MHz Square Wave
in
(t = t = 6 ns)
r
f
Adjust R at Setup so that I = 0 A
L
S
Enable = GND
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
25
105
135
R
= 600 Ω, C = 50 pF
L
L
R
= 10 kΩ, C = 10 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
35
145
190
L
L
—
Crosstalk Between Any Two Switches
(Figure 13)
(Test does not apply to HC4351)
dB
f
Sine Wave
in
Adjust f Voltage to Obtain 0 dBm at V
in IS
f
in
= 10 kHz, R = 600 Ω, C = 50 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
– 50
– 50
– 50
L
L
f
in
= 1 MHz, R = 50 Ω, C = 10 pF
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
– 60
– 60
– 60
L
L
THD
Total Harmonic Distortion
(Figure 15)
f
= 1 kHz, R = 10 kΩ, C = 50 pF
%
in
L
L
THD = THD
– THD
Measured
Source
V
V
= 4.0 V
= 8.0 V
sine wave
2.25
4.50
6.00
– 2.25
– 4.50
– 6.00
0.10
0.08
0.05
IS
IS
PP
PP
PP
sine wave
sine wave
V
IS
= 11.0 V
* Limits not tested. Determined by design and verified by qualification.
5
MOTOROLA
MC54/74HC4351 MC54/74HC4353
250
200
100
80
125°C
25°C
125°C
150
100
60
40
25°C
–55°C
–55°C
50
20
0
0.25 0.50
0.75
1.0
1.25
1.5
1.75
2.0
2.25
0
0.5
1.0
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V
IS
1.5
2.0
2.5
3.0
3.5
4.0
4.5
V
, INPUT VOLTAGE (VOLTS), REFERENCED TO V
IS EE
EE
Figure 1a. Typical On Resistance, V
– V
EE
= 2.0 V
Figure 1b. Typical On Resistance, V
– V = 4.5 V
EE
CC
CC
105
90
75
60
45
30
15
75
60
125°C
125°C
25°C
25°C
45
30
–55°C
–55°C
15
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
EE
9.0
V
, INPUT VOLTAGE (VOLTS), REFERENCED TO V
V
, INPUT VOLTAGE (VOLTS), REFERENCED TO V
IS
EE
IS
Figure 1c. Typical On Resistance, V
– V
EE
= 6.0 V
Figure 1d. Typical On Resistance, V
– V = 9.0 V
EE
CC
CC
PLOTTER
70
60
50
40
30
20
10
125°C
PROGRAMMABLE
MINI COMPUTER
DC ANALYZER
POWER
SUPPLY
25°C
–
+
V
CC
–55°C
DEVICE
UNDER TEST
ANALOG IN
COMMON OUT
0
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0
V
EE
GND
V
, INPUT VOLTAGE (VOLTS), REFERENCED TO V
IS
EE
Figure 1e. Typical On Resistance, V
CC
– V
EE
= 12.0 V
Figure 2. On Resistance Test Set–Up
MOTOROLA
6
MC54/74HC4351 MC54/74HC4353
V
V
CC
CC
V
CC
V
CC
20
20
V
V
V
V
EE
EE
ANALOG I/O
ANALOG I/O
OFF
OFF
OFF
OFF
A
A
CC
CC
COMMON O/I
NC
COMMON O/I
7
8
7
8
V
V
IH
IH
9
9
10
10
V
V
EE
EE
Figure 3. Maximum Off Channel Leakage Current,
Any One Channel, Test Set–Up
Figure 4. Maximum Off Channel Leakage Current,
Common Channel, Test Set–Up
V
V
OS
V
V
CC
20
CC
V
CC
20
0.1
µ
F
A
dB
METER
f
ON
ON
in
N/C
R
C *
L
COMMON O/I
L
OFF
EE
CC
V
CC
ANALOG I/O
V
7
8
9
10
7
8
9
V
V
IL
IH
10
V
EE
V
EE
*Includes all probe and jig capacitance.
Figure 5. Maximum On Channel Leakage Current,
Channel to Channel, Test Set–Up
Figure 6. Maximum On Channel Bandwidth,
Test Set–Up
V
V
OS
V
CC
V
IS
CC
20
20
0.1 µF
dB
METER
R
L
f
in
OFF
ON/OFF
OFF/ON
COMMON O/I
C *
TEST
POINT
ANALOG I/O
R
L
C *
R
L
L
R
L
L
R
L
7
8
9
10
V
CC
7
8
9
10
V
CC
V
≤
1 MHz
11
in
t = t = 6 ns
V
r
f
EE
V
GND
V
CC
EE
CHANNEL SELECT
*Includes all probe and jig capacitance.
*Includes all probe and jig capacitance.
Figure 7. Off Channel Feedthrough Isolation,
Test Set–Up
Figure 8. Feedthrough Noise, Channel Select to
Common Out, Test Set–Up
7
MOTOROLA
MC54/74HC4351 MC54/74HC4353
V
CC
V
CC
20
ON/OFF
OFF/ON
COMMON O/I
C *
TEST
POINT
ANALOG I/O
t
t
f
r
L
V
CC
V
CC
90%
50%
10%
CHANNEL SELECT
7
8
GND
9
10
t
t
PHL
PLH
50%
ANALOG OUT
CHANNEL SELECT
*Includes all probe and jig capacitance.
Figure 9a. Propagation Delays, Channel Select
to Analog Out
Figure 9b. Propagation Delay, Test Set–Up Channel
Select to Analog Out
V
CC
20
COMMON O/I
ANALOG I/O
TEST
POINT
ON
ANALOG
IN
V
CC
C *
L
V
CC
50%
7
8
GND
t
t
PHL
9
PLH
10
ANALOG
OUT
50%
*Includes all probe and jig capacitance.
Figure 10b. Propagation Delay, Test Set–Up
Analog In to Analog Out
Figure 10a. Propagation Delays, Analog In to
Analog Out
1
2
POSITION
POSITION
WHEN TESTING t
PHZ
AND t
PZH
WHEN TESTING t
PLZ
AND t
PZL
1
2
V
CC
20
V
V
CC
CC
1 k
Ω
ENABLE
50%
1
2
GND
ANALOG I/O
TEST
POINT
ON/OFF
t
t
PLZ
PZL
HIGH
C *
L
ANALOG
OUT
IMPEDANCE
50%
7
8
9
10
10%
90%
V
V
OL
ENABLE
t
t
PHZ
PZH
OH
ANALOG
OUT
50%
HIGH
IMPEDANCE
Figure 11a. Propagation Delay, Enable 1 or 2
to Analog Out
Figure 11b. Propagation Delay, Test Set–Up
Enable to Analog Out
MOTOROLA
8
MC54/74HC4351 MC54/74HC4353
V
CC
V
20
CC
V
CC
CHANNEL
SELECT
50%
ON/OFF
OFF/ON
COMMON O/I
C *
TEST
POINT
ANALOG I/O
GND
t
t
h
su
L
V
t
t
f
CC
r
V
CC
90%
50%
7
8
9
10
LATCH
ENABLE 2
10%
GND
11
t
w
LATCH ENABLE
COMMON O/I
50%
CHANNEL SELECT
t
t
,
PLH
*Includes all probe and jig capacitance.
PHL
Figure 12a. Propagation Delay, Latch Enable to
Analog Out
Figure 12b. Propagation Delay, Test Set–Up
Latch Enable to Analog Out
V
V
V
CC
IS
CC
A
V
CC
20
R
V
20
L
OS
f
ON
in
ON/OFF
OFF/ON
0.1
CC
µF
dB
METER
NC
ANALOG I/O
COMMON O/I
OFF
V
CC
V
V
EE
R
L
R
C *
R
C *
L
7
8
L
L
L
V
7
CC
8
9
9
10
11
10
V
EE
CHANNEL SELECT
*Includes all probe and jig capacitance.
Figure 13. Crosstalk Between Any Two
Switches, Test Set–Up
Figure 14. Power Dissipation Capacitance,
Test Set-Up
0
–10
–20
–30
–40
FUNDAMENTAL FREQUENCY
V
IS
V
CC
V
OS
20
0.1 µF
TO
f
ON
DISTORTION
METER
in
R
C *
L
L
–50
–60
–70
–80
V
DEVICE
CC
7
8
9
10
SOURCE
–90
V
EE
1.0
2.0
3.125
*Includes all probe and jig capacitance.
FREQUENCY (kHz)
Figure 15a. Total Harmonic Distortion, Test Set-Up
Figure 15b. Plot, Harmonic Distortion
9
MOTOROLA
MC54/74HC4351 MC54/74HC4353
ever, tying unused analog inputs and outputs to V
CC
or GND
APPLICATIONS INFORMATION
through a low value resistor helps minimize crosstalk and
feedthrough noise that may be picked up by an unused
switch.
Although used here, balanced supplies are not a require-
ment. The only constraints on the power supplies are that:
The Channel Select and Enable control pins should be at
V
or GND logic levels. V being recognized as a logic
CC
CC
high and GND being recognized as a logic low. In this
example:
V
= + 5 V = logic high
V
– GND = 2 to 6 volts
CC
CC
– GND = 0 to – 6 volts
GND = 0 V = logic low
V
EE
The maximum analog voltage swings are determined by
V
– V
= 2 to 12 volts
GND
When voltage transients above V and/or below V
CC
EE
the supply voltages V
voltage should not exceed V . Similarly, the negative peak
analog voltage should not go below V . In this example, the
and V . The positive peak analog
CC
EE
and V
EE
CC
are
EE
EE
CC
anticipated on the analog channels, external Germanium or
Schottky diodes (D ) are recommended as shown in
Figure 17. These diodes should be able to absorb the maxi-
mum anticipated current surges during clipping.
difference between V
and V
is ten volts. Therefore, us-
EE
CC
ing the configuration in Figure 16, a maximum analog signal
of ten volts peak–to–peak can be controlled. Unused analog
inputs/outputs may be left floating (i.e., not connected). How-
x
V
V
CC
EE
CC
+5 V
V
CC
20
ON/OFF
D
D
D
20
x
x
+ 5 V
– 5 V
+ 5 V
– 5 V
ANALOG
SIGNAL
ANALOG
SIGNAL
ON
D
x
x
+5 V
V
V
EE
7
8
9
10
15
13
12
11
TO EXTERNAL CMOS
CIRCUITRY
9
10
0 TO 5 V DIGITAL
SIGNALS
–5 V
V
EE
Figure 16. Application Example
Figure 17. External Germanium or
Schottky Clipping Diodes
+ 5 V
20
+ 5 V
20
ON/OFF
+ 5 V
+ 5 V
+ 5 V
+ 5 V
ANALOG
SIGNAL
ANALOG
ANALOG
SIGNAL
ANALOG
SIGNAL
ON/OFF
SIGNAL
V
V
V
V
EE
EE
EE
+ 5 V
EE
*
+ 5 V
V
V
R
R
R
R
CC
V
V
7
15
CC
7
8
9
10
15
8
13
12
11
LSTTL/NMOS
CIRCUITRY
LSTTL/NMOS
CIRCUITRY
13
12
11
9
10
HCT
BUFFER
* 2 k
≤
R
≤
10 k
EE
EE
a. Using Pull–Up Resistors
b. Using HCT Interface
Figure 18. Interfacing LSTTL/NMOS to CMOS Inputs
MOTOROLA
10
MC54/74HC4351 MC54/74HC4353
FUNCTION DIAGRAM HC4351
LATCH &
LEVEL SHIFTER
15
13
12
17
X0
A
B
C
X1
X2
X3
X4
LATCH &
LEVEL SHIFTER
LATCH &
LEVEL SHIFTER
6
X5
LATCH 11
ENABLE
7
2
ENABLE 1
X6
LEVEL SHIFTER
8
ENABLE 2
5
X7
4
X
FUNCTION DIAGRAM HC4353
LATCH &
LEVEL SHIFTER
15
A
17
X1
16
X0
18
X
13
B
LATCH &
LEVEL SHIFTER
1
Y1
2
Y0
19
Y
12
C
LATCH &
LEVEL SHIFTER
4
Z1
6
Z0
LATCH 11
ENABLE
5
Z
7
ENABLE 1
LEVEL SHIFTER
8
ENABLE 2
11
MOTOROLA
MC54/74HC4351 MC54/74HC4353
OUTLINE DIMENSIONS
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
ISSUE E
NOTES:
1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
20
1
11
10
3. DIMENSIONS A AND B INCLUDE MENISCUS.
B
C
MILLIMETERS
INCHES
A
DIM
A
B
C
D
F
MIN
23.88
6.60
3.81
0.38
1.40
MAX
25.15
7.49
5.08
0.56
1.65
MIN
MAX
0.990
0.295
0.200
0.022
0.065
0.940
0.260
0.150
0.015
0.055
L
F
G
H
J
K
L
2.54 BSC
0.100 BSC
0.51
0.20
3.18
1.27
0.30
4.06
0.020
0.008
0.125
0.050
0.012
0.160
N
J
7.62 BSC
0.300 BSC
H
K
M
G
M
N
0
15
0
15
D
0.25
1.02
0.010
0.040
SEATING
PLANE
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
20
1
11
10
B
L
C
INCHES
MILLIMETERS
DIM
A
B
C
D
MIN
MAX
1.070
0.260
0.180
0.022
MIN
25.66
6.10
3.81
0.39
MAX
27.17
6.60
4.57
0.55
1.010
0.240
0.150
0.015
–T–
SEATING
PLANE
K
E
0.050 BSC
1.27 BSC
M
0.050
0.070
1.27
1.77
F
G
J
K
L
N
E
0.100 BSC
2.54 BSC
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
G
F
J 20 PL
0.300 BSC
7.62 BSC
D 20 PL
0.25 (0.010)
M
M
0.25 (0.010)
T B
M
N
0
15
0
15
0.020
0.040
0.51
1.01
M
M
T
A
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–04
ISSUE E
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
10X P
–B–
M
M
0.010 (0.25)
B
1
10
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
20X D
DIM
A
B
C
D
MIN
12.65
7.40
2.35
0.35
0.50
MAX
12.95
7.60
2.65
0.49
0.90
MIN
MAX
0.510
0.299
0.104
0.019
0.035
J
0.499
0.292
0.093
0.014
0.020
M
S
S
0.010 (0.25)
T
A
B
F
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
0.25
0.10
0
0.32
0.25
7
0.010
0.004
0
0.012
0.009
7
R X 45
10.05
0.25
10.55
0.75
0.395
0.010
0.415
0.029
C
SEATING
PLANE
–T–
M
18X G
K
MOTOROLA
12
MC54/74HC4351 MC54/74HC4353
Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
andspecifically disclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters can and do vary in different
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associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
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相关型号：
MC74HC4511DD
Seven Segment Decoder/Driver, HC/UH Series, True Output, CMOS, PDSO16, SOIC-16
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