MC14017B_技术文档

SEMICONDUCTOR TECHNICAL DATA

L SUFFIX

CERAMIC

CASE 620

The MC14017B is a five–stage Johnson decade counter with built–in code

converter. High speed operation and spike–free outputs are obtained by use

of a Johnson decade counter design. The ten decoded outputs are normally

low, and go high only at their appropriate decimal time period. The output

changes occur on the positive–going edge of the clock pulse. This part can

be used in frequency division applications as well as decade counter or

decimal decode display applications.

P SUFFIX

PLASTIC

CASE 648

•

Fully Static Operation

DC Clock Input Circuit Allows Slow Rise Times

Carry Out Output for Cascading

D SUFFIX

SOIC

CASE 751B

Divide–by–N Counting

Supply Voltage Range = 3.0 Vdc to 18 Vdc

Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

Pin–for–Pin Replacement for CD4017B

Triple Diode Protection on All Inputs

ORDERING INFORMATION

MC14XXXBCP

MC14XXXBCL

MC14XXXBD

Plastic

Ceramic

SOIC

•

T

A

= – 55° to 125°C for all packages.

MAXIMUM RATINGS* (Voltages Referenced to V

)

SS

Symbol

Parameter

DC Supply Voltage

Value

Unit

V

DD

– 0.5 to + 18.0

FUNCTIONAL TRUTH TABLE

(Positive Logic)

V , V

in out

Input or Output Voltage (DC or Transient)

– 0.5 to V

DD

+ 0.5

V

l , l

in out

Input or Output Current (DC or Transient),

per Pin

± 10

mA

Clock

Decode

Clock Enable Reset Output=n

P

D

Power Dissipation, per Package†

Storage Temperature

500

mW

C

0

X

1

X

0

1

0

n

Q0

n+1

n

T

stg

– 65 to + 150

260

T

L

Lead Temperature (8–Second Soldering)

C

X

* Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

X

1

n

n+1

Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C

Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C

X = Don’t Care. If n < 5 Carry = “1”,

Otherwise = “0”.

LOGIC DIAGRAM

Q5

Q1

Q7

Q3

Q9

BLOCK DIAGRAM

1

2

6

7

11

CLOCK 14

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

3

2

4

7

10

1

5

6

14

CLOCK

ENABLE

12

C

Q

C

Q

C

Q

C

Q

C

Q

CARRY

13

15

C

D

R

C

D

R

C

D

R

C

D

R

CLOCK

D

R

Q

R

Q

R

Q

R

13

ENABLE

RESET

9

11

RESET 15

C

out

12

V

= PIN 16

= PIN 8

DD

SS

3

5

4

9

10

Q0

Q6

Q2

Q3

Q4

REV 3

1/94

Motorola, Inc. 1995

MC14017B

MOTOROLA CMOS LOGIC DATA

74

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

)

SS

– 55 C

25 C

Typ #

125 C

V

Vdc

DD

Characteristic

Output Voltage

Symbol

Unit

Min

Max

Min

Max

Min

Max

“0” Level

“1” Level

“0” Level

V

OL

5.0

10

15

—

0.05

—

0

0.05

—

0.05

Vdc

V

in

= V

DD

or 0

V

OH

5.0

10

15

4.95

9.95

14.95

—

4.95

9.95

14.95

5.0

10

15

—

4.95

9.95

14.95

—

Vdc

V

in

= 0 or V

DD

Input Voltage

(V = 4.5 or 0.5 Vdc)

V

IL

5.0

10

15

—

1.5

3.0

4.0

—

2.25

4.50

6.75

1.5

3.0

4.0

—

1.5

3.0

4.0

O

(V = 9.0 or 1.0 Vdc)

O

(V = 13.5 or 1.5 Vdc)

O

“1” Level

V

IH

Vdc

(V = 0.5 or 4.5 Vdc)

O

5.0

10

15

3.5

7.0

11

—

3.5

7.0

11

2.75

5.50

8.25

—

3.5

7.0

11

—

(V = 1.0 or 9.0 Vdc)

O

(V = 1.5 or 13.5 Vdc)

O

Output Drive Current

I

mAdc

OH

(V

= 2.5 Vdc)

= 4.6 Vdc)

= 9.5 Vdc)

= 13.5 Vdc)

Source

Sink

5.0

10

– 3.0

– 0.64

– 1.6

– 4.2

—

– 2.4

– 0.51

– 1.3

– 3.4

– 4.2

– 0.88

– 2.25

– 8.8

—

– 1.7

– 0.36

– 0.9

– 2.4

—

OH

15

(V

OL

(V

OL

(V

OL

= 0.4 Vdc)

= 0.5 Vdc)

= 1.5 Vdc)

I

5.0

10

15

0.64

1.6

4.2

—

0.51

1.3

3.4

0.88

2.25

8.8

—

0.36

0.9

2.4

—

mAdc

OL

Input Current

I

15

—

± 0.1

—

±0.00001

± 0.1

—

± 1.0

µAdc

in

Input Capacitance

C

—

5.0

7.5

—

pF

in

(V = 0)

in

Quiescent Current

(Per Package)

I

5.0

10

15

—

5.0

10

20

—

0.005

0.010

0.015

5.0

10

20

—

150

300

600

µAdc

DD

Total Supply Current**†

I

T

5.0

10

15

I

= (0.27 µA/kHz) f + I

= (0.55 µA/kHz) f + I

= (0.83 µA/kHz) f + I

T

DD

(Dynamic plus Quiescent,

Per Package)

(C = 50 pF on all outputs, all

L

buffers switching)

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

**The formulas given are for the typical characteristics only at 25 C.

†To calculate total supply current at loads other than 50 pF:

I (C ) = I (50 pF) + (C – 50) Vfk

T

L

T

L

where: I is in µA (per package), C in pF, V = (V

DD

– V ) in volts, f in kHz is input frequency, and k = 0.0011.

SS

T

L

PIN ASSIGNMENT

This device contains protection circuitry to guard against damage

due to high static voltages or electric fields. However, precautions must

be taken to avoid applications of any voltage higher than maximum rated

Q5

Q1

1

2

16

15

V

DD

RESET

CLOCK

voltages to this high-impedance circuit. For proper operation, V and

in

V

out

should be constrained to the range V

SS

≤ (V or V ) ≤ V .

in out DD

Q0

Q2

Q6

Q7

Q3

3

4

5

6

7

8

14

13

12

11

10

9

Unused inputs must always be tied to an appropriate logic voltage

level (e.g., either V or V ). Unused outputs must be left open.

CE

SS DD

C

out

Q9

Q4

Q8

V

SS

MOTOROLA CMOS LOGIC DATA

MC14017B

75

SWITCHING CHARACTERISTICS* (C = 50 pF, T = 25 C)

L

A

V

Vdc

DD

Characteristic

Output Rise and Fall Time

Symbol

Min

Typ #

Max

Unit

t

,

ns

TLH

t

, t

= (1.5 ns/pF) C + 25 ns

5.0

10

15

—

100

50

40

200

100

80

TLH THL

L

THL

, t

= (0.75 ns/pF) C + 12.5 ns

L

TLH THL

, t

TLH THL

= (0.55 ns/pF) C + 9.5 ns

L

Propagation Delay Time

Reset to Decode Output

t

,

ns

PLH

t

PHL

t

, t

= (1.7 ns/pF) C + 415 ns

= (0.66 ns/PF) C + 197 ns

L

= (0.5 ns/pF) C + 150 ns

5.0

10

15

—

500

230

175

1000

460

350

PLH PHL

L

, t

PLH PHL

, t

PLH PHL

L

Propagation Delay Time

,

PLH

Clock to C

t

PHL

out

= (1.7 ns/pF) C + 315 ns

= (0.66 ns/pF) C + 142 ns

= (0.5 ns/pF) C + 100 ns

L

t

, t

5.0

10

15

—

400

175

125

800

350

250

PLH PHL

L

, t

PLH PHL

, t

PLH PHL

Propagation Delay Time

Clock to Decode Output

,

PLH

t

PHL

t

, t

= (1.7 ns/pF) C + 415 ns

= (0.66 ns/pF) C + 197 ns

L

= (0.5 ns/pF) C + 150 ns

5.0

10

15

—

500

230

175

1000

460

350

PLH PHL

L

, t

PLH PHL

, t

PLH PHL

L

Turn–Off Delay Time

t

PLH

Reset to C

out

= (1.7 ns/pF) C + 315 ns

t

5.0

10

15

—

400

175

125

800

350

250

PLH

L

= (0.66 ns/pF) C + 142 ns

L

= (0.5 ns/pF) C + 100 ns

L

Clock Pulse Width

t

5.0

10

15

250

100

75

125

50

35

—

ns

MHz

ns

w(H)

Clock Frequency

f

cl

5.0

10

15

—

5.0

12

16

2.0

5.0

6.7

Reset Pulse Width

t

5.0

10

15

500

250

190

250

125

95

—

w(H)

Reset Removal Time

Clock Input Rise and Fall Time

Clock Enable Setup Time

Clock Enable Removal Time

t

5.0

10

15

750

275

210

375

135

105

—

ns

rem

t

,

5.0

10

15

—

TLH

THL

No Limit

t

su

5.0

10

15

350

150

115

175

75

52

—

ns

t

5.0

10

15

420

200

140

260

100

70

—

ns

rem

* The formulas given are for the typical characteristics only at 25 C.

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14017B

76

MOTOROLA CMOS LOGIC DATA

V

DD

V

Output

Sink Drive Source Drive

Output

out

CLOCK

ENABLE

V

Q0

SS

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Clock to

desired

outputs

(S1 to B)

Decode

Outputs

(S1 to A)

A

B

V

S1

DD

I

D

RESET

Clock to 5

thru 9

(S1 to B)

V

Carry

S1 to A

SS

V

=

V

DD

– V

GS

DD

Q9

out

EXTERNAL

POWER

SUPPLY

V

out

V – V

out DD

C

DS

CLOCK

V

SS

Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit

V

DD

0.01

CERAMIC

µF

I

500

µF

D

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

CLOCK

ENABLE

RESET

CLOCK

f

PULSE

GENERATOR

c

C

out

V

SS

C

L

Figure 2. Typical Power Dissipation Test Circuit

APPLICATIONS INFORMATION

Figure 3 shows a technique for extending the number of decoded output states for the MC14017B. Decoded outputs are se-

quential within each stage and from stage to stage, with no dead time (except propagation delay).

RESET

CLOCK

MC14017B

CE

Q0 Q1

CE

Q0Q1

CE

Q1

• • •

Q8 Q9

8 DECODED

OUTPUTS

9 DECODED

OUTPUTS

8 DECODED

OUTPUTS

CLOCK

FIRST STAGE

INTERMEDIATE STAGES

LAST STAGE

Figure 3. Counter Expansion

MOTOROLA CMOS LOGIC DATA

MC14017B

77

Pcp

Ncp

90%

V

DD

CLOCK

50%

V

SS

V

10%

20 ns

t

20 ns

rem

su

CLOCK

DD

ENABLE

V

SS

t

rem

RESET

20 ns

V

DD

V

SS

t

PLH

t

PHL

Q0

V

OH

V

OL

t

TLH

t

PHL

PLH

V

90%

10%

OH

50%

Q1

Q2

Q3

V

OL

t

THL

PLH

PHL

TLH

V

OH

V

OL

t

PHL

t

THL

PLH

TLH

V

OH

50%

V

OL

t

PLH

PHL

TLH

THL

V

OH

t

Q4

Q5

Q6

Q7

Q8

V

THL

OL

t

TLH

PLH

PHL

t

PHL

V

OH

V

OL

t

THL

TLH

t

PHL

PLH

10%

THL

V

90%

OH

V

OL

t

THL

t

PHL

PLH

V

OH

V

OL

t

THL

V

t

OH

PLH

V

OL

t

THL

PLH

TLH

t

PHL

V

OH

Q9

C

V

OL

t

PHL

t

TLH

THL

PHL

t

PLH

V

out

OH

V

OL

t

THL

t

TLH

Figure 4. AC Measurement Definition and Functional Waveforms

MC14017B

78

MOTOROLA CMOS LOGIC DATA

OUTLINE DIMENSIONS

L SUFFIX

CERAMIC DIP PACKAGE

CASE 620–10

ISSUE V

–A–

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030)

WHERE THE LEAD ENTERS THE CERAMIC

BODY.

16

1

9

8

–B–

C

L

INCHES

MILLIMETERS

DIM

A

B

C

D

MIN

MAX

0.785

0.295

0.200

0.020

MIN

19.05

6.10

–––

MAX

19.93

7.49

5.08

0.50

0.750

0.240

–––

–T–

SEATING

PLANE

0.015

0.39

K

N

E

0.050 BSC

1.27 BSC

F

0.055

0.065

1.40

1.65

G

H

K

L

M

N

0.100 BSC

2.54 BSC

M

E

0.008

0.125

0.015

0.170

0.21

3.18

0.38

4.31

F

J

16 PL

0.25 (0.010)

G

0.300 BSC

7.62 BSC

M

S

T

B

0

15

0

15

D 16 PL

0.25 (0.010)

0.020

0.040

0.51

1.01

M

S

T

A

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

–A–

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

16

1

9

8

B

S

INCHES

MILLIMETERS

DIM

A

B

C

D

F

MIN

MAX

0.770

0.270

0.175

0.021

0.70

MIN

18.80

6.35

3.69

0.39

1.02

MAX

19.55

6.85

4.44

0.53

1.77

F

0.740

0.250

0.145

0.015

0.040

C

L

SEATING

–T–

G

H

J

K

L

0.100 BSC

0.050 BSC

2.54 BSC

1.27 BSC

PLANE

K

M

0.008

0.015

0.130

0.305

10

0.21

0.38

3.30

7.74

10

H

J

0.110

0.295

0

2.80

7.50

0

G

D 16 PL

0.25 (0.010)

M

S

0.020

0.040

0.51

1.01

M

T

A

MOTOROLA CMOS LOGIC DATA

MC14017B

79

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

–A–

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

16

1

9

8

–B–

P 8 PL

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

M

S

0.25 (0.010)

B

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

G

MILLIMETERS

INCHES

DIM

A

B

C

D

MIN

9.80

3.80

1.35

0.35

0.40

MAX

10.00

4.00

1.75

0.49

1.25

MIN

MAX

0.393

0.157

0.068

0.019

0.049

F

0.386

0.150

0.054

0.014

0.016

R X 45

K

C

F

G

J

K

M

P

R

1.27 BSC

0.050 BSC

–T–

SEATING

PLANE

0.19

0.10

0

0.25

7

0.008

0.004

0

0.009

7

J

M

D

16 PL

5.80

0.25

6.20

0.50

0.229

0.010

0.244

0.019

M

S

0.25 (0.010)

T

B

A

Motorolareserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding

the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,

and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided

in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,

including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent

rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant

into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a

situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application,

Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or

unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and

trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

are registered

How to reach us:

USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;

JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,

P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454

3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315

MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609

INTERNET: http://Design–NET.com

ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,

51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

MC14017B

80

MOTOROLA CMOS LOGIC DATA

MC14017B/D

◊


型号：	MC14017B
厂家：	MOTOROLA
描述：	Decade Counter 十进制计数器计数器
文件：	总7页 (文件大小：261K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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