MC14017BCP [ONSEMI]
Decade Counter; 十进制计数器
| 型号： | MC14017BCP |
| 厂家： | 
ONSEMI |
| 描述： | Decade Counter |
| 文件： | 总8页 (文件大小：234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The MC14017B is a five–stage Johnson decade counter with
built–in code converter. High speed operation and spike–free outputs
are obtained by use of a Johnson decade counter design. The ten
decoded outputs are normally low, and go high only at their
appropriate decimal time period. The output changes occur on the
positive–going edge of the clock pulse. This part can be used in
frequency division applications as well as decade counter or decimal
decode display applications.
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MARKING
DIAGRAMS
• Fully Static Operation
16
• DC Clock Input Circuit Allows Slow Rise Times
• Carry Out Output for Cascading
• Divide–by–N Counting
PDIP–16
P SUFFIX
CASE 648
MC14017BCP
AWLYYWW
1
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
• Pin–for–Pin Replacement for CD4017B
16
SOIC–16
D SUFFIX
CASE 751B
14017B
AWLYWW
• Triple Diode Protection on All Inputs
1
16
SOEIAJ–16
F SUFFIX
CASE 966
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)
SS
MC14017B
AWLYWW
Symbol
Parameter
Value
Unit
V
V
DD
DC Supply Voltage Range
–0.5 to +18.0
1
V , V
Input or Output Voltage Range
(DC or Transient)
–0.5 to V + 0.5
V
in out
DD
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
I , I
in out
Input or Output Current
(DC or Transient) per Pin
±10
mA
P
D
Power Dissipation,
500
mW
per Package (Note 3.)
ORDERING INFORMATION
T
Ambient Temperature Range
Storage Temperature Range
–55 to +125
–65 to +150
260
°C
°C
°C
A
Device
Package
PDIP–16
SOIC–16
Shipping
T
stg
T
Lead Temperature
(8–Second Soldering)
MC14017BCP
MC14017BD
2000/Box
48/Rail
L
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
MC14017BDR2
SOIC–16 2500/Tape & Reel
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
MC14017BF
SOEIAJ–16
SOEIAJ–16
See Note 1.
See Note 1.
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
MC14017BFEL
1. For ordering information on the EIAJ version of the
SOIC packages, please contact your local ON
Semiconductor representative.
high–impedancecircuit. For proper operation, V and V should be constrained
in
out
to the range V
(V or V
)
V
DD
.
SS
in
out
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V or V ). Unused outputs must be left open.
SS
DD
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 3
MC14017B/D
MC14017B
PIN ASSIGNMENT
Q5
Q1
Q0
Q2
Q6
Q7
Q3
1
2
3
4
5
6
7
8
16
V
DD
15 RESET
14 CLOCK
13
12
CE
C
out
11 Q9
10 Q4
V
SS
9
Q8
FUNCTIONAL TRUTH TABLE
(Positive Logic)
BLOCK DIAGRAM
CLOCK 14
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
3
2
4
7
10
1
5
6
Clock
Decode
Clock Enable Reset Output=n
0
X
X
X
1
X
0
0
0
1
0
0
0
0
n
n
Q0
n+1
n
CLOCK
ENABLE
13
X
X
1
n
n+1
9
11
RESET 15
C
out
12
X = Don’t Care. If n < 5 Carry = “1”,
Otherwise = “0”.
V
V
= PIN 16
= PIN 8
DD
SS
LOGIC DIAGRAM
Q5
Q1
Q7
Q3
7
Q9
11
1
2
6
14
CLOCK
CLOCK
12
C
C
D
R
Q
C
C
D
Q
C
C
D
R
Q
C
C
D
R
Q
Q
C
C
D
R
Q
Q
ENABLE
CARRY
13
Q
R
Q
R
Q
R
R
R
R
15
RESET
3
5
4
9
10
Q0
Q6
Q2
Q3
Q4
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2
MC14017B
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
)
SS
– 55 C
25 C
125 C
V
Vdc
DD
(4.)
Characteristic
Output Voltage
Symbol
Unit
Min
Max
Min
Typ
Max
Min
Max
“0” Level
“1” Level
“0” Level
V
OL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
V
in
= V or 0
DD
V
OH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Vdc
V
in
= 0 or V
DD
Input Voltage
(V = 4.5 or 0.5 Vdc)
V
IL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
O
(V = 9.0 or 1.0 Vdc)
O
(V = 13.5 or 1.5 Vdc)
O
“1” Level
V
IH
Vdc
(V = 0.5 or 4.5 Vdc)
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
O
(V = 1.0 or 9.0 Vdc)
O
(V = 1.5 or 13.5 Vdc)
O
Output Drive Current
I
mAdc
OH
(V = 2.5 Vdc)
Source
Sink
5.0
5.0
10
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
OH
(V = 4.6 Vdc)
OH
(V = 9.5 Vdc)
OH
(V = 13.5 Vdc)
OH
15
(V = 0.4 Vdc)
I
OL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
OL
(V = 0.5 Vdc)
OL
(V = 1.5 Vdc)
OL
Input Current
Input Capacitance
I
15
—
—
—
± 0.1
—
—
±0.00001
± 0.1
—
—
± 1.0
µAdc
in
C
—
5.0
7.5
—
pF
in
(V = 0)
in
Quiescent Current
(Per Package)
I
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
µAdc
DD
(5.) (6.)
Total Supply Current
I
T
5.0
10
15
I = (0.27 µA/kHz) f + I
T
I = (0.55 µA/kHz) f + I
T
I = (0.83 µA/kHz) f + I
T
DD
DD
DD
(Dynamic plus Quiescent,
Per Package)
(C = 50 pF on all outputs, all
L
buffers switching)
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25 C.
6. To calculate total supply current at loads other than 50 pF:
I (C ) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is in µA (per package), C in pF, V = (V – V ) in volts, f in kHz is input frequency, and k = 0.0011.
T
L
DD
SS
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3
MC14017B
SWITCHING CHARACTERISTICS (7.) (C = 50 pF, T = 25 C)
L
A
V
Vdc
DD
(8.)
Characteristic
Output Rise and Fall Time
Symbol
Min
Typ
Max
Unit
t
,
ns
TLH
t
t
t
, t
= (1.5 ns/pF) C + 25 ns
t
THL
5.0
10
15
—
—
—
100
50
40
200
100
80
TLH THL
L
, t
= (0.75 ns/pF) C + 12.5 ns
TLH THL
L
, t
= (0.55 ns/pF) C + 9.5 ns
L
TLH THL
Propagation Delay Time
Reset to Decode Output
t
t
t
,
ns
ns
ns
ns
PLH
t
PHL
t
t
t
, t
= (1.7 ns/pF) C + 415 ns
= (0.66 ns/PF) C + 197 ns
L
= (0.5 ns/pF) C + 150 ns
5.0
10
15
—
—
—
500
230
175
1000
460
350
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
L
Propagation Delay Time
Clock to C
,
PLH
t
out
PHL
t
t
t
, t
= (1.7 ns/pF) C + 315 ns
= (0.66 ns/pF) C + 142 ns
L
= (0.5 ns/pF) C + 100 ns
L
5.0
10
15
—
—
—
400
175
125
800
350
250
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
Propagation Delay Time
Clock to Decode Output
,
PLH
t
PHL
t
t
t
, t
= (1.7 ns/pF) C + 415 ns
= (0.66 ns/pF) C + 197 ns
L
= (0.5 ns/pF) C + 150 ns
5.0
10
15
—
—
—
500
230
175
1000
460
350
PLH PHL
L
, t
PLH PHL
, t
PLH PHL
L
Turn–Off Delay Time
Reset to C
t
PLH
out
t
t
t
= (1.7 ns/pF) C + 315 ns
5.0
10
15
—
—
—
400
175
125
800
350
250
PLH
PLH
PLH
L
= (0.66 ns/pF) C + 142 ns
L
= (0.5 ns/pF) C + 100 ns
L
Clock Pulse Width
t
5.0
10
15
250
100
75
125
50
35
—
—
—
ns
MHz
ns
w(H)
Clock Frequency
f
cl
5.0
10
15
—
—
—
5.0
12
16
2.0
5.0
6.7
Reset Pulse Width
t
5.0
10
15
500
250
190
250
125
95
—
—
—
w(H)
Reset Removal Time
Clock Input Rise and Fall Time
Clock Enable Setup Time
Clock Enable Removal Time
t
5.0
10
15
750
275
210
375
135
105
—
—
—
ns
rem
t
,
5.0
10
15
—
TLH
t
No Limit
THL
t
5.0
10
15
350
150
115
175
75
52
—
—
—
ns
su
t
5.0
10
15
420
200
140
260
100
70
—
—
—
ns
rem
7. The formulas given are for the typical characteristics only at 25 C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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4
MC14017B
V
DD
V
out
Output
Sink Drive Source Drive
Output
CLOCK
ENABLE
V
SS
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Clock to
desired
outputs
(S1 to B)
Decode
Outputs
(S1 to A)
A
B
V
S1
S1
DD
I
D
RESET
CLOCK
Clock to 5
thru 9
(S1 to B)
V
SS
Carry
S1 to A
V
V
=
=
V
DD
– V
GS
DD
EXTERNAL
POWER
V
out
V
– V
out DD
DS
C
out
SUPPLY
V
SS
Figure 1. Typical Output Source and Output Sink Characteristics Test Circuit
V
DD
0.01 µF
CERAMIC
I
D
500 µF
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
CLOCK
ENABLE
RESET
CLOCK
f
c
PULSE
GENERATOR
C
out
V
SS
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
C
L
Figure 2. Typical Power Dissipation Test Circuit
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5
MC14017B
APPLICATIONS INFORMATION
Figure 3 shows a technique for extending the number of decoded output states for the MC14017B. Decoded outputs are
sequential within each stage and from stage to stage, with no dead time (except propagation delay).
RESET
RESET
RESET
CLOCK
CLOCK
CLOCK
MC14017B
MC14017B
MC14017B
• • •
Q8 Q9
CE
CE
CE
Q1
• • •
• • •
Q0 Q1
Q8 Q9
Q0Q1
Q8 Q9
8 DECODED
OUTPUTS
9 DECODED
OUTPUTS
8 DECODED
OUTPUTS
CLOCK
FIRST STAGE
INTERMEDIATE STAGES
LAST STAGE
Figure 3. Counter Expansion
Pcp
Ncp
90%
10%
V
DD
CLOCK
50%
V
SS
20 ns
t
t
su
20 ns
rem
V
DD
CLOCK
ENABLE
V
SS
t
rem
20 ns
20 ns
20 ns
V
DD
RESET
20 ns
V
SS
t
t
PLH
PLH
t
PHL
Q0
V
OH
V
OL
t
TLH
t
t
PHL
PLH
V
90%
10%
OH
50%
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
V
OL
t
t
t
t
THL
PLH
PHL
TLH
V
OH
V
OL
t
t
PHL
t
t
THL
PLH
TLH
V
OH
50%
V
OL
t
t
t
t
THL
PLH
PHL
TLH
V
OH
t
V
OL
THL
t
t
t
TLH
PLH
PHL
t
PHL
V
OH
V
OL
t
t
THL
TLH
t
t
PHL
90%
PLH
V
OH
10%
V
OL
t
t
THL
t
THL
t
PHL
PLH
V
OH
V
OL
t
THL
V
OH
t
PLH
V
OL
t
t
THL
PLH
TLH
t
PHL
t
V
OH
Q9
C
V
OL
t
t
t
PHL
t
TLH
THL
PHL
t
PLH
V
OH
out
V
OL
t
THL
t
TLH
Figure 4. AC Measurement Definition and Functional Waveforms
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6
MC14017B
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A–
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
16
1
9
8
B
S
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
INCHES
DIM MIN MAX
0.740 0.770 18.80 19.55
MILLIMETERS
MIN MAX
F
A
B
C
D
F
G
H
J
K
L
M
S
C
L
0.250 0.270
0.145 0.175
0.015 0.021
6.35
3.69
0.39
1.02
6.85
4.44
0.53
1.77
0.040
0.70
SEATING
PLANE
–T–
0.100 BSC
0.050 BSC
0.008 0.015
2.54 BSC
1.27 BSC
K
M
0.21
0.38
3.30
7.74
10
H
J
0.110
0.295 0.305
10
0.020 0.040
0.130
2.80
7.50
0
G
D 16 PL
0
0.51
1.01
M
M
0.25 (0.010)
T A
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
8
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00 0.386
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
R X 45
K
C
G
J
K
M
P
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
J
M
D
16 PL
7
0
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
M
S
S
0.25 (0.010)
T B
A
R
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7
MC14017B
PACKAGE DIMENSIONS
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE O
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
16
9
8
Q
1
H
E
M
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
A
DIM MIN
MAX
MIN
–––
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
1
–––
0.05
0.35
0.18
9.90
5.10
2.05
A
0.20 0.002
0.50 0.014
0.27 0.007
10.50 0.390
5.45 0.201
b
c
D
E
A
1
b
0.13 (0.005)
e
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
0
0.70
–––
8.20 0.291
0.85 0.020
1.50 0.043
10
0.90 0.028
0.78 –––
0.323
0.033
0.059
10
0.035
0.031
E
L
L
E
M
Q
0
1
Z
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
withoutfurthernoticetoanyproductsherein. SCILLCmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular
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including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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Email: r14525@onsemi.com
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