MC13007XP_技术文档

Order this document by MC13001X/D

MONOMAX

BLACK AND WHITE TV

SUBSYSTEM

The MONOMAX is a single chip IC that will perform the electronic

functions of a monochrome TV receiver, with the exception of the tuner,

sound channel, and power output stages. The MC13001XP and

MC13007XP will function as a drop–in replacement for the MC13001P and

MC13007P, but some external IF components can be removed for maximum

benefit. IF AGC range has been increased, video output impedance lowered,

and horizontal driver output current capability increased.

SEMICONDUCTOR

TECHNICAL DATA

• Full Performance Monochrome Receiver with Noise and Video

Processing (Black Level Clamp, DC Contrast, Beam Limiter)

• Video IF Detection On–Chip (No Coils, No Pins, except Inputs)

• Noise Filtering On–Chip (Minimum Pins and Externals)

• Oscillator Components On–Chip (No Precision Capacitors Required)

• MC13001XP for 525 Line NTSC and MC13007XP for 625 Line CCIR

• Low Dissipation in All Circuit Sections

• High Performance Vertical Countdown

• 2–Loop Horizontal System with Low Power Startup Mode

• Noise Protected Sync and Gated AGC System

P SUFFIX

PLASTIC PACKAGE

CASE 710

ORDERING INFORMATION

Operating

• Designed to work with TDA1190P or TDA3190P Sound IF and Audio

TemperatureRange

Device

Package

Output Devices

MC13001XP

MC13007XP

T

A

= 0° to +70°C

Plastic DIP

Figure 1. Basic Elements of the System

Black

Clamp

Sound

IF

VIF IF Decoupling

Contrast

Beam Limit

26 25 27

4

2

6

28

Video Process

Video IF

24 Video Out

Video

Process

Blank

Buffer

IF In

3

5

VIF

Detector

AGC

8

AGC Filter

AGC Sync

RF AGC 11

RF

AGC

RF AGC Delay 10

23 Vertical Sync

AGC

9

Feed Forward

Flyback

Buffer

Sync

Separator

Noise

Process

Flyback 15

Horizontal Sync

Vertical

22 Vertical Out

7

Separator

Vertical

Sync

Window

Control

& Reset

Vertical

Integrator

Vertical

Preamp

Vertical

21

Horizontal

Separator

Feedback

V

18

Regulator

CC

Phase

Detector 2

Vertical

Ramp

Clock

20 Vertical Size

525

+8.0V Out 19

Horizontal

Buffer

Phase

Detector 1

31.5 kHz

Oscillator

Variable

Slicer

2

17 Horizontal Out

2

13

12

14

Horizontal Phase

Detector 1

Horizontal Frequency

Horizontal Phase

Detector 2

Motorola, Inc. 1995

1

MOTOROLA ANALOG IC DEVICE DATA

MC13001X MC13007X

MAXIMUM RATINGS (T = 25°C, unless otherwise noted.)

A

Rating

Symbol

Value

Unit

Vdc

W

Power Supply Voltage – Pin 18

Power Dissipation

V

CC

+16

P

D

1.0

Horizontal Driver Current – Pin 17

RF AGC Current – Pin 11

I

–20

mA

°C/W

°C

hor

I

20

5.0

RFAGC

Video Detector Current – Pin 24

Vertical Driver Current – Pin 22

Auxiliary Regulator Current – Pin 19

Thermal Resistance Junction–to–Case

Maximum Junction Temperature

Storage Temperature Range

Operating Temperature Range

I

VID

5.0

vert

I

35

reg

Rθ

60

JC

J

T

150

T

–65 to + 150

0° to + 70

°C

stg

T

°C

A

RECOMMENDED OPERATING CONDITIONS

Rating

Symbol

Value

≤10

Unit

mA

Horizontal Output Drive Current

RF AGC Current

I

hor

I

≤10

RFAGC

Regulator Current

I

≤20

reg

ELECTRICAL CHARACTERISTICS (V

Characteristics

= 11.3 V, T = 25°C)

A

CC

Symbol

Min

44

Typ

–

Max

76

Unit

mA

Power Supply Current (Pins 18, 19)

Regulator Voltage (Pin 19)

I

CC

V

reg

7.2

8.2

8.8

Vdc

HORIZONTAL SPECIFICATIONS

Oscillator Frequency (Nominal) (Pin 12)

f

13

–

230

–

19

–

kHz

hor(NOM)

Oscillator Sensitivity

Hz/µA

%

Startup Frequency (I = 4.0 mA)

18

f

–10

–

+10

–

hor

Oscillator Temperature Stability (0 ≤ TA ≤ 75°C)

–

50

Hz

Phase Detector 1 (Charge/Discharge Current)

(Non–Standard Frame)

(Standard Frame)

Iφ

1

–

±900

±400

–

µA

mA

Vdc

Phase Detector 2

(Charge/Discharge Current)

Vφ

2

–

+1.0

–0.6

–

Phase Detector 1

(Output Voltage Limits)

Vφ

1

7.5 (max)

2.5 (min)

–

Phase Detector 2

(Output Voltage Limits)

Vφ

1

7.7 (max)

1.5 (min)

–

Phase Detector 1

(Leakage Current)

–

2.0

3.0

µA

Phase Detector 2

(Leakage Current)

–

Horizontal Delay Range

(Sync to Flyback)

–

18 (max)

5.0 (min)

–

µs

Horizontal Output Saturation Voltage

(I = 15 mA)

17

V

–

0.3

Vdc

17(sat)

Phase–Detector 1 (Gain Constant)

(Out–of–Lock)

(In–Lock)

µA/µs

–

5.0

10

–

Horizontal Pull–In Range

±500

±750

–

Hz

2

MOTOROLA ANALOG IC DEVICE DATA

MC13001X MC13007X

ELECTRICAL CHARACTERISTICS (continued) (V

= 11.3 V, T = 25°C)

CC

A

Characteristics

Symbol

Min

Typ

Max

Unit

VERTICAL SPECIFICATIONS

Output Current (Pin 22)

I

–0.6

–

mA

µA

22

Feedback Leakage Current (Pin 21)

Feedback Maximum Voltage

Ramp Retrace Current (Pin 20)

Ramp Leakage Current (Pin 20)

IF SPECIFICATIONS

6.0

–

21

V

–

5.1

–

Vdc

µA

21

I

20

500

–

900

0.3

–

µA

Regulator Voltage

Input Bias Voltage

V

–

7.5

4.2

–

Vdc

4

V

2,6

Input Resistance

Input Capacitance (V

R

C

–

6.0

2.0

–

kΩ

pF

in

Pin 8 = 4.0 V)

AGC

Sensitivity

–

80

–

µV

rms

(V = 0 V, 400 Hz 30% MOD, V = 0.8 V

8

)

pp

28

Bandwidth

BW

–

75

–

MHz

VIDEO SPECIFICATIONS

Zero Carrier Voltage (See Figure 5) (Pin 28)

–

7.0

1.4

–

Vdc

V

Output Voltage (See Figure 6) (Pin 24)

White to Back Porch

Differential Gain

Differential Phase (IRE Test Method)

–

6

4

–

%

Degrees

Contrast Bias Current (Pin 26)

Contrast Control Range

Beam Limiting Voltage (Pin 27)

AGC & SYNC

I

–

10

14:1

1.0

–

µA

26

V

Vdc

27

RF (Turner AGC Output Current (V = 5.5 V)

11

I

5.0

–

mA

µA

11

AGC Delay Bias Current

I

10

–10

1.0

–

AGC Feedforward Current

I

–

mA

Vdc

mA

9

AGC Threshold (Sync Tip at Pin 28)

Sync Separator Operating Point

Sync Separator Charge Current

V

4.7

–

5.1

–

28

V

4.2

5.0

7

I

–

7

Figure 2. Monomax AGC Characteristics

Figure 3. Video Output Response

0

5.0

4.0

3

2

1

0

Video Out (Pin 24) with Max Contrast

Sound IF Out (Pin 28)

–10

(Pin 9)

–20

–30

–40

–50

3.0

2.0

1.0

0

–1

–2

–3

–4

–5

–6

0

1.0

2.0

3.0

4.0

5.0

0

2.0

4.0

6.0

8.0

10

VIDEO OUTPUT RESPONSE (MHz)

AGC VOLTAGE, Pin 8 (V)

3

MOTOROLA ANALOG IC DEVICE DATA

MC13001X MC13007X

GENERAL DESCRIPTION

The Video IF Amplifier is a four–stage design with 80 µV,

Figure 5. Pin 28 Sound Output

sensitivity. It uses a 6.2 V supply decoupled at Pin 4. The first

two stages are gain controlled, and to ensure optimum noise

performance, the first stage control is delayed until the

second stage has been gain reduced by 15 dB. To bias the

amplifier, balanced dc feedback is used which is decoupled

at Pins 2 and 6 and then fed to the input Pins 3 and 5 by

internal 3.9 k resistors. The nominal bias voltage at these

input pins is approximately 4.2 Vdc. The input, because of the

high IF gain, should be driven from a balanced differential

source. For the same reason, care must be taken with the IF

decoupling.

7.0 V

Zero Carrier

87.5%

25%

Back Porch

5.1 V

3.6 V

AGC Threshold

Noise Threshold

The IF output is rectified in a full wave envelope detector

and detector nonlinearity is compensated by using a similar

nonlinear element in a feedback output buffer amplifier. The

Figure 6. Pin 24 Video Output

Max. Contrast

3.8V

detected 1.9 V

video at Pin 28 contains the sound

pp

intercarrier signal, and Pin 28 is normally used as the sound

takeoff point. The video frequency response, detector to Pin

28, is shown in Figure 3 and the detector intermodulation

performance can be seen by reference to Figure 4. Typical

Pin 28 video waveforms and voltage levels are shown in

Figure 5.

Min. Contrast

Back Porch

2.4V

1.7V

Max. Blanking Level

The video processing section of Monomax contains a

contrast control, black level clamp, a beam current limiter and

composite blanking. The video signal first passes through the

contrast control. This has a range of 14:1 for a 0 V to 5.0 V

change of voltage on Pin 26, which corresponds to a change

of video amplitude at Pin 24 of 1.4 V to 0.1 V (black to white

level). The beam current limiter operates on the contrast

control, reducing the video signal when the beam current

exceeds the limit set by external components. As the beam

current increases, the voltage at Pin 27 moves negatively

from its normal value of 1.5 V, and at 1.0 V operates the

contrast control, thus initiating beam limiting action. After the

contrast control, the video is passed through a buffer amplifier

and dc is restored by the black level clamp circuit before

being fed to Pin 24 where it is blanked. The black level clamp,

which is gated “on” during the second half of the flyback,

maintains the video black level at 2.4 V ± 0.1 V under all

conditions, including changes in contrast, temperature and

power supply. The loop integrating capacitor is at Pin 25 and

is normally at a voltage of 3.3 V. The frequency response of

the video at Pin 24 is shown in Figure 3 and it is blanked to

within 0.5 V of ground.

The AGC loop is a gated system, and for all normal

variations of the IF input signal, maintains the sync tip of a

noise filtered video signal at a reference voltage (5.1 V

Pin 28). The strobe for the AGC error amplifier is formed by

gating together the flyback pulse with the separated sync

pulse. Integration of the error signal is performed by the

capacitor at Pin 8, which forms the dominant AGC time

constant. Improved noise performance is obtained by the use

of a gated AGC system, noise protected by a dc coupled

noise canceling circuit. The false AGC lock conditions, which

can result from this combination, are prevented by an

anti–lockout circuit connected to the sync separator at Pin 7.

AGC lockout conditions, which occur due to large rapid

changes of signal level are detected at Pin 7 and recovery is

ensured under these conditions by changing the AGC into a

mean level system. The voltage at Pin 10 sets the point at

which tuner AGC takeover occurs and positive going tuner

control, suitable for an NPN RF transistor, is available at

Pin 11. The maximum output is 5.5 V at 5.0 mA. A

feed–forward output is provided at Pin 9. This enables the

AGC control voltage to be ac coupled into the tuner takeover

control at Pin 10. The coupling allows additional IF gain

reduction during signal transient conditions, thus

compensating for variations of AGC loop gain at the tuner

AGC takeover point. In this way the AGC system stability and

response are not degraded.

The previously mentioned noise protection is effected by

detecting negative–going noise spikes at the video detector

output. A dc coupled detector is used which turns on when a

noise spike exceeds the video sync tip by 1.4 V. This pulse is

then stretched and used to cancel the noise present on the

delayed video at the input to the sync separator. Cancellation

is performed by blanking the video to ground. Complete

cancellation of the noise spike results from the stretching of

the blanking pulse and the delay of the noise spike at the

input to the sync separator. Protection of both the horizontal

PLL and the AGC stems from the fact that both circuits use

the noise cancelled sync for gating.

Figure 4. Detector Products

10

45.74 MHz = 25 mVrms

42.17 MHz = 12.5 mVrms

41.25 MHz = Relative to

41.25 MHz = 45.75 MHz

– Reference = 3.58 MHz

0

–10

–20

–30

–40

–50

–60

4.5 MHz

920 kHz

2.66 MHz

–10

–20

–30

–40

–50

RELATIVE 41.25 MHz INPUT LEVEL (dB)

4

MOTOROLA ANALOG IC DEVICE DATA

MC13001X MC13007X

The composite sync is stripped from a delayed and filtered

The same divided oscillator frequency is also fed to Phase

Detector 2, where the flyback pulse is compared with it and

the resulting error used to change a variable slice level on the

oscillator ramp waveform. This therefore changes the timing

of the output square wave from the slicer and hence the

timing of the buffered horizontal output on Pin 17 (see

Figure 8). The error on Phase Detector 2 is reduced until the

phasing of the flyback pulse is correct with respect to the

divided oscillator waveform, and hence with respect to the

sync pulse.

video in a peak detecting type of sync separator. The

components connected to Pin 7 determine the slice and tilt

levels of the sync separator. For ideal horizontal sync

separation and to ensure correct operating of AGC anti–

lockup circuit, a relatively short time constant is required at

Pin 7. This time constant is less than optimum for good noise

free vertical separation, giving rise to a vertical slice level

near sync tip. An additional longer time–constant is therefore

coupled to the first via a diode. With the correct choice of time

constants, the diode is non–conducting during the horizontal

sync period, but conducts during the longer vertical period.

This connects the longer time constant to the sync separator

for the vertical period and stops the slice level from moving up

the sync tip. The separated composite sync is integrated

internally, and the time constant is such that only the longer

period vertical pulses produce a significant output pulse. The

output is then fed to the vertical sync separator, which further

processes the vertical pulse and provides increased noise

protection. The selection of the external components

connected to the vertical separator at Pin 23 permits a wide

range of performance options. A simple resistor divider from

the 8.2 V regulated supply gives adequate performance for

most conditions. The addition of an RC network will make the

slice level adapt to varying sync amplitude and give improved

weak signal performance. A resistor to the AGC voltage on

Pin 9 enables the sync slice level to be changed as a function

of signal level. This further improves the low signal level

separation while at the same time giving increased impulse

noise protection on strong signals.

Figure 8. Horizontal Waveforms

200 mV

pp

7

4.5 V

6.0 V

13

50 mV

pp

17

15

2.0 V

0 V

+0.9 V

0 V

–0.7 V

To improve the pull–in and noise characteristics of the first

PLL, the phase detector current is increased when the

vertical lock indicator signals an unlocked condition and is

decreased when locked. This increases the loop bandwidth

and pull–in range when out of lock, and decreases the loop

bandwidth when in lock, thus improving the noise

performance. In addition, the phase detector current during

the vertical period is reduced in order to minimize the

disturbance to the horizontal caused by the longer period

vertical phase detector pulses.

Horizontal Oscillator

The horizontal PLL (see Figure 7) is a two–loop system

using a 31.5 kHz oscillator which after a divider stage is

locked to the sync pulse using Phase Detector 1. The control

signal derived from this phase detector on Pin 13 is fed via a

high–value resistor to the frequency–control point on Pin 12.

Figure 7. Horizontal Oscillator Systems

Output

17

Divide

by 2

SLICE

Vary

SLICE

Level

(Phase)

Divide

by 2

Phase

Detector 2

31.5kHz

SLICE

Oscillator

14

Vary

Frequency

12

13

Phase

Detector 1

15

Deflection

Flyback

Sync

5

MOTOROLA ANALOG IC DEVICE DATA

MC13001X MC13007X

The oscillator itself is a novel design using an on–chip

The flyback gating input is on Pin 15 which is internally

clamped to 0.7 V in both directions and requires a negative

input current of 0.6 mA to operate the gate circuit. This input

can be a raw flyback pulse simply fed via a suitable resistor.

50 pF silicon nitride capacitor which has a temperature drift

of only 70 ppm/°C and negligible long term drift. This, in

conjunction with an external resistor, gives a drift of horizontal

frequency of less than 1.0 Hz/°C – i.e., less than 100 Hz over

the full operating temperature range of the chip. The pull–in

range of the PLL is about ±750 Hz, so normally this would

eliminate the need for any customer adjustment of the

frequency.

The second significant feature of this design is the use of a

virtual ground at the frequency control point which floats at a

potential derived from a divider across the power supply and

this is the same divider which determines the end–points of

the oscillator ramp. The frequency adjustment which is

necessary to take up tolerances in the on–chip capacitor is

fed in as a current to this virtual ground, and when this

adjustment current is derived from an external potentiometer

across the same supply there is no frequency variation with

supply voltage. Moreover, using the voltage from a

potentiometer for the adjustment instead of the simple

variable resistor normally used in RC oscillators makes the

frequency independent of the value of the potentiometer and

hence its temperature coefficient. The frequency control

current from the first phase detector is fed into this same

virtual ground, and as the sensitivity of the control is about

230 Hz/µA, a high value resistor can be used (680 kΩ) which

can be directly connected to the phase detector filter without

significant loading.

Vertical System

An output switching signal is taken from the 31.5 kHz

oscillator to clock the vertical counter which is used in place

of a conventional vertical oscillator circuit. The counter is

reset by the vertical sync pulse, but the period during which it

is permitted to reset is controlled by the window control.

Normally, when the counter is running synchronously, the

window is narrow to give some protection against spurious

noise pulses in the sync signal. If the counter output is not

coincident with sync however, after a short period the window

opens to five reset over a much wider count range, leading to

a fast picture roll towards lock. At weak signal, i.e., less than

200 µV IF input, the vertical system is forced to narrow mode

to give a steadier picture for commonly occurring types of

noise. The vertical sync, gated by the counter, then resets a

ramp generator on Pin 20 and the 1.5 V

ramp is

pp

buffered to Pin 22 by the vertical preamplifier. A differential

input to the preamp on Pin 21 compares the signal generated

across the resistor in series with the deflection coils with the

generated ramp and thus controls shape and amplitude of

the coil current.

The basic block diagram of the countdown system is

H

shown in Figure 9. The 31.5 kHz (2F ) clock from the

horizontal oscillator drives a 10–stage counter circuit which is

normally reset by the vertical sync pulse via the sync gate,

‘‘OR’’ gate and D flip–flop. This D input is also used to initiate

discharge of the ramp capacitor and hence causes picture

flyback.

This oscillator operates with almost constant frequency

to below 4.0 V and as the total PLL system consumes

less than 4.0 mA at this voltage, this gives an ideal

startup characteristic for receivers using deflection–derived

power supplies.

Figure 9. Monomax Vertical Countdown

0

Blanking

Pulse

Blanking

Latch

20

H

2F

Clock

Counter Reset

10 Stage Counter

514–526

‘‘Narrow’’

384–544

‘‘Wide’’

H/4

Delay

To

‘‘Wide’’

COINC

8H/2 Delay

2H/2 Delay

Window

Control

Coincidence

Detector

Define

Window

for Sync

D

D Flip–Flop

(Delay)

To

‘‘Narrow’’

Vertical

Sync

Sync Gate/

Ramp Latch

Clock

To Ramp

Pull–Down

6

MOTOROLA ANALOG IC DEVICE DATA

MC13001X MC13007X

The period during which sync can reset the counter and

Figure 10. Vertical Waveforms

cause flyback is determined by the window control which

defines a count range during which the gate is open. One of

two ranges is selected according to the condition of the

signal. The normal “narrow” range is 514 to 526 counts for a

525 line system and is selected after the coincidence

detector indicates that the reset is coincident, twice in

succession, with the 525 count from the counter. When the

detector indicates non–coincidence 8 times in succession,

then the window control switches to the “wide” mode (384 to

544 counts) to achieve rapid re–synchronization. For the 625

line version the counts are 614 to 626 for narrow mode and

484 to 644 for wide mode. Note that the OR gate after the

sync gate is used to terminate the count at the end of the

respective window if a sync pulse has not appeared.

This method accepts nonstandard signals almost in the

same way as a conventional triggered RC oscillator and has

a similar fast lock–in time. However, the use of a window

control on the counter reset ensures that when locked with a

normal standard broadcast signal the counter will reject most

spurious noise pulse.

7.0 V

23

6.0 V

–2.5 V

2.0 V

20

22

1.0 V pp

0 V

21

–4.0 V

500 mV pp

Power Supply

The power supply regulator, although of simple design,

provides two independent power supplies – one for the

horizontal PLL section and the other for the remainder of the

chip. The supplies share the same reference voltage but

the design of the main regulator is such that it can be

switched on independently to give minimum loading on the

“bleed” voltage source during startup phase of a

defection–derived supply system.

The blanking output is provided from a latch which is set by

the counter reset pulse and terminated by count 20 from the

counter chain.

Figure 11. Power Supply Circuit

Main

12 V Supply

V

– 8

BL

R

=

Horizontal

Startup Bleed

BL

–3

4 x 10

8.2 V to

External

Circuits

I

EXT

+ V

BL

R

6

BL

18

19

R

1

Q

5

3

Q

6

8.2V to

8.2 V to

R

2

All Monomax

Circuits Except

Horizontal

System

D

1

Q

2

1

D

2

R

3

I

(mA)

R (Ω)

6

EXT

Z

1

Q

4

< 5.0

150

82

Q

7

20

35

R

5

4

68

7

MOTOROLA ANALOG IC DEVICE DATA

MC13001X MC13007X

Figure 12. Test Circuit Diagram

6.6k

Detected

Video

100

56k

28

27

1

V

I

28

40

36k

1.0k

10k

V

reg

V

2

3

27

2.7k

3.9k

12k

22k

26

0.1nF

8.0k

3.5k

10nF

V

Pin 19

4

Regulated

Supply

25

24

4

5

0.1nF

12k

10nF

250

500

Blanking

2.5k

V

reg

Same as Pin 3

100

Video

2.2k

23

22

Vertical Sync

Integrated

Sync

6

Same as Pin 2

V

6

470k

50nF

V

7

8.2k

820

10nF

12V

7

8

220

Sync

470

I

22

180k

Video

I

7

V

21

2.2nF

4.7k

21

20

12V

27k

6.2V

10nF

V

8

I

+

–

20

750k

12V

Vertical

Countdown

9

5.0k

0.1µF

47k

I

9

35k

V

Source

8.2V

reg

Regulated Supply

10k

19

10

I

CC

0.1µF

220

I

10

Horizontal

Supply

12V

100

120V

18

17

11

12

22k

330

0.1nF

470

I

3.0k

11

82k

91k

5.0V

V

17

12

10nF

V

01

3.0V

16

15

13

14

5.0k

I

01

AGC

Gate

300

Flyback Pulse

V

02

10nF

I

02

8

MOTOROLA ANALOG IC DEVICE DATA

MC13001X MC13007X

Figure 13. Simplified Application

Video

Out

+8.2V

39k

1.2k

+8.2V

+24V

+12V

+120V

+120V +120V

33k

Vert

Feedback

Vert

Sync

50nF

High Voltage

Winding

220

27k

Vert

Size

To TDA1190P

1.0M

Sound IF

Contrast

+8.2V

Flyback

1

82k

Black

Level

Clamp

V

pk

150

Horiz

Drive

47k

R

3.3M

FB

4.7

µ

F

0.1

CC

0.05

V

pk

kΩ

R

=

FB

2.2k

2

+8.2V

Vert

Drive

V

10

26

reg

V

28

1

27

2

25

24

23

22

21

20

19

18

17

16

15

MC13001X MONOMAX

3

4

5

6

7

8

9

10

11

12

13

14

V

RF

AGC

Horiz

Freq

Horiz

Phase

Det. 1

Horiz

Phase

Det. 2

10nF

50nF

RF

0.33µF

1.0µF

8.2V

10nF

680k

680

0.1nF

+8.2V

8.2k

RF

AGC

Delay

10nF

Horiz

Freq

Video IF In

2% Metal Film

or Metal Oxide

+8.2V

120k

470k

22nF

1.0µF

2.7M

Sync Separator Components

Pin 9

Tuner

1.8M

2.2k

50nF

23

Vertical Sync, optional components

for extra performance with low signal strength.

See Application Note AN879 for further information.

9

MOTOROLA ANALOG IC DEVICE DATA

MC13001X MC13007X

OUTLINE DIMENSIONS

P SUFFIX

PLASTIC PACKAGE

CASE 710–02

ISSUE C

NOTES:

1. POSITIONAL TOLERANCE OF LEADS (D), SHALL

BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL

CONDITION, IN RELATION TO SEATING PLANE

AND EACH OTHER.

28

1

15

14

2. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

B

MILLIMETERS

INCHES

DIM

A

B

C

D

F

MIN

36.45

13.72

3.94

0.36

1.02

MAX

37.21

14.22

5.08

0.56

1.52

MIN

MAX

1.465

0.560

0.200

0.022

0.060

1.435

0.540

0.155

0.014

0.040

L

C

A

N

G

H

J

K

L

2.54 BSC

0.100 BSC

1.65

0.20

2.92

2.16

0.38

3.43

0.065

0.008

0.115

0.085

0.015

0.135

J

G

H

F

M

K

15.24 BSC

0.600 BSC

D

SEATING

PLANE

M

N

0

0.51

15

1.02

0

15

0.040

0.020

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representationorguaranteeregarding

the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different

applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does

not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in

systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of

the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such

unintendedor unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless

against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.

Motorola and

are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

How to reach us:

USA / EUROPE: Motorola Literature Distribution;

JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,

P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447

6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315

MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE (602) 244–6609

INTERNET: http://Design–NET.com

HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,

51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

MC13001X/D

◊

10

MOTOROLA ANALOG IC DEVICE DATA


型号：	MC13007XP
厂家：	MOTOROLA
描述：	MONOMAX BLACK AND WHITE TV SUBSYSTEM Monomax黑白电视机子系统消费电路商用集成电路电视光电二极管
文件：	总10页 (文件大小：272K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC13007XP [MOTOROLA]

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