MC13017P [MOTOROLA]
NTSC/PAL CHROMA 10 COLOR TV and TIMEBASE PROCESSOR; NTSC / PAL色度10彩电和TIMEBASE处理器
| 型号： | MC13017P |
| 厂家： | 
MOTOROLA |
| 描述： | NTSC/PAL CHROMA 10 COLOR TV and TIMEBASE PROCESSOR |
| 文件： | 总4页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document by MC13017/D
NTSC/PAL CHROMA 10
COLOR TV and
The MC13017 consists of all the necessary circuits for TV NTSC/PAL
decoding and timebase processing. It forms a kit set with the MC44301 VIF
and the TDA3190 Sound IF and Power for a low cost, high performance CTV
system.
TIMEBASE PROCESSOR
SEMICONDUCTOR
TECHNICAL DATA
• On–Chip Sync Separator
• Dual Loop Horizontal Timebase
• Direct Locked Vertical Counter
• X–Ray Protection
• Noise Blanking on Sync Separator
• NTSC/PAL Color Decoding
• Direct Interface with SECAM TDA3030B
• 4.43/3.579 MHz Crystal Reference
40
1
P SUFFIX
PLASTIC PACKAGE
CASE 711
• Three DC High Impedance Control Outputs for Contrast, Brightness, and
Saturation
• 12 V Supply
• Vertical Ramp Buffer Output
• Sandcastle Output
• Hue Control
PIN CONNECTIONS
V
1
2
3
4
5
6
7
8
9
40
V
CC2
CC3
V. Gnd
V. Feedback
V. Out
39 H. Gnd
38 H. O/P
37 PD2
Buffer Ramp
Ramp Cap
V. Height
36 H. Flyback
35 PD1
34 H. Freq
33 X–Ray
32 Contrast
MAXIMUM RATINGS (T = 25°C, unless otherwise noted.)
A
Sync Sep Cap
Sync I/P
Rating
Symbol
Value
Unit
Power Supply Voltages
V
, V
15
10
V
Brightness
Sandcastle
Pulse
Luma I/P 10
31
30
CC1 CC3
V
CC2
V
+ 12 V 11
Hue 12
CC1
Operating Temperature Range
Storage Temperature Range
T
A
0 to +70
5C
°C
V
29 R O/P
Chroma I/P 13
ACC 14
DL E 15
DL C 16
Sat 17
28 G O/P
T
– 55 to +125
stg
27 B O/P
Horizontal Output Voltage
Vertical Output Voltage
V
V
8.0
4.0
OH
OV
26 DC Ref & BL
25 Gnd
24 Xtal FB
23 Xtal Drive
22 VCO FLT
ID 18
V I/P 19
U I/P 20
21 90° FLT
(Top View)
ORDERING INFORMATION
Operating
Temperature Range
Device
Package
MC13017P
T
A
= 0° to +70°C
Plastic DIP
This document contains information on a product under development. Motorola reserves the right
to change or discontinue this product without notice.
Motorola, Inc. 1995
MC13017
PIN FUNCTION DESCRIPTION
Pin
1
Function
Description
V
CC3
+12 V supply for V power regulator.
CC2
2
Vert Gnd
Vertical output analog ground.
3
Vert Feedback
The Ramp on Pin 6 is internally inverted, level shifted and subtracted from the input to Pin 3. The
result appears as an output on an open collector at Pin 4.
4
5
6
Vert Out
Buffer Ramp
Ramp Cap
Vertical ramp output to external vertical power drive.
The vertical buffer ramp output of Pin 6.
The external cap is charged by a current controlled through vertical height control Pin 7 to
produce a vertical ramp. The discharge of the cap is controlled internally by the vertical counter.
7
Vert Height
Current input for vertical height control.
8, 9
Sync Sep Cap,
Sync I/P
Sync separator input is a NPN transistor stage with the signal presented at its base with a peak
level of about 4.0 V. The emitter is brought out to Pin 8 through a 200 Ω resistor so that a
capacitor with a series resistor may be connected. The circuit behaves as a peak detector with a
slicing level controlled by the choice of charge and discharge resistors. An additional time
constant is connected through a diode to prevent the slice level from riding up on the field sync.
11
12
V
+12 V supply for chroma.
CC1
Hue
This is Hue control for NTSC system. It should be connected to V
voltage at Pin 12 is smaller than 8.0 V, NTSC mode is selected.
at PAL system. When
CC1
15
16
DL E
DL C
Delay line drive open emitter terminal.
Delay line drive open collector terminal.
An external filter cap is connected at this pin for ID circuit.
V, U inputs after delay line to detectors.
90° phase shifter filter.
18
ID Filter
V, U
19, 20
21
90° Filter
VCO Filter
22
Color reference VCO filter.
23
24
Xtal 2
Xtal 1
A 4.43 MHz (PAL), or 3.579 MHz (NTSC) crystal is connected to the internal VCO for color
subcarrier reference frequency.
30
Sandcastle
Pulse Output
The Sandcastle Pulse Output is delivered through 200 Ω from an emitter–follower with 10 kΩ
pull–down. The blanking duration is determined by the applied flyback pulse. The burst gate
determined by the second half of the flyback levels are: Blanking (4.0 V), Burst Gate (11 V).
35
36
PD1
Horizontal phase detector current output. The PLL 1 is locked to the sync input
with 2H oscillator.
Horiz Flyback
Horizontal flyback, a positive input pulse exceeded threshold of 1.0 V is required, input
impedance is between 600 and 2.0 kΩ so that a minimum of 0.5 mA current
is needed to exceed the threshold voltage. The recommended peak current is
2.0 mA.
37
38
39
40
PD2
Second horizontal phase detector current output. The function of PLL 2 is to adjust the horizontal
drive in order to maintain the flyback in phase with the oscillator.
Horiz Out
Horiz Gnd
This is a saturated NPN transistor with a 2.0 kΩ internal load to regulate
supply V
CC2.
Horizontal analog output grounding should be connected nearby the external horizontal output
stage.
V
CC2
Regulated supply to horizontal timebase section. A diode is in series with 270 Ω from
V
CC3
+ 12 V to block the high voltage startup supply of 10 mA for horizontal oscillator.
2
MOTOROLA ANALOG IC DEVICE DATA
MC13017
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 711–03
ISSUE C
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D), SHALL
BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITION, IN RELATION TO SEATING PLANE
AND EACH OTHER.
40
21
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
B
MILLIMETERS
INCHES
1
20
DIM
A
B
C
D
F
G
H
J
K
L
M
N
MIN
51.69
13.72
3.94
0.36
1.02
MAX
52.45
14.22
5.08
0.56
1.52
MIN
MAX
2.065
0.560
0.200
0.022
0.060
2.035
0.540
0.155
0.014
0.040
L
A
C
N
2.54 BSC
0.100 BSC
1.65
0.20
2.92
15.24 BSC
0
2.16
0.38
3.43
0.065
0.008
0.115
0.600 BSC
0
0.085
0.015
0.135
J
K
SEATING
PLANE
M
H
G
F
D
15
1.02
15
0.040
0.51
0.020
3
MOTOROLA ANALOG IC DEVICE DATA
MC13017
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MC13017/D
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