M68HC08 [MOTOROLA]
Microcontrollers; 微控制器
| 型号： | M68HC08 |
| 厂家： | 
MOTOROLA |
| 描述： | Microcontrollers |
| 文件： | 总230页 (文件大小：2528K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC68HC908QY4
MC68HC908QT4
MC68HC908QY2
MC68HC908QT2
MC68HC908QY1
MC68HC908QT1
Data Sheet
M68HC08
Microcontrollers
MC68HC908QY4/D
9/2002
WWW.MOTOROLA.COM/SEMICONDUCTORS
MC68HC908QY4
MC68HC908QT4
MC68HC908QY2
MC68HC908QT2
MC68HC908QY1
MC68HC908QT1
Data Sheet
To provide the most up-to-date information, the revision of our
documents on the World Wide Web will be the most current. Your printed
copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://motorola.com/semiconductors
The following revision history table summarizes changes contained in
this document. For your convenience, the page number designators
have been linked to the appropriate location.
Motorola and the Stylized M Logo are registered trademarks of Motorola, Inc.
DigitalDNA is a trademark of Motorola, Inc.
© Motorola, Inc., 2002
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA
3
Revision History
Revision History
Revision
Level
Page
Number(s)
Date
Description
September,
2002
N/A
Initial release
N/A
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MOTOROLA
Data Sheet — MC68HC908QY4
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . .25
Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Section 3. Random-Access Memory (RAM) . . . . . . . . . .43
Section 4. FLASH Memory (FLASH) . . . . . . . . . . . . . . . .45
Section 5. Configuration Register (CONFIG) . . . . . . . . .55
Section 6. Central Processor Unit (CPU) . . . . . . . . . . . .59
Section 7. System Integration Module (SIM) . . . . . . . . .75
Section 8. Oscillator Module (OSC). . . . . . . . . . . . . . . .101
Section 9. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . .113
Section 10. Timer Interface Module (TIM) . . . . . . . . . . .129
Section 11. Analog-to-Digital Converter (ADC) . . . . . .151
Section 12. Input/Output (I/O) Ports . . . . . . . . . . . . . . .161
Section 13. External Interrupt (IRQ) . . . . . . . . . . . . . . .171
Section 14. Keyboard Interrupt Module (KBI). . . . . . . .177
Section 15. Computer Operating Properly (COP) . . . .189
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List of Sections
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List of Sections
Section 16. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . .195
Section 17. Break Module (BREAK) . . . . . . . . . . . . . . .201
Section 18. Electrical Specifications. . . . . . . . . . . . . . .211
Section 19. Mechanical Specifications . . . . . . . . . . . . .223
Section 20. Ordering Information . . . . . . . . . . . . . . . . .227
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
List of Sections MOTOROLA
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Data Sheet — MC68HC908QY4
Table of Contents
Section 1. General Description
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Pin Function Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Section 2. Memory
2.1
2.2
2.3
2.4
2.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . .33
Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .35
Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Section 3. Random-Access Memory (RAM)
3.1
3.2
3.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
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Section 4. FLASH Memory (FLASH)
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .48
FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .49
FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .49
FLASH Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . .53
4.10 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
4.11 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Section 5. Configuration Register (CONFIG)
5.1
5.2
5.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Section 6. Central Processor Unit (CPU)
6.1
6.2
6.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
6.4
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .63
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
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6.5
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .65
6.6
6.6.1
6.6.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
6.7
6.8
6.9
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .66
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Section 7. System Integration Module (SIM)
7.1
7.2
7.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
RST and IRQ Pins Initialization . . . . . . . . . . . . . . . . . . . . . . . .79
7.4
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . .79
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Clock Start-Up from POR. . . . . . . . . . . . . . . . . . . . . . . . . . .79
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . .80
7.4.1
7.4.2
7.4.3
7.5
7.5.1
7.5.2
7.5.2.1
7.5.2.2
7.5.2.3
7.5.2.4
7.5.2.5
Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . .80
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Active Resets from Internal Sources . . . . . . . . . . . . . . . . . .81
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Computer Operating Properly (COP) Reset. . . . . . . . . . .83
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Illegal Address Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . .84
7.6
SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . .85
SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . .85
SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . .85
7.6.1
7.6.2
7.6.3
7.7
Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
7.7.1
7.7.1.1
7.7.1.2
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7.7.2
Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .90
Interrupt Status Register 1. . . . . . . . . . . . . . . . . . . . . . . .91
Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . .91
Interrupt Status Register 3. . . . . . . . . . . . . . . . . . . . . . . .92
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . .93
7.7.2.1
7.7.2.2
7.7.2.3
7.7.3
7.7.4
7.7.5
7.8
7.8.1
7.8.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
7.9
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
SIM Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . . . .96
Break Flag Control Register. . . . . . . . . . . . . . . . . . . . . . . . .98
Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.9.1
7.9.2
7.9.3
Section 8. Oscillator Module (OSC)
8.1
8.2
8.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
8.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
Internal Oscillator Trimming. . . . . . . . . . . . . . . . . . . . . .103
Internal to External Clock Switching. . . . . . . . . . . . . . . .104
External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
XTAL Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
8.4.1
8.4.1.1
8.4.1.2
8.4.2
8.4.3
8.4.4
8.5
8.5.1
8.5.2
Oscillator Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . .107
Crystal Amplifier Output Pin
(OSC2/PTA4/BUSCLKX4) . . . . . . . . . . . . . . . . . . . . . .108
Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . .108
XTAL Oscillator Clock (XTALCLK). . . . . . . . . . . . . . . . . . .108
RC Oscillator Clock (RCCLK). . . . . . . . . . . . . . . . . . . . . . .109
Internal Oscillator Clock (INTCLK) . . . . . . . . . . . . . . . . . . .109
8.5.3
8.5.4
8.5.5
8.5.6
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8.5.7
8.5.8
Oscillator Out 2 (BUSCLKX4) . . . . . . . . . . . . . . . . . . . . . .109
Oscillator Out (BUSCLKX2) . . . . . . . . . . . . . . . . . . . . . . . .109
8.6
8.6.1
8.6.2
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
8.7
8.8
Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . .110
CONFIG2 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
8.9
8.9.1
8.9.2
Input/Output (I/O) Registers . . . . . . . . . . . . . . . . . . . . . . . . . .111
Oscillator Status Register. . . . . . . . . . . . . . . . . . . . . . . . . .111
Oscillator Trim Register (OSCTRIM) . . . . . . . . . . . . . . . . .112
Section 9. Monitor ROM (MON)
9.1
9.2
9.3
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
9.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
VTST Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
9.5
Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
Section 10. Timer Interface Module (TIM)
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
10.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
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10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
10.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
10.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
10.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
10.5.3.1
10.5.3.2
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .134
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .135
10.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . .135
10.5.4.1
10.5.4.2
10.5.4.3
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .136
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . .137
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
10.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
10.7 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
10.8 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .140
10.9 Input/Output Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
10.10 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
10.10.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . .141
10.10.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .143
10.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . .144
10.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . .145
10.10.5 TIM Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . .148
Section 11. Analog-to-Digital Converter (ADC)
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
11.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
11.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
11.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
11.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .155
11.4.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . .155
11.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
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11.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
11.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
11.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
11.7 Input/Output Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
11.8 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
11.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . .157
11.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
11.8.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . .159
Section 12. Input/Output (I/O) Ports
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
12.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
12.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
12.3.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . .164
12.3.3 Port A Input Pullup Enable Register. . . . . . . . . . . . . . . . . .166
12.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
12.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
12.4.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . .168
12.4.3 Port B Input Pullup Enable Register. . . . . . . . . . . . . . . . . .169
Section 13. External Interrupt (IRQ)
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
13.5 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
13.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .175
13.7 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .175
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Section 14. Keyboard Interrupt Module (KBI)
14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
14.4.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
14.4.2 Keyboard Status and Control Register. . . . . . . . . . . . . . . .182
14.4.3 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . .184
14.4.4 Auto Wake-up Interrupt Request . . . . . . . . . . . . . . . . . . . .185
14.5 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
14.6 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
14.7 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .187
Section 15. Computer Operating Properly (COP)
15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
15.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
15.4.1 BUSCLKX4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
15.4.2 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
15.4.3 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
15.4.4 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
15.4.5 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
15.4.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
15.4.7 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . .192
15.5 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
15.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
15.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
15.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
15.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
15.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
15.9 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .193
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Section 16. Low-Voltage Inhibit (LVI)
16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
16.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
16.4.2 Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . .198
16.4.3 Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . .198
16.4.4 LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
16.5 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
16.6 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
16.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
16.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
16.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
Section 17. Break Module (BREAK)
17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
17.4.1 Flag Protection During Break Interrupts. . . . . . . . . . . . . . .204
17.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .204
17.4.3 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . .204
17.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .204
17.5 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
17.5.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . .205
17.5.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .206
17.5.3 Break Auxiliary Register. . . . . . . . . . . . . . . . . . . . . . . . . . .207
17.5.4 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
17.5.5 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . .209
17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
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Section 18. Electrical Specifications
18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
18.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .212
18.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .213
18.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
18.6 5-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . .214
18.7 5-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
18.8 5-V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .216
18.9 3-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . .217
18.10 3-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
18.11 3-V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .219
18.12 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
18.13 Analog-to-Digital Converter Characteristics . . . . . . . . . . . . . .221
18.14 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
Section 19. Mechanical Specifications
19.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
19.3 8-Pin Plastic Dual In-Line Package (Case #626) . . . . . . . . . .224
19.4 8-Pin Small Outline Integrated Circuit Package
(Case #968). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
19.5 16-Pin Plastic Dual In-Line Package (Case #648D). . . . . . . .225
19.6 16-Pin Small Outline Integrated Circuit Package
(Case #751G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
19.7 16-Pin Thin Shrink Small Outline Package
(Case #948F). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
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Section 20. Ordering Information
20.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
20.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
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MOTOROLA
Data Sheet — MC68HC908QY4
List of Figures
Figure
Title
Page
1-1
1-2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
MCU Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
2-1
2-2
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . .36
4-1
4-2
4-3
4-4
FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . . . . .47
FLASH Programming Flowchart. . . . . . . . . . . . . . . . . . . . . . . .52
FLASH Block Protect Register (FLBPR). . . . . . . . . . . . . . . . . .53
FLASH Block Protect Start Address. . . . . . . . . . . . . . . . . . . . .53
5-1
5-2
Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . . .56
Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . . .57
6-1
6-2
6-3
6-4
6-5
6-6
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . .63
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . .78
SIM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Interrupt Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
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List of Figures
Figure
Title
Page
7-10 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
7-11 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . .89
7-12 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . . .91
7-13 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . . .91
7-14 Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . . .92
7-15 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
7-16 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . . .94
7-17 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . .94
7-18 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
7-19 Stop Mode Recovery from Interrupt . . . . . . . . . . . . . . . . . . . . .96
7-20 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . . .96
7-21 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . .98
7-22 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . .99
8-1
8-2
8-3
8-4
XTAL Oscillator External Connections . . . . . . . . . . . . . . . . . .106
RC Oscillator External Connections . . . . . . . . . . . . . . . . . . . .107
Oscillator Status Register (OSCSTAT). . . . . . . . . . . . . . . . . .111
Oscillator Trim Register (OSCTRIM) . . . . . . . . . . . . . . . . . . .112
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
Monitor Mode Circuit (External Clock, No High Voltage) . . . .116
Monitor Mode Circuit (Internal Clock, No High Voltage). . . . .116
Monitor Mode Circuit (External Clock, with High Voltage) . . .117
Low-Voltage Monitor Mode Entry Flowchart. . . . . . . . . . . . . .119
Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
Stack Pointer at Monitor Mode Entry . . . . . . . . . . . . . . . . . . .127
9-10 Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .128
10-1 TIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
10-2 TIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .132
10-3 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .136
10-4 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . .141
10-5 TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . . . .144
10-6 TIM Counter Modulo Registers (TMODH:TMODL). . . . . . . . .144
10-7 TIM Channel Status and Control Registers (TSC0:TSC1) . . .145
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List of Figures
Figure
Title
Page
10-8 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
10-9 TIM Channel Registers (TCH0H/L:TCH1H/L). . . . . . . . . . . . .149
11-1 ADC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .152
11-2 ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
11-3 ADC Status and Control Register (ADSCR). . . . . . . . . . . . . .157
11-4 ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . .159
11-5 ADC Input Clock Register (ADICLK) . . . . . . . . . . . . . . . . . . .159
12-1 I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .162
12-2 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .163
12-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . .164
12-4 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
12-5 Port A Input Pullup Enable Register (PTAPUE) . . . . . . . . . . .166
12-6 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .167
12-7 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .168
12-8 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
12-9 Port B Input Pullup Enable Register (PTBPUE) . . . . . . . . . . .169
13-1 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .172
13-2 IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . .173
13-3 IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . .176
14-1 KBI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .178
14-2 Keyboard Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . .179
14-3 Keyboard Status and Control Register (KBSCR) . . . . . . . . . .183
14-4 Keyboard Interrupt Enable Register (KBIER) . . . . . . . . . . . . .184
14-5 Auto Wake-up Interrupt Request Generation Logic . . . . . . . .185
15-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
15-2 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . . . .192
16-1 LVI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .196
16-2 LVI Status Register (LVISR). . . . . . . . . . . . . . . . . . . . . . . . . .199
17-1 Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .203
17-2 Break I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . .203
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA
List of Figures
21
List of Figures
Figure
Title
Page
17-3 Break Status and Control Register (BRKSCR). . . . . . . . . . . .205
17-4 Break Address Register High (BRKH) . . . . . . . . . . . . . . . . . .206
17-5 Break Address Register Low (BRKL) . . . . . . . . . . . . . . . . . . .206
17-6 Break Auxiliary Register (BRKAR) . . . . . . . . . . . . . . . . . . . . .207
17-7 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . .208
17-8 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . .209
18-1 RC versus Frequency (5 Volts @ 25°C). . . . . . . . . . . . . . . . .216
18-2 RC versus Frequency (3 Volts @ 25°C). . . . . . . . . . . . . . . . .219
18-3 Typical Operating IDD, with All Modules Turned On (25°C) . .220
18-4 Typical Wait Mode IDD, with ADC Turned On (25°C) . . . . . . .220
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
22 List of Figures MOTOROLA
Data Sheet — MC68HC908QY4
List of Tables
Table
Title
Page
1-1
1-2
1-3
Summary of Device Variations . . . . . . . . . . . . . . . . . . . . . . . . .25
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Function Priority in Shared Pins . . . . . . . . . . . . . . . . . . . . . . . .32
2-1
4-1
Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Examples of Protect Start Address. . . . . . . . . . . . . . . . . . . . . .54
6-1
6-2
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
7-1
7-2
7-3
7-4
Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
8-1
8-2
OSC2 Pin Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Oscillator Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
Monitor Mode Signal Requirements and Options. . . . . . . . . .117
Mode Difference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . .121
READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . .123
WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . .124
IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . .124
IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . .125
READSP (Read Stack Pointer) Command. . . . . . . . . . . . . . .126
RUN (Run User Program) Command. . . . . . . . . . . . . . . . . . .126
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA List of Tables 23
List of Tables
Table
Title
Page
10-1 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
10-2 Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
10-3 Mode, Edge, and Level Selection. . . . . . . . . . . . . . . . . . . . . .147
11-1 MUX Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158
11-2 ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160
12-1 Port A Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
12-2 Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
12-3 Port B Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
16-1 LVIOUT Bit Indication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
20-1 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
24 List of Tables MOTOROLA
Data Sheet — MC68HC908QY4
Section 1. General Description
1.1 Contents
1.2
1.3
1.4
1.5
1.6
1.7
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Pin Function Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
1.2 Introduction
The MC68HC908QY4 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08
Family is a Complex Instruction Set Computer (CISC) with a Von
Neumann architecture. All MCUs in the family use the enhanced
M68HC08 central processor unit (CPU08) and are available with a
variety of modules, memory sizes and types, and package types.
Table 1-1. Summary0.o4 f Device Variations
FLASH
Memory Size
Analog-to-Digital
Converter
Pin
Count
Device
MC68HC908QT1
MC68HC908QT2
MC68HC908QT4
MC68HC908QY1
MC68HC908QY2
MC68HC908QY4
1536 bytes
1536 bytes
4096 bytes
1536 bytes
1536 bytes
4096 bytes
—
8 pins
8 pins
4 ch, 8 bit
4 ch, 8 bit
—
8 pins
16 pins
16 pins
16 pins
4 ch, 8 bit
4 ch, 8 bit
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA General Description 25
General Description
1.3 Features
Features include:
• High-performance M68HC08 CPU core
• Fully upward-compatible object code with M68HC05 Family
• 5-V and 3-V operating voltages (VDD)
• 8-MHz internal bus operation at 5 V, 4-MHz at 3 V
• Trimmable internal oscillator
– 3.2 MHz internal bus operation
– 8-bit trim capability
– ± 25% untrimmed
– ± 5% trimmed
• Auto wake-up from STOP capability
• Configuration (CONFIG) register for MCU configuration options,
including:
– Low-voltage inhibit (LVI) trip point
• In-system FLASH programming
• FLASH security(1)
• On-chip in-application programmable FLASH memory (with
internal program/erase voltage generation)
– MC68HC908QY4 and MC68HC908QT4 — 4096 bytes
– MC68HC908QY2, MC68HC908QY1, MC68HC908QT2, and
MC68HC908QT1 — 1536 bytes
• 128 bytes of on-chip random-access memory (RAM)
• 2-channel, 16-bit timer interface module (TIM)
• 4-channel, 8-bit analog-to-digital converter (ADC) on
MC68HC908QY2, MC68HC908QY4, MC68HC908QT2, and
MC68HC908QT4
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
26 General Description MOTOROLA
General Description
Features
• 5 or 13 bidirectional input/output (I/O) lines and one input only:
– Six shared with keyboard interrupt function and ADC
– Two shared with timer channels
– One shared with external interrupt (IRQ)
– Eight extra I/O lines on 16-pin package only
– High current sink/source capability on all port pins
– Selectable pullups on all ports, selectable on an individual bit
basis
– Three-state ability on all port pins
• 6-bit keyboard interrupt with wakeup feature (KBI)
• Low-voltage inhibit (LVI) module features:
– Software selectable trip point in CONFIG register
• System protection features:
– Computer operating properly (COP) watchdog
– Low-voltage detection with reset
– Illegal opcode detection with reset
– Illegal address detection with reset
• External asynchronous interrupt pin with internal pullup (IRQ)
shared with general-purpose input pin
• Master asynchronous reset pin (RST) shared with
general-purpose input/output (I/O) pin
• Power-on reset
• Internal pullups on IRQ and RST to reduce external components
• Memory mapped I/O registers
• Power saving stop and wait modes
• MC68HC908QY4, MC68HC908QY2, and MC68HC908QY1 are
available in these packages:
– 16-pin plastic dual in-line package (PDIP)
– 16-pin small outline integrated circuit (SOIC) package
– 16-pin thin shrink small outline package (TSSOP)
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA
General Description
27
General Description
• MC68HC908QT4, MC68HC908QT2, and MC68HC908QT1 are
available in these packages:
– 8-pin PDIP
– 8-pin SOIC
Features of the CPU08 include the following:
• Enhanced HC05 programming model
• Extensive loop control functions
• 16 addressing modes (eight more than the HC05)
• 16-bit index register and stack pointer
• Memory-to-memory data transfers
• Fast 8 × 8 multiply instruction
• Fast 16/8 divide instruction
• Binary-coded decimal (BCD) instructions
• Optimization for controller applications
• Efficient C language support
1.4 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908QY4.
1.5 Pin Assignments
The MC68HC908QT4, MC68HC908QT2, and MC68HC908QT1 are
available in 8-pin packages and the MC68HC908QY4,
MC68HC908QY2, and MC68HC908QY1 in 16-pin packages.
Figure 1-2 shows the pin assignment for these packages.
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
28
General Description
MOTOROLA
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
PTB[0:7]
V
DD
PTB
POWER SUPPLY
V
SS
DDRB
PTA0/AD0/TCH0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2
CLOCK
GENERATOR
CPU CONTROL
ALU
68HC08 CPU
PTA3/RST/KBI3
PTA4/OSC2/AD2/KBI4
PTA5/OSC1/AD3/KBI5
SYSTEM INTEGRATION
MODULE
ACCUMULATOR
INDEX REGISTER
CPU REGISTERS
SINGLE INTERRUPT
MODULE
STACK POINTER
BREAK
MODULE
PROGRAM COUNTER
POWER-ON RESET
MODULE
CONDITION CODE REGISTER
V 1 1 H I N Z C
16-BIT
TIMER MODULE
MC68HC908QY4 AND MC68HC908QT4: 4096 BYTES
MC68HC908QY2, MC68HC908QY1, MC68HC908QT2,
AND MC68HC908QT1: 1536 BYTES
USER FLASH
128 BYTES RAM
COP
MODULE
MONITOR ROM
RST, IRQ: Pins have internal (about 30K Ohms) pull up
PTA[0:5]: High current sink and source capability
PTA[0:5]: Pins have programmable keyboard interrupt and pull up
PTB[0:7]: Not available on 8-pin devices – MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4
Figure 1-1. Block Diagram
General Description
V
V
VDD
V
SS
SS
1
2
3
4
8
7
6
5
DD
PTA5/OSC1/KBI5
PTA4/OSC2/KBI4
1
2
3
4
8
7
6
5
PTA5/OSC1/AD3/KBI5
PTA4/OSC2/AD2/KBI4
PTA0/AD0/TCH0/KBI0
PTA0/TCH0/KBI0
PTA1/AD1/TCH1/KBI1
PTA2/IRQ/KBI2
PTA1/TCH1/KBI1
PTA2/IRQ/KBI2
PTA3/RST/KBI3
PTA3/RST/KBI3
8-PIN ASSIGNMENT
MC68HC908QT1 PDIP/SOIC
8-PIN ASSIGNMENT
MC68HC908QT2 AND MC68HC908QT4 PDIP/SOIC
VDD
PTB7
PTB6
V
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DD
SS
PTB7
PTB6
PTB0
PTB0
PTB1
PTB1
PTA5/OSC1/AD3/KBI5
PTA4/OSC2/AD2/KBI4
PTA0/AD0/TCH0/KBI0
PTA1/AD1/TCH1/KBI1
PTA5/OSC1/KBI5
PTA4/OSC2/KBI4
PTA0/TCH0/KBI0
PTA1/TCH1/KBI1
PTB2
PTB5
PTB4
PTB2
PTB5
PTB4
PTB3
PTB3
PTA2/IRQ/KBI2
PTA2/IRQ/KBI2
PTA3/RST/KBI3
PTA3/RST/KBI3
16-PIN ASSIGNMENT
MC68HC908QY1 PDIP/SOIC
16-PIN ASSIGNMENT
MC68HC908QY2 AND MC68HC908QY4 PDIP/SOIC
16
15
14
13
12
11
10
9
PTA1/AD1/TCH1/KBI1
16
15
14
13
12
11
10
9
PTA0/AD0/TCH0/KBI0
PTB1
PTA1/TCH1/KBI1
PTB2
1
2
3
4
5
6
7
8
PTA0/TCH0/KBI0
PTB1
1
2
3
4
5
6
7
8
PTB2
PTB0
PTB0
PTB3
PTB3
V
PTA2/IRQ/KBI2
V
PTA2/IRQ/KBI2
SS
SS
V
V
PTA3/RST/KBI3
PTB4
PTA3/RST/KBI3
PTB4
DD
DD
PTB7
PTB6
PTB7
PTB6
PTB5
PTB5
PTA5/OSC1/AD3/KBI5
PTA5/OSC1/KBI5
PTA4/OSC2/AD2/KBI4
PTA4/OSC2/KBI4
16-PIN ASSIGNMENT
MC68HC908QY1 TSSOP
16-PIN ASSIGNMENT
MC68HC908QY2 AND MC68HC908QY4 TSSOP
Figure 1-2. MCU Pin Assignments
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
30 General Description MOTOROLA
General Description
Pin Functions
1.6 Pin Functions
Table 1-2 provides a description of the pin functions.
Table 1-2. Pin Functions
Pin
Name
Description
Input/Output
V
Power supply
Power
DD
SS
V
Power supply ground
Power
Input/Output
Input
PTA0 — General purpose I/O port
AD0 — A/D channel 0 input
PTA0
PTA1
TCH0 — Timer Channel 0 I/O
Input/Output
Input
KBI0 — Keyboard interrupt input 0
PTA1 — General purpose I/O port
AD1 — A/D channel 1 input
Input/Output
Input
TCH1 — Timer Channel 1 I/O
Input/Output
Input
KBI1 — Keyboard interrupt input 1
PTA2 — General purpose input-only port
IRQ — External interrupt with programmable pullup and Schmitt trigger input
KBI2 — Keyboard interrupt input 2
PTA3 — General purpose I/O port
RST — Reset input, active low with internal pullup and Schmitt trigger
KBI3 — Keyboard interrupt input 3
PTA4 — General purpose I/O port
Input
PTA2
PTA3
Input
Input
Input/Output
Input
Input
Input/Output
OSC2 —XTAL oscillator output (XTAL option only)
Output
Output
RC or internal oscillator output (OSC2EN = 1 in PTAPUE register)
PTA4
AD2 — A/D channel 2 input
Input
Input
KBI4 — Keyboard interrupt input 4
PTA5 — General purpose I/O port
OSC1 —XTAL, RC, or external oscillator input
AD3 — A/D channel 3 input
Input/Output
Input
PTA5
Input
KBI5 — Keyboard interrupt input 5
8 general-purpose I/O ports.
Input
(1)
Input/Output
PTB[0:7]
1. The PTB pins are not available on the 8-pin packages.
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA General Description 31
General Description
1.7 Pin Function Priority
Table 1-3 is meant to resolve the priority if multiple functions are enabled
on a single pin.
NOTE: Upon reset all pins come up as input ports regardless of the priority table.
Table 1-3. Function Priority in Shared Pins
Pin Name
PTA[0]
PTA[1]
PTA[2]
PTA[3]
PTA[4]
PTA[5]
Highest-to-Lowest Priority Sequence
AD0 → TCH0 → KBI[0] → PTA[0]
AD1 →TCH1 → KBI[1] → PTA[1]
IRQ → KBI[2] → PTA[2]
RST → KBI[3] → PTA[3]
OSC2 → AD2 → KBI[4] → PTA[4]
OSC1 → AD3 → KBI[5] → PTA[5]
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
32 General Description MOTOROLA
Data Sheet — MC68HC908QY4
Section 2. Memory
2.1 Contents
2.2
2.3
2.4
2.5
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . .33
Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . .35
Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.2 Introduction
The central processor unit (CPU08) can address 64 Kbytes of memory
space. The memory map, shown in Figure 2-1, includes:
• 4096 bytes of user FLASH for MC68HC908QT4 and
MC68HC908QY4
• 1536 bytes of user FLASH for MC68HC908QT2,
MC68HC908QT1, MC68HC908QY2, and MC68HC908QY1
• 128 bytes of random access memory (RAM)
• 48 bytes of user-defined vectors, located in FLASH
• 416 bytes of monitor read-only memory (ROM)
• 1536 bytes of FLASH program and erase routines, located in
ROM
2.3 Unimplemented Memory Locations
Accessing a reserved location can have unpredictable effects on MCU
operation. In Figure 2-1 and in register figures in this document,
unimplemented locations are shaded.
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA
Memory
33
Memory
$0000
↓
$003F
I/O REGISTERS
64 BYTES
$0040
↓
$007F
RESERVED
64 BYTES
$0080
↓
$00FF
RAM
128 BYTES
$0100
↓
$27FF
$0100
↓
$27FF
UNIMPLEMENTED
9984 BYTES
UNIMPLEMENTED
9984 BYTES
$2800
↓
$2DFF
$2800
↓
$2DFF
AUXILIARY ROM
1536 BYTES
AUXILIARY ROM
1536 BYTES
$2E00
↓
$EDFF
$2E00
↓
UNIMPLEMENTED
49152 BYTES
UNIMPLEMENTED
51712 BYTES
$F7FF
$EE00
↓
$FDFF
FLASH MEMORY
MC68HC908QT4 AND MC68HC908QY4
4096 BYTES
$F800
↓
$FDFF
FLASH MEMORY
1536 BYTES
$FE00
$FE01
$FE02
$FE03
$FE04
$FE05
$FE06
$FE07
$FE08
$FE09
$FE0A
$FE0B
$FE0C
BREAK STATUS REGISTER (BSR)
RESET STATUS REGISTER (SRSR)
MC68HC908QT1, MC68HC908QT2,
MC68HC908QY1, and MC68HC908QY2
Memory Map
BREAK AUXILIARY REGISTER (BRKAR)
BREAK FLAG CONTROL REGISTER (BFCR)
INTERRUPT STATUS REGISTER 1 (INT1)
INTERRUPT STATUS REGISTER 2 (INT2)
INTERRUPT STATUS REGISTER 3 (INT3)
RESERVED FOR FLASH TEST CONTROL REGISTER (FLTCR)
FLASH CONTROL REGISTER (FLCR)
BREAK ADDRESS HIGH REGISTER (BRKH)
BREAK ADDRESS LOW REGISTER (BRKL)
BREAK STATUS AND CONTROL REGISTER (BRKSCR)
LVISR
$FE0D
↓
$FE0F
RESERVED FOR FLASH TEST
3 BYTES
$FE10
↓
MONITOR ROM 416 BYTES
$FFAF
$FFB0
↓
$FFBD
FLASH
14 BYTES
$FFBE
$FFBF
$FFC0
FLASH BLOCK PROTECT REGISTER (FLBPR)
RESERVED FLASH
INTERNAL OSCILLATOR TRIM VALUE
$FFC1
RESERVED FLASH
$FFC2
↓
$FFCF
FLASH
14 BYTES
$FFD0
↓
$FFFF
USER VECTORS
48 BYTES
Figure 2-1. Memory Map
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
34 Memory MOTOROLA
Memory
Reserved Memory Locations
2.4 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on MCU
operation. In Figure 2-1 and in register figures in this document,
reserved locations are marked with the word Reserved or with the
letter R.
2.5 Input/Output (I/O) Section
Addresses $0000–$003F, shown in Figure 2-2, contain most of the
control, status, and data registers. Additional I/O registers have these
addresses:
• $FE00 — Break status register, BSR
• $FE01 — Reset status register, SRSR
• $FE02 — Break auxiliary register, BRKAR
• $FE03 — Break flag control register, BFCR
• $FE04 — Interrupt status register 1, INT1
• $FE05 — Interrupt status register 2, INT2
• $FE06 — Interrupt status register 3, INT3
• $FE07 — Reserved
• $FE08 — FLASH control register, FLCR
• $FE09 — Break address register high, BRKH
• $FE0A — Break address register low, BRKL
• $FE0B — Break status and control register, BRKSCR
• $FE0C — LVI status register, LVISR
• $FE0D — Reserved
• $FFBE — FLASH block protect register, FLBPR
• $FFC0 — Internal OSC trim value — Optional
• $FFFF — COP control register, COPCTL
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA
Memory
35
Memory
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
PTA0
U
Read:
0
AWUL
PTA2
Port A Data Register
PTA5
U
PTA4
U
PTA3
U
PTA1
U
$0000
(PTA) Write:
See page 163.
Reset:
Read:
U
0
U
Port B Data Register
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
$0001
$0002
$0003
(PTB) Write:
See page 167.
Reset:
Read:
Unaffected by reset
Unimplemented
Unimplemented
0
0
0
Data Direction Register A
(DDRA) Write:
DDRA5
DDRA4
DDRA3
DDRA1
DDRA0
$0004
$0005
See page 164.
Reset:
Read:
0
DDRB7
0
0
DDRB6
0
0
DDRB5
0
0
DDRB4
0
0
DDRB3
0
0
DDRB2
0
0
DDRB1
0
0
DDRB0
0
Data Direction Register B
(DDRB) Write:
See page 168.
Reset:
Read:
Unimplemented
Unimplemented
$0006
↓
$000A
0
0
Port A Input Pullup Enable
OSC2EN
0
PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
$000B
$000C
Register (PTAPUE) Write:
See page 166.
Reset:
0
0
0
0
0
0
Read:
Port B Input Pullup Enable
PTBPUE7 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3 PTBPUE2 PTBPUE1 PTBPUE0
Register (PTBPUE) Write:
See page 169.
Reset:
0
0
0
0
0
0
0
0
Unimplemented
Unimplemented
$000D
↓
$0019
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 6)
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
36 Memory MOTOROLA
Memory
Input/Output (I/O) Section
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
KEYF
0
ACKK
0
Keyboard Status and
IMASKK MODEK
$001A Control Register (KBSCR) Write:
See page 183.
Reset:
0
0
0
AWUIE
0
0
KBIE5
0
0
KBIE4
0
0
KBIE3
0
0
KBIE1
0
0
KBIE0
0
Read:
Keyboard Interrupt
KBIE2
0
$001B Enable Register (KBIER) Write:
See page 184.
Reset:
0
$001C
$001D
$001E
Unimplemented
Read:
0
0
0
0
0
0
0
IRQF1
0
0
ACK1
0
IRQ Status and Control
IMASK1 MODE1
Register (INTSCR) Write:
See page 176.
Reset:
0
R
0
0
R
0
0
Read:
Configuration Register 2
IRQPUD IRQEN
OSCOPT1 OSCOPT0
R
0
RSTEN
(1)
(CONFIG2) Write:
See page 56.
(2)
Reset:
0
0
0
0
0
1. One-time writable register after each reset.
2. RSTEN reset to logic 0 by a power-on reset (POR) only.
Read:
Configuration Register 1
COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC
STOP
0
COPD
0
(1)
$001F
(CONFIG1) Write:
See page 57.
(2)
Reset:
0
0
0
0
0
0
1. One-time writable register after each reset.
2. LVI5OR3 reset to logic 0 by a power-on reset (POR) only.
Read:
TOF
0
0
0
TIM Status and Control
TOIE
TSTOP
PS2
PS1
PS0
$0020
$0021
$0022
Register (TSC) Write:
TRST
0
See page 141.
Reset:
0
0
1
0
0
0
0
Read: Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TIM Counter Register High
(TCNTH) Write:
See page 144.
Reset:
Read:
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TIM Counter Register
Low (TCNTL) Write:
See page 144.
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 6)
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA Memory 37
Memory
Addr.
Register Name
Bit 7
Bit 15
1
6
Bit 14
1
5
Bit 13
1
4
Bit 12
1
3
Bit 11
1
2
Bit 10
1
1
Bit 9
1
Bit 0
Read:
TIM Counter Modulo
Bit 8
$0023 Register High (TMODH) Write:
See page 144.
Reset:
1
Bit 0
1
Read:
TIM Counter Modulo
Register Low (TMODL) Write:
Bit 7
Bit 6
1
Bit 5
1
Bit 4
1
Bit 3
1
Bit 2
1
Bit 1
1
$0024
See page 144.
Reset:
1
Read: CH0F
TIM Channel 0 Status and
CH0IE
0
MS0B
0
MS0A
0
ELS0B
0
ELS0A
0
TOV0
0
CH0MAX
0
$0025 Control Register (TSC0) Write:
0
0
See page 145.
Reset:
Read:
TIM Channel 0
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
$0026
$0027
Register High (TCH0H) Write:
See page 149.
Reset:
Indeterminate after reset
Bit 4 Bit 3
Indeterminate after reset
Read:
TIM Channel 0
Register Low (TCH0L) Write:
Bit 7
Bit 6
Bit 5
0
Bit 2
Bit 1
Bit 0
See page 149.
Reset:
Read: CH1F
TIM Channel 1 Status and
CH1IE
0
MS1A
0
ELS1B
0
ELS1A
0
TOV1
0
CH1MAX
$0028 Control Register (TSC1) Write:
0
0
See page 145.
Reset:
0
0
Read:
TIM Channel 1
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
$0029
$002A
Register High (TCH1H) Write:
See page 149.
Reset:
Indeterminate after reset
Bit 4 Bit 3
Indeterminate after reset
Read:
TIM Channel 1
Register Low (TCH1L) Write:
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
See page 149.
Reset:
Unimplemented
Unimplemented
$002B
↓
$0035
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 6)
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
38 Memory MOTOROLA
Memory
Input/Output (I/O) Section
Addr.
$0036
$0037
Register Name
Bit 7
R
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
ECGON
0
Bit 0
Read:
ECGST
Oscillator Status Register
(OSCSTAT) Write:
See page 111.
Reset:
0
0
Unimplemented Read:
Oscillator Trim Register Read:
TRIM7
1
TRIM6
0
TRIM5
0
TRIM4
0
TRIM3
0
TRIM2
0
TRIM1
0
TRIM0
0
(OSCTRIM)
See page 112.
$0038
Write:
Reset:
Unimplemented
$0039
↓
$003B
Unimplemented
Read: COCO
ADC Status and Control
AIEN
0
ADCO
0
CH4
1
CH3
1
CH2
1
CH1
1
CH0
1
$003C
$003D
Register (ADSCR) Write:
See page 157.
Reset:
0
Unimplemented
Read:
AD7
AD6
AD5
AD4
AD3
AD2
0
AD1
0
AD0
0
ADC Data Register
$003E
$003F
$FE00
(ADR) Write:
See page 159.
Reset:
Indeterminate after reset
Read:
0
0
ADC Input Clock Register
ADIV2
ADIV1
ADIV0
(ADICLK) Write:
See page 159.
Reset:
Read:
0
0
0
0
0
0
0
SBSW
See note 1
0
0
Break Status Register
R
R
R
R
R
R
R
(BSR) Write:
See page 208.
Reset:
1. Writing a logic 0 clears SBSW.
Read: POR
PIN
COP
ILOP
ILAD
MODRST
0
LVI
0
0
0
SIM Reset Status Register
(SRSR) Write:
See page 96.
$FE01
POR:
1
0
0
0
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 6)
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA Memory 39
Memory
Addr.
Register Name
Break Auxiliary
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
0
BDCOP
$FE02
Register (BRKAR) Write:
See page 207.
Reset:
0
0
0
0
0
0
0
0
Read:
Break Flag Control
BCFE
R
R
R
R
R
R
R
$FE03
Register (BFCR) Write:
See page 209.
Reset:
0
0
Read:
IF5
R
0
IF4
R
0
IF3
R
0
0
R
0
IF1
R
0
0
R
0
0
R
Interrupt Status Register 1
$FE04
$FE05
(INT1) Write:
R
0
See page 176.
Reset:
0
Read:
IF14
R
0
0
0
0
0
0
0
0
Interrupt Status Register 2
(INT2) Write:
R
0
R
0
R
0
R
0
R
0
R
0
R
See page 176.
Reset:
Read:
0
0
0
0
0
0
0
0
IF15
R
Interrupt Status Register 3
$FE06
$FE07
(INT3) Write:
R
0
R
0
R
0
R
0
R
0
R
0
R
0
See page 176.
Reset:
0
Reserved
R
R
R
R
R
R
R
R
Read:
0
0
0
0
FLASH Control Register
HVEN
0
MASS
0
ERASE
0
PGM
0
$FE08
$FE09
$FE0A
$FE0B
(FLCR) Write:
See page 47.
Reset:
Read:
0
Bit 15
0
0
Bit 14
0
0
Bit 13
0
0
Bit 12
0
Break Address High
Bit 11
0
Bit 10
0
Bit 9
0
Bit 8
0
Register (BRKH) Write:
See page 206.
Reset:
Read:
Break Address low
Bit 7
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register (BRKL) Write:
See page 206.
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
Read:
Break Status and Control
BRKE
0
BRKA
Register (BRKSCR) Write:
See page 205.
Reset:
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 6)
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
40 Memory MOTOROLA
Memory
Input/Output (I/O) Section
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
R
LVI Status Register
$FE0C
(LVISR) Write:
See page 199.
Reset:
0
0
0
0
0
0
0
0
Reserved for FLASHTest
R
R
R
R
R
R
R
R
$FE0D
↓
$FE0F
Reserved for FLASHTest
Unimplemented
R
R
R
R
R
R
R
R
$FFB0
↓
$FFBD
Unimplemented
Read:
0
0
FLASH Block Protect
BPR7
0
BPR6
0
BPR5
0
BPR4
0
BPR3
0
BPR2
0
BPR1
0
$FFBE
$FFBF
Register (FLBPR) Write:
See page 53.
Reset:
Unimplemented
Read:
TRIM7
TRIM6
TRIM5
TRIM4
TRIM3
TRIM2
TRIM1
TRIM0
Internal Oscillator Trim
$FFC0
$FFC1
Write:
Value (Optional)
Reset:
1
0
0
0
0
0
0
0
Reserved
R
R
R
R
R
R
R
R
Unimplemented
Unimplemented
$FFC2
↓
$FFCF
Read:
LOW BYTE OF RESET VECTOR
WRITING CLEARS COP COUNTER (ANY VALUE)
Unaffected by reset
COP Control Register
$FFFF
(COPCTL) Write:
See page 192.
Reset:
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 6)
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA Memory 41
Memory
.
Table 2-1. Vector Addresses
Vector Priority Vector Address
Vector
$FFDE
$FFDF
$FFE0
$FFE1
ADC conversion complete vector (high)
ADC conversion complete vector (low)
Keyboard vector (high)
Lowest
IF15
IF14
Keyboard vector (low)
IF13
↓
—
Not used
IF6
$FFF2
$FFF3
$FFF4
$FFF5
$FFF6
$FFF7
—
TIM overflow vector (high)
TIM overflow vector (low)
TIM Channel 1 vector (high)
TIM Channel 1 vector (low)
TIM Channel 0 vector (high)
TIM Channel 0 vector (low)
Not used
IF5
IF4
IF3
IF2
IF1
$FFFA
$FFFB
$FFFC
$FFFD
$FFFE
$FFFF
IRQ vector (high)
IRQ vector (low)
SWI vector (high)
—
—
SWI vector (low)
Reset vector (high)
Highest
Reset vector (low)
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
42 Memory MOTOROLA
Data Sheet — MC68HC908QY4
Section 3. Random-Access Memory (RAM)
3.1 Contents
3.2
3.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
3.2 Introduction
This section describes the 128 bytes of random-access memory (RAM).
3.3 Functional Description
Addresses $0080–$00FF are RAM locations. The location of the stack
RAM is programmable. The 16-bit stack pointer allows the stack to be
anywhere in the 64-Kbyte memory space.
NOTE: For correct operation, the stack pointer must point only to RAM
locations.
Before processing an interrupt, the central processor unit (CPU) uses
five bytes of the stack to save the contents of the CPU registers.
NOTE: For M6805, M146805, and M68HC05 compatibility, the H register is not
stacked.
During a subroutine call, the CPU uses two bytes of the stack to store
the return address. The stack pointer decrements during pushes and
increments during pulls.
NOTE: Be careful when using nested subroutines. The CPU may overwrite data
in the RAM during a subroutine or during the interrupt stacking
operation.
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA
Random-Access Memory (RAM)
43
Random-Access Memory (RAM)
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
44
Random-Access Memory (RAM)
MOTOROLA
Data Sheet — MC68HC908QY4
Section 4. FLASH Memory (FLASH)
4.1 Contents
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .48
FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . .49
FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .49
FLASH Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . .53
4.10 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
4.11 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
4.2 Introduction
This section describes the operation of the embedded FLASH memory.
The FLASH memory can be read, programmed, and erased from a
single external supply. The program and erase operations are enabled
through the use of an internal charge pump.
• MC68HC908QY4 and MC68HC908QT4: 4096 bytes user FLASH
from $EE00–$FDFF
• MC68HC908QY2, MC68HC908QT2, MC68HC908QY1 and
MC68HC908QT1: 1536 bytes user FLASH from $F800–$FDFF
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA FLASH Memory (FLASH) 45
FLASH Memory (FLASH)
4.3 Functional Description
The FLASH memory consists of an array of 4096 or 1536 bytes with an
additional 48 bytes for user vectors. The minimum size of FLASH
memory that can be erased is 64 bytes; and the maximum size of FLASH
memory that can be programmed in a program cycle is 32 bytes (a row).
Program and erase operations are facilitated through control bits in the
FLASH control register (FLCR). Details for these operations appear later
in this section. The address ranges for the user memory and vectors are:
• $EE00 – $FDFF; user memory, 4096 bytes: MC68HC908QY4 and
MC68HC908QT4
• $F800 – $FDFF; user memory, 1536 bytes: MC68HC908QY2,
MC68HC908QT2, MC68HC908QY1 and MC68HC908QT1
• $FFD0 – $FFFF; user interrupt vectors, 48 bytes.
NOTE: An erased bit reads as logic 1 and a programmed bit reads as logic 0.
A security feature prevents viewing of the FLASH contents.(1)
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
46
FLASH Memory (FLASH)
MOTOROLA
FLASH Memory (FLASH)
FLASH Control Register
4.4 FLASH Control Register
The FLASH control register (FLCR) controls FLASH program and erase
operations.
Address: $FE08
Bit 7
0
6
0
5
0
4
0
3
HVEN
0
2
MASS
0
1
ERASE
0
Bit 0
PGM
0
Read:
Write:
Reset:
0
0
0
0
Figure 4-1. FLASH Control Register (FLCR)
HVEN — High Voltage Enable Bit
This read/write bit enables high voltage from the charge pump to the
memory for either program or erase operation. It can only be set if
either PGM =1 or ERASE =1 and the proper sequence for program
or erase is followed.
1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off
MASS — Mass Erase Control Bit
This read/write bit configures the memory for mass erase operation.
1 = Mass Erase operation selected
0 = Mass Erase operation unselected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation.
ERASE is interlocked with the PGM bit such that both bits cannot be
equal to 1 or set to 1 at the same time.
1 = Erase operation selected
0 = Erase operation unselected
PGM — Program Control Bit
This read/write bit configures the memory for program operation.
PGM is interlocked with the ERASE bit such that both bits cannot be
equal to 1 or set to 1 at the same time.
1 = Program operation selected
0 = Program operation unselected
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA
FLASH Memory (FLASH)
47
FLASH Memory (FLASH)
4.5 FLASH Page Erase Operation
Use the following procedure to erase a page of FLASH memory. A page
consists of 64 consecutive bytes starting from addresses $XX00,
$XX40, $XX80, or $XXC0. The 48-byte user interrupt vectors area also
forms a page. Any FLASH memory page can be erased alone.
1. Set the ERASE bit and clear the MASS bit in the FLASH control
register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH location within the address range of
the block to be erased.
4. Wait for a time, tnvs (minimum 10 µs).
5. Set the HVEN bit.
6. Wait for a time, tErase (minimum 1 ms or 4 ms).
7. Clear the ERASE bit.
8. Wait for a time, tnvh (minimum 5 µs).
9. Clear the HVEN bit.
10. After time, trcv (typical 1 µs), the memory can be accessed in read
mode again.
NOTE: Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, but other unrelated operations
may occur between the steps.
In applications that need up to 10,000 program/erase cycles, use the
4 ms page erase specification to get improved long-term reliability. Any
application can use this 4 ms page erase specification. However, in
applications where a FLASH location will be erased and reprogrammed
less than 1000 times, and speed is important, use the 1 ms page erase
specification to get a lower minimum erase time.
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FLASH Memory (FLASH)
MOTOROLA
FLASH Memory (FLASH)
FLASH Mass Erase Operation
4.6 FLASH Mass Erase Operation
Use the following procedure to erase the entire FLASH memory to read
as logic 1:
1. Set both the ERASE bit and the MASS bit in the FLASH control
register.
2. Read from the FLASH block protect register.
3. Write any data to any FLASH address(1) within the FLASH
memory address range.
4. Wait for a time, tnvs (minimum 10 µs).
5. Set the HVEN bit.
6. Wait for a time, tErase (minimum 4 ms).
7. Clear the ERASE and MASS bits.
NOTE: Mass erase is disabled whenever any block is protected (FLBPR does
not equal $FF).
8. Wait for a time, tnvh1 (minimum 100 µs).
9. Clear the HVEN bit.
10. After time, trcv (typical 1 µs), the memory can be accessed in read
mode again.
NOTE: Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order as shown, but other unrelated operations
may occur between the steps.
4.7 FLASH Program Operation
Programming of the FLASH memory is done on a row basis. A row
consists of 32 consecutive bytes starting from addresses $XX00,
$XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0, or $XXE0. Use the
following step-by-step procedure to program a row of FLASH memory
Figure 4-2 shows a flowchart of the programming algorithm.
NOTE: Only bytes which are currently $FF may be programmed.
1. When in monitor mode, with security sequence failed (see 9.5 Security), write to the FLASH
block protect register instead of any FLASH address.
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FLASH Memory (FLASH)
49
FLASH Memory (FLASH)
1. Set the PGM bit. This configures the memory for program
operation and enables the latching of address and data for
programming.
2. Read from the FLASH block protect register.
3. Write any data to any FLASH location within the address range
desired.
4. Wait for a time, tnvs (minimum 10 µs).
5. Set the HVEN bit.
6. Wait for a time, tpgs (minimum 5 µs).
7. Write data to the FLASH address being programmed(1).
8. Wait for time, tPROG (minimum 30 µs).
9. Repeat step 7 and 8 until all desired bytes within the row are
programmed.
10. Clear the PGM bit(1).
11. Wait for time, tnvh (minimum 5 µs).
12. Clear the HVEN bit.
13. After time, trcv (typical 1 µs), the memory can be accessed in read
mode again.
NOTE: The COP register at location $FFFF should not be written between steps
5-12, when the HVEN bit is set. Since this register is located at a valid
FLASH address, unpredictable behavior may occur if this location is
written while HVEN is set.
This program sequence is repeated throughout the memory until all data
is programmed.
NOTE: Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps. Do not exceed tPROG maximum, see 18.14
Memory Characteristics.
1. The time between each FLASH address change, or the time between the last FLASH address
programmed to clearing PGM bit, must not exceed the maximum programming time, t
maximum.
PROG
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FLASH Memory (FLASH)
FLASH Protection
4.8 FLASH Protection
Due to the ability of the on-board charge pump to erase and program the
FLASH memory in the target application, provision is made to protect
blocks of memory from unintentional erase or program operations due to
system malfunction. This protection is done by use of a FLASH block
protect register (FLBPR). The FLBPR determines the range of the
FLASH memory which is to be protected. The range of the protected
area starts from a location defined by FLBPR and ends to the bottom of
the FLASH memory ($FFFF). When the memory is protected, the HVEN
bit cannot be set in either ERASE or PROGRAM operations.
NOTE: In performing a program or erase operation, the FLASH block protect
register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit.
When the FLBPR is programmed with all 0 s, the entire memory is
protected from being programmed and erased. When all the bits are
erased (all 1’s), the entire memory is accessible for program and erase.
When bits within the FLBPR are programmed, they lock a block of
memory. The address ranges are shown in 4.9 FLASH Block Protect
Register. Once the FLBPR is programmed with a value other than $FF,
any erase or program of the FLBPR or the protected block of FLASH
memory is prohibited. Mass erase is disabled whenever any block is
protected (FLBPR does not equal $FF). The FLBPR itself can be erased
or programmed only with an external voltage, VTST, present on the IRQ
pin. This voltage also allows entry from reset into the monitor mode.
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FLASH Memory (FLASH)
51
FLASH Memory (FLASH)
Algorithm for Programming
a Row (32 Bytes) of FLASH Memory
1
2
3
SET PGM BIT
READ THE FLASH BLOCK PROTECT REGISTER
WRITE ANY DATA TO ANY FLASH ADDRESS
WITHIN THE ROW ADDRESS RANGE DESIRED
4
5
6
WAIT FOR A TIME, tnvs
SET HVEN BIT
WAIT FOR A TIME, tpgs
7
8
WRITE DATA TO THE FLASH ADDRESS
TO BE PROGRAMMED
WAIT FOR A TIME, tPROG
COMPLETED
Y
9
PROGRAMMING
THIS ROW?
N
10
CLEAR PGM BIT
WAIT FOR A TIME, tnvh
CLEAR HVEN BIT
11
12
13
NOTES:
The time between each FLASH address change (step 6 to step 9),
or the time between the last FLASH address programmed
to clearing PGM bit (step 6 to step 9)
WAIT FOR A TIME, trcv
END OF PROGRAMMING
must not exceed the maximum programming
time, t
max.
PROG
This row program algorithm assumes the row/s
to be programmed are initially erased.
Figure 4-2. FLASH Programming Flowchart
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52 FLASH Memory (FLASH) MOTOROLA
FLASH Memory (FLASH)
FLASH Block Protect Register
4.9 FLASH Block Protect Register
The FLASH block protect register is implemented as a byte within the
FLASH memory, and therefore can only be written during a
programming sequence of the FLASH memory. The value in this register
determines the starting address of the protected range within the FLASH
memory.
Address: $FFBE
Bit 7
BPR7
U
6
BPR6
U
5
BPR5
U
4
BPR4
U
3
BPR3
U
2
BPR2
U
1
BPR1
U
Bit 0
BPR0
U
Read:
Write:
Reset:
U = Unaffected by reset. Initial value from factory is 1.
Write to this register is by a programming sequence to the FLASH memory.
Figure 4-3. FLASH Block Protect Register (FLBPR)
BPR[7:0] — FLASH Protection Register Bits [7:0]
These eight bits in FLBPR represent bits [13:6] of a 16-bit memory
address. Bits [15:14] are logic 1s and bits [5:0] are logic 0s.
The resultant 16-bit address is used for specifying the start address
of the FLASH memory for block protection. The FLASH is protected
from this start address to the end of FLASH memory, at $FFFF. With
this mechanism, the protect start address can be XX00, XX40, XX80,
or XXC0 within the FLASH memory. See Figure 4-4 and Table 4-1.
16-BIT MEMORY ADDRESS
START ADDRESS OF
FLBPR VALUE
1
1
0
0
0
0
0
0
FLASH BLOCK PROTECT
Figure 4-4. FLASH Block Protect Start Address
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FLASH Memory (FLASH)
Table 4-1. Examples of Protect Start Address
BPR[7:0]
$00–$B8
Start of Address of Protect Range
The entire FLASH memory is protected.
$EE40 (1110 1110 0100 0000)
$EE80 (1110 1110 1000 0000)
$EEC0 (1110 1110 1100 0000)
$EF00 (1110 1111 0000 0000)
$B9 (1011 1001)
$BA (1011 1010)
$BB (1011 1011)
$BC (1011 1100)
and so on...
$DE (1101 1110)
$DF (1101 1111)
$F780 (1111 0111 1000 0000)
$F7C0 (1111 0111 1100 0000)
$FF80 (1111 1111 1000 0000)
FLBPR, OSCTRIM, and vectors are protected
$FE (1111 1110)
$FF
The entire FLASH memory is not protected.
4.10 Wait Mode
Putting the MCU into wait mode while the FLASH is in read mode does
not affect the operation of the FLASH memory directly, but there will not
be any memory activity since the CPU is inactive.
The WAIT instruction should not be executed while performing a
program or erase operation on the FLASH, or the operation will
discontinue and the FLASH will be on standby mode.
4.11 Stop Mode
Putting the MCU into stop mode while the FLASH is in read mode does
not affect the operation of the FLASH memory directly, but there will not
be any memory activity since the CPU is inactive.
The STOP instruction should not be executed while performing a
program or erase operation on the FLASH, or the operation will
discontinue and the FLASH will be on standby mode
NOTE: Standby mode is the power-saving mode of the FLASH module in which
all internal control signals to the FLASH are inactive and the current
consumption of the FLASH is at a minimum.
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FLASH Memory (FLASH)
MOTOROLA
Data Sheet — MC68HC908QY4
Section 5. Configuration Register (CONFIG)
5.1 Contents
5.2
5.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
5.2 Introduction
This section describes the configuration registers (CONFIG1 and
CONFIG2). The configuration registers enable or disable the following
options:
• Stop mode recovery time (32 × BUSCLKX4 cycles or
4096 × BUSCLKX4 cycles)
• STOP instruction
• Computer operating properly module (COP)
• COP reset period (COPRS): (213–24) × BUSCLKX4 or
(218–24) × BUSCLKX4
• Low-voltage inhibit (LVI) enable and trip voltage selection
• OSC option selection
• IRQ pin
• RST pin
• Auto wake-up timeout period
5.3 Functional Description
The configuration registers are used in the initialization of various
options. The configuration registers can be written once after each reset.
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Configuration Register (CONFIG)
55
Configuration Register (CONFIG)
Most of the configuration register bits are cleared during reset. Since the
various options affect the operation of the microcontroller unit (MCU) it
is recommended that this register be written immediately after reset. The
configuration register is located at $001E and $001F, and may be read
at anytime.
NOTE: The CONFIG registers are one-time writable by the user after each
reset. Upon a reset, the CONFIG registers default to predetermined
settings as shown in Figure 5-1 and Figure 5-2.
Address: $001E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
POR:
IRQPUD IRQEN
R
OSCOPT1 OSCOPT0
R
R
RSTEN
0
0
0
0
0
0
0
0
0
0
0
0
U
0
0
0
R
= Reserved
U = Unaffected
Figure 5-1 Configuration Register 2 (CONFIG2)
IRQPUD — IRQ Pin Pullup Control Bit
1 = Internal pullup is disconnected
0 = Internal pullup is connected between IRQ pin and VDD
IRQEN — IRQ Pin Function Selection Bit
1 = Interrupt request function active in pin
0 = Interrupt request function inactive in pin
OSCOPT1 and OSCOPT0 — Selection Bits for Oscillator Option
(0, 0) Internal oscillator
(0, 1) External oscillator
(1, 0) External RC oscillator
(1, 1) External XTAL oscillator
RSTEN — RST Pin Function Selection
1 = Reset function active in pin
0 = Reset function inactive in pin
NOTE: The RSTEN bit is cleared by a power-on reset (POR) only. Other resets
will leave this bit unaffected.
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Configuration Register (CONFIG)
MOTOROLA
Configuration Register (CONFIG)
Functional Description
Address: $001F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
COPRS LVISTOP LVIRSTD LVIPWRD LVI5OR3 SSREC
STOP
COPD
Write:
Reset:
POR:
0
0
0
0
0
0
U
0
0
0
0
0
0
0
0
0
R
= Reserved
U = Unaffected
Figure 5-2 Configuration Register 1 (CONFIG1)
COPRS (Out of STOP Mode) — COP Reset Period Selection Bit
1 = COP reset short cycle = (213 – 24) × BUSCLKX4
0 = COP reset long cycle = (218 – 24) × BUSCLKX4
COPRS (In STOP Mode) — Auto Wake-up Period Selection Bit
1 = Auto wake-up short cycle = (29) × INTRCOSC
0 = Auto wake-up long cycle = (214) × INTRCOSC
LVISTOP — LVI Enable in Stop Mode Bit
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the
LVI to operate during stop mode. Reset clears LVISTOP.
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable Bit
LVIRSTD disables the reset signal from the LVI module.
1 = LVI module resets disabled
0 = LVI module resets enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module.
1 = LVI module power disabled
0 = LVI module power enabled
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Configuration Register (CONFIG)
57
Configuration Register (CONFIG)
LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit
LVI5OR3 selects the voltage operating mode of the LVI module. The
voltage mode selected for the LVI should match the operating VDD for
the LVI’s voltage trip points for each of the modes.
1 = LVI operates in 5-V mode
0 = LVI operates in 3-V mode
NOTE: The LVI5OR3 bit is cleared by a power-on reset (POR) only. Other
resets will leave this bit unaffected.
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of
32 BUSCLKX4 cycles instead of a 4096 BUSCLKX4 cycle delay.
1 = Stop mode recovery after 32 BUSCLKX4 cycles
0 = Stop mode recovery after 4096 BUSCLKX4 cycles
NOTE: Exiting stop mode by an LVI reset will result in the long stop recovery.
When using the LVI during normal operation but disabling during stop
mode, the LVI will have an enable time of tEN. The system
stabilization time for power-on reset and long stop recovery (both
4096 BUSCLKX4 cycles) gives a delay longer than the LVI enable
time for these startup scenarios. There is no period where the MCU is
not protected from a low-power condition. However, when using the
short stop recovery configuration option, the 32 BUSCLKX4 delay
must be greater than the LVI’s turn on time to avoid a period in startup
where the LVI is not protecting the MCU.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
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Configuration Register (CONFIG)
MOTOROLA
Data Sheet — MC68HC908QY4
Section 6. Central Processor Unit (CPU)
6.1 Contents
6.2
6.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
6.4
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .63
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.5
Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .65
6.6
6.6.1
6.6.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
6.7
6.8
6.9
CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .66
Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
6.2 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully
object-code-compatible version of the M68HC05 CPU. The CPU08
Reference Manual (Motorola document order number CPU08RM/AD)
contains a description of the CPU instruction set, addressing modes,
and architecture.
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MOTOROLA Central Processor Unit (CPU) 59
Central Processor Unit (CPU)
6.3 Features
Features of the CPU include:
• Object code fully upward-compatible with M68HC05 Family
• 16-bit stack pointer with stack manipulation instructions
• 16-bit index register with x-register manipulation instructions
• 8-MHz CPU internal bus frequency
• 64-Kbyte program/data memory space
• 16 addressing modes
• Memory-to-memory data moves without using accumulator
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• Enhanced binary-coded decimal (BCD) data handling
• Modular architecture with expandable internal bus definition for
extension of addressing range beyond 64 Kbytes
• Low-power stop and wait modes
6.4 CPU Registers
Figure 6-1 shows the five CPU registers. CPU registers are not part of
the memory map.
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60 Central Processor Unit (CPU) MOTOROLA
Central Processor Unit (CPU)
CPU Registers
7
0
0
0
0
0
ACCUMULATOR (A)
15
15
15
H
X
INDEX REGISTER (H:X)
STACK POINTER (SP)
PROGRAM COUNTER (PC)
7
V 1
1
H
I
N Z C CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 6-1. CPU Registers
6.4.1 Accumulator
The accumulator is a general-purpose 8-bit register. The CPU uses the
accumulator to hold operands and the results of arithmetic/logic
operations.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Unaffected by reset
Figure 6-2. Accumulator (A)
6.4.2 Index Register
The 16-bit index register allows indexed addressing of a 64-Kbyte
memory space. H is the upper byte of the index register, and X is the
lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the
index register to determine the conditional address of the operand.
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MOTOROLA Central Processor Unit (CPU) 61
Central Processor Unit (CPU)
The index register can serve also as a temporary data storage location.
Bit
15
Bit
0
14 13 12 11 10
9
8
7
6
5
4
3
2
1
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X = Indeterminate
Figure 6-3. Index Register (H:X)
6.4.3 Stack Pointer
The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset, the stack pointer is preset to
$00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The
stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.
Bit
15
Bit
0
14 13 12 11 10
9
8
7
6
5
4
3
2
1
Read:
Write:
Reset:
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Figure 6-4. Stack Pointer (SP)
NOTE: The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct
address (page 0) space. For correct operation, the stack pointer must
point only to RAM locations.
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Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
CPU Registers
6.4.4 Program Counter
The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.
Bit
15
Bit
0
14 13 12 11 10
9
8
7
6
5
4
3
2
1
Read:
Write:
Reset:
Loaded with Vector from $FFFE and $FFFF
Figure 6-5. Program Counter (PC)
6.4.5 Condition Code Register
The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and 5
are set permanently to logic 1. The following paragraphs describe the
functions of the condition code register.
Bit 7
V
6
1
1
5
1
1
4
3
I
2
1
Bit 0
C
Read:
Write:
Reset:
H
X
N
X
Z
X
X
1
X
X = Indeterminate
Figure 6-6. Condition Code Register (CCR)
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MOTOROLA Central Processor Unit (CPU) 63
Central Processor Unit (CPU)
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.
1 = Overflow
0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an add-without-carry (ADD) or
add-with-carry (ADC) operation. The half-carry flag is required for
binary-coded decimal (BCD) arithmetic operations. The DAA
instruction uses the states of the H and C flags to determine the
appropriate correction factor.
1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.
1 = Interrupts disabled
0 = Interrupts enabled
NOTE: To maintain M6805 Family compatibility, the upper byte of the index
register (H) is not stacked automatically. If the interrupt service routine
modifies H, then the user must stack and unstack H using the PSHH and
PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is
serviced first.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack and restores the interrupt mask from the stack. After any
reset, the interrupt mask is set and can be cleared only by the clear
interrupt mask software instruction (CLI).
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
64
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
Arithmetic/Logic Unit (ALU)
N — Negative flag
The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting
bit 7 of the result.
1 = Negative result
0 = Non-negative result
Z — Zero flag
The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.
1 = Zero result
0 = Non-zero result
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions — such as bit test and
branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7
0 = No carry out of bit 7
6.5 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the
instruction set.
Refer to the CPU08 Reference Manual (Motorola document order
number CPU08RM/AD) for a description of the instructions and
addressing modes and more detail about the architecture of the CPU.
6.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption
standby modes.
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA
Central Processor Unit (CPU)
65
Central Processor Unit (CPU)
6.6.1 Wait Mode
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
6.6.2 Stop Mode
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
6.7 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break
interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD or with
$FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
66
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
Instruction Set Summary
6.8 Instruction Set Summary
Table 6-1 provides a summary of the M68HC08 instruction set.
Table 6-1. Instruction Set Summary (Sheet 1 of 7)
Effect
Source
Form
on CCR
Operation
Description
V H I N Z C
ADC #opr
IMM
DIR
EXT
IX2
A9 ii
B9 dd
C9 hh ll
D9 ee ff
E9 ff
2
3
4
4
3
2
4
5
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Add with Carry
A ← (A) + (M) + (C)
–
IX1
IX
SP1
SP2
F9
ADC opr,SP
ADC opr,SP
9EE9 ff
9ED9 ee ff
ADD #opr
ADD opr
IMM
DIR
EXT
IX2
AB ii
BB dd
CB hh ll
DB ee ff
EB ff
2
3
4
4
3
2
4
5
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
Add without Carry
A ← (A) + (M)
–
IX1
IX
SP1
SP2
FB
9EEB ff
9EDB ee ff
AIS #opr
AIX #opr
Add Immediate Value (Signed) to SP
Add Immediate Value (Signed) to H:X
–
–
–
–
–
–
–
–
–
–
– IMM
– IMM
A7 ii
AF ii
2
2
SP ← (SP) + (16 « M)
H:X ← (H:X) + (16 « M)
AND #opr
AND opr
IMM
DIR
EXT
A4 ii
B4 dd
C4 hh ll
D4 ee ff
E4 ff
2
3
4
4
3
2
4
5
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
IX2
Logical AND
A ← (A) & (M)
0
–
–
–
–
–
IX1
IX
SP1
SP2
F4
9EE4 ff
9ED4 ee ff
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP
DIR
INH
INH
IX1
IX
38 dd
48
4
1
1
4
3
5
Arithmetic Shift Left
(Same as LSL)
58
C
0
68 ff
78
b7
b7
b0
b0
SP1
9E68 ff
ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP
DIR
INH
INH
IX1
IX
37 dd
47
4
1
1
4
3
5
57
C
Arithmetic Shift Right
–
–
–
–
67 ff
77
SP1
9E67 ff
BCC rel
Branch if Carry Bit Clear
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
–
–
–
– REL
24 rr
3
DIR (b0) 11 dd
DIR (b1) 13 dd
DIR (b2) 15 dd
DIR (b3) 17 dd
DIR (b4) 19 dd
DIR (b5) 1B dd
DIR (b6) 1D dd
DIR (b7) 1F dd
4
4
4
4
4
4
4
4
BCLR n, opr
Clear Bit n in M
Mn ← 0
–
–
–
BCS rel
BEQ rel
Branch if Carry Bit Set (Same as BLO)
Branch if Equal
PC ← (PC) + 2 + rel ? (C) = 1
PC ← (PC) + 2 + rel ? (Z) = 1
–
–
–
–
–
–
–
–
–
–
– REL
– REL
25 rr
27 rr
3
3
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA Central Processor Unit (CPU)
67
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 2 of 7)
Effect
Source
Form
on CCR
Operation
Description
V H I N Z C
Branch if Greater Than or Equal To
(Signed Operands)
BGE opr
–
–
–
–
–
–
–
–
–
–
– REL
– REL
90 rr
92 rr
3
PC ← (PC) + 2 + rel ? (N V) = 0
Branch if Greater Than (Signed
Operands)
BGT opr
3
3
PC ← (PC) + 2 + rel ? (Z) | (N
V) = 0
BHCC rel
BHCS rel
BHI rel
Branch if Half Carry Bit Clear
Branch if Half Carry Bit Set
Branch if Higher
PC ← (PC) + 2 + rel ? (H) = 0
PC ← (PC) + 2 + rel ? (H) = 1
PC ← (PC) + 2 + rel ? (C) | (Z) = 0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– REL
– REL
– REL
28 rr
29 rr
22 rr
3
3
3
Branch if Higher or Same
(Same as BCC)
BHS rel
PC ← (PC) + 2 + rel ? (C) = 0
–
–
–
–
–
– REL
24 rr
BIH rel
BIL rel
Branch if IRQ Pin High
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 1
PC ← (PC) + 2 + rel ? IRQ = 0
–
–
–
–
–
–
–
–
–
–
– REL
– REL
2F rr
2E rr
3
3
BIT #opr
BIT opr
IMM
DIR
EXT
A5 ii
B5 dd
C5 hh ll
D5 ee ff
E5 ff
2
3
4
4
3
2
4
5
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP
IX2
Bit Test
(A) & (M)
0
–
–
–
IX1
IX
SP1
SP2
F5
9EE5 ff
9ED5 ee ff
Branch if Less Than or Equal To
(Signed Operands)
BLE opr
–
–
–
–
–
– REL
93 rr
3
PC ← (PC) + 2 + rel ? (Z) | (N
V) = 1
BLO rel
BLS rel
Branch if Lower (Same as BCS)
Branch if Lower or Same
PC ← (PC) + 2 + rel ? (C) = 1
–
–
–
–
–
–
–
–
–
–
– REL
– REL
25 rr
23 rr
3
3
PC ← (PC) + 2 + rel ? (C) | (Z) = 1
BLT opr
BMC rel
BMI rel
BMS rel
BNE rel
BPL rel
BRA rel
Branch if Less Than (Signed Operands)
Branch if Interrupt Mask Clear
Branch if Minus
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– REL
– REL
– REL
– REL
– REL
– REL
– REL
91 rr
2C rr
2B rr
2D rr
26 rr
2A rr
20 rr
3
3
3
3
3
3
3
PC ← (PC) + 2 + rel ? (N
V) =1
PC ← (PC) + 2 + rel ? (I) = 0
PC ← (PC) + 2 + rel ? (N) = 1
PC ← (PC) + 2 + rel ? (I) = 1
PC ← (PC) + 2 + rel ? (Z) = 0
PC ← (PC) + 2 + rel ? (N) = 0
PC ← (PC) + 2 + rel
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
Branch Always
DIR (b0) 01 dd rr
DIR (b1) 03 dd rr
DIR (b2) 05 dd rr
DIR (b3) 07 dd rr
DIR (b4) 09 dd rr
DIR (b5) 0B dd rr
DIR (b6) 0D dd rr
DIR (b7) 0F dd rr
5
5
5
5
5
5
5
5
BRCLR n,opr,rel Branch if Bit n in M Clear
PC ← (PC) + 3 + rel ? (Mn) = 0
PC ← (PC) + 2
–
–
–
–
–
–
–
–
–
–
BRN rel
Branch Never
– REL
21 rr
3
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
68 Central Processor Unit (CPU) MOTOROLA
Central Processor Unit (CPU)
Instruction Set Summary
Table 6-1. Instruction Set Summary (Sheet 3 of 7)
Effect
Source
Form
on CCR
Operation
Description
V H I N Z C
DIR (b0) 00 dd rr
DIR (b1) 02 dd rr
DIR (b2) 04 dd rr
DIR (b3) 06 dd rr
DIR (b4) 08 dd rr
DIR (b5) 0A dd rr
DIR (b6) 0C dd rr
DIR (b7) 0E dd rr
5
5
5
5
5
5
5
5
BRSET n,opr,rel Branch if Bit n in M Set
PC ← (PC) + 3 + rel ? (Mn) = 1
–
–
–
–
–
–
–
–
–
DIR (b0) 10 dd
DIR (b1) 12 dd
DIR (b2) 14 dd
DIR (b3) 16 dd
DIR (b4) 18 dd
DIR (b5) 1A dd
DIR (b6) 1C dd
DIR (b7) 1E dd
4
4
4
4
4
4
4
4
BSET n,opr
BSR rel
Set Bit n in M
Mn ← 1
–
–
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
Branch to Subroutine
–
–
–
–
–
–
–
–
–
–
– REL
AD rr
4
PC ← (PC) + rel
CBEQ opr,rel
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 3 + rel ? (X) – (M) = $00
PC ← (PC) + 3 + rel ? (A) – (M) = $00
PC ← (PC) + 2 + rel ? (A) – (M) = $00
PC ← (PC) + 4 + rel ? (A) – (M) = $00
DIR
31 dd rr
41 ii rr
51 ii rr
61 ff rr
71 rr
5
4
4
5
4
6
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
IMM
IMM
Compare and Branch if Equal
–
IX1+
IX+
CBEQ opr,SP,rel
SP1
9E61 ff rr
CLC
CLI
Clear Carry Bit
C ← 0
I ← 0
–
–
–
–
–
–
–
–
–
0 INH
98
9A
1
2
Clear Interrupt Mask
0
– INH
CLR opr
CLRA
M ← $00
A ← $00
X ← $00
H ← $00
M ← $00
M ← $00
M ← $00
DIR
INH
3F dd
4F
3
1
1
1
3
2
4
CLRX
INH
5F
CLRH
Clear
0
–
–
–
–
0
1
– INH
IX1
IX
SP1
8C
CLR opr,X
CLR ,X
6F ff
7F
CLR opr,SP
9E6F ff
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP
IMM
DIR
EXT
IX2
IX1
IX
A1 ii
B1 dd
C1 hh ll
D1 ee ff
E1 ff
2
3
4
4
3
2
4
5
Compare A with M
(A) – (M)
F1
SP1
SP2
9EE1 ff
9ED1 ee ff
COM opr
COMA
M ← (M) = $FF – (M)
A ← (A) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
DIR
INH
33 dd
43
4
1
1
4
3
5
COMX
INH
53
Complement (One’s Complement)
0
–
–
–
–
1
COM opr,X
COM ,X
COM opr,SP
IX1
63 ff
73
9E63 ff
IX
SP1
CPHX #opr
CPHX opr
IMM
DIR
65 ii ii+1
75 dd
3
4
Compare H:X with M
(H:X) – (M:M + 1)
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA Central Processor Unit (CPU)
69
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 4 of 7)
Effect
Source
Form
on CCR
Operation
Description
V H I N Z C
CPX #opr
IMM
DIR
EXT
IX2
A3 ii
B3 dd
C3 hh ll
D3 ee ff
E3 ff
2
3
4
4
3
2
4
5
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP
Compare X with M
(X) – (M)
–
–
IX1
IX
SP1
SP2
F3
9EE3 ff
9ED3 ee ff
(A)10
DAA
Decimal Adjust A
U
–
–
–
–
INH
72
2
A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 3 + rel ? (result) ≠ 0
PC ← (PC) + 2 + rel ? (result) ≠ 0
PC ← (PC) + 4 + rel ? (result) ≠ 0
5
3
3
5
4
6
DBNZ opr,rel
DBNZA rel
DBNZX rel
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel
DIR
INH
3B dd rr
4B rr
5B rr
6B ff rr
7B rr
9E6B ff rr
Decrement and Branch if Not Zero
–
–
–
– INH
IX1
IX
SP1
DEC opr
DECA
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
3A dd
4A
4
1
1
4
3
5
DECX
INH
5A
Decrement
Divide
–
–
–
–
–
DEC opr,X
DEC ,X
DEC opr,SP
IX1
6A ff
7A
9E6A ff
IX
SP1
A ← (H:A)/(X)
H ← Remainder
DIV
–
–
INH
52
7
EOR #opr
EOR opr
IMM
DIR
EXT
A8 ii
B8 dd
C8 hh ll
D8 ee ff
E8 ff
2
3
4
4
3
2
4
5
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP
IX2
Exclusive OR M with A
0
–
–
–
–
–
A ← (A M)
IX1
IX
SP1
SP2
F8
9EE8 ff
9ED8 ee ff
INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
3C dd
4C
5C
6C ff
7C
9E6C ff
4
1
1
4
3
5
INH
Increment
–
IX1
IX
SP1
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR
EXT
– IX2
IX1
BC dd
CC hh ll
DC ee ff
EC ff
2
3
4
3
2
Jump
PC ← Jump Address
–
–
–
–
–
–
–
–
–
–
IX
FC
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
DIR
EXT
– IX2
IX1
BD dd
CD hh ll
DD ee ff
ED ff
4
5
6
5
4
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
Jump to Subroutine
IX
FD
LDA #opr
LDA opr
IMM
DIR
EXT
A6 ii
B6 dd
C6 hh ll
D6 ee ff
E6 ff
2
3
4
4
3
2
4
5
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP
IX2
Load A from M
A ← (M)
0
–
–
–
IX1
IX
SP1
SP2
F6
9EE6 ff
9ED6 ee ff
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
70 Central Processor Unit (CPU) MOTOROLA
Central Processor Unit (CPU)
Instruction Set Summary
Table 6-1. Instruction Set Summary (Sheet 5 of 7)
Effect
Source
Form
on CCR
Operation
Description
V H I N Z C
LDHX #opr
LDHX opr
IMM
DIR
45 ii jj
55 dd
3
4
Load H:X from M
H:X ← (M:M + 1)
0
–
–
–
–
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP
IMM
DIR
EXT
IX2
IX1
IX
AE ii
BE dd
CE hh ll
DE ee ff
EE ff
FE
9EEE ff
9EDE ee ff
2
3
4
4
3
2
4
5
Load X from M
X ← (M)
0
–
–
SP1
SP2
LSL opr
LSLA
DIR
INH
INH
IX1
IX
38 dd
48
4
1
1
4
3
5
LSLX
Logical Shift Left
(Same as ASL)
58
C
0
–
–
–
–
LSL opr,X
LSL ,X
LSL opr,SP
68 ff
78
9E68 ff
b7
b7
b0
b0
SP1
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP
DIR
INH
INH
IX1
IX
34 dd
44
4
1
1
4
3
5
54
0
C
Logical Shift Right
0
64 ff
74
SP1
9E64 ff
MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr
DD
4E dd dd
5E dd
5
4
4
4
(M)Destination ← (M)Source
DIX+
IMD
IX+D
Move
0
–
–
–
–
6E ii dd
7E dd
H:X ← (H:X) + 1 (IX+D, DIX+)
MUL
Unsigned multiply
X:A ← (X) × (A)
–
0
–
–
0 INH
42
5
NEG opr
NEGA
DIR
INH
INH
IX1
IX
30 dd
40
4
1
1
4
3
5
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
NEGX
50
Negate (Two’s Complement)
–
–
NEG opr,X
NEG ,X
NEG opr,SP
60 ff
70
9E60 ff
SP1
NOP
NSA
No Operation
None
–
–
–
–
–
–
–
–
–
–
– INH
– INH
9D
62
1
3
Nibble Swap A
A ← (A[3:0]:A[7:4])
ORA #opr
ORA opr
IMM
DIR
EXT
AA ii
BA dd
CA hh ll
DA ee ff
EA ff
2
3
4
4
3
2
4
5
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP
IX2
Inclusive OR A and M
A ← (A) | (M)
0
–
–
–
IX1
IX
SP1
SP2
FA
9EEA ff
9EDA ee ff
PSHA
PSHH
PSHX
PULA
PULH
PULX
Push A onto Stack
Push H onto Stack
Push X onto Stack
Pull A from Stack
Pull H from Stack
Pull X from Stack
Push (A); SP ← (SP) – 1
Push (H); SP ← (SP) – 1
Push (X); SP ← (SP) – 1
SP ← (SP + 1); Pull (A)
SP ← (SP + 1); Pull (H)
SP ← (SP + 1); Pull (X)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
– INH
– INH
– INH
87
8B
89
86
8A
88
2
2
2
2
2
2
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA Central Processor Unit (CPU)
71
Central Processor Unit (CPU)
Table 6-1. Instruction Set Summary (Sheet 6 of 7)
Effect
Source
Form
on CCR
Operation
Description
V H I N Z C
ROL opr
DIR
INH
INH
IX1
IX
39 dd
49
4
1
1
4
3
5
ROLA
ROLX
59
C
Rotate Left through Carry
–
–
ROL opr,X
ROL ,X
69 ff
79
9E69 ff
b7
b0
ROL opr,SP
SP1
ROR opr
RORA
DIR
INH
INH
IX1
IX
36 dd
46
4
1
1
4
3
5
RORX
56
C
Rotate Right through Carry
–
–
–
–
ROR opr,X
ROR ,X
ROR opr,SP
66 ff
76
9E66 ff
b7
b0
SP1
RSP
Reset Stack Pointer
Return from Interrupt
SP ← $FF
–
–
–
–
–
–
– INH
9C
1
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTI
INH
80
7
SP ← SP + 1; Pull (PCH)
SP ← SP + 1; Pull (PCL)
RTS
Return from Subroutine
Subtract with Carry
–
–
–
–
– INH
81
4
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A2 ii
B2 dd
C2 hh ll
D2 ee ff
E2 ff
2
3
4
4
3
2
4
5
A ← (A) – (M) – (C)
F2
9EE2 ff
9ED2 ee ff
SEC
SEI
Set Carry Bit
C ← 1
I ← 1
–
–
–
–
–
–
–
–
–
1 INH
99
9B
1
2
Set Interrupt Mask
1
– INH
STA opr
DIR
EXT
IX2
B7 dd
C7 hh ll
D7 ee ff
E7 ff
3
4
4
3
2
4
5
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP
Store A in M
M ← (A)
0
–
–
– IX1
IX
F7
SP1
SP2
9EE7 ff
9ED7 ee ff
STHX opr
Store H:X in M
(M:M + 1) ← (H:X)
0
–
–
–
– DIR
– INH
35 dd
8E
4
1
STOP
Enable IRQ Pin; Stop Oscillator
I ← 0; Stop Oscillator
–
0
–
–
STX opr
DIR
EXT
IX2
BF dd
CF hh ll
DF ee ff
EF ff
3
4
4
3
2
4
5
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP
Store X in M
M ← (X)
0
–
–
–
–
– IX1
IX
FF
SP1
SP2
9EEF ff
9EDF ee ff
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP
IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2
A0 ii
B0 dd
C0 hh ll
D0 ee ff
E0 ff
2
3
4
4
3
2
4
5
Subtract
A ← (A) – (M)
F0
9EE0 ff
9ED0 ee ff
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
72 Central Processor Unit (CPU) MOTOROLA
Central Processor Unit (CPU)
Opcode Map
Table 6-1. Instruction Set Summary (Sheet 7 of 7)
Effect
Source
Form
on CCR
Operation
Description
V H I N Z C
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
SWI
Software Interrupt
–
–
1
–
–
– INH
83
9
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
TAP
TAX
TPA
Transfer A to CCR
Transfer A to X
CCR ← (A)
X ← (A)
INH
– INH
– INH
84
97
85
2
1
1
–
–
–
–
–
–
–
–
–
–
Transfer CCR to A
A ← (CCR)
TST opr
TSTA
DIR
INH
3D dd
4D
3
1
1
3
2
4
TSTX
INH
5D
Test for Negative or Zero
(A) – $00 or (X) – $00 or (M) – $00
0
–
–
–
TST opr,X
TST ,X
TST opr,SP
IX1
6D ff
7D
9E6D ff
IX
SP1
TSX
TXA
TXS
Transfer SP to H:X
Transfer X to A
H:X ← (SP) + 1
A ← (X)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
95
9F
94
2
1
2
Transfer H:X to SP
(SP) ← (H:X) – 1
A
C
CCR
Accumulator
Carry/borrow bit
Condition code register
n
Any bit
opr Operand (one or two bytes)
PC Program counter
dd
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct to direct addressing mode
Direct addressing mode
Direct to indexed with post increment addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
dd rr
DD
DIR
DIX+
ee ff
EXT
ff
rel
Relative program counter offset byte
rr
Relative program counter offset byte
SP1 Stack pointer, 8-bit offset addressing mode
SP2 Stack pointer 16-bit offset addressing mode
SP Stack pointer
Offset byte in indexed, 8-bit offset addressing
H
H
hh ll
I
ii
Half-carry bit
Index register high byte
High and low bytes of operand address in extended addressing
Interrupt mask
Immediate operand byte
U
V
X
Z
&
|
Undefined
Overflow bit
Index register low byte
Zero bit
Logical AND
Logical OR
IMD
Immediate source to direct destination addressing mode
IMM
INH
IX
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, no offset, post increment addressing mode
Logical EXCLUSIVE OR
Contents of
–( ) Negation (two’s complement)
( )
IX+
#
Immediate value
IX+D
IX1
IX1+
IX2
M
Indexed with post increment to direct addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 8-bit offset, post increment addressing mode
Indexed, 16-bit offset addressing mode
Memory location
«
←
?
Sign extend
Loaded with
If
Concatenated with
Set or cleared
Not affected
:
N
Negative bit
—
6.9 Opcode Map
The opcode map is provided in Table 6-2.
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA Central Processor Unit (CPU)
73
Table 6-2. Opcode Map
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
DIR
DIR
REL
DIR
3
INH
4
INH
IX1
SP1
9E6
IX
7
INH
INH
IMM
A
DIR
B
EXT
C
IX2
SP2
IX1
E
SP1
9EE
IX
F
MSB
0
1
2
5
6
8
9
D
9ED
LSB
5
4
3
4
1
NEGA
INH
1
4
5
3
7
3
2
3
4
4
5
3
4
2
0
BRSET0 BSET0
BRA
NEG
NEGX
NEG
NEG
NEG
IX
RTI
BGE
SUB
SUB
SUB
SUB
SUB
SUB
SUB
SUB
IX
3
DIR
5
2
DIR
4
2
2
2
2
2
2
2
2
REL 2 DIR
1
1
INH
4
2
IX1 3 SP1
5
1
2
1
1
1
2
1
1
1
1
1
2
1
1
2
1
1
1
INH
2
2
2
2
1
1
REL 2 IMM
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
DIR
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
EXT 3 IX2
4
4
4
4
4
4
4
4
4
4
4
4
SP2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IX1
3
3
3
3
3
3
3
3
3
3
3
3
SP1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
BRN
REL 3 DIR
3
BHI
REL
3
BLS
REL 2 DIR
3
BCC
REL 2 DIR
3
BCS
REL 2 DIR
3
BNE
REL 2 DIR
3
BEQ
REL 2 DIR
3
5
4
6
CBEQ
SP1
4
CBEQ
IX+
2
DAA
INH
3
COM
IX
3
LSR
IX
4
CPHX
DIR
3
ROR
IX
3
ASR
IX
3
LSL
IX
3
ROL
IX
3
DEC
IX
4
DBNZ
IX
3
INC
IX
4
3
BLT
REL 2 IMM
3
BGT
REL 2 IMM
3
BLE
REL 2 IMM
2
CMP
3
4
CMP
EXT 3 IX2
4
SBC
EXT 3 IX2
4
CPX
EXT 3 IX2
4
AND
EXT 3 IX2
4
BIT
EXT 3 IX2
4
LDA
EXT 3 IX2
4
STA
EXT 3 IX2
4
EOR
EXT 3 IX2
4
ADC
EXT 3 IX2
4
ORA
EXT 3 IX2
4
ADD
EXT 3 IX2
3
JMP
EXT 3 IX2
5
JSR
EXT 3 IX2
4
LDX
EXT 3 IX2
4
STX
EXT 3 IX2
4
5
3
4
2
CMP
IX
2
SBC
IX
2
CPX
IX
2
AND
IX
2
BIT
IX
2
LDA
IX
2
STA
IX
2
EOR
IX
2
ADC
IX
2
ORA
IX
2
ADD
IX
2
JMP
IX
4
JSR
IX
2
LDX
IX
2
STX
IX
1
2
BRCLR0 BCLR0
CBEQ CBEQA CBEQX CBEQ
RTS
CMP
CMP
CMP
CMP
CMP
3
DIR
5
2
DIR
4
3
1
IMM
5
3
1
IMM 3 IX1+
4
INH
DIR
SP2
IX1
SP1
7
DIV
INH
3
2
SBC
3
4
SBC
5
3
4
BRSET1 BSET1
MUL
NSA
SBC
SBC
SBC
SBC
3
DIR
5
2
DIR
4
INH
1
1
2
2
3
2
2
2
2
2
3
2
2
3
2
INH
DIR
SP2
IX1
SP1
4
1
4
COM
IX1
4
LSR
IX1
3
CPHX
IMM
4
ROR
IX1
4
ASR
IX1
4
LSL
IX1
4
ROL
IX1
4
DEC
IX1
5
DBNZ
IX1
4
INC
IX1
3
TST
IX1
4
MOV
IMD
5
COM
SP1
5
LSR
SP1
9
2
CPX
3
4
CPX
5
3
4
3
BRCLR1 BCLR1
COM
COMA
1
COMX
SWI
CPX
CPX
CPX
CPX
3
DIR
5
2
DIR
4
INH
1
LSRA
INH
3
LDHX
IMM
1
INH
3
3
1
1
1
1
1
1
1
1
1
1
INH
DIR
SP2
IX1
SP1
4
LSR
1
LSRX
INH
4
LDHX
DIR
2
2
2
3
4
AND
5
3
4
4
BRSET2 BSET2
TAP
TXS
AND
AND
AND
AND
AND
3
DIR
5
2
DIR
4
1
3
1
2
INH
INH
2
2
2
2
2
2
2
2
IMM
DIR
SP2
IX1
SP1
4
1
2
2
BIT
IMM
2
LDA
IMM
2
AIS
IMM
3
BIT
DIR
3
LDA
DIR
4
BIT
5
BIT
SP2
5
LDA
SP2
3
4
BIT
SP1
4
LDA
SP1
5
BRCLR2 BCLR2
STHX
TPA
TSX
BIT
3
DIR
5
2
DIR
4
INH
INH
IX1
4
1
1
5
ROR
SP1
5
ASR
SP1
5
LSL
SP1
5
ROL
SP1
5
DEC
SP1
6
DBNZ
SP1
5
INC
SP1
4
TST
SP1
2
4
LDA
3
LDA
IX1
6
BRSET3 BSET3
ROR
RORA
RORX
PULA
3
DIR
5
2
DIR
4
1
INH
1
INH
3
3
3
3
3
4
3
3
INH
4
ASR
1
ASRA
INH
1
LSLA
INH
1
ROLA
INH
1
DECA
INH
1
ASRX
INH
1
LSLX
INH
1
ROLX
INH
1
DECX
INH
2
PSHA
INH
2
PULX
INH
2
PSHX
INH
2
PULH
INH
2
PSHH
INH
1
CLRH
INH
1
3
4
STA
5
3
4
7
BRCLR3 BCLR3
TAX
STA
STA
STA
STA
3
DIR
5
2
DIR
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
INH
DIR
SP2
IX1
SP1
4
LSL
1
2
3
4
EOR
5
3
4
8
BRSET4 BSET4 BHCC
CLC
EOR
EOR
EOR
EOR
EOR
3
DIR
5
2
DIR
4
2
REL 2 DIR
3
INH
IMM
DIR
SP2
IX1
SP1
4
ROL
1
2
3
4
ADC
5
3
4
9
BRCLR4 BCLR4 BHCS
SEC
ADC
ADC
ADC
ADC
ADC
3
DIR
5
2
DIR
4
2
2
2
2
2
2
2
REL 2 DIR
3
BPL
REL 2 DIR
3
BMI
REL 3 DIR
INH
IMM
DIR
SP2
IX1
SP1
4
DEC
2
CLI
INH
2
SEI
INH
1
RSP
INH
2
3
4
ORA
5
3
4
A
B
C
D
E
F
BRSET5 BSET5
ORA
ORA
ORA
ORA
ORA
3
DIR
5
2
DIR
4
IMM
DIR
SP2
IX1
SP1
5
3
3
2
3
4
ADD
5
3
4
BRCLR5 BCLR5
DBNZ DBNZA DBNZX
ADD
ADD
ADD
ADD
ADD
3
DIR
5
2
DIR
4
2
1
1
3
1
INH
1
2
1
1
2
1
INH
1
INCX
INH
IMM
DIR
SP2
IX1
SP1
3
4
INC
2
JMP
DIR
4
JMP
3
JMP
IX1
BRSET6 BSET6
BMC
INCA
3
DIR
5
2
DIR
4
REL 2 DIR
INH
3
BMS
REL 2 DIR
3
BIL
3
TST
1
1
2
TST
IX
1
4
4
6
JSR
5
BRCLR6 BCLR6
TSTA
TSTX
NOP
BSR
JSR
JSR
3
DIR
5
2
DIR
4
INH
5
INH
4
INH
2
2
2
REL
DIR
IX1
4
1
STOP
INH
1
WAIT
INH
2
3
4
LDX
5
3
4
BRSET7 BSET7
MOV
DD
1
CLRA
INH
MOV
DIX+
1
CLRX
INH
MOV
IX+D
LDX
LDX
LDX
LDX
LDX
*
1
TXA
INH
3
DIR
5
2
DIR
4
REL
3
BIH
1
1
IMM
DIR
4
4
SP2
IX1
3
3
SP1
3
CLR
3
CLR
IX1
4
CLR
SP1
2
CLR
IX
2
AIX
IMM
3
4
STX
5
3
4
BRCLR7 BCLR7
DIR DIR
STX
STX
STX
STX
3
2
REL 2 DIR
3
1
DIR
SP2
IX1
SP1
INH Inherent
REL Relative
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+ Indexed, No Offset with
Post Increment
IX1+ Indexed, 1-Byte Offset with
Post Increment
MSB
0
High Byte of Opcode in Hexadecimal
Cycles
IMM Immediate
DIR Direct
IX
Indexed, No Offset
LSB
IX1 Indexed, 8-Bit Offset
IX2 Indexed, 16-Bit Offset
IMD Immediate-Direct
EXT Extended
DD Direct-Direct
IX+D Indexed-Direct DIX+ Direct-Indexed
*Pre-byte for stack pointer indexed instructions
5
Low Byte of Opcode in Hexadecimal
0
BRSET0 Opcode Mnemonic
DIR Number of Bytes / Addressing Mode
3
N O N - D I S C L O S U R E
A G R E E M E N T
R E Q U I R E D
Data Sheet — MC68HC908QY4
Section 7. System Integration Module (SIM)
7.1 Contents
7.2
7.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
RST and IRQ Pins Initialization . . . . . . . . . . . . . . . . . . . . . . . .79
7.4
SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . .79
Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Clock Start-Up from POR. . . . . . . . . . . . . . . . . . . . . . . . . . .79
Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . .80
7.4.1
7.4.2
7.4.3
7.5
7.5.1
7.5.2
7.5.2.1
7.5.2.2
7.5.2.3
7.5.2.4
7.5.2.5
Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . .80
External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Active Resets from Internal Sources . . . . . . . . . . . . . . . . . .81
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Computer Operating Properly (COP) Reset. . . . . . . . . . .83
Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Illegal Address Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . .84
7.6
SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . .85
SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . .85
SIM Counter and Reset States. . . . . . . . . . . . . . . . . . . . . . .85
7.6.1
7.6.2
7.6.3
7.7
7.7.1
Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Interrupt Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . .90
Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . .91
Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . .91
Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . .92
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
7.7.1.1
7.7.1.2
7.7.2
7.7.2.1
7.7.2.2
7.7.2.3
7.7.3
7.7.4
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MOTOROLA System Integration Module (SIM) 75
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7.7.5
Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . .93
7.8
7.8.1
7.8.2
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
7.9
SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
SIM Reset Status Register. . . . . . . . . . . . . . . . . . . . . . . . . .96
Break Flag Control Register. . . . . . . . . . . . . . . . . . . . . . . . .98
Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.9.1
7.9.2
7.9.3
7.2 Introduction
This section describes the system integration module (SIM), which
supports up to 24 external and/or internal interrupts. Together with the
central processor unit (CPU), the SIM controls all microcontroller unit
(MCU) activities. A block diagram of the SIM is shown in Figure 7-1.
Figure 7-2 is a summary of the SIM I/O registers. The SIM is a system
state controller that coordinates CPU and exception timing.
The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and
computer operating properly (COP) timeout
• Interrupt control:
– Acknowledge timing
– Arbitration control timing
– Vector address generation
• CPU enable/disable timing
• Modular architecture expandable to 128 interrupt sources
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76 System Integration Module (SIM) MOTOROLA
System Integration Module (SIM)
Introduction
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
STOP/WAIT
CONTROL
SIMOSCEN (TO OSCILLATOR)
SIM
COUNTER
COP CLOCK
BUSCLKX4 (FROM OSCILLATOR)
BUSCLKX2 (FROM OSCILLATOR)
÷2
V
DD
CLOCK
CONTROL
CLOCK GENERATORS
INTERNAL CLOCKS
INTERNAL
PULL-UP
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
RESET
PIN LOGIC
POR CONTROL
RESET PIN CONTROL
MASTER
RESET
CONTROL
COP TIMEOUT (FROM COP MODULE)
LVI RESET (FROM LVI MODULE)
SIM RESET STATUS REGISTER
FORCED MON MODE ENTRY (FROM MENRST MODULE)
RESET
INTERRUPT SOURCES
CPU INTERFACE
INTERRUPT CONTROL
AND PRIORITY DECODE
Figure 7-1. SIM Block Diagram
Table 7-1. Signal Name Conventions
Signal Name
Description
BUSCLKX4
Buffered clock from the internal, RC or XTAL oscillator circuit.
The BUSCLKX4 frequency divided by two. This signal is again divided by two in the SIM
to generate the internal bus clocks (bus clock = BUSCLKX4 ÷ 4).
BUSCLKX2
Address bus
Data bus
PORRST
IRST
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
R/W
Read/write signal
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Addr.
Register Name
Bit 7
R
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
Bit 0
R
Read:
SBSW
Note 1
0
Break Status Register
$FE00
(BSR) Write:
See page 99.
Reset:
0
0
1. Writing a logic 0 clears SBSW.
Read:
POR
PIN
COP
ILOP
ILAD
MODRST
LVI
0
SIM Reset Status
$FE01
$FE02
Register (SRSR) Write:
See page 96.
POR:
1
0
0
0
0
0
0
0
Reserved
R
R
R
R
R
R
R
R
Read:
Break Flag Control
BCFE
R
R
R
R
R
R
R
$FE03
$FE04
$FE05
$FE06
Register (BFCR) Write:
See page 98.
Reset:
0
0
Read:
IF5
R
0
IF4
R
0
IF3
R
0
0
R
0
IF1
0
R
0
0
R
Interrupt Status
Register 1 (INT1) Write:
R
0
R
See page 91.
Reset:
0
0
Read:
IF14
R
0
0
0
0
0
0
0
0
Interrupt Status
Register 2 (INT2) Write:
R
0
R
0
R
0
R
0
R
R
0
R
See page 91.
Reset:
0
0
Read:
0
0
0
0
0
0
0
IF15
R
Interrupt Status
Register 3 (INT3) Write:
R
0
R
0
R
0
R
0
R
0
R
R
0
See page 92.
Reset:
0
0
= Unimplemented
R
= Reserved
Figure 7-2. SIM I/O Register Summary
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System Integration Module (SIM)
RST and IRQ Pins Initialization
7.3 RST and IRQ Pins Initialization
RST and IRQ pins come out of reset as PTA3 and PTA2 respectively.
RST and IRQ functions can be activated by programing CONFIG2
accordingly. Refer to Section 5. Configuration Register (CONFIG).
7.4 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, BUSCLKX2, as shown in Figure 7-3.
FROM
OSCILLATOR
BUSCLKX4
BUSCLKX2
SIM COUNTER
FROM
OSCILLATOR
BUS CLOCK
GENERATORS
÷ 2
SIM
Figure 7-3. SIM Clock Signals
7.4.1 Bus Timing
In user mode, the internal bus frequency is the oscillator frequency
(BUSCLKX4) divided by four.
7.4.2 Clock Start-Up from POR
When the power-on reset module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after
the 4096 BUSCLKX4 cycle POR time out has completed. The RST pin
is driven low by the SIM during this entire period. The IBUS clocks start
upon completion of the time out.
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7.4.3 Clocks in Stop Mode and Wait Mode
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
BUSCLKX4 to clock the SIM counter. The CPU and peripheral clocks do
not become active until after the stop delay time out. This time out is
selectable as 4096 or 32 BUSCLKX4 cycles. See 7.8.2 Stop Mode.
In wait mode, the CPU clocks are inactive. The SIM also produces two
sets of clocks for other modules. Refer to the wait mode subsection of
each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
7.5 Reset and System Initialization
The MCU has these reset sources:
• Power-on reset module (POR)
• External reset pin (RST)
• Computer operating properly module (COP)
• Low-voltage inhibit module (LVI)
• Illegal opcode
• Illegal address
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in
monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.
An internal reset clears the SIM counter (see 7.6 SIM Counter), but an
external reset does not. Each of the resets sets a corresponding bit in
the SIM reset status register (SRSR). See 7.9 SIM Registers.
7.5.1 External Pin Reset
The RST pin circuits include an internal pullup device. Pulling the
asynchronous RST pin low halts all processing. The PIN bit of the SIM
reset status register (SRSR) is set as long as RST is held low for a
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MOTOROLA
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Reset and System Initialization
minimum of 67 BUSCLKX4 cycles, assuming that the POR was not the
source of the reset. See Table 7-2 for details. Figure 7-4 shows the
relative timing.
Table 7-2. PIN Bit Set Timing
Reset Type
POR
Number of Cycles Required to Set PIN
4163 (4096 + 64 + 3)
All others
67 (64 + 3)
BUSCLKX2
RST
VECT H VECT L
ADDRESS BUS PC
Figure 7-4. External Reset Timing
7.5.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 BUSCLKX4
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles (see
Figure 7-5). An internal reset can be caused by an illegal address, illegal
opcode, COP time out, LVI, or POR (see Figure 7-6).
IRST
RST PULLED LOW BY MCU
32 CYCLES
RST
32 CYCLES
BUSCLKX4
ADDRESS
BUS
VECTOR HIGH
Figure 7-5. Internal Reset Timing
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ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
INTERNAL RESET
LVI
Figure 7-6. Sources of Internal Reset
NOTE: For POR resets, the SIM cycles through 4096 BUSCLKX4 cycles during
which the SIM forces the RST pin low. The internal reset signal then
follows the sequence from the falling edge of RST shown in Figure 7-5.
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
7.5.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module
(POR) generates a pulse to indicate that power on has occurred. The
external reset pin (RST) is held low while the SIM counter counts out
4096 BUSCLKX4 cycles. Sixty-four BUSCLKX4 cycles later, the CPU
and memories are released from reset to allow the reset vector
sequence to occur.
At power on, the following events occur:
• A POR pulse is generated.
• The internal reset signal is asserted.
• The SIM enables the oscillator to drive BUSCLKX4.
• Internal clocks to the CPU and modules are held inactive for 4096
BUSCLKX4 cycles to allow stabilization of the oscillator.
• The RST pin is driven low during the oscillator stabilization time.
• The POR bit of the SIM reset status register (SRSR) is set and all
other bits in the register are cleared.
See Figure 7-7.
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Reset and System Initialization
OSC1
PORRST
4096
CYCLES
32
CYCLES
32
CYCLES
BUSCLKX4
BUSCLKX2
RST
ADDRESS BUS
$FFFE
$FFFF
Figure 7-7. POR Recovery
7.5.2.2 Computer Operating Properly (COP) Reset
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
SIM reset status register (SRSR). The SIM actively pulls down the RST
pin for all internal reset sources.
To prevent a COP module time out, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and stages 12–5 of the
SIM counter. The SIM counter output, which occurs at least every
(212 – 24) BUSCLKX4 cycles, drives the COP counter. The COP should
be serviced as soon as possible out of reset to guarantee the maximum
amount of time before the first time out.
The COP module is disabled during a break interrupt with monitor mode
when BDCOP bit is set in break auxiliary register (BRKAR).
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7.5.2.3 Illegal Opcode Reset
The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.
If the stop enable bit, STOP, in the mask option register is logic 0, the
SIM treats the STOP instruction as an illegal opcode and causes an
illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.
7.5.2.4 Illegal Address Reset
An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not
generate a reset. The SIM actively pulls down the RST pin for all internal
reset sources.
7.5.2.5 Low-Voltage Inhibit (LVI) Reset
The LVI asserts its output to the SIM when the VDD voltage falls to the
LVI trip voltage VTrip. The LVI bit in the SIM reset status register (SRSR)
is set, and the external reset pin (RST) is held low while the SIM counter
counts out 4096 BUSCLKX4 cycles. Sixty-four BUSCLKX4 cycles later,
the CPU and memories are released from reset to allow the reset vector
sequence to occur. The SIM actively pulls down the (RST) pin for all
internal reset sources.
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SIM Counter
7.6 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in
stop mode recovery to allow the oscillator time to stabilize before
enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM
counter uses 12 stages for counting, followed by a 13th stage that
triggers a reset of SIM counters and supplies the clock for the COP
module. The SIM counter is clocked by the falling edge of BUSCLKX4.
7.6.1 SIM Counter During Power-On Reset
The power-on reset module (POR) detects power applied to the MCU.
At power-on, the POR circuit asserts the signal PORRST. Once the SIM
is initialized, it enables the oscillator to drive the bus clock state machine.
7.6.2 SIM Counter During Stop Mode Recovery
The SIM counter also is used for stop mode recovery. The STOP
instruction clears the SIM counter. After an interrupt, break, or reset, the
SIM senses the state of the short stop recovery bit, SSREC, in the
configuration register 1 (CONFIG1). If the SSREC bit is a logic 1, then
the stop recovery is reduced from the normal delay of 4096 BUSCLKX4
cycles down to 32 BUSCLKX4 cycles. This is ideal for applications using
canned oscillators that do not require long start-up times from stop
mode. External crystal applications should use the full stop recovery
time, that is, with SSREC cleared in the configuration register 1
(CONFIG1).
7.6.3 SIM Counter and Reset States
External reset has no effect on the SIM counter (see 7.8.2 Stop Mode
for details.) The SIM counter is free-running after all reset states. See
7.5.2 Active Resets from Internal Sources for counter control and
internal reset recovery sequences.
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7.7 Exception Control
Normal sequential program execution can be changed in three different
ways:
1. Interrupts
a. Maskable hardware CPU interrupts
b. Non-maskable software interrupt instruction (SWI)
2. Reset
3. Break interrupts
7.7.1 Interrupts
An interrupt temporarily changes the sequence of program execution to
respond to a particular event. Figure 7-8 flow charts the handling of
system interrupts.
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced (or the I bit is cleared).
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume. Figure 7-9 shows interrupt entry timing.
Figure 7-10 shows interrupt recovery timing.
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System Integration Module (SIM)
Exception Control
FROM RESET
YES
BREAK INTERRUPT?
NO
YES
I BIT SET?
NO
YES
YES
IRQ
INTERRUPT?
NO
TIMER
INTERRUPT?
NO
STACK CPU REGISTERS
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
(AS MANY INTERRUPTS AS EXIST ON CHIP)
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
YES
YES
NO
RTI
INSTRUCTION?
UNSTACK CPU REGISTERS
EXECUTE INSTRUCTION
NO
Figure 7-8. Interrupt Processing
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MODULE
INTERRUPT
I BIT
ADDRESS BUS
DATA BUS
R/W
DUMMY
SP
SP – 1
SP – 2
SP – 3
SP – 4
VECT H
VECT L START ADDR
DUMMY PC – 1[7:0] PC – 1[15:8]
X
A
CCR
V DATA H V DATA L OPCODE
Figure 7-9. Interrupt Entry
MODULE
INTERRUPT
I BIT
ADDRESS BUS
DATA BUS
R/W
SP – 4
SP – 3
SP – 2
SP – 1
SP
PC
PC + 1
CCR
A
X
PC – 1[7:0] PC – 1[15:8] OPCODE OPERAND
Figure 7-10. Interrupt Recovery
7.7.1.1 Hardware Interrupts
A hardware interrupt does not stop the current instruction. Processing of
a hardware interrupt begins after completion of the current instruction.
When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the
condition code register), and if the corresponding interrupt enable bit is
set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction
execution, the highest priority interrupt is serviced first. Figure 7-11
demonstrates what happens when two interrupts are pending. If an
interrupt is pending upon exit from the original interrupt service routine,
the pending interrupt is serviced before the LDA instruction is executed.
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MOTOROLA
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Exception Control
CLI
LDA #$FF
BACKGROUND ROUTINE
INT1
INT2
PSHH
INT1 INTERRUPT SERVICE ROUTINE
PULH
RTI
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 7-11. Interrupt Recognition Example
The LDA opcode is prefetched by both the INT1 and INT2
return-from-interrupt (RTI) instructions. However, in the case of the INT1
RTI prefetch, this is a redundant operation.
NOTE: To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
7.7.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an
interrupt regardless of the state of the interrupt mask (I bit) in the
condition code register.
NOTE: A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
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7.7.2 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt
sources. Table 7-3 summarizes the interrupt sources and the interrupt
status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 7-3. Interrupt Sources
INT
Register
Flag
Vector
Address
(1)
Priority
Source
Flag
Mask
Highest Reset
—
—
—
—
—
—
$FFFE–$FFFF
$FFFC–$FFFD
$FFFA–$FFFB
$FFF6–$FFF7
$FFF4–$FFF5
$FFF2–$FFF3
$FFDE–$FFDF
SWI instruction
IRQ pin
IRQF1 IMASK1
IF1
IF3
IF4
IF5
IF14
Timer channel 0 interrupt CH0F
Timer channel 1 interrupt CH1F
CH0IE
CH1IE
TOIE
Timer overflow interrupt
Keyboard interrupt
TOF
KEYF IMASKK
COCO AIEN
ADC conversion
IF15
$FFE0–$FFE1
complete interrupt
Lowest
1. The I bit in the condition code register is a global mask for all interrupt sources except the
SWI instruction.
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7.7.2.1 Interrupt Status Register 1
Address: $FE04
Bit 7
6
5
IF4
R
4
IF3
R
3
0
2
IF1
R
1
0
Bit 0
0
Read:
Write:
Reset:
0
R
0
IF5
R
R
0
R
0
R
0
0
0
0
0
R
= Reserved
Figure 7-12. Interrupt Status Register 1 (INT1)
IF1 and IF3–IF5 — Interrupt Flags
These flags indicate the presence of interrupt requests from the
sources shown in Table 7-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0, 1, 3, and 7 — Always read 0
7.7.2.2 Interrupt Status Register 2
Address: $FE05
Bit 7
6
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
IF14
R
0
R
R
0
R
0
R
0
R
0
R
0
R
0
0
0
R
= Reserved
Figure 7-13. Interrupt Status Register 2 (INT2)
IF14 — Interrupt Flags
This flag indicates the presence of interrupt requests from the sources
shown in Table 7-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0–6 — Always read 0
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7.7.2.3 Interrupt Status Register 3
Address: $FE06
Bit 7
6
5
0
4
0
3
0
2
0
1
0
Bit 0
IF15
R
Read:
Write:
Reset:
0
R
0
0
R
R
0
R
0
R
0
R
0
R
0
0
0
R
= Reserved
Figure 7-14. Interrupt Status Register 3 (INT3)
IF15 — Interrupt Flags
These flags indicate the presence of interrupt requests from the
sources shown in Table 7-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 1–7 — Always read 0
7.7.3 Reset
All reset sources always have equal and highest priority and cannot be
arbitrated.
7.7.4 Break Interrupts
The break module can stop normal program flow at a software
programmable break point by asserting its break interrupt output. (See
Section 17. Break Module (BREAK).) The SIM puts the CPU into the
break state by forcing it to the SWI vector location. Refer to the break
interrupt subsection of each module to see how each module is affected
by the break state.
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System Integration Module (SIM)
Low-Power Modes
7.7.5 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can
be cleared during break mode. The user can select whether flags are
protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the break flag control register (BFCR).
Protecting flags in break mode ensures that set flags will not be cleared
while in break mode. This protection allows registers to be freely read
and written during break mode without losing status flag information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in
break mode, a flag remains cleared even when break mode is exited.
Status flags with a two-step clearing mechanism — for example, a read
of one register followed by the read or write of another — are protected,
even when the first step is accomplished prior to entering break mode.
Upon leaving break mode, execution of the second step will clear the flag
as normal.
7.8 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low
power-consumption mode for standby situations. The SIM holds the
CPU in a non-clocked state. The operation of each of these modes is
described below. Both STOP and WAIT clear the interrupt mask (I) in the
condition code register, allowing interrupts to occur.
7.8.1 Wait Mode
In wait mode, the CPU clocks are inactive while the peripheral clocks
continue to run. Figure 7-15 shows the timing for wait mode entry.
ADDRESS BUS
DATA BUS
R/W
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
NOTE: Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
Figure 7-15. Wait Mode Entry Timing
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System Integration Module (SIM)
A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred. In
wait mode, the CPU clocks are inactive. Refer to the wait mode
subsection of each module to see if the module is active or inactive in
wait mode. Some modules can be programmed to be active in wait
mode.
Wait mode can also be exited by a reset or break. A break interrupt
during wait mode sets the SIM break stop/wait bit, SBSW, in the break
status register (BSR). If the COP disable bit, COPD, in the configuration
register is logic 0, then the computer operating properly module (COP)
is enabled and remains active in wait mode.
Figure 7-16 and Figure 7-17 show the timing for wait recovery.
ADDRESS BUS
DATA BUS
$6E0B
$A6
$6E0C
$00FF
$00FE
$00FD
$00FC
$A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 7-16. Wait Recovery from Interrupt or Break
32
CYCLES
32
CYCLES
ADDRESS BUS
$6E0B
$A6
RST VCT H RST VCTL
DATA BUS $A6
$A6
RST
BUSCLKX4
Figure 7-17. Wait Recovery from Internal Reset
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System Integration Module (SIM)
Low-Power Modes
7.8.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from stop
mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (BUSCLKX2 and BUSCLKX4) in
stop mode, stopping the CPU and peripherals. Stop recovery time is
selectable using the SSREC bit in the configuration register 1
(CONFIG1). If SSREC is set, stop recovery is reduced from the normal
delay of 4096 BUSCLKX4 cycles down to 32. This is ideal for the internal
oscillator, RC oscillator, and external oscillator options which do not
require long start-up times from stop mode.
NOTE: External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time
the recovery period. Figure 7-18 shows stop mode entry timing and
Figure 7-19 shows the stop mode recovery time from interrupt or break
NOTE: To minimize stop current, all pins configured as inputs should be driven
to a logic 1 or logic 0.
CPUSTOP
ADDRESS BUS
DATA BUS
R/W
STOP ADDR
STOP ADDR + 1
SAME
SAME
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
NOTE: Previous data can be operand data or the STOP opcode, depending on the last
instruction.
Figure 7-18. Stop Mode Entry Timing
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STOP RECOVERY PERIOD
BUSCLKX4
INTERRUPT
ADDRESS BUS
STOP + 2
STOP + 2
SP
SP – 1
SP – 2
SP – 3
STOP +1
Figure 7-19. Stop Mode Recovery from Interrupt
7.9 SIM Registers
The SIM has three memory mapped registers. Table 7-4 shows the
mapping of these registers.
Table 7-4. SIM Registers
Address
$FE00
$FE01
$FE03
Register
BSR
Access Mode
User
SRSR
BFCR
User
User
7.9.1 SIM Reset Status Register
This register contains seven flags that show the source of the last reset.
Clear the SIM reset status register by reading it. A power-on reset sets
the POR bit and clears all other bits in the register.
Address: $FE01
Bit 7
POR
6
5
4
3
2
1
Bit 0
0
Read:
Write:
POR:
PIN
COP
ILOP
ILAD
MODRST
LVI
1
0
0
0
0
0
0
0
= Unimplemented
Figure 7-20. SIM Reset Status Register (SRSR)
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SIM Registers
POR — Power-On Reset Bit
1 = Last reset caused by POR circuit
0 = Read of SRSR
PIN — External Reset Bit
1 = Last reset caused by external reset pin (RST)
0 = POR or read of SRSR
COP — Computer Operating Properly Reset Bit
1 = Last reset caused by COP counter
0 = POR or read of SRSR
ILOP — Illegal Opcode Reset Bit
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
ILAD — Illegal Address Reset Bit (opcode fetches only)
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
MODRST — Monitor Mode Entry Module Reset bit
1 = Last reset caused by monitor mode entry when vector locations
$FFFE and $FFFF are $FF after POR while IRQB = VDD
0 = POR or read of SRSR
LVI — Low Voltage Inhibit Reset bit
1 = Last reset caused by LVI circuit
0 = POR or read of SRSR
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7.9.2 Break Flag Control Register
The break control register (BFCR) contains a bit that enables software
to clear status bits while the MCU is in a break state.
Address: $FE03
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
BCFE
R
R
R
R
R
R
0
R
=Reserved
Figure 7-21. Break Flag Control Register (BFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
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SIM Registers
7.9.3 Break Status Register
The break status register (BSR) contains a flag to indicate that a break
caused an exit from wait mode. This register is only used in emulation
mode.
Address: $FE00
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
SBSW
Note 1
0
R
R
R
R
R
R
R
= Reserved
1. Writing a logic 0 clears SBSW.
Figure 7-22. Break Status Register (BSR)
SBSW — SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait mode
after exiting from a break interrupt. Clear SBSW by writing a logic 0 to
it. Reset clears SBSW.
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it.
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Data Sheet — MC68HC908QY4
Section 8. Oscillator Module (OSC)
8.1 Contents
8.2
8.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
8.4
8.4.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
8.4.1.1
8.4.1.2
8.4.2
Internal Oscillator Trimming. . . . . . . . . . . . . . . . . . . . . .103
Internal to External Clock Switching. . . . . . . . . . . . . . . .104
External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
8.4.3
8.4.4
XTAL Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106
8.5
Oscillator Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . .107
Crystal Amplifier Output Pin (OSC2/PTA4/BUSCLKX4) . .108
Oscillator Enable Signal (SIMOSCEN). . . . . . . . . . . . . . . .108
XTAL Oscillator Clock (XTALCLK). . . . . . . . . . . . . . . . . . .108
RC Oscillator Clock (RCCLK). . . . . . . . . . . . . . . . . . . . . . .109
Internal Oscillator Clock (INTCLK) . . . . . . . . . . . . . . . . . . .109
Oscillator Out 2 (BUSCLKX4) . . . . . . . . . . . . . . . . . . . . . .109
Oscillator Out (BUSCLKX2) . . . . . . . . . . . . . . . . . . . . . . . .109
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.5.8
8.6
8.6.1
8.6.2
Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
8.7
8.8
Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . .110
CONFIG2 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
8.9
8.9.1
8.9.2
Input/Output (I/O) Registers . . . . . . . . . . . . . . . . . . . . . . . . . .111
Oscillator Status Register. . . . . . . . . . . . . . . . . . . . . . . . . .111
Oscillator Trim Register (OSCTRIM) . . . . . . . . . . . . . . . . .112
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Oscillator Module (OSC)
8.2 Introduction
The oscillator module is used to provide a stable clock source for the
microcontroller system and bus. The oscillator module generates two
output clocks, BUSCLKX2 and BUSCLKX4. The BUSCLKX4 clock is
used by the system integration module (SIM) and the computer
operating properly module (COP). The BUSCLKX2 clock is divided by
two in the SIM to be used as the bus clock for the microcontroller.
Therefore the bus frequency will be one forth of the BUSCLKX4
frequency.
8.3 Features
The oscillator has these four clock source options available:
1. Internal oscillator: An internally generated, fixed frequency clock,
trimmable to ± 5%. This is the default option out of reset.
2. External oscillator: An external clock that can be driven directly
into OSC1.
3. External RC: A built-in oscillator module (RC oscillator) that
requires an external R connection only. The capacitor is internal to
the chip.
4. External crystal: A built-in oscillator module (XTAL oscillator) that
requires an external crystal or ceramic-resonator.
8.4 Functional Description
The oscillator contains these major subsystems:
• Internal oscillator circuit
• Internal or external clock switch control
• External clock circuit
• External crystal circuit
• External RC clock circuit
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MOTOROLA
Oscillator Module (OSC)
Functional Description
8.4.1 Internal Oscillator
The internal oscillator circuit is designed for use with no external
components to provide a clock source with tolerance less than ±25%
untrimmed. An 8-bit trimming register allows the adjust to a tolerance of
less than ±5%.
The internal oscillator will generate a clock of 12.8 MHz typical (INTCLK)
resulting in a bus speed (internal clock ÷ 4) of 3.2 MHz. 3.2 MHz came
from the maximum bus speed guaranteed at 3 V which is 4 MHz. Since
the internal oscillator will have a ±25% tolerance (pre-trim), then the
+25% case should not allow a frequency higher than 4 MHz:
3.2 MHz + 25% = 4 MHz
Figure 8-2 shows how BUSCLKX4 is derived from INTCLK and, like the
RC oscillator, OSC2 can output BUSCLKX4 by setting OSC2EN in
PTAPUE register. See Section 12. Input/Output (I/O) Ports.
8.4.1.1 Internal Oscillator Trimming
The 8-bit trimming register, OSCTRIM, allows a clock period adjust of
+127 and –128 steps. Increasing OSCTRIM value increases the clock
period. Trimming will allow the internal clock frequency value fit in a ±5%
range around12.8 MHz.
There’s an option to order a trimmed version of MC68HC908QY4. The
trimming value will be provided in a known FLASH location, $FFC0. So
that the user would be able to copy this byte from the FLASH to the
OSCTRIM register right at the beginning of assembly code.
Reset loads OSCTRIM with a default value of $80.
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8.4.1.2 Internal to External Clock Switching
When external clock source (external OSC, RC, or XTAL) is desired, the
user must perform the following steps:
1. For external crystal circuits only, OSCOPT[1:0] = 1:1: To help
precharge an external crystal oscillator, set PTA4 (OSC2) as an
output and drive high for several cycles. This may help the crystal
circuit start more robustly.
2. Set CONFIG2 bits OSCOPT[1:0] according to Table 8-2. The
oscillator module control logic will then set OSC1 as an external
clock input and, if the external crystal option is selected, OSC2 will
also be set as the clock output.
3. Create a software delay to wait the stabilization time needed for
the selected clock source (crystal, resonator, RC) as
recommended by the component manufacturer. A good rule of
thumb for crystal oscillators is to wait 4096 cycles of the crystal
frequency, i.e., for a 4-MHz crystal, wait approximately 1 msec.
4. After the manufacturer’s recommended delay has elapsed, the
ECGON bit in the OSC status register (OSCSTAT) needs to be set
by the user software.
5. After ECGON set is detected, the OSC module checks for
oscillator activity by waiting two external clock rising edges.
6. The OSC module then switches to the external clock. Logic
provides a glitch free transition.
7. The OSC module first sets the ECGST bit in the OSCSTAT
register and then stops the internal oscillator.
NOTE: Once transition to the external clock is done, the internal oscillator will
only be reactivated with reset. No post-switch clock monitor feature is
implemented (clock does not switch back to internal if external clock
dies).
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Oscillator Module (OSC)
Functional Description
8.4.2 External Oscillator
The external clock option is designed for use when a clock signal is
available in the application to provide a clock source to the
microcontroller. The OSC1 pin is enabled as an input by the oscillator
module. The clock signal is used directly to create BUSCLKX4 and also
divided by two to create BUSCLKX2.
In this configuration, the OSC2 pin cannot output BUSCLKX4. So the
OSC2EN bit in the port A pullup enable register will be clear to enable
PTA4 I/O functions on the pin.
8.4.3 XTAL Oscillator
The XTAL oscillator circuit is designed for use with an external crystal or
ceramic resonator to provide an accurate clock source. In this
configuration, the OSC2 pin is dedicated to the external crystal circuit.
The OSC2EN bit in the port A pullup enable register has no effect when
this clock mode is selected.
In its typical configuration, the XTAL oscillator is connected in a Pierce
oscillator configuration, as shown in Figure 8-1. This figure shows only
the logical representation of the internal components and may not
represent actual circuitry. The oscillator configuration uses five
components:
• Crystal, X1
• Fixed capacitor, C1
• Tuning capacitor, C2 (can also be a fixed capacitor)
• Feedback resistor, RB
• Series resistor, RS (optional)
NOTE: The series resistor (RS) is included in the diagram to follow strict Pierce
oscillator guidelines and may not be required for all ranges of operation,
especially with high frequency crystals. Refer to the crystal
manufacturer’s data for more information.
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Oscillator Module (OSC)
FROM SIM
TO SIM
BUSCLKX4
TO SIM
BUSCLKX2
XTALCLK
÷ 2
SIMOSCEN
MCU
OSC1
OSC2
RS(1)
RB
X
1
C1
C2
Note 1.
RS can be zero (shorted) when used with higher-frequency crystals. Refer to
manufacturer’s data. See Section 18. Electrical Specifications for component
value requirements.
Figure 8-1. XTAL Oscillator External Connections
8.4.4 RC Oscillator
The RC oscillator circuit is designed for use with external R to provide a
clock source with tolerance less than 25%.
In its typical configuration, the RC oscillator requires two external
components, one R and one C. In the MC68HC908QY4, the capacitor is
internal to the chip. The R value should have a tolerance of 1% or less,
to obtain a clock source with less than 25% tolerance. The oscillator
configuration uses one component, REXT
.
In this configuration, the OSC2 pin can be left in the reset state as PTA4.
Or, the OSC2EN bit in the port A pullup enable register can be set to
enable the OSC2 function on the pin without affecting the clocks.
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Oscillator Module (OSC)
Oscillator Module Signals
OSCRCOPT
TO SIM
BUSCLKX4
FROM SIM
TO SIM
BUSCLKX2
INTCLK
RCCLK
0
1
SIMOSCEN
EXTERNAL RC
OSCILLATOR
EN
÷ 2
1
0
PTA4
I/O
PTA4
OSC2EN
MCU
OSC1
PTA4/BUSCLKX4 (OSC2)
V
DD
See Section 18. Electrical Specifications
for component value requirements.
REXT
Figure 8-2. RC Oscillator External Connections
8.5 Oscillator Module Signals
The following paragraphs describe the signals that are inputs to and
outputs from the oscillator module.
8.5.1 Crystal Amplifier Input Pin (OSC1)
The OSC1 pin is either an input to the crystal oscillator amplifier, an input
to the RC oscillator circuit, or an external clock source.
For the internal oscillator configuration, the OSC1 pin can assume other
functions according to Table 1-3. Function Priority in Shared Pins.
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8.5.2 Crystal Amplifier Output Pin (OSC2/PTA4/BUSCLKX4)
For the XTAL oscillator device, the OSC2 pin is the crystal oscillator
inverting amplifier output.
For the external clock option, the OSC2 pin is dedicated to the PTA4 I/O
function. The OSC2EN bit has no effect.
For the internal oscillator or RC oscillator options, the OSC2 pin can
assume other functions according to Table 1-3. Function Priority in
Shared Pins, or the output of the oscillator clock (BUSCLKX4).
Table 8-1. OSC2 Pin Function
Option
OSC2 Pin Function
Inverting OSC1
PTA4 I/O
XTAL oscillator
External clock
Internal oscillator Controlled by OSC2EN bit in PTAPUE register
or
OSC2EN = 0: PTA4 I/O
RC oscillator
OSC2EN = 1: BUSCLKX4 output
8.5.3 Oscillator Enable Signal (SIMOSCEN)
The SIMOSCEN signal comes from the system integration module (SIM)
and enables/disables either the XTAL oscillator circuit, the RC oscillator,
or the internal oscillator.
8.5.4 XTAL Oscillator Clock (XTALCLK)
XTALCLK is the XTAL oscillator output signal. It runs at the full speed of
the crystal (fXCLK) and comes directly from the crystal oscillator circuit.
Figure 8-1 shows only the logical relation of XTALCLK to OSC1 and
OSC2 and may not represent the actual circuitry. The duty cycle of
XTALCLK is unknown and may depend on the crystal and other external
factors. Also, the frequency and amplitude of XTALCLK can be unstable
at start up.
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Low Power Modes
8.5.5 RC Oscillator Clock (RCCLK)
RCCLK is the RC oscillator output signal. Its frequency is directly
proportional to the time constant of external R and internal C. Figure 8-2
shows only the logical relation of RCCLK to OSC1 and may not
represent the actual circuitry.
8.5.6 Internal Oscillator Clock (INTCLK)
INTCLK is the internal oscillator output signal. Its nominal frequency is
fixed to 12.8 MHz, but it can be also trimmed using the oscillator
trimming feature of the OSCTRIM register (see 8.4.1.1 Internal
Oscillator Trimming).
8.5.7 Oscillator Out 2 (BUSCLKX4)
BUSCLKX4 is the same as the input clock (XTALCLK, RCCLK, or
INTCLK). This signal is driven to the SIM module and is used to
determine the COP cycles.
8.5.8 Oscillator Out (BUSCLKX2)
The frequency of this signal is equal to half of the BUSCLKX4, this signal
is driven to the SIM for generation of the bus clocks used by the CPU
and other modules on the MCU. BUSCLKX2 will be divided again in the
SIM and results in the internal bus frequency being one fourth of either
the XTALCLK, RCCLK, or INTCLK frequency.
8.6 Low Power Modes
The WAIT and STOP instructions put the MCU in low-power
consumption standby modes.
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8.6.1 Wait Mode
The WAIT instruction has no effect on the oscillator logic. BUSCLKX2
and BUSCLKX4 continue to drive to the SIM module.
8.6.2 Stop Mode
The STOP instruction disables either the XTALCLK, the RCCLK, or
INTCLK output, hence BUSCLKX2 and BUSCLKX4.
8.7 Oscillator During Break Mode
The oscillator continues to drive BUSCLKX2 and BUSCLKX4 when the
device enters the break state.
8.8 CONFIG2 Options
Two CONFIG2 register options affect the operation of the oscillator
module: OSCOPT1 and OSCOPT0. All CONFIG2 register bits will have
a default configuration. Refer to Section 5. Configuration Register
(CONFIG) for more information on how the CONFIG2 register is used.
Table 8-2 shows how the OSCOPT bits are used to select the oscillator
clock source.
Table 8-2. Oscillator Modes
OSCOPT1 OSCOPT0
Oscillator Modes
Internal Oscillator
External Oscillator
External RC
0
0
1
1
0
1
0
1
External Crystal
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110 Oscillator Module (OSC) MOTOROLA
Oscillator Module (OSC)
Input/Output (I/O) Registers
8.9 Input/Output (I/O) Registers
The oscillator module contains these two registers:
1. Oscillator status register (OSCSTAT)
2. Oscillator trim register (OSCTRIM)
8.9.1 Oscillator Status Register
The oscillator status register (OSCSTAT) contains the bits for switching
from internal to external clock sources
Address:
$0036
Bit 7
6
5
R
0
4
R
0
3
R
0
2
R
0
1
ECGON
0
Bit 0
Read:
Write:
Reset:
ECGST
R
R
0
0
0
R
=Reserved
Figure 8-3. Oscillator Status Register (OSCSTAT)
ECGON — External Clock Generator On Bit
This read/write bit enables external clock generator, so that the
switching process can be initiated. This bit is forced low during reset.
This bit is ignored in monitor mode with the internal oscillator
bypassed, PTM or CTM mode.
1 = External clock generator enabled
0 = External clock generator disabled
ECGST — External Clock Status Bit
This read-only bit indicates whether or not an external clock source is
engaged to drive the system clock.
1 = An external clock source engaged
0 = An external clock source disengaged
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA
Oscillator Module (OSC)
111
Oscillator Module (OSC)
8.9.2 Oscillator Trim Register (OSCTRIM)
Address: $0038
Bit 7
TRIM7
1
6
TRIM6
0
5
TRIM5
0
4
TRIM4
0
3
TRIM3
0
2
TRIM2
0
1
TRIM71
0
Bit 0
TRIM0
0
Read:
Write:
Reset:
Figure 8-4. Oscillator Trim Register (OSCTRIM)
TRIM7–TRIM0 — Internal Oscillator Trim Factor Bits
These read/write bits change the size of the internal capacitor used
by the internal oscillator. By measuring the period of the internal clock
and adjusting this factor accordingly, the frequency of the internal
clock can be fine tuned. Increasing (decreasing) this factor by one
increases (decreases) the period by appoximately 0.2% of the
untrimmed period (the period for TRIM = $80). The trimmed frequency
is guaranteed not to vary by more than ±5% over the full specified
range of temperature and voltage. The reset value is $80, which sets
the frequency to 12.8 MHz (3.2 MHz bus speed) ±25%.
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112
Oscillator Module (OSC)
MOTOROLA
Data Sheet — MC68HC908QY4
Section 9. Monitor ROM (MON)
9.1 Contents
9.2
9.3
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
9.4
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
VTST Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.5
Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
9.2 Introduction
This section describes the monitor read-only memory (MON) and the
monitor mode entry methods. The monitor ROM allows complete testing
of the microcontroller unit (MCU) through a single-wire interface with a
host computer. Monitor mode entry can be achieved without use of the
higher test voltage, VTST, as long as vector addresses $FFFE and
$FFFF are blank, thus reducing the hardware requirements for in-circuit
programming.
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MOTOROLA Monitor ROM (MON) 113
Monitor ROM (MON)
9.3 Features
Features of the monitor ROM include:
• Normal user-mode pin functionality on most pins
• One pin dedicated to serial communication between monitor
read-only memory (ROM) and host computer
• Standard mark/space non-return-to-zero (NRZ) communication
with host computer
• Execution of code in random-access memory (RAM) or FLASH
• FLASH memory security feature(1)
• FLASH memory programming interface
• Use of external 9.83 MHz crystal or clock to generate internal
frequency of 2.4576 MHz
• Simple internal oscillator mode of operation (no external clock or
high voltage)
• 574 bytes monitor ROM code size
• Monitor mode entry without high voltage, VTST, if reset vector is
blank ($FFFE and $FFFF contain $FF)
• Standard monitor mode entry if high voltage is applied to IRQ
9.4 Functional Description
The monitor ROM receives and executes commands from a host
computer. Figure 9-1, Figure 9-2, and Figure 9-3 show example circuits
used to enter monitor mode and communicate with a host computer via
a standard RS-232 interface.
Simple monitor commands can access any memory address. In monitor
mode, the MCU can execute code downloaded into RAM by a host
computer while most MCU pins retain normal operating mode functions.
All communication between the host computer and the MCU is through
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
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114
Monitor ROM (MON)
MOTOROLA
Monitor ROM (MON)
Functional Description
the PTA0 pin. A level-shifting and multiplexing interface is required
between PTA0 and the host computer. PTA0 is used in a wired-OR
configuration and requires a pullup resistor.
The monitor code has been updated from previous versions of the
monitor code to allow enabling the internal oscillator to generate the
internal clock. This addition, which is enabled when IRQ is held low out
of reset, is intended to support serial communication/programming at
9600 baud in monitor mode by using the internal oscillator, and the
internal oscillator user trim value OSCTRIM (FLASH location $FFC0, if
programmed) to generate the desired internal frequency (3.2 MHz).
Since this feature is enabled only when IRQ is held low out of reset, it
cannot be used when the reset vector is programmed (i.e., the value is
not $FFFF) because entry into monitor mode in this case requires VTST
on IRQ. The IRQ pin must remain low during this monitor session in
order to maintain communication.
Table 9-1 shows the pin conditions for entering monitor mode. As
specified in the table, monitor mode may be entered after a power-on
reset (POR) and will allow communication at 9600 baud provided one of
the following sets of conditions is met:
• If $FFFE and $FFFF does not contain $FF (programmed state):
– The external clock is 9.8304 MHz
– IRQ = VTST
• If $FFFE and $FFFF contain $FF (erased state):
– The external clock is 9.8304 MHz
– IRQ = VDD (this can be implemented through the internal IRQ
pullup)
• If $FFFE and $FFFF contain $FF (erased state):
– IRQ = VSS (internal oscillator is selected, no external clock
required)
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA
Monitor ROM (MON)
115
Monitor ROM (MON)
V
DD
N.C.
RST (PTA3)
V
DD
0.1 µF
MAX232
V
DD
1
16
15
2
9.8304 MHz CLOCK
C1+
OSC1 (PTA5)
+
+
1 µF
1 µF
3
1 µF
C1–
+
PTA1
PTA4
N.C.
N.C.
10 kΩ*
4
C2+
V+
VDD
+
IRQ (PTA2)
PTA0
1 µF
6
V–
5
C2–
1 µF
10 kΩ
+
74HC125
DB9
5
10
9
6
2
7
8
74HC125
3
4
3
5
V
2
SS
1
* Value not critical
Figure 9-1. Monitor Mode Circuit (External Clock, No High Voltage)
V
DD
N.C.
N.C.
RST (PTA3)
V
DD
0.1 µF
MAX232
V
DD
OSC1 (PTA5)
IRQ (PTA2)
1
16
15
2
C1+
+
+
+
1 µF
1 µF
1 µF
PTA1
PTA4
N.C.
N.C.
3
4
1 µF
C1–
+
10 kΩ*
C2+
V+
V
DD
6
V–
5
C2–
1 µF
10 kΩ
+
74HC125
DB9
5
10
9
6
2
3
7
8
PTA0
V
SS
74HC125
3
4
2
1
5
* Value not critical
Figure 9-2. Monitor Mode Circuit (Internal Clock, No High Voltage)
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
116 Monitor ROM (MON) MOTOROLA
Monitor ROM (MON)
Functional Description
V
DD
V
DD
10 kΩ*
0.1 µF
RST (PTA3)
V
DD
0.1 µF
9.8304 MHz CLOCK
V
OSC1 (PTA5)
DD
MAX232
V
DD
1
16
15
2
10 kΩ*
10 kΩ*
C1+
V
TST
+
+
PTA1
PTA4
+
1 µF
1 µF
3
4
C1–
1 µF
1 k
Ω
+
C2+
V+
IRQ (PTA2)
PTA0
V
DD
1 µF
6
V–
5
9.1 V
C2–
1 µF
10 kΩ
+
V
74HC125
6
DB9
SS
5
10
9
2
7
8
74HC125
3
4
3
5
2
1
* Value not critical
Figure 9-3. Monitor Mode Circuit (External Clock, with High Voltage)
Table 9-1. Monitor Mode Signal Requirements and Options
External
Bus
$FFFE/
$FFFF
Mode
IRQ RST
PTA1 PTA4 Clock Frequency
COP
Comment
(MHz)
(MHz)
PTA1 and PTA4 voltages
are required. RST and
OSC1 functions are
active
V
TST
V
V
DD
X
1
0
9.8304
2.4576
Disabled
monitor
mode
TST
OSC1 function is active.
RST and IRQ only
available if later
Forced
monitor
mode
$FF
(blank)
V
X
X
X
9.8304
2.4576
Disabled
DD
configured.
Forced
monitor
mode
RST, IRQ, and OSC1
Disabled only available if later
configured.
$FF
(blank)
V
V
X
X
X
X
X
X
X
X
3.2
SS
Not
$FF
(programmed)
Enters user mode
Enabled RST pin only available if
later configured
DD
User
mode
or
V
—
SS
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MOTOROLA Monitor ROM (MON) 117
Monitor ROM (MON)
If entering monitor mode without high voltage on IRQ (above condition
set 2 or 3, where applied voltage is VDD or VSS), then startup port pin
requirements and conditions, (PTA1/PTA4) are not in effect. This is to
reduce circuit requirements when performing in-circuit programming.
NOTE: If the reset vector is blank and monitor mode is entered, the chip will see
an additional reset cycle after the initial power-on reset (POR). Once the
part has been programmed, the traditional method of applying a voltage,
VTST, to IRQ must be used to enter monitor mode.
The computer operating properly (COP) module is disabled in monitor
mode based on these conditions:
• If monitor mode was entered as a result of the reset vector being
blank (above condition set 2 or 3), the COP is always disabled
regardless of the state of IRQ.
• If monitor mode was entered with VTST on IRQ (condition set 1),
then the COP is disabled as long as VTST is applied to IRQ.
NOTE: The PTA0 pin must be at logic 1 (pullup) during chip power up to enter
monitor mode properly.
Figure 9-4 shows a simplified diagram of the monitor mode entry when
the reset vector is blank and just 1 x VDD voltage is applied to the IRQ
pin. An external oscillator of 9.8304 MHz is required for a baud rate of
9600, as the internal bus frequency is automatically set to the external
frequency divided by four. No external clock is required if IRQ = 0 since
chip clock will be drive by internal clock generator.
Enter monitor mode with pin configuration shown in Figure 9-1 by pulling
RST low and then high. The rising edge of RST latches monitor mode.
Once monitor mode is latched, the values on the specified pins can
change.
Once out of reset, the MCU waits for the host to send eight security bytes
(see 9.5 Security). After the security bytes, the MCU sends a break
signal (10 consecutive logic 0s) to the host, indicating that it is ready to
receive a command.
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118
Monitor ROM (MON)
MOTOROLA
Monitor ROM (MON)
Functional Description
POR RESET
NO
IS VECTOR
BLANK?
NORMAL USER
MODE
YES
MONITOR MODE
EXECUTE
MONITOR
CODE
NO
POR
TRIGGERED?
YES
Figure 9-4. Low-Voltage Monitor Mode Entry Flowchart
9.4.1 Forced Monitor Mode
If the voltage applied to the IRQ is less than VTST, the MCU will come
out of reset in user mode. The MENRST module monitors the reset
vector fetches and will assert an internal reset if it detects that the reset
vectors are erased ($FF). When the MCU comes out of reset, it is forced
into monitor mode without requiring high voltage on the IRQ pin. Once
out of reset, the monitor code is initially executing off the internal clock
at its default frequency.
If IRQ is tied high, all pins will default to regular input port functions
except for PTA0 and PTA5 which will operate as a serial communication
port and OSC1 input respectively (refer to Figure 9-1). That will allow the
clock to be driven from an external source through OSC1 pin.
If IRQ is tied low, all pins will default to regular input port function except
for PTA0 which will operate as serial communication port. Refer to
Figure 9-2.
Regardless of the state of the IRQ pin, it will not function as a port input
pin in monitor mode. Bit 2 of the Port A data register will always read 0.
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA
Monitor ROM (MON)
119
Monitor ROM (MON)
The BIH and BIL instructions will behave as if the IRQ pin is enabled,
regardless of the settings in the configuration register. See Section 5.
Configuration Register (CONFIG).
The COP module is disabled in forced monitor mode. Any reset other
than a power-on reset (POR) will automatically force the MCU to come
back to the forced monitor mode.
In monitor mode, the MCU uses different vectors for reset, SWI
(software interrupt), and break interrupt than those for user mode. The
alternate vectors are in the $FE page instead of the $FF page and allow
code execution from the internal monitor firmware instead of user code.
NOTE: Exiting monitor mode after it has been initiated by having a blank reset
vector requires a power-on reset (POR). Pulling RST (when RST pin
available) low will not exit monitor mode in this situation.
Table 9-2 summarizes the differences between user mode and monitor
mode regarding vectors.
Table 9-2. Mode Difference
Functions
Reset
Vector
High
Reset
Vector
Low
Break
Vector
High
Break
Vector
Low
SWI
Vector
High
SWI
Vector
Low
Modes
User
Monitor
$FFFE
$FEFE
$FFFF
$FEFF
$FFFC
$FEFC
$FFFD
$FEFD
$FFFC
$FEFC
$FFFD
$FEFD
9.4.2 VTST Monitor Mode
RST and OSC1 functions will be active on the PTA3 and PTA5 pins
respectively as long as VTST is applied to IRQ pin. If the IRQ pin is
lowered (no longer VTST) then the chip will still be operating in monitor
mode, but the pin functions will be determined by the settings in the
configuration registers (see Section 5. Configuration Register
(CONFIG)) when VTST was lowered, except for the IRQ pin. IRQ will not
function as a port input pin in monitor mode. Bit 2 of the Port A data
register will always read 0. The BIH and BIL instructions will behave as
if the IRQ pin is enabled, regardless of the settings in the configuration
registers.
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120
Monitor ROM (MON)
MOTOROLA
Monitor ROM (MON)
Functional Description
9.4.3 Data Format
Communication with the monitor ROM is in standard non-return-to-zero
(NRZ) mark/space data format. Transmit and receive baud rates must
be identical.
NEXT
START
BIT
START
BIT
BIT 6
STOP
BIT
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 7
Figure 9-5. Monitor Data Format
9.4.4 Break Signal
A start bit (logic 0) followed by nine logic 0 bits is a break signal. When
the monitor receives a break signal, it drives the PTA0 pin high for the
duration of two bits and then echoes back the break signal.
MISSING STOP BIT
2-STOP BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 9-6. Break Transaction
9.4.5 Baud Rate
The communication baud rate is controlled by the external frequency
and the divide ratio is 1024.
Table 9-3 has the external frequency required to achieve a standard
baud rate of 9600 bps. Other standard baud rates can be accomplished
using proportionally higher or lower frequency generators. If a crystal is
used as the source, be aware of the upper frequency limit that the MCU
can operate.
Table 9-3. Monitor Baud Rate Selection
External Frequency
9.8304 MHz
—
IRQ
Internal Frequency
Baud Rate (bps)
V
TST
2.4576 MHz
9600
or V
DD
V
3.2 MHz (Trimmed)
9600
SS
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MOTOROLA Monitor ROM (MON) 121
Monitor ROM (MON)
9.4.6 Commands
The monitor ROM firmware uses these commands:
• READ (read memory)
• WRITE (write memory)
• IREAD (indexed read)
• IWRITE (indexed write)
• READSP (read stack pointer)
• RUN (run user program)
The monitor ROM firmware echoes each received byte back to the PTA0
pin for error checking. An 11-bit delay at the end of each command
allows the host to send a break character to cancel the command. A
delay of two bit times occurs before each echo and before READ,
IREAD, or READSP data is returned. The data returned by a read
command appears after the echo of the last byte of the command.
NOTE: Wait one bit time after each echo before sending the next byte.
FROM
HOST
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW
READ
READ
DATA
4
4
1
1
4
1
3, 2
4
ECHO
RETURN
Notes:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
3 = Cancel command delay, 11 bit times
4 = Wait 1 bit time before sending next byte.
Figure 9-7. Read Transaction
FROM
HOST
ADDRESS
HIGH
ADDRESS
HIGH
ADDRESS
LOW
ADDRESS
LOW
DATA
DATA
WRITE
WRITE
3
3
1
1
3
1
3
1
2, 3
ECHO
Notes:
1 = Echo delay, 2 bit times
2 = Cancel command delay, 11 bit times
3 = Wait 1 bit time before sending next byte.
Figure 9-8. Write Transaction
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122 Monitor ROM (MON) MOTOROLA
Monitor ROM (MON)
Functional Description
A brief description of each monitor mode command is given in
Table 9-4 through Table 9-9.
Table 9-4. READ (Read Memory) Command
Description Read byte from memory
Operand 2-byte address in high-byte:low-byte order
Data
Returned
Returns contents of specified address
Opcode $4A
Command Sequence
SENT TO
MONITOR
ADDRESS ADDRESS ADDRESS
HIGH HIGH LOW
ADDRESS
LOW
READ
READ
DATA
ECHO
RETURN
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MOTOROLA Monitor ROM (MON) 123
Monitor ROM (MON)
Table 9-5. WRITE (Write Memory) Command
Description Write byte to memory
2-byte address in high-byte:low-byte order; low byte followed by
data byte
Operand
Data
Returned
None
Opcode $49
Command Sequence
FROM
HOST
ADDRESS ADDRESS ADDRESS ADDRESS
DATA
DATA
WRITE
ECHO
WRITE
HIGH
HIGH
LOW
LOW
Table 9-6. IREAD (Indexed Read) Command
Description Read next 2 bytes in memory from last address accessed
Operand 2-byte address in high byte:low byte order
Data
Returned
Returns contents of next two addresses
Opcode $1A
Command Sequence
FROM
HOST
IREAD
DATA
DATA
IREAD
ECHO
RETURN
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
124 Monitor ROM (MON) MOTOROLA
Monitor ROM (MON)
Functional Description
Table 9-7. IWRITE (Indexed Write) Command
Description Write to last address accessed + 1
Operand Single data byte
Data
None
Returned
Opcode $19
Command Sequence
FROM
HOST
DATA
DATA
IWRITE
IWRITE
ECHO
A sequence of IREAD or IWRITE commands can access a block of
memory sequentially over the full 64-Kbyte memory map.
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA
Monitor ROM (MON)
125
Monitor ROM (MON)
Table 9-8. READSP (Read Stack Pointer) Command
Description Reads stack pointer
Operand None
Data Returns incremented stack pointer value (SP + 1) in
Returned high-byte:low-byte order
Opcode $0C
Command Sequence
FROM
HOST
SP
HIGH
SP
LOW
READSP
READSP
ECHO
RETURN
Table 9-9. RUN (Run User Program) Command
Description Executes PULH and RTI instructions
Operand None
Data
None
Returned
Opcode $28
Command Sequence
FROM
HOST
RUN
RUN
ECHO
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126 Monitor ROM (MON) MOTOROLA
Monitor ROM (MON)
Security
The MCU executes the SWI and PSHH instructions when it enters
monitor mode. The RUN command tells the MCU to execute the PULH
and RTI instructions. Before sending the RUN command, the host can
modify the stacked CPU registers to prepare to run the host program.
The READSP command returns the incremented stack pointer value,
SP + 1. The high and low bytes of the program counter are at addresses
SP + 5 and SP + 6.
SP
HIGH BYTE OF INDEX REGISTER
CONDITION CODE REGISTER
ACCUMULATOR
SP + 1
SP + 2
SP + 3
SP + 4
SP + 5
SP + 6
SP + 7
LOW BYTE OF INDEX REGISTER
HIGH BYTE OF PROGRAM COUNTER
LOW BYTE OF PROGRAM COUNTER
Figure 9-9. Stack Pointer at Monitor Mode Entry
9.5 Security
A security feature discourages unauthorized reading of FLASH locations
while in monitor mode. The host can bypass the security feature at
monitor mode entry by sending eight security bytes that match the bytes
at locations $FFF6–$FFFD. Locations $FFF6–$FFFD contain
user-defined data.
NOTE: Do not leave locations $FFF6–$FFFD blank. For security reasons,
program locations $FFF6–$FFFD even if they are not used for vectors.
During monitor mode entry, the MCU waits after the power-on reset for
the host to send the eight security bytes on pin PTA0. If the received
bytes match those at locations $FFF6–$FFFD, the host bypasses the
security feature and can read all FLASH locations and execute code
from FLASH. Security remains bypassed until a power-on reset occurs.
If the reset was not a power-on reset, security remains bypassed and
security code entry is not required. See Figure 9-10.
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MOTOROLA
Monitor ROM (MON)
127
Monitor ROM (MON)
V
DD
4096 + 32 CGMXCLK CYCLES
RST
FROM HOST
PA0
256 BUS CYCLES
(MINIMUM)
1
1
4
1
4
2
1
FROM MCU
Notes:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
4 = Wait 1 bit time before sending next byte.
Figure 9-10. Monitor Mode Entry Timing
Upon power-on reset, if the received bytes of the security code do not
match the data at locations $FFF6–$FFFD, the host fails to bypass the
security feature. The MCU remains in monitor mode, but reading a
FLASH location returns an invalid value and trying to execute code from
FLASH causes an illegal address reset. After receiving the eight security
bytes from the host, the MCU transmits a break character, signifying that
it is ready to receive a command.
NOTE: The MCU does not transmit a break character until after the host sends
the eight security bytes.
To determine whether the security code entered is correct, check to see
if bit 6 of RAM address $80 is set. If it is, then the correct security code
has been entered and FLASH can be accessed.
If the security sequence fails, the device should be reset by a power-on
reset and brought up in monitor mode to attempt another entry. After
failing the security sequence, the FLASH module can also be mass
erased by executing an erase routine that was downloaded into internal
RAM. The mass erase operation clears the security code locations so
that all eight security bytes become $FF (blank).
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Monitor ROM (MON)
MOTOROLA
Data Sheet — MC68HC908QY4
Section 10. Timer Interface Module (TIM)
10.1 Contents
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
10.4 Pin Name Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130
10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
10.5.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
10.5.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
10.5.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133
10.5.3.1
10.5.3.2
Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .134
Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .135
10.5.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . .135
10.5.4.1
10.5.4.2
10.5.4.3
Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .136
Buffered PWM Signal Generation . . . . . . . . . . . . . . . . .137
PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
10.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
10.7 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
10.8 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .140
10.9 Input/Output Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
10.10 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
10.10.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . .141
10.10.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .143
10.10.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . .144
10.10.4 TIM Channel Status and Control Registers . . . . . . . . . . . .145
10.10.5 TIM Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . .148
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MOTOROLA Timer Interface Module (TIM) 129
Timer Interface Module (TIM)
10.2 Introduction
This section describes the timer interface module (TIM). The TIM is a
two-channel timer that provides a timing reference with input capture,
output compare, and pulse-width-modulation functions. Figure 10-1 is a
block diagram of the TIM.
10.3 Features
Features of the TIM include the following:
• Two input capture/output compare channels
– Rising-edge, falling-edge, or any-edge input capture trigger
– Set, clear, or toggle output compare action
• Buffered and unbuffered pulse width modulation (PWM) signal
generation
• Programmable TIM clock input with 7-frequency internal bus clock
prescaler selection
• Free-running or modulo up-count operation
• Toggle any channel pin on overflow
• TIM counter stop and reset bits
10.4 Pin Name Conventions
The TIM shares two input/output (I/O) pins with two port A I/O pins. The
full names of the TIM I/O pins are listed in Table 10-1. The generic pin
name appear in the text that follows.
Table 10-1. Pin Name Conventions
TIM Generic Pin Names:
Full TIM Pin Names:
TCH0
TCH1
PTA0/TCH0
PTA1/TCH1
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130 Timer Interface Module (TIM) MOTOROLA
Timer Interface Module (TIM)
Functional Description
10.5 Functional Description
Figure 10-1 shows the structure of the TIM. The central component of
the TIM is the 16-bit TIM counter that can operate as a free-running
counter or a modulo up-counter. The TIM counter provides the timing
reference for the input capture and output compare functions. The TIM
counter modulo registers, TMODH:TMODL, control the modulo value of
the TIM counter. Software can read the TIM counter value at any time
without affecting the counting sequence.
The two TIM channels are programmable independently as input
capture or output compare channels.
PRESCALER SELECT
INTERNAL
BUS CLOCK
PRESCALER
TSTOP
TRST
PS2
PS1
PS0
16-BIT COUNTER
TOF
INTERRUPT
LOGIC
TOIE
16-BIT COMPARATOR
TMODH:TMODL
TOV0
ELS0B
ELS0A
PORT
LOGIC
CHANNEL 0
16-BIT COMPARATOR
TCH0H:TCH0L
CH0MAX
TCH0
CH0F
INTERRUPT
LOGIC
16-BIT LATCH
CH0IE
MS0A
MS0B
CH1F
TOV1
ELS1B
ELS1A
PORT
LOGIC
CHANNEL 1
16-BIT COMPARATOR
TCH1H:TCH1L
CH1MAX
TCH1
INTERRUPT
LOGIC
16-BIT LATCH
CH1IE
MS1A
Figure 10-1. TIM Block Diagram
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MOTOROLA Timer Interface Module (TIM) 131
Timer Interface Module (TIM)
Addr.
Register Name
Bit 7
TOF
0
6
5
4
0
3
2
1
Bit 0
Read:
Write:
Reset:
0
TIM Status and Control
Register
TOIE
TSTOP
PS2
PS1
PS0
$0020
TRST
0
(TSC)
See page 141.
0
0
1
0
0
0
0
Read: Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
TIM Counter Register High
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
(TCNTH) Write:
See page 144.
Reset:
Read:
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TIM Counter Register Low
(TCNTL) Write:
See page 144.
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
Bit 15
1
0
Bit 14
1
0
Bit 13
1
0
Bit 12
1
0
Bit 11
1
0
Bit 10
1
0
Bit 9
1
0
Bit 8
1
TIM Counter Modulo
Register High
(TMODH)
See page 144.
TIM Counter Modulo
Register Low
(TMODL)
Bit 7
1
Bit 6
1
Bit 5
1
Bit 4
1
Bit 3
1
Bit 2
1
Bit 1
1
Bit 0
1
See page 144.
Read: CH0F
TIM Channel 0 Status and
Control Register
(TSC0)
CH0IE
0
MS0B
0
MS0A
0
ELS0B ELS0A
TOV0 CH0MAX
Write:
Reset:
Read:
Write:
Reset:
Read:
Write:
Reset:
0
0
See page 145.
0
0
0
0
TIM Channel 0
Register High
(TCH0H)
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
See page 149.
Indeterminate after reset
Bit 4 Bit 3
Indeterminate after reset
TIM Channel 0
Register Low
(TCH0L)
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
See page 149.
Read: CH1F
0
0
TIM Channel 1 Status and
Control Register
(TSC1)
CH1IE
0
MS1A
0
ELS1B ELS1A
TOV1 CH1MAX
Write:
0
0
See page 145.
Reset:
0
0
0
0
= Unimplemented
Figure 10-2. TIM I/O Register Summary
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132 Timer Interface Module (TIM) MOTOROLA
Timer Interface Module (TIM)
Functional Description
Addr.
Register Name
TIM Channel 1
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
Write:
Reset:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Register High
(TCH1H)
See page 149.
$0029
Indeterminate after reset
Bit 4 Bit 3
Indeterminate after reset
TIM Channel 1
Register Low
(TCH1L)
Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 0
$002A
See page 149.
= Unimplemented
Figure 10-2. TIM I/O Register Summary (Continued)
10.5.1 TIM Counter Prescaler
The TIM clock source is one of the seven prescaler outputs. The
prescaler generates seven clock rates from the internal bus clock. The
prescaler select bits, PS[2:0], in the TIM status and control register
(TSC) select the TIM clock source.
10.5.2 Input Capture
With the input capture function, the TIM can capture the time at which an
external event occurs. When an active edge occurs on the pin of an input
capture channel, the TIM latches the contents of the TIM counter into the
TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is
programmable. Input captures can generate TIM central processor unit
(CPU) interrupt requests.
10.5.3 Output Compare
With the output compare function, the TIM can generate a periodic pulse
with a programmable polarity, duration, and frequency. When the
counter reaches the value in the registers of an output compare channel,
the TIM can set, clear, or toggle the channel pin. Output compares can
generate TIM CPU interrupt requests.
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Timer Interface Module (TIM)
133
Timer Interface Module (TIM)
10.5.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare
pulses as described in 10.5.3 Output Compare. The pulses are
unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an
output compare value could cause incorrect operation for up to two
counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new
value prevents any compare during that counter overflow period. Also,
using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass
the new value before it is written.
Use the following methods to synchronize unbuffered changes in the
output compare value on channel x:
• When changing to a smaller value, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current output compare pulse. The interrupt routine has until
the end of the counter overflow period to write the new value.
• When changing to a larger output compare value, enable TIM
overflow interrupts and write the new value in the TIM overflow
interrupt routine. The TIM overflow interrupt occurs at the end of
the current counter overflow period. Writing a larger value in an
output compare interrupt routine (at the end of the current pulse)
could cause two output compares to occur in the same counter
overflow period.
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Timer Interface Module (TIM)
MOTOROLA
Timer Interface Module (TIM)
Functional Description
10.5.3.2 Buffered Output Compare
Channels 0 and 1 can be linked to form a buffered output compare
channel whose output appears on the TCH0 pin. The TIM channel
registers of the linked pair alternately control the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The output compare value in the TIM
channel 0 registers initially controls the output on the TCH0 pin. Writing
to the TIM channel 1 registers enables the TIM channel 1 registers to
synchronously control the output after the TIM overflows. At each
subsequent overflow, the TIM channel registers (0 or 1) that control the
output are the ones written to last. TSC0 controls and monitors the
buffered output compare function, and TIM channel 1 status and control
register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin,
TCH1, is available as a general-purpose I/O pin.
NOTE: In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should
track the currently active channel to prevent writing a new value to the
active channel. Writing to the active channel registers is the same as
generating unbuffered output compares.
10.5.4 Pulse Width Modulation (PWM)
By using the toggle-on-overflow feature with an output compare channel,
the TIM can generate a PWM signal. The value in the TIM counter
modulo registers determines the period of the PWM signal. The channel
pin toggles when the counter reaches the value in the TIM counter
modulo registers. The time between overflows is the period of the PWM
signal.
As Figure 10-3 shows, the output compare value in the TIM channel
registers determines the pulse width of the PWM signal. The time
between overflow and output compare is the pulse width. Program the
TIM to clear the channel pin on output compare if the state of the PWM
pulse is logic 1. Program the TIM to set the pin if the state of the PWM
pulse is logic 0.
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MOTOROLA
Timer Interface Module (TIM)
135
Timer Interface Module (TIM)
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
PULSE
WIDTH
TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 10-3. PWM Period and Pulse Width
The value in the TIM counter modulo registers and the selected
prescaler output determines the frequency of the PWM output. The
frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM counter modulo registers produces a PWM
period of 256 times the internal bus clock period if the prescaler select
value is 000. See 10.10.1 TIM Status and Control Register.
The value in the TIM channel registers determines the pulse width of the
PWM output. The pulse width of an 8-bit PWM signal is variable in 256
increments. Writing $0080 (128) to the TIM channel registers produces
a duty cycle of 128/256 or 50%.
10.5.4.1 Unbuffered PWM Signal Generation
Any output compare channel can generate unbuffered PWM pulses as
described in 10.5.4 Pulse Width Modulation (PWM). The pulses are
unbuffered because changing the pulse width requires writing the new
pulse width value over the old value currently in the TIM channel
registers.
An unsynchronized write to the TIM channel registers to change a pulse
width value could cause incorrect operation for up to two PWM periods.
For example, writing a new value before the counter reaches the old
value but after the counter reaches the new value prevents any compare
during that PWM period. Also, using a TIM overflow interrupt routine to
write a new, smaller pulse width value may cause the compare to be
missed. The TIM may pass the new value before it is written.
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Timer Interface Module (TIM)
MOTOROLA
Timer Interface Module (TIM)
Functional Description
Use the following methods to synchronize unbuffered changes in the
PWM pulse width on channel x:
• When changing to a shorter pulse width, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the
PWM period to write the new value.
• When changing to a longer pulse width, enable TIM overflow
interrupts and write the new value in the TIM overflow interrupt
routine. The TIM overflow interrupt occurs at the end of the current
PWM period. Writing a larger value in an output compare interrupt
routine (at the end of the current pulse) could cause two output
compares to occur in the same PWM period.
NOTE: In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to
self-correct in the event of software error or noise. Toggling on output
compare also can cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
10.5.4.2 Buffered PWM Signal Generation
Channels 0 and 1 can be linked to form a buffered PWM channel whose
output appears on the TCH0 pin. The TIM channel registers of the linked
pair alternately control the pulse width of the output.
Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The TIM channel 0 registers initially
control the pulse width on the TCH0 pin. Writing to the TIM channel 1
registers enables the TIM channel 1 registers to synchronously control
the pulse width at the beginning of the next PWM period. At each
subsequent overflow, the TIM channel registers (0 or 1) that control the
pulse width are the ones written to last. TSC0 controls and monitors the
buffered PWM function, and TIM channel 1 status and control register
(TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1,
is available as a general-purpose I/O pin.
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Timer Interface Module (TIM)
137
Timer Interface Module (TIM)
NOTE: In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. User software should track the
currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as
generating unbuffered PWM signals.
10.5.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered
PWM signals, use the following initialization procedure:
1. In the TIM status and control register (TSC):
a. Stop the TIM counter by setting the TIM stop bit, TSTOP.
b. Reset the TIM counter and prescaler by setting the TIM reset
bit, TRST.
2. In the TIM counter modulo registers (TMODH:TMODL), write the
value for the required PWM period.
3. In the TIM channel x registers (TCHxH:TCHxL), write the value for
the required pulse width.
4. In TIM channel x status and control register (TSCx):
a. Write 0:1 (for unbuffered output compare or PWM signals) or
1:0 (for buffered output compare or PWM signals) to the
mode select bits, MSxB:MSxA. See Table 10-3.
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on
compare) to the edge/level select bits, ELSxB:ELSxA. The
output action on compare must force the output to the
complement of the pulse width level. See Table 10-3.
NOTE: In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to
self-correct in the event of software error or noise. Toggling on output
compare can also cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
5. In the TIM status control register (TSC), clear the TIM stop bit,
TSTOP.
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Timer Interface Module (TIM)
MOTOROLA
Timer Interface Module (TIM)
Interrupts
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially
control the buffered PWM output. TIM status control register 0 (TSCR0)
controls and monitors the PWM signal from the linked channels. MS0B
takes priority over MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM
overflows. Subsequent output compares try to force the output to a state
it is already in and have no effect. The result is a 0% duty cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the
TOVx bit generates a 100% duty cycle output. See 10.10.4 TIM Channel
Status and Control Registers.
10.6 Interrupts
The following TIM sources can generate interrupt requests:
• TIM overflow flag (TOF) — The TOF bit is set when the TIM
counter reaches the modulo value programmed in the TIM counter
modulo registers. The TIM overflow interrupt enable bit, TOIE,
enables TIM overflow CPU interrupt requests. TOF and TOIE are
in the TIM status and control register.
• TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIM CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests
are enabled when CHxIE =1. CHxF and CHxIE are in the TIM
channel x status and control register.
10.7 Wait Mode
The WAIT instruction puts the MCU in low power-consumption standby
mode.
The TIM remains active after the execution of a WAIT instruction. In wait
mode the TIM registers are not accessible by the CPU. Any enabled
CPU interrupt request from the TIM can bring the MCU out of wait mode.
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MOTOROLA Timer Interface Module (TIM) 139
Timer Interface Module (TIM)
If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.
10.8 TIM During Break Interrupts
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the break flag control register (BFCR) enables software to clear status
bits during the break state. See 7.9.2 Break Flag Control Register.
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a two-step read/write clearing procedure. If software
does the first step on such a bit before the break, the bit cannot change
during the break state as long as BCFE is at logic 0. After the break,
doing the second step clears the status bit.
10.9 Input/Output Signals
Port A shares two of its pins with the TIM. The two TIM channel I/O pins
are PTA0/TCH0 and PTA1/TCH1.
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTA0/TCH0 can be configured as
a buffered output compare or buffered PWM pin.
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Timer Interface Module (TIM)
MOTOROLA
Timer Interface Module (TIM)
Input/Output Registers
10.10 Input/Output Registers
The following I/O registers control and monitor operation of the TIM:
• TIM status and control register (TSC)
• TIM control registers (TCNTH:TCNTL)
• TIM counter modulo registers (TMODH:TMODL)
• TIM channel status and control registers (TSC0 and TSC1)
• TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)
10.10.1 TIM Status and Control Register
The TIM status and control register (TSC) does the following:
• Enables TIM overflow interrupts
• Flags TIM overflows
• Stops the TIM counter
• Resets the TIM counter
• Prescales the TIM counter clock
Address: $0020
Bit 7
TOF
0
6
TOIE
0
5
TSTOP
1
4
0
3
0
2
PS2
0
1
PS1
0
Bit 0
PS0
0
Read:
Write:
Reset:
TRST
0
0
0
= Unimplemented
Figure 10-4. TIM Status and Control Register (TSC)
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Timer Interface Module (TIM)
TOF — TIM Overflow Flag Bit
This read/write flag is set when the TIM counter reaches the modulo
value programmed in the TIM counter modulo registers. Clear TOF by
reading the TIM status and control register when TOF is set and then
writing a logic 0 to TOF. If another TIM overflow occurs before the
clearing sequence is complete, then writing logic 0 to TOF has no
effect. Therefore, a TOF interrupt request cannot be lost due to
inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic
1 to TOF has no effect.
1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value
TOIE — TIM Overflow Interrupt Enable Bit
This read/write bit enables TIM overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.
1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled
TSTOP — TIM Stop Bit
This read/write bit stops the TIM counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM
counter until software clears the TSTOP bit.
1 = TIM counter stopped
0 = TIM counter active
NOTE: Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM
prescaler. Setting TRST has no effect on any other registers.
Counting resumes from $0000. TRST is cleared automatically after
the TIM counter is reset and always reads as logic 0. Reset clears the
TRST bit.
1 = Prescaler and TIM counter cleared
0 = No effect
NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIM counter
at a value of $0000.
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Timer Interface Module (TIM)
Input/Output Registers
PS[2:0] — Prescaler Select Bits
These read/write bits select one of the seven prescaler outputs as the
input to the TIM counter as Table 10-2 shows. Reset clears the
PS[2:0] bits.
Table 10-2. Prescaler Selection
PS2
0
PS1
0
PS0
0
TIM Clock Source
Internal bus clock ÷ 1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
Not available
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
10.10.2 TIM Counter Registers
The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
TCNTH do not affect the latched TCNTL value until TCNTL is read.
Reset clears the TIM counter registers. Setting the TIM reset bit (TRST)
also clears the TIM counter registers.
NOTE: If you read TCNTH during a break interrupt, be sure to unlatch TCNTL
by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL
retains the value latched during the break.
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Timer Interface Module (TIM)
Address: $0021 TCNTH
Bit 7
6
5
4
3
2
1
Bit 0
Bit 8
Read: Bit 15
Write:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Reset:
Address: $0022
Bit 7
Bit 7
0
0
TCNTL
6
0
0
0
0
0
0
5
4
3
2
1
Bit 0
Bit 0
Read:
Write:
Reset:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0
0
0
0
0
0
0
0
= Unimplemented
Figure 10-5. TIM Counter Registers (TCNTH:TCNTL)
10.10.3 TIM Counter Modulo Registers
The read/write TIM modulo registers contain the modulo value for the
TIM counter. When the TIM counter reaches the modulo value, the
overflow flag (TOF) becomes set, and the TIM counter resumes counting
from $0000 at the next timer clock. Writing to the high byte (TMODH)
inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is
written. Reset sets the TIM counter modulo registers.
Address: $0023
Bit 7
TMODH
6
5
Bit13
1
4
Bit12
1
3
Bit11
1
2
Bit10
1
1
Bit9
1
Bit 0
Bit8
1
Read:
Bit15
Write:
Bit14
Reset:
1
1
TMODL
6
Address: $0024
Bit 7
5
Bit5
1
4
Bit4
1
3
Bit3
1
2
Bit2
1
1
Bit1
1
Bit 0
Bit0
1
Read:
Bit7
Write:
Bit6
1
Reset:
1
Figure 10-6. TIM Counter Modulo Registers (TMODH:TMODL)
NOTE: Reset the TIM counter before writing to the TIM counter modulo registers.
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Timer Interface Module (TIM)
Input/Output Registers
10.10.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers does the following:
• Flags input captures and output compares
• Enables input capture and output compare interrupts
• Selects input capture, output compare, or PWM operation
• Selects high, low, or toggling output on output compare
• Selects rising edge, falling edge, or any edge as the active input
capture trigger
• Selects output toggling on TIM overflow
• Selects 0% and 100% PWM duty cycle
• Selects buffered or unbuffered output compare/PWM operation
Address: $0025
Bit 7
TSC0
6
5
MS0B
0
4
MS0A
0
3
ELS0B
0
2
ELS0A
0
1
TOV0
0
Bit 0
CH0MAX
0
Read: CH0F
CH0IE
Write:
0
0
Reset:
0
Address: $0028
Bit 7
TSC1
6
5
0
4
MS1A
0
3
ELS1B
0
2
ELS1A
0
1
TOV1
0
Bit 0
CH1MAX
0
Read: CH1F
CH1IE
Write:
0
0
Reset:
0
0
= Unimplemented
Figure 10-7. TIM Channel Status and Control
Registers (TSC0:TSC1)
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIM
counter registers matches the value in the TIM channel x registers.
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Clear CHxF by reading the TIM channel x status and control register
with CHxF set and then writing a logic 0 to CHxF. If another interrupt
request occurs before the clearing sequence is complete, then writing
logic 0 to CHxF has no effect. Therefore, an interrupt request cannot
be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupt service requests on
channel x. Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIM channel 0 status and control register.
Setting MS0B disables the channel 1 status and control register and
reverts TCH1 to general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:A ≠ 00, this read/write bit selects either input capture
operation or unbuffered output compare/PWM operation.
See Table 10-3.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level
of the TCHx pin (see Table 10-3). Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE: Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIM status and control register
(TSC).
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Timer Interface Module (TIM)
Input/Output Registers
ELSxB and ELSxA — Edge/Level Select Bits
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to an I/O port, and pin TCHx is available as a general-purpose I/O pin.
Table 10-3 shows how ELSxB and ELSxA work. Reset clears the
ELSxB and ELSxA bits.
Table 10-3. Mode, Edge, and Level Selection
MSxB MSxA ELSxB ELSxA
Mode
Configuration
Pin under port control;
initial output level high
X
X
0
1
0
0
0
0
Output preset
Pin under port control;
initial output level low
0
0
0
0
0
1
1
0
Capture on rising edge only
Capture on falling edge only
Input capture
Capture on rising
or falling edge
0
0
1
1
0
0
0
1
1
1
1
1
0
1
1
0
1
1
1
0
1
1
0
1
Toggle output on compare
Clear output on compare
Set output on compare
Toggle output on compare
Clear output on compare
Set output on compare
Output
compare
or PWM
1
X
X
X
Buffered
output
compare or
buffered PWM
NOTE: After initially enabling a TIM channel register for input capture operation
and selecting the edge sensitivity, clear CHxF to ignore any erroneous
edge detection flags.
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Timer Interface Module (TIM)
TOVx — Toggle-On-Overflow Bit
When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIM counter
overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
NOTE: When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 1, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As
Figure 10-8 shows, the CHxMAX bit takes effect in the cycle after it
is set or cleared. The output stays at the 100% duty cycle level until
the cycle after CHxMAX is cleared.
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
OVERFLOW
PERIOD
TCHx
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
CHxMAX
Figure 10-8. CHxMAX Latency
10.10.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the
input capture function or the output compare value of the output
compare function. The state of the TIM channel registers after reset is
unknown.
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Timer Interface Module (TIM)
Input/Output Registers
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIM channel x registers (TCHxH) inhibits input captures until the low
byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of
the TIM channel x registers (TCHxH) inhibits output compares until the
low byte (TCHxL) is written.
Address: $0026
Bit 7
TCH0H
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Bit 15
Write:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Reset:
Indeterminate after reset
Address: $0027
Bit 7
TCH0L
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Bit 7
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Reset:
Indeterminate after reset
Address: $0029
Bit 7
TCH1H
6
5
4
3
2
1
Bit 0
Bit 8
Read:
Bit 15
Write:
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Reset:
Indeterminate after reset
Address: $02A
Bit 7
TCH1L
6
5
4
3
2
1
Bit 0
Bit 0
Read:
Bit 7
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Reset:
Indeterminate after reset
Figure 10-9. TIM Channel Registers (TCH0H/L:TCH1H/L)
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Timer Interface Module (TIM)
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Timer Interface Module (TIM)
MOTOROLA
Data Sheet — MC68HC908QY4
Section 11. Analog-to-Digital Converter (ADC)
11.1 Contents
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
11.4.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
11.4.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
11.4.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
11.4.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .155
11.4.5 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . .155
11.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
11.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
11.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
11.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
11.7 Input/Output Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
11.8 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
11.8.1 ADC Status and Control Register. . . . . . . . . . . . . . . . . . . .157
11.8.2 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
11.8.3 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . .159
11.2 Introduction
This section describes the analog-to-digital converter (ADC). The ADC
is an 8-bit, 4-channel analog-to-digital converter. The ADC module is
only available on the MC68HC908QY2, MC68HC908QT2,
MC68HC908QY4, and MC68HC908QT4.
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Analog-to-Digital Converter (ADC)
11.3 Features
Features of the ADC module include:
• 4 channels with multiplexed input
• Linear successive approximation with monotonicity
• 8-bit resolution
• Single or continuous conversion
• Conversion complete flag or conversion complete interrupt
• Selectable ADC clock
Figure 11-1 provides a summary of the input/output (I/O) registers.
Addr.
$003C
$003D
Register Name
Bit 7
Read: COCO
Write:
6
AIEN
0
5
ADCO
0
4
CH4
1
3
CH3
1
2
CH2
1
1
CH1
1
Bit 0
CH0
1
ADC Status and Control
Register
(ADSCR)
See page 157.
Reset:
0
Unimplemented
Read:
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
ADC Data Register
$003E
$003F
(ADR) Write:
See page 159.
Reset:
Read:
Indeterminate after reset
0
0
0
0
0
0
0
0
ADC Input Clock Register
ADIV2
0
ADIV1
0
ADIV0
0
(ADICLK) Write:
See page 159.
Reset:
0
0
= Unimplemented
Figure 11-1. ADC I/O Register Summary
11.4 Functional Description
Four ADC channels are available for sampling external sources at pins
PTA0, PTA1, PTA4, and PTA5. An analog multiplexer allows the single
ADC converter to select one of the four ADC channels as an ADC
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Analog-to-Digital Converter (ADC)
Functional Description
voltage input (ADCVIN). ADCVIN is converted by the successive
approximation register-based counters. The ADC resolution is eight bits.
When the conversion is completed, ADC puts the result in the ADC data
register and sets a flag or generates an interrupt.
Figure 11-2 shows a block diagram of the ADC.
INTERNAL
DATA BUS
READ DDRA
WRITE DDRA
DISABLE
DDRAx
RESET
WRITE PTA
READ PTA
ADCx
PTAx
DISABLE
ADC CHANNEL x
ADC DATA REGISTER
ADC VOLTAGE IN
ADCVIN
CONVERSION
COMPLETE
CHANNEL
SELECT
(1 OF 4 CHANNELS)
INTERRUPT
LOGIC
CH[4:0]
ADC
ADC CLOCK
AIEN
COCO
CLOCK
GENERATOR
BUS CLOCK
ADIV[2:0]
Figure 11-2. ADC Block Diagram
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Analog-to-Digital Converter (ADC)
11.4.1 ADC Port I/O Pins
PTA0, PTA1, PTA4, and PTA5 are general-purpose I/O pins that are
shared with the ADC channels. The channel select bits (ADC status and
control register (ADSCR), $003C), define which ADC channel/port pin
will be used as the input signal. The ADC overrides the port I/O logic by
forcing that pin as input to the ADC. The remaining ADC channels/port
pins are controlled by the port I/O logic and can be used as
general-purpose I/O. Writes to the port register or data direction register
(DDR) will not have any affect on the port pin that is selected by the ADC.
Read of a port pin which is in use by the ADC will return a logic 0 if the
corresponding DDR bit is at logic 0. If the DDR bit is at logic 1, the value
in the port data latch is read.
11.4.2 Voltage Conversion
When the input voltage to the ADC equals VDD, the ADC converts the
signal to $FF (full scale). If the input voltage equals VSS, the ADC
converts it to $00. Input voltages between VDD and VSS are a
straight-line linear conversion. All other input voltages will result in $FF
if greater than VDD and $00 if less than VSS.
NOTE: Input voltage should not exceed the analog supply voltages.
11.4.3 Conversion Time
Sixteen ADC internal clocks are required to perform one conversion. The
ADC starts a conversion on the first rising edge of the ADC internal clock
immediately following a write to the ADSCR. If the ADC internal clock is
selected to run at 1 MHz, then one conversion will take 16 µs to
complete. With a 1-MHz ADC internal clock the maximum sample rate
is 62.5 kHz.
16 ADC Clock Cycles
Conversion Time =
ADC Clock Frequency
Number of Bus Cycles = Conversion Time × Bus Frequency
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Analog-to-Digital Converter (ADC)
Interrupts
11.4.4 Continuous Conversion
In the continuous conversion mode, the ADC continuously converts the
selected channel filling the ADC data register (ADR) with new data after
each conversion. Data from the previous conversion will be overwritten
whether that data has been read or not. Conversions will continue until
the ADCO bit is cleared. The COCO bit (ADSCR, $003C) is set after
each conversion and can be cleared by writing the ADC status and
control register or reading of the ADC data register.
11.4.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes.
11.5 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a
central processor unit (CPU) interrupt after each ADC conversion. A
CPU interrupt is generated if the COCO bit is at logic 0. The COCO bit
is not used as a conversion complete flag when interrupts are enabled.
11.6 Low-Power Modes
The following subsections describe the ADC in low-power modes.
11.6.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled
CPU interrupt request from the ADC can bring the microcontroller unit
(MCU) out of wait mode. If the ADC is not required to bring the MCU out
of wait mode, power down the ADC by setting the CH[4:0] bits in ADSCR
to logic 1’s before executing the WAIT instruction.
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11.6.2 Stop Mode
The ADC module is inactive after the execution of a STOP instruction.
Any pending conversion is aborted. ADC conversions resume when the
MCU exits stop mode. Allow one conversion cycle to stabilize the analog
circuitry before attempting a new ADC conversion after exiting stop
mode.
11.7 Input/Output Signals
The ADC module has four channels that are shared with I/O port A.
ADC voltage in (ADCVIN) is the input voltage signal from one of the four
ADC channels to the ADC module.
11.8 Input/Output Registers
These I/O registers control and monitor ADC operation:
• ADC status and control register (ADSCR)
• ADC data register (ADR)
• ADC clock register (ADICLK)
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Analog-to-Digital Converter (ADC)
Input/Output Registers
11.8.1 ADC Status and Control Register
The following paragraphs describe the function of the ADC status and
control register (ADSCR).
Address: $003C
Bit 7
Read: COCO
Write:
6
AIEN
0
5
ADCO
0
4
CH4
1
3
CH3
1
2
CH2
1
1
CH1
1
Bit 0
CH0
1
Reset:
0
= Unimplemented
Figure 11-3. ADC Status and Control Register (ADSCR)
COCO — Conversions Complete Bit
When the AIEN bit is a logic 0, the COCO is a read-only bit which is
set each time a conversion is completed. This bit is cleared whenever
ADSCR is written or whenever the ADR is read. Reset clears this bit.
1 = Conversion completed (AIEN = 0)
0 = Conversion not completed (AIEN = 0)
When the AIEN bit is a logic 1 (CPU interrupt enabled), the COCO is
a read-only bit, and will always be logic 0 when read.
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC
conversion. The interrupt signal is cleared when ADR is read or
ADSCR is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled
0 = ADC interrupt disabled
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update
ADR at the end of each conversion. Only one conversion is allowed
when this bit is cleared. Reset clears the ADCO bit.
1 = Continuous ADC conversion
0 = One ADC conversion
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CH[4:0] — ADC Channel Select Bits
CH4, CH3, CH2, CH1, and CH0 form a 5-bit field which is used to
select one of the four ADC channels. The five select bits are detailed
in Table 11-1. Care should be taken when using a port pin as both an
analog and a digital input simultaneously to prevent switching noise
from corrupting the analog signal.
The ADC subsystem is turned off when the channel select bits are all
set to 1. This feature allows for reduced power consumption for the
MCU when the ADC is not used. Reset sets all of these bits to a
logic 1.
NOTE: Recovery from the disabled state requires one conversion cycle to
stabilize.
Table 11-1. MUX Channel Select
ADC
CH4
CH3
CH2
CH1
CH0
Input Select
Channel
ADC0
ADC1
ADC2
ADC3
—
0
0
0
0
0
↓
0
0
0
0
0
↓
0
0
0
0
1
↓
0
0
1
1
0
↓
0
1
0
1
0
↓
PTA0
PTA1
PTA4
PTA5
(1)
—
Unused
1
1
1
1
1
1
0
0
1
1
1
0
0
1
0
—
—
Reserved
Unused
(2)
—
1
1
1
0
1
—
V
DDA
(2)
1
1
1
1
1
1
1
1
0
1
—
—
V
SSA
ADC power off
1. If any unused channels are selected, the resulting ADC conversion will be unknown.
2. The voltage levels supplied from internal reference nodes, as specified in the table, are used
to verify the operation of the ADC converter both in production test and for user applications.
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MOTOROLA
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Input/Output Registers
11.8.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time
an ADC conversion completes.
Address: $003E
Bit 7
AD7
6
5
4
3
2
1
Bit 0
AD0
Read:
Write:
Reset:
AD6
AD5
AD4
AD3
AD2
AD1
Indeterminate after reset
= Unimplemented
Figure 11-4. ADC Data Register (ADR)
11.8.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
Address: $003F
Bit 7
ADIV2
0
6
ADIV1
0
5
ADIV0
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
0
0
0
0
0
= Unimplemented
Figure 11-5. ADC Input Clock Register (ADICLK)
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide
ratio used by the ADC to generate the internal ADC clock. Table 11-2
shows the available clock configurations. The ADC clock should be
set to approximately 1 MHz.
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Analog-to-Digital Converter (ADC)
Table 11-2. ADC Clock Divide Ratio
ADIV2
ADIV1
ADIV0
ADC Clock Rate
0
0
0
1
1
X
0
1
0
1
X
Bus clock ÷ 1
Bus clock ÷ 2
Bus clock ÷ 4
Bus clock ÷ 8
Bus clock ÷ 16
0
0
0
1
X = don’t care
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160 Analog-to-Digital Converter (ADC) MOTOROLA
Data Sheet — MC68HC908QY4
Section 12. Input/Output (I/O) Ports
12.1 Contents
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
12.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
12.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
12.3.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . .164
12.3.3 Port A Input Pullup Enable Register. . . . . . . . . . . . . . . . . .166
12.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
12.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167
12.4.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . .168
12.4.3 Port B Input Pullup Enable Register. . . . . . . . . . . . . . . . . .169
12.2 Introduction
The MC68HC908QT1, MC68HC908QT2, and MC68HC908QT4 have
five bidirectional input-output (I/O) pins and one input only pin. The
MC68HC908QY1, MC68HC908QY2, and MC68HC908QY4 have
thirteen bidirectional pins and one input only pin. All I/O pins are
programmable as inputs or outputs.
NOTE: Connect any unused I/O pins to an appropriate logic level, either VDD or
VSS. Although the I/O ports do not require termination for proper
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
Figure 12-1 provides a summary of the I/O registers.
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Input/Output (I/O) Ports
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
AWUL
PTA2
Port A Data Register
PTA5
PTA4
PTA3
PTA1
PTA0
$0000
(PTA) Write:
See page 163.
Reset:
Read:
Unaffected by reset
PTB4 PTB3
Unaffected by reset
Port B Data Register
PTB7
0
PTB6
0
PTB5
PTB2
0
PTB1
PTB0
$0001
$0004
$0005
$000B
$000C
(PTB) Write:
See page 167.
Reset:
Read:
Data Direction Register A
DDRA5
DDRA4
DDRA3
DDRA1
DDRA0
(DDRA) Write:
See page 164.
Reset:
Read:
0
0
DDRB6
0
0
DDRB5
0
0
DDRB4
0
0
DDRB3
0
0
DDRB2
0
0
DDRB1
0
0
DDRB0
0
Data Direction Register B
DDRB7
(DDRB) Write:
See page 168.
Reset:
0
OSC2EN
0
Port A Input Pullup Read:
Enable Register
PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
Write:
(PTAPUE)
See page 166. Reset:
0
0
0
0
0
0
0
Port B Input Pullup Read:
Enable Register
PTBPUE7 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3 PTBPUE2 PTBPUE1 PTBPUE0
Write:
(PTBPUE)
See page 169. Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-1. I/O Port Register Summary
12.3 Port A
Port A is an 6-bit special function port that shares all six of its pins with
the keyboard interrupt (KBI) module (see Section 14. Keyboard
Interrupt Module (KBI)). Each port A pin also has a software
configurable pullup device if the corresponding port pin is configured as
an input port.
NOTE: PTA2 is input only.
When the IRQ function is enabled in the configuration register 2
(CONFIG2), bit 2 of the port A data register (PTA) will always read a
logic 0. In this case, the BIH and BIL instructions can be used to read the
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162 Input/Output (I/O) Ports MOTOROLA
Input/Output (I/O) Ports
Port A
logic level on the PTA2 pin. When the IRQ function is disabled, these
instructions will behave as if the PTA2 pin is a logic 1. However, reading
bit 2 of PTA will read the actual logic level on the pin.
12.3.1 Port A Data Register
The port A data register (PTA) contains a data latch for each of the six
port A pins.
Address: $0000
Bit 7
0
6
5
4
3
2
1
Bit 0
Read:
Write:
AWUL
PTA2
PTA5
PTA4
PTA3
PTA1
PTA0
Reset:
Unaffected by reset
KBI4 KBI3
Additional Functions:
KBI5
KBI2
KBI1
KBI0
= Unimplemented
Figure 12-2. Port A Data Register (PTA)
PTA[5:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of
each port A pin is under the control of the corresponding bit in data
direction register A. Reset has no effect on port A data.
AWUL — Auto Wake-up Latch Data Bit
This is a read-only bit which has the value of the auto wake-up
interrupt request latch. The wake-up request signal is generated
internally (see 14.4.4 Auto Wake-up Interrupt Request). There is no
PTA6 port nor any of the associated bits such as PTA6 data register,
pullup enable or direction.
KBI[5:0] — Port A Keyboard Interrupts
The keyboard interrupt enable bits, KBIE5–KBIE0, in the keyboard
interrupt control enable register (KBIER) enable the port A pins as
external interrupt pins (see Section 14. Keyboard Interrupt Module
(KBI)).
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Input/Output (I/O) Ports
12.3.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is
an input or an output. Writing a logic 1 to a DDRA bit enables the output
buffer for the corresponding port A pin; a logic 0 disables the output
buffer.
Address: $0004
Bit 7
0
6
0
5
DDRA5
0
4
DDRA4
0
3
DDRA3
0
2
0
1
DDRA1
0
Bit 0
DDRA0
0
Read:
Write:
Reset:
0
0
0
= Unimplemented
Figure 12-3. Data Direction Register A (DDRA)
DDRA[5:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[5:0], configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
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MOTOROLA
Input/Output (I/O) Ports
Port A
Figure 12-4 shows the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004)
PTAPUEx
DDRAx
RESET
30 k
WRITE PTA ($0000)
PTAx
PTAx
READ PTA ($0000)
TO KEYBOARD INTERRUPT CIRCUIT
Figure 12-4. Port A I/O Circuit
NOTE: Figure 12-4 does not apply to PTA2
When DDRAx is a logic 1, reading address $0000 reads the PTAx data
latch. When DDRAx is a logic 0, reading address $0000 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit.
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Input/Output (I/O) Ports
12.3.3 Port A Input Pullup Enable Register
The port A input pullup enable register (PTAPUE) contains a software
configurable pullup device for each if the six port A pins. Each bit is
individually configurable and requires the corresponding data direction
register, DDRAx, to be configured as input. Each pullup device is
automatically and dynamically disabled when its corresponding DDRAx
bit is configured as output.
Address: $000B
Bit 7
OSC2EN
0
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE2 PTAPUE0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-5. Port A Input Pullup Enable Register (PTAPUE)
OSC2EN — Enable PTA4 on OSC2 Pin
This read/write bit configures the OSC2 pin function when internal
oscillator or RC oscillator option is selected. This bit has no effect for
the XTAL or external oscillator options.
1 = OSC2 pin outputs the internal or RC oscillator clock
(BUSCLKX4)
0 = OSC2 pin configured for PTA4 I/O, having all the interrupt and
pullup functions
PTAPUE[5:0] — Port A Input Pullup Enable Bits
These read/write bits are software programmable to enable pullup
devices on port A pins.
1 = Corresponding port A pin configured to have internal pull if its
DDRA bit is set to 0
0 = Pullup device is disconnected on the corresponding port A pin
regardless of the state of its DDRA bit
Table 12-1 summarizes the operation of the port A pins.
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MOTOROLA
Input/Output (I/O) Ports
Port B
Table 12-1. Port A Pin Functions
Accesses to DDRA
I/O Pin
Accesses to PTA
PTAPUE
Bit
DDRA
Bit
PTA
Bit
Mode
Read/Write
Read
Write
(2)
(1)
(3)
(3)
(5)
1
0
X
0
0
1
DDRA5–DDRA0
DDRA5–DDRA0
DDRA5–DDRA0
Pin
Pin
Input, V
X
PTA5–PTA0
PTA5–PTA0
PTA5–PTA0
DD
(4)
X
X
Input, Hi-Z
Output
PTA5–PTA0
1. X = don’t care
2. I/O pin pulled to V by internal pullup.
DD
3. Writing affects data register, but does not affect input.
4. Hi-Z = high impedance
5. Output does not apply to PTA2
12.4 Port B
Port B is an 8-bit general purpose I/O port. Port B is only available on the
MC68HC908QY1, MC68HC908QY2, and MC68HC908QY4.
12.4.1 Port B Data Register
The port B data register (PTB) contains a data latch for each of the eight
port B pins.
Address: $0001
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
Unaffected by reset
Figure 12-6. Port B Data Register (PTB)
PTB[7:0] — Port B Data Bits
These read/write bits are software programmable. Data direction of
each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.
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Input/Output (I/O) Ports
12.4.2 Data Direction Register B
Data direction register B (DDRB) determines whether each port B pin is
an input or an output. Writing a logic 1 to a DDRB bit enables the output
buffer for the corresponding port B pin; a logic 0 disables the output
buffer.
Address: $0005
Bit 7
DDRB7
0
6
DDRB6
0
5
DDRB5
0
4
DDRB4
0
3
2
1
DDRB1
0
Bit 0
DDRB0
0
Read:
Write:
Reset:
DDRB3 DDRB2
0
0
Figure 12-7. Data Direction Register B (DDRB)
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[7:0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE: Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1. Figure 12-8 shows
the port B I/O logic.
READ DDRB ($0005)
PTBPUEx
WRITE DDRB ($0005)
DDRBx
RESET
30 k
WRITE PTB ($0001)
PTBx
PTBx
READ PTB ($0001)
Figure 12-8. Port B I/O Circuit
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168 Input/Output (I/O) Ports MOTOROLA
Input/Output (I/O) Ports
Port B
When DDRBx is a logic 1, reading address $0001 reads the PTBx data
latch. When DDRBx is a logic 0, reading address $0001 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 12-2 summarizes the operation
of the port B pins.
Table 12-2. Port B Pin Functions
Accesses to DDRB
Read/Write
Accesses to PTB
DDRB PTB
I/O Pin
Mode
Bit
Bit
Read
Write
(1)
(2)
(3)
0
1
DDRB7–DDRB0
DDRB7–DDRB0
Pin
Pin
X
Input, Hi-Z
Output
PTB7–PTB0
X
PTB7–PTB0
1. X = don’t care
2. Hi-Z = high impedance
3. Writing affects data register, but does not affect the input.
12.4.3 Port B Input Pullup Enable Register
The port B input pullup enable register (PTBPUE) contains a software
configurable pullup device for each of the eight port B pins. Each bit is
individually configurable and requires the corresponding data direction
register, DDRBx, be configured as input. Each pullup device is
automatically and dynamically disabled when its corresponding DDRBx
bit is configured as output.
Address: $000C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
PTBPUE7 PTBPUE6 PTBPUE5 PTBPUE4 PTBPUE3 PTBPUE2 PTBPUE2 PTBPUE0
0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-9. Port B Input Pullup Enable Register (PTBPUE)
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MOTOROLA Input/Output (I/O) Ports 169
Input/Output (I/O) Ports
PTBPUE[7:0] — Port B Input Pullup Enable Bits
These read/write bits are software programmable to enable pullup
devices on port B pins
1 = Corresponding port B pin configured to have internal pull if its
DDRB bit is set to 0
0 = Pullup device is disconnected on the corresponding port B pin
regardless of the state of its DDRB bit.
Table 12-3 summarizes the operation of the port B pins.
Table 12-3. Port B Pin Functions
Accesses to DDRB
Read/Write
Accesses to PTB
PTBPUE
Bit
DDRB
Bit
PTB
Bit
I/O Pin
Mode
Read
Write
(2)
(4)
(1)
(3)
(3)
1
0
DDRB7–DDRB0
Pin
Input, V
X
PTB7–PTB0
PTB7–PTB0
DD
0
0
1
X
X
DDRB7–DDRB0
DDRB7–DDRB0
Pin
Input, Hi-Z
Output
X
PTB7–PTB0
PTB7–PTB0
1. X = don’t care
2. I/O pin pulled to V by internal pullup.
DD
3. Writing affects data register, but does not affect input.
4. Hi-Z = high impedance
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Data Sheet — MC68HC908QY4
Section 13. External Interrupt (IRQ)
13.1 Contents
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
13.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
13.5 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174
13.6 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .175
13.7 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .175
13.2 Introduction
13.3 Features
The IRQ pin (external interrupt), shared with PTA2 (general purpose
input) and keyboard interrupt (KBI), provides a maskable interrupt input.
Features of the IRQ module include the following:
• External interrupt pin, IRQ
• IRQ interrupt control bits
• Hysteresis buffer
• Programmable edge-only or edge and level interrupt sensitivity
• Automatic interrupt acknowledge
• Selectable internal pullup resistor
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MOTOROLA External Interrupt (IRQ) 171
External Interrupt (IRQ)
13.4 Functional Description
IRQ pin functionality is enabled by setting configuration register 2
(CONFIG2) IRQEN bit accordingly. A 0 disables the IRQ function and
IRQ will assume the other shared functionalities. A1 enables the IRQ
function.
A logic 0 applied to the external interrupt pin can latch a central
processur unit (CPU) interrupt request. Figure 13-1 shows the structure
of the IRQ module.
Interrupt signals on the IRQ pin are latched into the IRQ latch. An
interrupt latch remains set until one of the following actions occurs:
• Vector fetch — A vector fetch automatically generates an interrupt
acknowledge signal that clears the IRQ latch.
• Software clear — Software can clear the interrupt latch by writing
to the acknowledge bit in the interrupt status and control register
(ISCR). Writing a logic 1 to the ACK1 bit clears the IRQ latch.
• Reset — A reset automatically clears the interrupt latch.
ACK1
RESET
TO CPU FOR
BIL/BIH
INSTRUCTIONS
VECTOR
FETCH
DECODER
V
DD
IRQPUD
INTERNAL
PULLUP
DEVICE
V
DD
IRQF1
CLR
D
Q
SYNCHRO-
NIZER
IRQ
INTERRUPT
REQUEST
CK
IRQ
IRQ
FF
IMASK1
MODE1
HIGH
VOLTAGE
DETECT
TO MODE
SELECT
LOGIC
Figure 13-1. IRQ Module Block Diagram
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172 External Interrupt (IRQ) MOTOROLA
External Interrupt (IRQ)
Functional Description
The external interrupt pin is falling-edge-triggered and is software-
configurable to be either falling-edge or falling-edge and low-level
triggered. The MODE1 bit in the ISCR controls the triggering sensitivity
of the IRQ pin.
When the interrupt pin is edge-triggered only, the CPU interrupt request
remains set until a vector fetch, software clear, or reset occurs.
When the interrupt pin is both falling-edge and low-level triggered, the
CPU interrupt request remains set until both of the following occur:
• Vector fetch or software clear
• Return of the interrupt pin to logic 1
The vector fetch or software clear may occur before or after the interrupt
pin returns to logic 1. As long as the pin is low, the interrupt request
remains pending. A reset will clear the latch and the MODE1 control bit,
thereby clearing the interrupt even if the pin stays low.
When set, the IMASK1 bit in the ISCR mask all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the IMASK1 bit is clear.
NOTE: The interrupt mask (I) in the condition code register (CCR) masks
all interrupt requests, including external interrupt requests.
See 7.7 Exception Control.
Figure 13-2 provides a summary of the IRQ I/O register.
Addr.
Register Name
Bit 7
6
5
4
3
2
0
1
Bit 0
Read:
Write:
Reset:
0
0
0
0
IRQF1
IRQ Status and Control
Register
IMASK1 MODE1
$001D
ACK1
0
(INTSCR)
See page 176.
0
0
0
0
0
0
0
= Unimplemented
Figure 13-2. IRQ I/O Register Summary
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MOTOROLA External Interrupt (IRQ) 173
External Interrupt (IRQ)
13.5 IRQ Pin
A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch.
A vector fetch, software clear, or reset clears the IRQ latch.
If the MODE1 bit is set, the IRQ pin is both falling-edge sensitive and
low-level sensitive. With MODE1 set, both of the following actions must
occur to clear IRQ:
• Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic 1 to
the ACK1 bit in the interrupt status and control register (ISCR).
The ACK1 bit is useful in applications that poll the IRQ pin and
require software to clear the IRQ latch. Writing to the ACK1 bit
prior to leaving an interrupt service routine can also prevent
spurious interrupts due to noise. Setting ACK1 does not affect
subsequent transitions on the IRQ pin. A falling edge that occurs
after writing to the ACK1 bit latches another interrupt request. If
the IRQ mask bit, IMASK1, is clear, the CPU loads the program
counter with the vector address at locations $FFFA and $FFFB.
• Return of the IRQ pin to logic 1 — As long as the IRQ pin is at logic
0, IRQ remains active.
The vector fetch or software clear and the return of the IRQ pin to logic 1
may occur in any order. The interrupt request remains pending as long
as the IRQ pin is at logic 0. A reset will clear the latch and the MODE1
control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE1 bit is clear, the IRQ pin is falling-edge sensitive only. With
MODE1 clear, a vector fetch or software clear immediately clears the
IRQ latch.
The IRQF1 bit in the ISCR register can be used to check for pending
interrupts. The IRQF1 bit is not affected by the IMASK1 bit, which makes
it useful in applications where polling is preferred.
NOTE: When the IRQ function is enabled in the CONFIG2 register, the BIH and
BIL instructions can be used to read the logic level on the IRQ pin. If the
IRQ function is disabled, these instructions will behave as if the IRQ pin
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External Interrupt (IRQ)
MOTOROLA
External Interrupt (IRQ)
IRQ Module During Break Interrupts
is a logic 1, regardless of the actual level on the pin. Conversely, when
the IRQ function is enabled, bit 2 of the port A data register will always
read a logic 0.
NOTE: When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.
An internal pullup resistor to VDD is connected to the IRQ pin; this can
be disabled by setting the IRQPUD bit in the CONFIG2 register ($001E).
13.6 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ latch can
be cleared during the break state. The BCFE bit in the break flag control
register (BFCR) enables software to clear the latches during the break
state. See Section 7. System Integration Module (SIM).
To allow software to clear the IRQ latch during a break interrupt, write a
logic 1 to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect the latches during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the ACK1 bit in the
IRQ status and control register during the break state has no effect on
the IRQ latch.
13.7 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors
operation of the IRQ module, see Section 5. Configuration Register
(CONFIG).
The ISCR has the following functions:
• Shows the state of the IRQ flag
• Clears the IRQ latch
• Masks IRQ and interrupt request
• Controls triggering sensitivity of the IRQ interrupt pin
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External Interrupt (IRQ)
Address: $001D
Bit 7
0
6
0
5
0
4
0
3
2
1
Bit 0
Read:
Write:
Reset:
IRQF1
IMASK1 MODE1
ACK1
0
0
0
0
0
0
0
0
= Unimplemented
Figure 13-3. IRQ Status and Control Register (INTSCR)
IRQF1 — IRQ Flag
This read-only status bit is high when the IRQ interrupt is pending.
1 = IRQ interrupt pending
0 = IRQ interrupt not pending
ACK1 — IRQ Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ latch. ACK1
always reads as logic 0. Reset clears ACK1.
IMASK1 — IRQ Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ interrupt requests.
Reset clears IMASK1.
1 = IRQ interrupt requests disabled
0 = IRQ interrupt requests enabled
MODE1 — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ pin.
Reset clears MODE1.
1 = IRQ interrupt requests on falling edges and low levels
0 = IRQ interrupt requests on falling edges only
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Data Sheet — MC68HC908QY4
Section 14. Keyboard Interrupt Module (KBI)
14.1 Contents
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177
14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179
14.4.1 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
14.4.2 Keyboard Status and Control Register. . . . . . . . . . . . . . . .182
14.4.3 Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . .184
14.4.4 Auto Wake-up Interrupt Request . . . . . . . . . . . . . . . . . . . .185
14.5 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
14.6 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
14.7 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .187
14.2 Introduction
The keyboard interrupt module (KBI) provides six independently
maskable external interrupts, which are accessible via the PTA0–PTA5
pins, plus one internal maskable interrupt controlled by the auto wake-up
logic.
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Keyboard Interrupt Module (KBI)
14.3 Features
Features of the keyboard interrupt module include:
• Six keyboard interrupt pins with separate keyboard interrupt
enable bits and one keyboard interrupt mask
• One internal interrupt controlled by the auto wake-up logic, with
separate interrupt enable bit, sharing the same keyboard interrupt
mask
• Software configurable pullup device if input pin is configured as
input port bit
• Programmable edge-only or edge and level interrupt sensitivity
• Exit from low-power modes
Figure 14-1 provides a summary of the input/output (I/O) registers
Addr.
Register Name
Keyboard Status
and Control Register
(KBSCR)
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Read:
0
0
0
0
KEYF
0
ACKK
0
IMASKK MODEK
$001A
See page 183.
0
0
0
AWUIE
0
0
KBIE5
0
0
KBIE4
0
0
KBIE3
0
0
KBIE1
0
0
KBIE0
0
Keyboard Interrupt Enable
KBIE2
0
$001B
Register (KBIER) Write:
See page 184.
Reset:
0
= Unimplemented
Figure 14-1. KBI I/O Register Summary
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Keyboard Interrupt Module (KBI)
Functional Description
14.4 Functional Description
INTERNAL BUS
VECTOR FETCH
DECODER
ACKK
KBI0
VDD
RESET
KEYF
CLR
.
D
Q
SYNCHRONIZER
KBIE0
.
CK
TO PULLUP ENABLE
.
KEYBOARD
INTERRUPT
REQUEST
IMASKK
KBI5
KEYBOARD
INTERRUPT FF
MODEK
KBIE5
TO PULLUP ENABLE
(1)
AWUIREQ
1. For AWUGEN logic refer to Figure 14-5.
Figure 14-2. Keyboard Interrupt Block Diagram
Writing to the KBIE0–KBIE5 bits in the keyboard interrupt enable register
(KBIER) independently enables or disables each port A pin as a
keyboard interrupt pin. Enabling a keyboard interrupt pin in port A also
enables its internal pullup device irrespective of PTAPUEx bits in the
port A input pullup enable register (see 12.3.3 Port A Input Pullup
Enable Register). A logic 0 applied to an enabled keyboard interrupt pin
latches a keyboard interrupt request.
Writing the AWUIE bit in the keyboard interrupt enable register enables
or disables the auto wake-up interrupt input (see Figure 14-5). A logic 1
applied to the AWUIREQ input with auto wake-up interrupt request
enabled, latches a keyboard interrupt request.
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Keyboard Interrupt Module (KBI)
A keyboard interrupt is latched when one or more keyboard interrupt
inputs goes low after all were high. The MODEK bit in the keyboard
status and control register controls the triggering mode of the keyboard
interrupt.
• If the keyboard interrupt is edge-sensitive only, a falling edge on a
keyboard interrupt input does not latch an interrupt request if
another keyboard pin is already low. To prevent losing an interrupt
request on one input because another input is still low, software
can disable the latter input while it is low.
• If the keyboard interrupt is falling edge and low-level sensitive, an
interrupt request is present as long as any keyboard interrupt input
is low.
If the MODEK bit is set, the keyboard interrupt inputs are both falling
edge and low-level sensitive, and both of the following actions must
occur to clear a keyboard interrupt request:
• Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the interrupt request.
Software may generate the interrupt acknowledge signal by
writing a logic 1 to the ACKK bit in the keyboard status and control
register (KBSCR). The ACKK bit is useful in applications that poll
the keyboard interrupt inputs and require software to clear the
keyboard interrupt request. Writing to the ACKK bit prior to leaving
an interrupt service routine can also prevent spurious interrupts
due to noise. Setting ACKK does not affect subsequent transitions
on the keyboard interrupt inputs. A falling edge that occurs after
writing to the ACKK bit latches another interrupt request. If the
keyboard interrupt mask bit, IMASKK, is clear, the central
processor unit (CPU) loads the program counter with the vector
address at locations $FFE0 and $FFE1.
• Return of all enabled keyboard interrupt inputs to logic 1 — As
long as any enabled keyboard interrupt pin is at logic 0, the
keyboard interrupt remains set. The auto wake-up interrupt input,
AWUIREQ, will be cleared only by writing to ACKK bit in KBSCR
or reset.
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Keyboard Interrupt Module (KBI)
Functional Description
The vector fetch or software clear and the return of all enabled keyboard
interrupt pins to logic 1 may occur in any order.
If the MODEK bit is clear, the keyboard interrupt pin is falling-edge
sensitive only. With MODEK clear, a vector fetch or software clear
immediately clears the keyboard interrupt request.
Reset clears the keyboard interrupt request and the MODEK bit, clearing
the interrupt request even if a keyboard interrupt input stays at logic 0.
The keyboard flag bit (KEYF) in the keyboard status and control register
can be used to see if a pending interrupt exists. The KEYF bit is not
affected by the keyboard interrupt mask bit (IMASKK) which makes it
useful in applications where polling is preferred.
To determine the logic level on a keyboard interrupt pin, use the data
direction register to configure the pin as an input and then read the data
register.
NOTE: Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction
register. However, the data direction register bit must be a logic 0 for
software to read the pin.
Auto wake-up latch, AWUL, can be read directly from the bit 6 position
of port A data register (PTA). This is a read-only bit which is occupying
and empty bit position on PTA. No PTA associated registers, such as
PTA6 data, PTA6 direction, and PTA6 pullup exist for this bit.
14.4.1 Keyboard Initialization
When a keyboard interrupt pin is enabled, it takes time for the internal
pullup to reach a logic 1. Therefore a false interrupt can occur as soon
as the pin is enabled. This does not apply to an auto wake-up interrupt,
which is internally generated without pullup.
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Keyboard Interrupt Module (KBI)
To prevent a false interrupt on keyboard initialization:
1. Mask keyboard interrupts by setting the IMASKK bit in the
keyboard status and control register.
2. Enable the KBI pins by setting the appropriate KBIEx bits in the
keyboard interrupt enable register.
3. Write to the ACKK bit in the keyboard status and control register
to clear any false interrupts.
4. Clear the IMASKK bit.
An interrupt signal on an edge-triggered pin can be acknowledged
immediately after enabling the pin. An interrupt signal on an edge- and
level-triggered interrupt pin must be acknowledged after a delay that
depends on the external load.
Another way to avoid a false interrupt:
1. Configure the keyboard pins as outputs by setting the appropriate
DDRA bits in the data direction register A.
2. Write logic 1s to the appropriate port A data register bits.
3. Enable the KBI pins by setting the appropriate KBIEx bits in the
keyboard interrupt enable register.
14.4.2 Keyboard Status and Control Register
The keyboard status and control register (KBSCR):
• Flags keyboard interrupt requests
• Acknowledges keyboard interrupt requests
• Masks keyboard interrupt requests
• Controls keyboard interrupt triggering sensitivity
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Keyboard Interrupt Module (KBI)
MOTOROLA
Keyboard Interrupt Module (KBI)
Functional Description
Address: $001A
Bit 7
6
0
5
0
4
0
3
2
1
Bit 0
Read:
Write:
Reset:
0
KEYF
0
ACKK
0
IMASKK MODEK
0
0
0
0
0
0
0
= Unimplemented
Figure 14-3. Keyboard Status and Control Register (KBSCR)
Bits 7–4 — Not used
These read-only bits always read as logic 0s.
KEYF — Keyboard Flag Bit
This read-only bit is set when a keyboard interrupt is pending on
port A or auto wake-up. Reset clears the KEYF bit.
1 = Keyboard interrupt pending
0 = No keyboard interrupt pending
ACKK — Keyboard Acknowledge Bit
Writing a logic 1 to this write-only bit clears the keyboard interrupt
request on port A and auto wake-up logic. ACKK always reads as
logic 0. Reset clears ACKK.
IMASKK— Keyboard Interrupt Mask Bit
Writing a logic 1 to this read/write bit prevents the output of the
keyboard interrupt mask from generating interrupt requests on port A
or auto wake-up. Reset clears the IMASKK bit.
1 = Keyboard interrupt requests masked
0 = Keyboard interrupt requests not masked
MODEK — Keyboard Triggering Sensitivity Bit
This read/write bit controls the triggering sensitivity of the keyboard
interrupt pins on port A and auto wake-up. Reset clears MODEK.
1 = Keyboard interrupt requests on falling edges and low levels
0 = Keyboard interrupt requests on falling edges only
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Keyboard Interrupt Module (KBI)
14.4.3 Keyboard Interrupt Enable Register
The port A keyboard interrupt enable register (KBIER) enables or
disables each port A pin or auto wake-up to operate as a keyboard
interrupt input.
Address: $001B
Bit 7
0
6
AWUIE
0
5
KBIE5
0
4
KBIE4
0
3
KBIE3
0
2
KBIE2
0
1
KBIE1
0
Bit 0
KBIE0
0
Read:
Write:
Reset:
0
Figure 14-4. Keyboard Interrupt Enable Register (KBIER)
KBIE5–KBIE0 — Port A Keyboard Interrupt Enable Bits
Each of these read/write bits enables the corresponding keyboard
interrupt pin on port A to latch interrupt requests. Reset clears the
keyboard interrupt enable register.
1 = KBIx pin enabled as keyboard interrupt pin
0 = KBIx pin not enabled as keyboard interrupt pin
AWUIE — Auto Wake-up Interrupt Enable Bit
This read/write bit enables the auto wake-up interrupt input to latch
interrupt requests. Reset clears AWUIE.
1 = Auto wake-up enabled as interrupt input
0 = Auto wake-up not enabled as interrupt input
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Keyboard Interrupt Module (KBI)
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Keyboard Interrupt Module (KBI)
Functional Description
14.4.4 Auto Wake-up Interrupt Request
COPRS (FROM CONFIG1)
V
DD
AUTOWUGEN
TO PTA READ, BIT 6
1 = DIV 29
0 = DIV 214
D
E
AWUL
Q
SHORT
INT RC OSC
OVERFLOW
RST
AWUIREQ
R
32KHz
EN
CLK
TO KBI INTERRUPT LOGIC
(SEE Figure 14-2)
CLRLOGIC
RESET
ACKK
CLEAR
(CGMXCLK)
BUSCLKX4
CLK
RST
RESET
ISTOP
RESET
AWUIE
Figure 14-5. Auto Wake-up Interrupt Request Generation Logic
The function of the auto wake-up logic is to generate periodic wake-up
requests to bring the microcontroller unit (MCU) out of stop mode. The
wake-up requests are treated as regular keyboard interrupt requests,
with the difference that instead of a pin, the interrupt signal is generated
by an internal logic.
Entering stop mode will enable the auto wake-up generation logic. An
internal RC oscillator (exclusive for the auto wake-up feature) drives the
wake-up request generator. Once the overflow count is reached in the
generator counter, a wake-up request, AWUIREQ, is latched and sent to
the KBI logic (see Figure 14-2).
Wake-up interrupt requests will only be serviced if the associated
interrupt enable bit, AWUIE, in KBIER is set.
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Keyboard Interrupt Module (KBI)
The overflow count can be selected from two options defined by the
COPRS bit in CONFIG1. This bit was “borrowed” from the computer
operating properly (COP) using the fact that the COP feature is idle (no
MCU clock available) in stop mode. The typical values of the periodic
wake-up request (5 V, room temperature) are:
• COPRS = 0: 512 ms
• COPRS = 1: 16 ms
The auto wake-up RC oscillator is highly dependent on operating voltage
and temperature.
The wake-up request is latched to allow the interrupt source
identification. The latched value, AWUL, can be read directly from the
bit 6 position of PTA data register. This is a read-only bit which is
occupying an empty bit position on PTA. No PTA associated registers,
such as PTA6 data, PTA6 direction, and PTA6 pullup exist for this bit.
The latch can be cleared by writing to the ACKK bit in the KBSCR
register. Reset also clears the latch. AWUIE bit in KBI interrupt enable
register (see Figure 14-2) has no effect on AWUL reading.
14.5 Wait Mode
14.6 Stop Mode
The keyboard module remains active in wait mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of wait mode.
The keyboard module remains active in stop mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of stop mode.
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Keyboard Interrupt Module (KBI)
Keyboard Module During Break Interrupts
14.7 Keyboard Module During Break Interrupts
The system integration module (SIM) controls whether the keyboard
interrupt latch can be cleared during the break state. The BCFE bit in the
break flag control register (BFCR) enables software to clear status bits
during the break state.
To allow software to clear the keyboard interrupt latch during a break
interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the
break state, it remains cleared when the MCU exits the break state.
To protect the latch during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the keyboard
acknowledge bit (ACKK) in the keyboard status and control register
during the break state has no effect.
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Keyboard Interrupt Module (KBI)
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Keyboard Interrupt Module (KBI)
MOTOROLA
Data Sheet — MC68HC908QY4
Section 15. Computer Operating Properly (COP)
15.1 Contents
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
15.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
15.4.1 BUSCLKX4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
15.4.2 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
15.4.3 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191
15.4.4 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
15.4.5 Reset Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
15.4.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
15.4.7 COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . .192
15.5 COP Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
15.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
15.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
15.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
15.8.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
15.8.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
15.9 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .193
15.2 Introduction
The computer operating properly (COP) module contains a free-running
counter that generates a reset if allowed to overflow. The COP module
helps software recover from runaway code. Prevent a COP reset by
clearing the COP counter periodically. The COP module can be disabled
through the COPD bit in the configuration 1 (CONFIG1) register.
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Computer Operating Properly (COP)
15.3 Functional Description
SIM MODULE
12-BIT SIM COUNTER
SIM RESET CIRCUIT
BUSCLKX4
RESET STATUS REGISTER
INTERNAL RESET SOURCES(1)
RESET VECTOR FETCH
COPCTL WRITE
COP CLOCK
COP MODULE
6-BIT COP COUNTER
COPEN (FROM SIM)
COPD (FROM CONFIG1)
RESET
CLEAR
COP COUNTER
COPCTL WRITE
COP RATE SELECT
(COPRS FROM CONFIG1)
1. See Section 7. System Integration Module (SIM) for more details.
Figure 15-1. COP Block Diagram
The COP counter is a free-running 6-bit counter preceded by the 12-bit
system integration module (SIM) counter. If not cleared by software, the
COP counter overflows and generates an asynchronous reset after
218 – 24 or 213 – 24 BUSCLKX4 cycles; depending on the state of the
COP rate select bit, COPRS, in configuration register 1. With a 218 – 24
BUSCLKX4 cycle overflow option, a 8-MHz crystal gives a COP timeout
period of 32.766 ms. Writing any value to location $FFFF before an
overflow occurs prevents a COP reset by clearing the COP counter and
stages 12–5 of the SIM counter.
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Computer Operating Properly (COP)
MOTOROLA
Computer Operating Properly (COP)
I/O Signals
NOTE: Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 × BUSCLKX4 cycles and sets
the COP bit in the reset status register (RSR). See 7.9.1 SIM Reset
Status Register.
NOTE: Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
15.4 I/O Signals
The following paragraphs describe the signals shown in Figure 15-1.
15.4.1 BUSCLKX4
BUSCLKX4 is the oscillator output signal. BUSCLKX4 frequency is
equal to the crystal frequency or the RC-oscillator frequency.
15.4.2 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 15.5 COP
Control Register) clears the COP counter and clears bits 12–5 of the
SIM counter. Reading the COP control register returns the low byte of
the reset vector.
15.4.3 Power-On Reset
The power-on reset (POR) circuit in the SIM clears the SIM counter
4096 × BUSCLKX4 cycles after power up.
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Computer Operating Properly (COP)
15.4.4 Internal Reset
An internal reset clears the SIM counter and the COP counter.
15.4.5 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data
bus. A reset vector fetch clears the SIM counter.
15.4.6 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the
configuration register (CONFIG). See Section 5. Configuration
Register (CONFIG).
15.4.7 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS)
in the configuration register 1 (CONFIG1). See Section 5.
Configuration Register (CONFIG).
15.5 COP Control Register
The COP control register (COPCTL) is located at address $FFFF and
overlaps the reset vector. Writing any value to $FFFF clears the COP
counter and starts a new timeout period. Reading location $FFFF
returns the low byte of the reset vector.
Address: $FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
LOW BYTE OF RESET VECTOR
CLEAR COP COUNTER
Unaffected by reset
Figure 15-2. COP Control Register (COPCTL)
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Computer Operating Properly (COP)
Interrupts
15.6 Interrupts
The COP does not generate CPU interrupt requests.
15.7 Monitor Mode
The COP is disabled in monitor mode when VTST is present on the IRQ
pin.
15.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
15.8.1 Wait Mode
15.8.2 Stop Mode
The COP continues to operate during wait mode. To prevent a COP
reset during wait mode, periodically clear the COP counter.
Stop mode turns off the BUSCLKX4 input to the COP and clears the SIM
counter. Service the COP immediately before entering or after exiting
stop mode to ensure a full COP timeout period after entering or exiting
stop mode.
15.9 COP Module During Break Mode
The COP is disabled during a break interrupt with monitor mode when
BDCOP bit is set in break auxiliary register (BRKAR).
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Computer Operating Properly (COP)
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Computer Operating Properly (COP)
MOTOROLA
Data Sheet — MC68HC908QY4
Section 16. Low-Voltage Inhibit (LVI)
16.1 Contents
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196
16.4.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
16.4.2 Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . .198
16.4.3 Voltage Hysteresis Protection . . . . . . . . . . . . . . . . . . . . . .198
16.4.4 LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .198
16.5 LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199
16.6 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
16.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
16.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
16.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200
16.2 Introduction
This section describes the low-voltage inhibit (LVI) module, which
monitors the voltage on the VDD pin and can force a reset when the VDD
voltage falls below the LVI trip falling voltage, VTRIPF
.
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Low-Voltage Inhibit (LVI)
16.3 Features
Features of the LVI module include:
• Programmable LVI reset
• Programmable power consumption
• Selectable LVI trip voltage
• Programmable stop mode operation
16.4 Functional Description
Figure 16-1 shows the structure of the LVI module. LVISTOP,
LVIPWRD, LVI5OR3, and LVIRSTD are user selectable options found in
the configuration register (CONFIG1). See Section 5. Configuration
Register (CONFIG).
V
DD
STOP INSTRUCTION
LVISTOP
FROM CONFIG
FROM CONFIG
LVIRSTD
LVIPWRD
FROM CONFIG
VDD > LVITRIP = 0
LVI RESET
LOW V
DD
DETECTOR
VDD ≤ LVITRIP = 1
LVIOUT
LVI5OR3
FROM CONFIG
Figure 16-1. LVI Module Block Diagram
The LVI is enabled out of reset. The LVI module contains a bandgap
reference circuit and comparator. Clearing the LVI power disable bit,
LVIPWRD, enables the LVI to monitor VDD voltage. Clearing the LVI
reset disable bit, LVIRSTD, enables the LVI module to generate a reset
when VDD falls below a voltage, VTRIPF. Setting the LVI enable in stop
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Low-Voltage Inhibit (LVI)
MOTOROLA
Low-Voltage Inhibit (LVI)
Functional Description
mode bit, LVISTOP, enables the LVI to operate in stop mode. Setting the
LVI 5-V or 3-V trip point bit, LVI5OR3, enables the trip point voltage,
VTRIPF, to be configured for 5-V operation. Clearing the LVI5OR3 bit
enables the trip point voltage, VTRIPF, to be configured for 3-V operation.
The actual trip thresholds are specified in 18.6 5-V DC Electrical
Characteristics and 18.9 3-V DC Electrical Characteristics.
NOTE: After a power-on reset, the LVI’s default mode of operation is 3 volts. If
a 5-V system is used, the user must set the LVI5OR3 bit to raise the trip
point to 5-V operation.
If the user requires 5-V mode and sets the LVI5OR3 bit after power-on
reset while the VDD supply is not above the VTRIPR for 5-V mode, the
microcontroller unit (MCU) will immediately go into reset. The next time
the LVI releases the reset, the supply will be above the VTRIPR for 5-V
mode.
Once an LVI reset occurs, the MCU remains in reset until VDD rises
above a voltage, VTRIPR, which causes the MCU to exit reset. See
Section 7. System Integration Module (SIM) for the reset recovery
sequence.
The output of the comparator controls the state of the LVIOUT flag in the
LVI status register (LVISR) and can be used for polling LVI operation
when the LVI reset is disabled.
16.4.1 Polled LVI Operation
In applications that can operate at VDD levels below the VTRIPF level,
software can monitor VDD by polling the LVIOUT bit. In the configuration
register, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.
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Low-Voltage Inhibit (LVI)
16.4.2 Forced Reset Operation
In applications that require VDD to remain above the VTRIPF level,
enabling LVI resets allows the LVI module to reset the MCU when VDD
falls below the VTRIPF level. In the configuration register, the LVIPWRD
and LVIRSTD bits must be at logic 0 to enable the LVI module and to
enable LVI resets.
16.4.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having VDD fall below VTRIPF), the LVI
will maintain a reset condition until VDD rises above the rising trip point
voltage, VTRIPR. This prevents a condition in which the MCU is
continually entering and exiting reset if VDD is approximately equal to
VTRIPF. VTRIPR is greater than VTRIPF by the hysteresis voltage, VHYS
.
16.4.4 LVI Trip Selection
The LVI5OR3 bit in the configuration register selects whether the LVI is
configured for 5-V or 3-V protection.
NOTE: The microcontroller is guaranteed to operate at a minimum supply
voltage. The trip point (VTRIPF [5 V] or VTRIPF [3 V]) may be lower than
this. See 18.6 5-V DC Electrical Characteristics and
18.9 3-V DC Electrical Characteristics for the actual trip point voltages.
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Low-Voltage Inhibit (LVI)
MOTOROLA
Low-Voltage Inhibit (LVI)
LVI Status Register
16.5 LVI Status Register
The LVI status register (LVISR) indicates if the VDD voltage was
detected below the VTRIPF level while LVI resets have been disabled.
Address: $FE0C
Bit 7
Read: LVIOUT
Write:
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
R
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
Figure 16-2. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the VDD voltage falls below the
VTRIPF trip voltage and is cleared when VDD voltage rises above
VTRIPR. The difference in these threshold levels results in a hysteresis
that prevents oscillation into and out of reset (see Table 16-1). Reset
clears the LVIOUT bit.
Table 16-1. LVIOUT Bit Indication
V
LVIOUT
DD
V
> V
0
DD
TRIPR
TRIPF
V
< V
1
DD
V
< V < V
DD TRIPR
Previous value
TRIPF
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Low-Voltage Inhibit (LVI)
16.6 LVI Interrupts
The LVI module does not generate interrupt requests.
16.7 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-
consumption standby modes.
16.7.1 Wait Mode
16.7.2 Stop Mode
If enabled, the LVI module remains active in wait mode. If enabled to
generate resets, the LVI module can generate a reset and bring the MCU
out of wait mode.
When the LVIPWRD bit in the configuration register is cleared and the
LVISTOP bit in the configuration register is set, the LVI module remains
active in stop mode. If enabled to generate resets, the LVI module can
generate a reset and bring the MCU out of stop mode.
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Data Sheet — MC68HC908QY4
Section 17. Break Module (BREAK)
17.1 Contents
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
17.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
17.4.1 Flag Protection During Break Interrupts. . . . . . . . . . . . . . .204
17.4.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .204
17.4.3 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . .204
17.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .204
17.5 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205
17.5.1 Break Status and Control Register. . . . . . . . . . . . . . . . . . .205
17.5.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . .206
17.5.3 Break Auxiliary Register. . . . . . . . . . . . . . . . . . . . . . . . . . .207
17.5.4 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
17.5.5 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . .209
17.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
17.2 Introduction
This section describes the break module. The break module can
generate a break interrupt that stops normal program flow at a defined
address to enter a background program.
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Break Module (BREAK)
17.3 Features
Features of the break module include:
• Accessible input/output (I/O) registers during the break Interrupt
• Central processor unit (CPU) generated break interrupts
• Software-generated break interrupts
• Computer operating properly (COP) disabling during break
interrupts
17.4 Functional Description
When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal (BKPT)
to the system integration module (SIM). The SIM then causes the CPU
to load the instruction register with a software interrupt instruction (SWI)
after completion of the current CPU instruction. The program counter
vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode).
The following events can cause a break interrupt to occur:
• A CPU generated address (the address in the program counter)
matches the contents of the break address registers.
• Software writes a logic 1 to the BRKA bit in the break status and
control register.
When a CPU generated address matches the contents of the break
address registers, the break interrupt begins after the CPU completes its
current instruction. A return-from-interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the microcontroller unit
(MCU) to normal operation. Figure 17-1 shows the structure of the break
module.
Figure 17-2 provides a summary of the I/O registers.
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Break Module (BREAK)
MOTOROLA
Break Module (BREAK)
Functional Description
ADDRESS BUS[15:8]
BREAK ADDRESS REGISTER HIGH
8-BIT COMPARATOR
ADDRESS BUS[15:0]
CONTROL
BKPT
(TO SIM)
8-BIT COMPARATOR
BREAK ADDRESS REGISTER LOW
ADDRESS BUS[7:0]
Figure 17-1. Break Module Block Diagram
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SBSW
Break Status Register
(BSR) Write:
R
R
R
R
R
R
R
(1)
$FE00
Note
See page 208.
Reset:
Read:
0
Bit 1
0
Break Auxiliary Register
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 0
0
$FE02
$FE03
$FE09
$FE0A
$FE0B
(BRKAR) Write:
See page 207.
Reset:
Read:
Break Flag Control
Register (BFCR) Write:
BCFE
0
R
R
R
R
R
R
R
See page 209.
Reset:
Read:
Break Address High
Bit15
0
Bit14
0
Bit13
0
Bit12
0
Bit11
0
Bit10
0
Bit9
0
Bit8
0
Register (BRKH) Write:
See page 206.
Reset:
Read:
Break Address Low
Bit 7
0
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register (BRKL) Write:
See page 206.
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
Read:
Break Status and Control
BRKE
0
BRKA
0
Register (BRKSCR) Write:
See page 205.
Reset:
0
0
0
0
0
0
1. Writing a logic 0 clears SBSW.
= Unimplemented
R
= Reserved
Figure 17-2. Break I/O Register Summary
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Break Module (BREAK)
17.4.1 Flag Protection During Break Interrupts
The system integration module (SIM) controls whether or not module
status bits can be cleared during the break state. The BCFE bit in the
break flag control register (BFCR) enables software to clear status bits
during the break state. See 7.9.2 Break Flag Control Register and the
Break Interrupts subsection for each module.
17.4.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD
in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
17.4.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
17.4.4 COP During Break Interrupts
The COP is disabled during a break interrupt with monitor mode when
BDCOP bit is set in break auxiliary register (BRKAR).
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Break Module (BREAK)
MOTOROLA
Break Module (BREAK)
Break Module Registers
17.5 Break Module Registers
These registers control and monitor operation of the break module:
• Break status and control register (BRKSCR)
• Break address register high (BRKH)
• Break address register low (BRKL)
• Break status register (BSR)
• Break flag control register (BFCR)
17.5.1 Break Status and Control Register
The break status and control register (BRKSCR) contains break module
enable and status bits.
Address: $FE0B
Bit 7
BRKE
0
6
BRKA
0
5
0
4
0
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 17-3. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches.
Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled
BRKA — Break Active Bit
This read/write status and control bit is set when a break address
match occurs. Writing a logic 1 to BRKA generates a break interrupt.
Clear BRKA by writing a logic 0 to it before exiting the break routine.
Reset clears the BRKA bit.
1 = Break address match
0 = No break address match
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Break Module (BREAK)
17.5.2 Break Address Registers
The break address registers (BRKH and BRKL) contain the high and low
bytes of the desired breakpoint address. Reset clears the break address
registers.
Address: $FE09
Bit 7
Bit 15
0
6
Bit 14
0
5
Bit 13
0
4
Bit 12
0
3
Bit 11
0
2
Bit 10
0
1
Bit 9
0
Bit 0
Bit 8
0
Read:
Write:
Reset:
Figure 17-4. Break Address Register High (BRKH)
Address: $FE0A
Bit 7
6
Bit 6
0
5
Bit 5
0
4
Bit 4
0
3
Bit 3
0
2
Bit 2
0
1
Bit 1
0
Bit 0
Bit 0
0
Read:
Bit 7
Write:
Reset:
0
Figure 17-5. Break Address Register Low (BRKL)
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Break Module (BREAK)
Break Module Registers
17.5.3 Break Auxiliary Register
The break auxiliary register (BRKAR) contains a bit that enables
software to disable the COP while the MCU is in a state of break interrupt
with monitor mode.
Address: $FE02
Bit 7
0
6
0
5
0
4
0
3
0
2
0
1
0
Bit 0
BDCOP
0
Read:
Write:
Reset:
0
0
0
0
0
0
0
= Unimplemented
Figure 17-6. Break Auxiliary Register (BRKAR)
BDCOP — Break Disable COP Bit
This read/write bit disables the COP during a break interrupt. Reset
clears the BDCOP bit.
1 = COP disabled during break interrupt
0 = COP enabled during break interrupt.
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Break Module (BREAK)
17.5.4 Break Status Register
The break status register (BSR) contains a flag to indicate that a break
caused an exit from wait mode. This register is only used in emulation
mode.
Address: $FE00
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
SBSW
R
R
R
R
R
R
(1)
Note
0
R
= Reserved
1. Writing a logic 0 clears SBSW.
Figure 17-7. Break Status Register (BSR)
SBSW — SIM Break Stop/Wait
This status bit is useful in applications requiring a return to wait mode
after exiting from a break interrupt. Clear SBSW by writing a logic 0 to
it. Reset clears SBSW.
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it.
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MOTOROLA
Break Module (BREAK)
Low-Power Modes
17.5.5 Break Flag Control Register
The break control register (BFCR) contains a bit that enables software
to clear status bits while the MCU is in a break state.
Address: $FE03
Bit 7
6
5
4
3
2
1
Bit 0
R
Read:
Write:
Reset:
BCFE
R
R
R
R
R
R
0
R
= Reserved
Figure 17-8. Break Flag Control Register (BFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
17.6 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes. If enabled, the break module will remain
enabled in wait and stop modes. However, since the internal address
bus does not increment in these modes, a break interrupt will never be
triggered.
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Break Module (BREAK)
209
Break Module (BREAK)
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Break Module (BREAK)
MOTOROLA
Data Sheet — MC68HC908QY4
Section 18. Electrical Specifications
18.1 Contents
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
18.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .212
18.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .213
18.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
18.6 5-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . .214
18.7 5-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
18.8 5-V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .216
18.9 3-V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . .217
18.10 3-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218
18.11 3-V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .219
18.12 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
18.13 Analog-to-Digital Converter Characteristics . . . . . . . . . . . . . .221
18.14 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
18.2 Introduction
This section contains electrical and timing specifications.
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Electrical Specifications
18.3 Absolute Maximum Ratings
Maximum ratings are the extreme limits to which the microcontroller unit
(MCU) can be exposed without permanently damaging it.
NOTE: This device is not guaranteed to operate properly at the maximum
ratings. Refer to 18.6 5-V DC Electrical Characteristics and
18.9 3-V DC Electrical Characteristics for guaranteed operating
conditions.
(1)
Symbol
Value
Unit
V
Characteristic
Supply voltage
V
–0.3 to +6.0
DD
V
V
–0.3 to V +0.3
Input voltage
V
IN
SS
DD
V
V
–0.3 to +9.1
SS
Mode entry voltage, IRQ pin
Maximum current per pin excluding
V
TST
I
±15
±25
mA
mA
PTA0–PTA5, V , and V
DD
SS
Maximum current for pins
PTA0–PTA5
I
I
PTA0— PTA5
T
Storage temperature
–55 to +150
100
°C
mA
mA
STG
Maximum current out of V
I
SS
MVSS
Maximum current into V
I
100
DD
MVDD
1. Voltages references to V
.
SS
NOTE: This device contains circuitry to protect the inputs against damage due
to high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to this high-impedance circuit. For proper
operation, it is recommended that VIN and VOUT be constrained to the
range VSS ≤ (VIN or VOUT) ≤ VDD. Reliability of operation is enhanced if
unused inputs are connected to an appropriate logic voltage level (for
example, either VSS or VDD.)
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
212
Electrical Specifications
MOTOROLA
Electrical Specifications
Functional Operating Range
18.4 Functional Operating Range
Characteristic
Symbol
Value
– 40 to +125
Unit
°C
– 40 to +125
– 40 to +85
T
Operating temperature range
Operating voltage range
A
– 40 to +85
V
5 V ± 10%
3 V ± 10%
V
DD
18.5 Thermal Characteristics
Characteristic
Symbol
Value
Unit
Thermal resistance
8-pin PDIP
8-pin SOIC
16-pin PDIP
16-pin SOIC
16-pin TSSOP
95
70
66
70
70
θ
°C/W
JA
P
I/O pin power dissipation
User determined
P = (I x V
W
W
I/O
)
DD
D
DD
(1)
P
Power dissipation
D
+ P = K/(T + 273°C)
I/O
J
P x (T + 273°C)
D
A
(2)
K
W/°C
Constant
2
+ P x θ
D
JA
T
T + (P x θ )
Average junction temperature
Maximum junction temperature
°C
°C
J
A
D
JA
T
100
JM
1. Power dissipation is a function of temperature.
2. K constant unique to the device. K can be determined for a known T and measured P With
A
D.
this value of K, P and T can be determined for any value of T .
D
J
A
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MOTOROLA Electrical Specifications 213
Electrical Specifications
18.6 5-V DC Electrical Characteristics
(1)
(2)
Symbol
Min
Max
Unit
Characteristic
Output high voltage
Typ
I
I
I
= –2.0 mA, all I/O pins
V
V
V
–0.4
Load
Load
Load
DD
DD
DD
—
—
—
—
—
—
V
V
OH
= –10.0 mA, all I/O pins
= –15.0 mA, PTA0–PTA5 only
–1.5
–0.8
Output low voltage
I
I
I
= 1.6 mA, all I/O pins
Load
Load
Load
—
—
—
—
—
—
0.4
1.5
0.8
V
V
OL
= 10.0 mA, all I/O pins
= 15.0 mA, PTA0–PTA5 only
Input high voltage
PTA0–PTA5, PTB0–PTB7, RST, IRQ, OSC1
V
0.7 x V
V
—
—
V
V
IH
DD
DD
Input low voltage
PTA0–PTA5, PTB0–PTB7, RST, IRQ, OSC1
V
V
0.3 x V
DD
IL
SS
I
DC injection current, all ports
–2
—
—
+2
mA
mA
INJ
I
Total dc current injection (sum of all I/O)
–25
+25
INJTOT
V
supply current
DD
(3)
—
—
—
7
5
10
5.5
5
mA
mA
µA
Run, f = 4 MHz
OP
I
DD
(4)
Wait
(5)
0.1
Stop , –40°C to 85°C
I
Digital I/O ports Hi-Z leakage current
Input current
—
—
—
—
± 10
± 1
µA
µA
IL
I
IN
C
Capacitance
Ports (as input or output)
—
—
—
—
12
8
OUT
pF
C
IN
(6)
V
0
—
—
—
100
—
mV
V/ms
V
POR rearm voltage
POR
POR
(7)
R
0.035
V + 2.5
DD
POR rise time ramp rate
V
Monitor mode entry voltage
9.1
TST
(8)
Pullup resistors
R
16
3.90
26
36
kΩ
PU
RST, IRQ, PTA0–PTA5, PTB0–PTB7
V
Low-voltage inhibit reset, trip falling voltage
4.20
4.50
V
TRIPF
Continued on next page
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
214 Electrical Specifications MOTOROLA
Electrical Specifications
5-V Control Timing
(1)
(2)
Symbol
Min
4.00
—
Max
4.60
—
Unit
V
Characteristic
Typ
V
Low-voltage inhibit reset, trip rising voltage
Low-voltage inhibit reset/recover hysteresis
4.30
100
TRIPR
V
mV
HYS
1. V = 4.5 to 5.5 Vdc, V = 0 Vdc, T = T to T , unless otherwise noted.
DD
SS
A
L
H
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Run (operating) I measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than
DD
100 pF on all outputs. All ports configured as inputs. Measured with all modules enabled.
4. Wait I measured using external square wave clock source (f = 4MHz); all inputs 0.2 V from rail; no dc loads; less than
DD
OP
100 pF on all outputs.
5. All ports configured as inputs. All ports driven 0.2 V or less from rail. No dc loads. On the 8-pin versions, port B is configured
as inputs with pullups enabled.
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum V is not reached before the internal POR reset is released, RST must be driven low externally until minimum
DD
V
is reached.
DD
8. R
and R
are measured at V = 5.0 V.
PU1
PU2 DD
18.7 5-V Control Timing
(1)
Symbol
Min
—
Max
8
Unit
MHz
ns
Characteristic
(2)
f
Internal operating frequency
OP
(3)
t
750
—
RST input pulse width low
IRL
1. V = 4.5 to 5.5 Vdc, V = 0 Vdc, T = T to T ; timing shown with respect to 20% V and 70% V , unless otherwise
DD
SS
A
L
H
DD
SS
noted.
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this
information.
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA
Electrical Specifications
215
Electrical Specifications
18.8 5-V Oscillator Characteristics
Characteristic
Internal oscillator frequency
Crystal frequency, XTALCLK
RC oscillator frequency, RCCLK
Symbol
Min
—
1
Typ
12.8
—
Max
—
Unit
MHz
MHz
MHz
MHz
f
INTCLK
f
32
OSCXCLK
f
2
—
12
RCCLK
(1)
f
dc
—
32
External clock reference frequency
OSCXCLK
(2)
C
—
—
—
—
—
—
2 x C
2 x C
10
—
—
—
—
—
—
—
Crystal load capacitance
L
(2)
C
Crystal fixed capacitance
1
L
L
(2)
C
—
Crystal tuning capacitance
2
R
Feedback bias resistor
MΩ
—
B
(2), (3)
R
—
Series resistor
S
R
RC oscillator external resistor
See Figure 18-1
—
EXT
1. No more than 10% duty cycle deviation from 50%.
2. Consult crystal vendor data sheet.
3. Not required for high frequency crystals
14
12
10
8
5 V @ 25°C
MCU
OSC1
6
V
DD
4
REXT
2
0
0
10
20
30
40
50
Resistor, REXT (kΩ)
Figure 18-1. RC versus Frequency (5 Volts @ 25°C)
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
216 Electrical Specifications MOTOROLA
Electrical Specifications
3-V DC Electrical Characteristics
18.9 3-V DC Electrical Characteristics
(1)
(2)
Symbol
Min
Max
Unit
Characteristic
Output high voltage
Typ
I
I
I
= –0.6 mA, all I/O pins
V
V
V
–0.3
Load
Load
Load
DD
DD
DD
—
—
—
—
—
—
V
V
OH
= –4.0 mA, all I/O pins
–1.0
–0.6
= –10.0 mA, PTA0–PTA4 only
Output low voltage
—
—
—
—
—
—
0.3
1.0
0.6
I
I
I
= 0.5 mA, all I/O pins
Load
Load
Load
V
V
OL
= 6.0 mA, all I/O pins
= 10.0 mA, PTA0-PTA5 only
Input high voltage
PTA0–PTA5, PTB0–PTB7, RST, IRQ, OSC1
V
0.7 x V
V
—
—
V
V
IH
DD
DD
Input low voltage
PTA0–PTA5, PTB0–PTB7, RST, IRQ, OSC1
V
V
0.3 x V
DD
IL
SS
I
DC injection current, all ports
–2
—
—
+2
mA
mA
INJ
I
Total dc current injection (sum of all I/O)
–25
+25
INJTOT
V
supply current
DD
(3)
(4)
Run, f = 2 MHz
—
—
—
5
1
8
2.5
5
mA
mA
µA
OP
I
DD
Wait, f = 2 MHz
OP
(5)
0.1
Stop ,–40°C to 85°C
I
Digital I/O ports Hi-Z leakage current
Input leakage current
—
—
—
—
± 10
± 1
µA
µA
IL
I
IN
C
Capacitance
Ports (as input or output)
—
—
—
—
12
8
OUT
pF
C
IN
(6)
V
R
0
—
—
—
100
mV
V/ms
V
POR rearm voltage
POR
POR
(7)
0.035
+ 2.5
—
POR rise time ramp rate
V
V
V
+ 4.0
DD
Monitor mode entry voltage
TST
DD
(8)
Pullup resistors
R
16
2.40
26
36
2.70
kΩ
PU
RST, IRQ, PTA0–PTA5, PTB0–PTB7
V
Low-voltage inhibit reset, trip falling voltage
2.55
V
TRIPF
Continued on next page
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA Electrical Specifications 217
Electrical Specifications
(1)
(2)
Symbol
Min
2.50
—
Max
2.80
—
Unit
V
Characteristic
Typ
V
Low-voltage inhibit reset, trip rising voltage
Low-voltage inhibit reset/recover hysteresis
2.65
60
TRIPR
V
mV
HYS
1. V = 2.7 to 3.3 Vdc, V = 0 Vdc, T = T to T , unless otherwise noted.
DD
SS
A
L
H
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Run (operating) I measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than
DD
100 pF on all outputs. All ports configured as inputs. Measured with all modules enabled.
4. Wait I measured using external square wave clock source (f = 4 MHz); all inputs 0.2 V from rail; no dc loads; less than
DD
OP
100 pF on all outputs.
5. All ports configured as inputs. All ports driven 0.2 V or less from rail. No dc loads. On the 8-pin versions, port B is configured
as inputs with pullups enabled.
6. Maximum is highest voltage that POR is guaranteed.
7. If minimum V is not reached before the internal POR reset is released, RST must be driven low externally until minimum
DD
V
is reached.
DD
8. R
and R
are measured at V = 5.0 V
PU1
PU2 DD
18.10 3-V Control Timing
(1)
Symbol
Min
—
Max
4
Unit
MHz
µs
Characteristic
(2)
f
Internal operating frequency
OP
(3)
t
1.5
—
RST input pulse width low
IRL
1. V = 2.7 to 3.3 Vdc, V = 0 Vdc, T = T to T ; timing shown with respect to 20% V and 70% V , unless otherwise
DD
SS
A
L
H
DD
DD
noted.
2. Some modules may require a minimum frequency greater than dc for proper operation; see appropriate table for this
information.
3. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
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218
Electrical Specifications
MOTOROLA
Electrical Specifications
3-V Oscillator Characteristics
18.11 3-V Oscillator Characteristics
Characteristic
Internal oscillator frequency
Crystal frequency, XTALCLK
RC oscillator frequency, RCCLK
Symbol
Min
—
1
Typ
12.8
—
Max
—
Unit
MHz
MHz
MHz
MHz
f
INTCLK
f
f
16
OSCXCLK
f
2
—
12
RCCLK
(1)
dc
—
16
External clock reference frequency
OSCXCLK
(2)
C
—
—
—
—
—
—
—
—
—
—
—
—
—
Crystal load capacitance
L
(2)
C
2 x C
2 x C
Crystal fixed capacitance
1
L
L
(2)
C
—
Crystal tuning capacitance
2
R
Feedback bias resistor
10
MΩ
—
B
(2), (3)
R
—
Series resistor
S
R
RC oscillator external resistor
See Figure 18-2
—
EXT
1. No more than 10% duty cycle deviation from 50%
2. Consult crystal vendor data sheet
3. Not required for high frequency crystals
14
12
10
8
3 V @ 25°C
MCU
OSC1
6
VDD
REXT
4
2
0
0
10
20
30
40
50
RESISTOR, REXT (KΩ)
Figure 18-2. RC versus Frequency (3 Volts @ 25°C)
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MOTOROLA Electrical Specifications 219
Electrical Specifications
18.12 Typical Supply Currents
14
12
10
8
IDD (mA)
6
4
2
0
5.5 V
3.3 V
0
1
2
3
4
5
6
7
8
9
fOP OR fBUS (MHz)
Figure 18-3. Typical Operating IDD
,
with All Modules Turned On (25°C)
2
1.75
1.50
1.25
1
IDD (mA)
0.75
0.5
5.5 V
3.3 V
0.25
0
0
1
2
3
4
5
6
7
8
fOP OR fBUS (MHz)
Figure 18-4. Typical Wait Mode IDD
,
with ADC Turned On (25°C)
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220 Electrical Specifications MOTOROLA
Electrical Specifications
Analog-to-Digital Converter Characteristics
18.13 Analog-to-Digital Converter Characteristics
Characteristic
Supply voltage
Symbol
Min
Max
Unit
Comments
2.7
5.5
V
V
—
DDAD
(V min) (V max)
DD
DD
V
V
V
Input voltages
Resolution
V
—
ADIN
SS
DD
B
8
8
Bits
LSB
—
AD
A
Absolute accuracy
± 0.5
± 1.5
Includes quantization
AD
t
= 1/f
,
ADIC
ADIC
f
ADC internal clock
0.5
1.048
MHz
V
ADIC
tested only at 1 MHz
R
V
V
Conversion range
Power-up time
—
AD
SS
DD
t
t
t
t
cycles
t
t
t
= 1/f
= 1/f
= 1/f
= V
16
16
5
ADPU
ADIC
ADIC
ADIC
ADIC
ADIC
ADIC
ADIC
ADIC
t
cycles
cycles
Conversion time
17
—
ADC
(1)
t
Sample time
ADS
ADIC
(2)
Z
V
00
FE
—
—
01
FF
8
Hex
Zero input reading
ADI
IN
SS
DD
(3)
F
V
= V
IN
Hex
pF
Full-scale reading
Input capacitance
ADI
C
Not tested
ADI
(3)
—
± 1
µA
—
Input leakage
1. Source impedances greater than 10 kΩ adversely affect internal RC charging time during input sampling.
2. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions.
3. The external system error caused by input leakage current is approximately equal to the product of R source and input
current.
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA
Electrical Specifications
221
Electrical Specifications
18.14 Memory Characteristics
Characteristic
RAM data retention voltage
Symbol
Min
1.3
1
Max
—
Unit
V
V
RDR
FLASH program bus clock frequency
FLASH read bus clock frequency
—
—
MHz
Hz
(1)
32 k
8M
f
Read
FLASH page erase time
<1 K cycles
<10 K cycles
(2)
1
4
—
—
ms
t
Erase
(3)
FLASH mass erase time
4
10
5
—
—
—
—
—
40
—
ms
us
us
us
us
us
us
t
MErase
t
FLASH PGM/ERASE to HVEN set up time
FLASH high-voltage hold time
FLASH high-voltage hold time (mass erase)
FLASH program hold time
nvs
t
nvh
t
100
5
nvhl
t
pgs
t
FLASH program time
30
1
PROG
(4)
FLASH return to read time
t
rcv
(5)
FLASH cumulative program hv period
—
4
ms
t
HV
(6)
—
10 k
10 k
10
—
—
—
Cycles
Cycles
Years
FLASH row erase endurance
(7)
—
—
FLASH row program endurance
(8)
FLASH data retention time
1. f
is defined as the frequency range for which the FLASH memory can be read.
Read
2. If the page erase time is longer than t
memory.
(Min), there is no erase disturb, but it reduces the endurance of the FLASH
Erase
3. If the mass erase time is longer than t
memory.
(Min), there is no erase disturb, but it reduces the endurance of the FLASH
MErase
4. t is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by clearing
rcv
HVEN to logic 0.
5. t is defined as the cumulative high voltage programming time to the same row before next erase.
HV
t
must satisfy this condition: t
+ t
+ t
+ (t
x 32) ≤ t max.
HV
nvs
nvh
pgs
PROG HV
6. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many
erase/program cycles.
7. The minimum row endurance value specifies each row of the FLASH memory is guaranteed to work for at least this many
erase/program cycles.
8. The FLASH is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified.
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
222
Electrical Specifications
MOTOROLA
Data Sheet — MC68HC908QY4
Section 19. Mechanical Specifications
19.1 Contents
19.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
19.3 8-Pin Plastic Dual In-Line Package
(Case #626). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
19.4 8-Pin Small Outline Integrated Circuit Package
(Case #968). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224
19.5 16-Pin Plastic Dual In-Line Package
(Case #648D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
19.6 16-Pin Small Outline Integrated Circuit Package
(Case #751G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
19.7 16-Pin Thin Shrink Small Outline Package
(Case #948F). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226
19.2 Introduction
This section gives the dimensions for:
• 8-pin plastic dual in-line package (PDIP)
• 8-pin small outline integrated circuit (SOIC) package
• 16-pin PDIP
• 16-pin SOIC
• 16-pin thin shrink small outline package (TSSOP)
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA Mechanical Specifications 223
Mechanical Specifications
19.3 8-Pin Plastic Dual In-Line Package (Case #626)
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGECONTOUROPTIONAL(ROUNDOR
SQUARE CORNERS).
8
5
3. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
-B-
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
1
4
A
B
C
D
F
G
H
J
K
L
M
N
9.40 10.16 0.370 0.400
6.10
3.94
0.38
1.02
6.60 0.240 0.260
4.45 0.155 0.175
0.51 0.015 0.020
1.78 0.040 0.070
F
-A-
NOTE 2
L
2.54 BSC
0.100 BSC
1.27 0.030 0.050
0.30 0.008 0.012
3.43 0.115 0.135
0.76
0.20
2.92
C
7.62 BSC
0.300 BSC
--- 10
1.01 0.030 0.040
---
0.76
10
°
°
J
-T-
SEATING
PLANE
N
STYLE 1:
1.
2.
3.
4.
5.
6.
7.
8.
AC IN
M
D
DC + IN
DC - IN
AC IN
GROUND
OUTPUT
K
G
H
M
M
M
0.13 (0.005)
T A
B
AUXILIARY
VCC
19.4 8-Pin Small Outline Integrated Circuit Package (Case #968)
NOTES:
L
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
8
5
E
2. CONTROLLING DIMENSION: MILLIMETER
3. DIMENSION D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD
FLASH OR PROTRUSIONS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
Q
1
E
H
E
×
M
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
1
4
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTUSION. ALLOWABLE
DAMBAR PROTRUSION SHALLBE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL
CONDITION. DAMBAR CANNOT BE LOCATED
ON THE LOWER RADIUS OR THE FOOT
MINIMUM SPACE BETWEEN PROTRUSIONS
AND ADJACENT LEAD TO BE 0.46 (0.018).
L
Z
DETAIL P
D
e
P
MILLIMETERS
INCHES
DIM MIN
MAX
MIN MAX
A
A
b
c
D
E
---
2.05
--- 0.081
0.05
0.35
0.18
5.10
5.10
0.20 0.002 0.008
0.50 0.014 0.020
0.27 0.007 0.011
5.50 0.201 0.217
5.45 0.201 0.215
1
b
c
M
0.13 (0.005)
0.10 (0.004)
e
E
1.27 BSC
0.050 BSC
8.20 0.291 0.323
0.85 0.020 0.033
1.50 0.043 0.059
H
7.40
0.50
1.10
L
L
E
M
Q
Z
0
0.70
---
10
0
10
°
°
°
°
0.90 0.028 0.035
0.94 --- 0.037
1
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
224 Mechanical Specifications MOTOROLA
Mechanical Specifications
16-Pin Plastic Dual In-Line Package (Case #648D)
19.5 16-Pin Plastic Dual In-Line Package (Case #648D)
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
5. MOLD FLASH OR PROTRUSIONS SHALL
NOT EXCEED 0.25 (0.010).
-A-
16
9
8
-B-
S
1
6. ROUNDED CORNERS OPTIONAL.
F
INCHES
DIM MIN MAX
MILLIMETERS
MIN MAX
L
C
A
B
C
D
F
G
H
J
K
L
M
S
0.740 0.760 18.80 19.30
0.245 0.260
0.145 0.175
0.015 0.021
0.050 0.070
0.100 BSC
6.23
3.69
0.39
1.27
2.54 BSC
1.27 BSC
6.60
4.44
0.53
1.77
SEATING
PLANE
-T-
M
K
J
0.050 BSC
H
0.008 0.015
0.120 0.140
0.295 0.305
0.21
0.38
3.55
7.74
G
3.05
7.50
0
D 16 PL
0
10
10
M
S
S
°
°
°
°
0.25 (0.010)
T B
A
0.015 0.035
0.39
0.88
19.6 16-Pin Small Outline Integrated Circuit Package (Case #751G)
A
NOTES:
D
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND
TOLERANCES PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
q
16
9
4. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
5. DIMENSIONB DOESNOTINCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESSOFTHEB DIMENSIONATMAXIMUM
MATERIAL CONDITION.
1
8
MILLIMETERS
B
16X B
DIM MIN
2.35
A1 0.10
MAX
2.65
0.25
0.49
0.32
A
M
S
S
0.25
T A
B
B
C
D
E
e
H
h
L
q
0.35
0.23
10.15 10.45
7.40 7.60
1.27 BSC
10.05 10.55
0.25
0.40
0
0.75
1.00
7
SEATING
PLANE
14X
e
°
°
C
T
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA Mechanical Specifications 225
Mechanical Specifications
19.7 16-Pin Thin Shrink Small Outline Package (Case #948F)
16X KREF
M
S
S
0.10 (0.004)
T U
V
NOTES:
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
S
0.15 (0.006)T U
K
5. CONTROLLING DIMENSION: MILLIMETER.
6. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
7. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEADFLASHORPROTRUSIONSHALL
NOT EXCEED
K1
16
9
2X L/2
J1
B
-U-
SECTION N-N
L
0.25 (0.010) PER SIDE.
J
8. DIMENSIONKDOES NOT INCLUDEDAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
PIN 1
IDENT.
8
1
N
0.25 (0.010)
10. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
S
0.15 (0.006)T U
A
M
-V-
N
F
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
B
C
D
F
G
H
J
4.90
4.30
---
0.05
0.50
0.65 BSC
0.18
0.09
5.10 0.193 0.200
4.50 0.169 0.177
DETAIL E
1.20
--- 0.047
0.15 0.002 0.006
0.75 0.020 0.030
-W-
C
0.026 BSC
0.28 0.007 0.011
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.10 (0.004)
J1 0.09
0.19
H
DETAIL E
SEATING
PLANE
K
-T-
D
G
K1 0.19
L
6.40 BSC
0.252 BSC
M
0
8
0
8
°
°
°
°
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
226 Mechanical Specifications MOTOROLA
Data Sheet — MC68HC908QY4
Section 20. Ordering Information
20.1 Contents
20.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
20.3 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
20.2 Introduction
This section contains ordering numbers for MC68HC908QY1,
MC68HC908QY2, MC68HC908QY4, MC68HC908QT1,
MC68HC908QT2, and MC69HC908QT4.
20.3 MC Order Numbers
Table 20-1. MC Order Numbers
MC Order Number
ADC
—
FLASH Memory
1536 bytes
1536 bytes
4096 bytes
1536 bytes
1536 bytes
4096 bytes
Package
MC68HC908QY1
MC68HC908QY2
MC68HC908QY4
MC68HC908QT1
MC68HC908QT2
MC68HC908QT4
16-pins
PDIP, SOIC,
and TSSOP
Yes
Yes
—
8-pins
PDIP or SOIC
Yes
Yes
Temperature and package designators:
C = –40°C to +85°C
V = –40°C to +105°C (available for V = 5 V only)
DD
M = –40°C to +125°C (available for V = 5 V only)
DD
P = Plastic dual in-line package (PDIP)
DW = Small outline integrated circuit package (SOIC)
DT = Thin shrink small outline package (TSSOP)
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
MOTOROLA Ordering Information 227
Ordering Information
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
228
Ordering Information
MOTOROLA
HOW TO REACH US:
USA/EUROPE/LOCATIONS NOT LISTED:
Motorola Literature Distribution;
P.O. Box 5405, Denver, Colorado 80217
1-303-675-2140 or 1-800-441-2447
JAPAN:
Motorola Japan Ltd.; SPS, Technical Information Center,
3-20-1, Minami-Azabu Minato-ku, Tokyo 106-8573 Japan
81-3-3440-3569
ASIA/PACIFIC:
Information in this document is provided solely to enable system and software
implementers to use Motorola products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits or
integrated circuits based on the information in this document.
Motorola Semiconductors H.K. Ltd.;
Silicon Harbour Centre, 2 Dai King Street,
Tai Po Industrial Estate, Tai Po, N.T., Hong Kong
852-26668334
Motorola reserves the right to make changes without further notice to any products
herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters which may be provided in Motorola data sheets
and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts.
Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as
components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which
the failure of the Motorola product could create a situation where personal injury or
death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that Motorola
was negligent regarding the design or manufacture of the part.
TECHNICAL INFORMATION CENTER:
1-800-521-6274
HOME PAGE:
http://www.motorola.com/semiconductors
Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark
Office. digital dna is a trademark of Motorola, Inc. All other product or service
names are the property of their respective owners. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
© Motorola, Inc. 2002
MC68HC908QY4/D
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