V62C1804096 [MOSEL]
512K X 8, CMOS STATIC RAM; 512K ×8 ， CMOS静态RAM
| 型号： | V62C1804096 |
| 厂家： | 
MOSEL VITELIC, CORP |
| 描述： | 512K X 8, CMOS STATIC RAM |
| 文件： | 总10页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
V62C1804096
512K X 8, CMOS STATIC RAM
Features
Description
■ High-speed: 85, 100 ns
■ Ultra low standby current of 2µA (max.)
■ Fully static operation
■ All inputs and outputs directly compatible
■ Three state outputs
The V62C1804096 is a very low power CMOS
static RAM organized as 524,288 words by 8 bits.
Easy memory expansion is provided by an active
LOW CE1, and active HIGH CE2, an active LOW
OE, and three static I/O’s. This device has an
automatic power-down mode feature when
deselected.
■ Ultra low data retention current (V
■ Operating voltage: 1.8V–2.3V
■ Packages
= 1.0V)
CC
– 36-Ball CSP BGA (8mm x 10mm)
Functional Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Input Buffer
I/O8
I/O1
1024
x
4096
OE
Column Decoder
WE
CE1
CE2
Control
Circuit
A10 A11 A12 A13 A14 A15 A16 A17 A18
Device Usage Chart
Package
Outline
Operating
Temperature
Range
Access Time (ns)
Power
Temperature
Mark
B
•
85
•
100
L
LL
0°C to 70 °C
•
•
•
•
•
Blank
I
–40°C to +85°C
•
•
V62C1804096 Rev. 1.0 October 2001
1
V62C1804096
WE
Write Enable Input
Pin Descriptions
A –A Address Inputs
These 19 address inputs select one of the 512K x 8
bit segments in the RAM.
The write enable input is active LOW and controls
read and write operations. With the chip enabled,
when WE is HIGH and OE is LOW, output data will
be present at the I/O pins; when WE is LOW and
OE is HIGH, the data present on the I/O pins will be
written into the selected memory locations.
0
18
CE , CE Chip Enable Inputs
1
2
CE is active LOW and CE is active HIGH. Both
1
2
chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
I/O –I/O Data Input and Data Output Ports
These 8 bidirectional ports are used to read data
from and write data into the RAM.
1
8
V
Power Supply
Ground
CC
OE
Output Enable Input
GND
The Output Enable input is active LOW. With chip
enabled, when OE is LOW and WE HIGH, data of
the selected memory location will be available on
the I/O pins. When OE is HIGH, the I/O pins will be
in the high impedance state.
Pin Configurations (Top View)
36 BGA
1
2
3
4
5
6
1
2
3
4
5
6
A0
A1 CE2 A3
A2 WE A4
A6
A8
A
B
C
A
B
C
D
E
F
I/O5
I/O6
VSS
A7 I/O1
NB I/O2
NB NC
A5
NB NB NB NB VCC
D
VCC
I/O7
I/O8
A9
NB NB NB NB VSS
NB A18 A17 NB I/O3
OE CE1 A16 A15 I/O4
A10 A11 A12 A13 A14
E
F
G
G
H
Note: NC means no connect.
H
NB means no ball.
TOP VIEW
TOP VIEW
V62C1804096 Rev. 1.0 October 2001
2
V62C1804096
Part Number Information
1
80
V
62
C
4096
–
MOSEL-VITELIC
MANUFACTURED
TEMP.
SRAM
FAMILY
OPERATING
VOLTAGE
DENSITY
4096K
PKG
BLANK = 0°C to 70°C
I = -40°C to +85°C
PWR.
SPEED
62 = STANDARD
85 ns
100 ns
C = CMOS PROCESS
T = TSOP STANDARD
B = BGA
= 1.8V–2.3V
1
ORGANIZATION
= 8-bit
L = LOW POWER
LL = LOW LOW POWER
80
Absolute Maximum Ratings (1)
Symbol
Parameter
Supply Voltage
Input Voltage
Commercial
Industrial
Units
V
V
-0.5 to + VCC + 0.5 -0.5 to + VCC + 0.5
-0.5 to + VCC + 0.5 -0.5 to + VCC + 0.5
CC
V
N
V
V
Input/Output Voltage Applied
Temperature Under Bias
Storage Temperature
V
+ 0.3
V + 0.3
CC
V
DQ
CC
T
-10 to +125
-55 to +125
-65 to +135
-65 to +150
°C
°C
BIAS
T
STG
NOTE:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Capacitance*
Truth Table
T = 25°C, f = 1.0MHz
A
I/O
Mode
Standby
Standby
Output Disable
Read
CE
H
X
CE
X
OE
X
WE Operation
Symbol Parameter
Conditions Max. Unit
1
2
CIN
Input Capacitance
Output Capacitance
VIN = 0V
VI/O = 0V
6
8
pF
pF
X
X
H
H
L
High Z
High Z
High Z
DOUT
DIN
COUT
L
X
NOTE:
L
H
H
1. This parameter is guaranteed and not tested.
L
H
L
Write
L
H
X
NOTE:
X = Don’t Care, L = LOW, H = HIGH
V62C1804096 Rev. 1.0 October 2001
3
V62C1804096
DC Electrical Characteristics (over all temperature ranges, V = 1.8V–2.3V)
CC
Symbol Parameter
Test Conditions
Min.
-0.3
1.6
Typ.
—
Max.
Units
V
(1,2)
(1)
VIL
VIH
IIL
Input LOW Voltage
0.4
Input HIGH Voltage
—
VCC+0.3
V
Input Leakage Current
Output Leakage Current
Output LOW Voltage
Output HIGH Voltage
VCC = Max, VIN = 0V to VCC
VCC = Max, CE1 = VIH, VOUT = 0V to VCC
VCC = Min, IOL = 2mA
—
—
1
1
µA
µA
V
IOL
—
—
VOL
VOH
—
—
0.4
—
VCC = Min, IOH = -0.5mA
VCC–0.4
—
V
(3)
(3)
Symbol Parameter
ICC1 Average Operating Current, CE1 = VIL, CE2 = VCC – 0.2, Output Open,
Comm.
Ind.
Units
f = fmax
25
2
30
3
mA
V
CC = Max.
f = 1 MHz
ISB
TTL Standby Current
L
LL
L
0.4
0.3
5
0.5
0.3
7
mA
µA
CE1 >=VIH, CE2 <= VIL, VCC = Max., f = 0
ISB1
CMOS Standby Current, CE1 Š VCC – 0.2V, CE2 ð 0.2V,
V
IN>= VCC – 0.2V or VIN <=0.2V, VCC = Max., f = 0
LL
2
3
NOTES:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. IL (Min.) = -3.0V for pulse width < tRC/2.
V
3. Maximum value.
AC Test Conditions
AC Test Loads and Waveforms
Input Pulse Levels
0 to 1.6V
5 ns
Input Rise and Fall Times
Timing Reference Levels
Output Load
TTL
CL*
0.9V
see below
CL = 30pF + 1TTL Load
* Includes scope and jig capacitance
V62C1804096 Rev. 1.0 October 2001
4
V62C1804096
Data Retention Characteristics
Symbol
Parameter
Power
Min.
Typ.(2)
Max.
Units
VDR
VCC for Data Retention
1.0
—
2.3
V
CE1 ≥ VCC – 0.2V, CE2 < 0.2V, VIN ≥ VCC – 0.2V,
or VIN ≤ 0.2V
ICCDR
Data Retention Current
Com’l
L
LL
L
—
—
—
—
1
0.5
—
—
—
—
3
1.5
5
µA
CE1 ≥ VDR – 0.2V, CE2 < 0.2V, VIN ≥ VCC – 0.2V,
or VIN ≤ 0.2V, VDR = 1.0V
Ind.
LL
2
tCDR
tR
NOTES:
Chip Deselect to Data Retention Time
0
—
—
ns
ns
(1)
Operation Recovery Time (see Retention Waveform)
t
RC
1.
2.
t
T
RC = Read Cycle Time
A = +25°C.
Low VCC Data Retention Waveform (1) (CE1 Controlled)
Data Retention Mode
DR ≥ 1V
VCC
CE1
1.8V
tCDR
1.8V
1.6V
V
tR
CE1 ≥ VCC – 0.2V
1.6V
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGING
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGING
FROM L TO H
DON'T CARE:
ANY CHANGE
PERMITTED
CHANGING:
STATE
UNKNOWN
CENTER
DOES NOT
APPLY
LINE IS HIGH
IMPEDANCE
“OFF” STATE
V62C1804096 Rev. 1.0 October 2001
5
V62C1804096
AC Electrical Characteristics
(over all temperature ranges)
Read Cycle
85
100
Parameter
Name
Parameter
Min.
85
—
Max.
—
Min.
100
—
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Read Cycle Time
RC
t
Address Access Time
85
85
85
85
—
100
100
100
40
AA
t
Chip Enable Access Time
Chip Enable Access Time
Output Enable to Output Valid
Chip Enable to Output in Low Z
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
—
—
ACS1
t
—
—
ACS2
t
—
—
OE
t
10
10
5
15
15
10
—
—
CLZ1
t
—
—
CLZ2
t
—
—
OLZ
t
—
30
30
—
35
CHZ
t
—
—
35
OHZ
t
10
10
—
OH
Write Cycle
85
100
Parameter
Name
Parameter
Min.
85
70
0
Max.
—
Min.
70
60
0
Max.
—
Unit
ns
t
Write Cycle Time
WC
t
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
—
—
ns
CW
t
—
—
ns
AS
t
70
60
5
—
60
50
5
—
ns
AW
t
—
—
ns
WP
t
Write Recovery Time
Write to Output High-Z
Data Setup to End of Write
Data Hold from End of Write
—
—
ns
WR
t
—
40
0
25
—
—
45
0
30
—
ns
WHZ
t
ns
DW
t
—
—
ns
DH
V62C1804096 Rev. 1.0 October 2001
6
V62C1804096
Switching Waveforms (Read Cycle)
(1, 2)
Read Cycle 1
tRC
ADDRESS
OE
tAA
tOE
tOH
(5)
tOHZ
tOLZ
I/O
(1, 2, 4)
Read Cycle 2
tRC
ADDRESS
tAA
tOH
tOH
I/O
(1, 3, 4)
Read Cycle 3
ADDRESS
CE1
CE2
I/O
tACS1
tACS2
(5)
tCHZ
(5)
tCLZ1
(5)
tCLZ2
NOTES:
1. WE = VIH
2. CE1 = VIL and CE2 = VIH
.
.
3. Address valid prior to or coincident with CE1 transition LOW and/or CE2 transition HIGH.
4. OE = VIL.
5. Transition is measured ±500mV from steady state with CL = 5pF. This parameter is guaranteed and not 100% tested.
V62C1804096 Rev. 1.0 October 2001
7
V62C1804096
Switching Waveforms (Write Cycle)
(4)
Write Cycle 1 (WE Controlled)
tWC
ADDRESS
(2)
tWR
(6)
tCW
CE1
CE2
tAW
(6)
tCW
tAS
WE
(1)
tWP
OUTPUT
tDW
tDH
tWHZ
INPUT
Write Cycle 2 (CE Controlled)
ADDRESS
(4)
tWC
(2)
tWR
(6)
tCW
(4)
CE1
CE2
WE
tAW
(6)
tCW
tAS
High-Z
OUTPUT
INPUT
tDW
tDH
(5)
NOTES:
1. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to
initiate and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to
the second transition edge of the signal that terminates the write.
2.
tWR is measured from the earlier of CE1 or WE going high, or CE2 going LOW at the end of the write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
4. OE = VIL or VIH. However it is recommended to keep OE at VIH during write cycle to avoid bus contention.
5. If CE1 is LOW and CE2 is HIGH during this period, I/O pins are in the output state. Then the data input signals of opposite phase
to the outputs must not be applied to them.
6.
tCW is measured from CE1 going low or CE2 going HIGH to the end of write.
V62C1804096 Rev. 1.0 October 2001
8
V62C1804096
Package Diagrams
36 Ball—8x10 BGA
D
SYMBOL
UNIT.MM
1.05+0.15
0.25±0.05
0.35±.0.05
0.30(TYP)
10.00±0.10
5.25
D1
A
A1
b
6
5
4
3
c
D
D1
E
8.00±0.10
3.75
E1
e
0.75TYP
0.10
aaa
2
1
A
B
C
D
E
F
G
H
b
SOLDER BALL
BOTTOM VIEW
aaa
SIDE VIEW
V62C1804096 Rev. 1.0 October 2001
9
WORLDWIDE OFFICES
V62C1804096
U.S.A.
TAIWAN
SINGAPORE
UK & IRELAND
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
7F, NO. 102
10 ANSON ROAD #23-13
INTERNATIONAL PLAZA
SINGAPORE 079903
PHONE: 65-3231801
FAX: 65-3237013
SUITE 50, GROVEWOOD
BUSINESS CENTRE
STRATHCLYDE BUSINESS
PARK
MIN-CHUAN E. ROAD, SEC. 3
TAIPEI
PHONE: 886-2-2545-1213
FAX: 886-2-2545-1209
BELLSHILL, LANARKSHIRE,
SCOTLAND, ML4 3NQ
PHONE: 44-1698-748515
FAX: 44-1698-748516
NO 19 LI HSIN ROAD
JAPAN
ONZE 1852 BUILDING 6F
2-14-6 SHINTOMI, CHUO-KU
TOKYO 104-0041
PHONE: 03-3537-1400
FAX: 03-3537-1402
SCIENCE BASED IND. PARK
HSIN CHU, TAIWAN, R.O.C.
PHONE: 886-3-579-5888
FAX: 886-3-566-5888
GERMANY
(CONTINENTAL
EUROPE & ISRAEL)
BENZSTRASSE 32
71083 HERRENBERG
GERMANY
PHONE: +49 7032 2796-0
FAX: +49 7032 2796 22
U.S. SALES OFFICES
NORTHWESTERN
3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000
FAX: 408-433-0952
SOUTHWESTERN
302 N. EL CAMINO REAL #200
SAN CLEMENTE, CA 92672
PHONE: 949-361-7873
FAX: 949-361-7807
CENTRAL,
NORTHEASTERN &
SOUTHEASTERN
604 FIELDWOOD CIRCLE
RICHARDSON, TX 75081
PHONE: 214-352-3775
FAX: 214-904-9029
© Copyright , MOSEL VITELIC Inc.
Printed in U.S.A.
The information in this document is subject to change without
notice.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461
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