MH8S64BBKG-10L [MITSUBISHI]

536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM; 536870912 - BIT ( 8388608 - WORD 64位) SynchronousDRAM
MH8S64BBKG-10L
型号: MH8S64BBKG-10L
厂家: Mitsubishi Group    Mitsubishi Group
描述:

536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
536870912 - BIT ( 8388608 - WORD 64位) SynchronousDRAM

存储 内存集成电路 动态存储器 时钟
文件: 总55页 (文件大小:576K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
DESCRIPTION  
Utilizes industry standard 4M x 16 Synchronous DRAMs  
The MH8S64BBKG is 8388608 - word by 64-bit  
Synchronous DRAM module. This consists of eight  
industry standard 4Mx16 Synchronous DRAMs in  
TSOP and one industory standard EEPROM in  
TSSOP.  
TSOP and industry standard EEPROM in TSSOP  
144-pin (72-pin dual in-line package)  
single 3.3V±0.3V power supply  
The mounting of TSOP on a card edge Dual Inline  
package provides any application where high  
densities and large quantities of memory are  
required.  
This is a socket type - memory modules, suitable for  
easy interchange or addition of modules.  
Clock frequency 100MHz(max.)  
Fully synchronous operation referenced to clock rising  
edge  
4 bank operation controlled by BA0,1(Bank Address)  
/CAS latency- 2/3(programmable)  
Burst length- 1/2/4/8/Full Page(programmable)  
Burst type- sequential / interleave(programmable)  
Column access - random  
FEATURES  
CLK Access Time  
Frequency  
(Component SDRAM)  
-7,-7L  
-8,-8L  
6.0ns(CL=3)  
6.0ns(CL=3)  
100MHz  
100MHz  
Auto precharge / All bank precharge controlled by A10  
Auto refresh and Self refresh  
100MHz  
8.0ns(CL=3)  
-10,-10L  
4096 refresh cycle /64ms  
LVTTL Interface  
PC100 compliant  
APPLICATION  
main memory or graphic memory in computer systems  
PCB Outline  
(Front)  
(Back)  
1
2
143  
144  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 1 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
PIN CONFIGURATION  
Front side  
Pin Name  
Back side  
Pin Name  
Front side  
Pin Name  
Back side  
Pin Name  
PIN  
Number  
PIN  
Number  
PIN  
Number  
PIN  
Number  
1
Vss  
DQ0  
DQ1  
DQ2  
DQ3  
Vcc  
2
Vss  
DQ32  
DQ33  
DQ34  
DQ35  
Vcc  
73  
75  
74  
CLK1  
Vss  
NC  
Vss  
3
4
76  
5
6
78  
NC  
NC  
77  
7
8
79  
80  
NC  
NC  
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
52  
54  
56  
58  
60  
62  
64  
66  
68  
70  
72  
81  
Vcc  
82  
Vcc  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
45  
47  
49  
51  
53  
55  
57  
59  
61  
63  
65  
67  
69  
71  
83  
DQ16  
DQ17  
DQ18  
DQ19  
Vss  
84  
DQ48  
DQ49  
DQ50  
DQ51  
Vss  
DQ4  
DQ5  
DQ6  
DQ7  
Vss  
DQ36  
DQ37  
DQ38  
DQ39  
Vss  
86  
85  
88  
87  
89  
90  
91  
92  
93  
DQ20  
DQ21  
DQ22  
DQ23  
Vcc  
94  
DQ52  
DQ53  
DQ54  
DQ55  
Vcc  
DQMB0  
DQMB4  
DQMB5  
Vcc  
96  
95  
DQMB1  
Vcc  
97  
98  
99  
100  
102  
104  
106  
108  
110  
112  
114  
116  
118  
120  
122  
124  
126  
128  
130  
132  
134  
136  
138  
140  
142  
144  
A0  
A3  
101  
103  
105  
107  
109  
111  
113  
115  
117  
119  
121  
123  
125  
127  
129  
131  
133  
135  
137  
139  
141  
143  
A1  
A4  
A6  
A7  
A2  
A5  
A8  
BA0  
Vss  
Vss  
Vss  
Vss  
DQ8  
DQ9  
DQ10  
DQ11  
Vcc  
DQ40  
DQ41  
DQ42  
DQ43  
Vcc  
A9  
BA1  
A10  
A11  
Vcc  
Vcc  
DQMB2  
DQMB3  
Vss  
DQMB6  
DQMB7  
Vss  
DQ12  
DQ13  
DQ14  
DQ15  
Vss  
DQ44  
DQ45  
DQ46  
DQ47  
Vss  
DQ24  
DQ25  
DQ26  
DQ27  
Vcc  
DQ56  
DQ57  
DQ58  
DQ59  
Vcc  
NC  
NC  
DQ28  
DQ29  
DQ30  
DQ31  
Vss  
DQ60  
DQ61  
DQ62  
DQ63  
Vss  
NC  
NC  
CLK0  
Vcc  
CKE0  
Vcc  
/RAS  
/WE  
/S0  
/CAS  
CKE1  
NC  
SDA  
Vcc  
SCL  
/S1  
Vcc  
NC  
NC = No Connection  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 2 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
Block Diagram  
/S0  
/S1  
DQMB4  
DQML  
DQML  
DQML  
DQML  
/CS  
/CS  
/CS  
/CS  
DQMB0  
DQ0  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
D0  
D4  
D2  
D6  
DQMU  
DQMU  
DQMU  
DQMU  
DQMB1  
DQMB5  
I/O 8  
I/O 8  
I/O 8  
I/O 8  
DQ8  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
DQ9  
I/O 9  
I/O 9  
I/O 9  
I/O 9  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
I/O 10  
I/O 11  
I/O 12  
I/O 13  
I/O 14  
I/O 15  
I/O 10  
I/O 11  
I/O 12  
I/O 13  
I/O 14  
I/O 15  
I/O 10  
I/O 11  
I/O 12  
I/O 13  
I/O 14  
I/O 15  
I/O 10  
I/O 11  
I/O 12  
I/O 13  
I/O 14  
I/O 15  
DQMB6  
DQML  
DQML  
DQML  
DQML  
/CS  
DQMB2  
/CS  
/CS  
/CS  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
I/O 0  
I/O 1  
I/O 2  
I/O 3  
I/O 4  
I/O 5  
I/O 6  
I/O 7  
D1  
D5  
D3  
D7  
DQMU  
DQMU  
DQMU  
DQMU  
DQMB3  
DQMB7  
I/O 8  
I/O 8  
I/O 8  
I/O 8  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
I/O 9  
I/O 9  
I/O 9  
I/O 9  
I/O 10  
I/O 11  
I/O 12  
I/O 13  
I/O 14  
I/O 15  
I/O 10  
I/O 11  
I/O 12  
I/O 13  
I/O 14  
I/O 15  
I/O 10  
I/O 11  
I/O 12  
I/O 13  
I/O 14  
I/O 15  
I/O 10  
I/O 11  
I/O 12  
I/O 13  
I/O 14  
I/O 15  
10W  
CLK1  
CLK0  
CKE0  
CKE1  
/RAS  
/CAS  
/WE  
4loads  
4loads  
D0 - D3  
D4 - D7  
D0 - D7  
D0 - D7  
D0 - D7  
SERIAL PD  
A0 A1 A2  
SDA  
SCL  
BA0,BA1,A<11:0>  
Vcc  
D0 - D7  
D0 - D7  
Vss  
D0 - D7  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
3
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
Serial Presence Detect Table I  
Byte  
0
Function described  
Defines # bytes written into serial memory at module mfgr  
Total # bytes of SPD memory device  
Fundamental memory type  
SPD enrty data  
128  
SPD DATA(hex)  
80  
08  
04  
0C  
08  
02  
40  
00  
01  
1
256 Bytes  
SDRAM  
A0-A11  
A0-A7  
2
3
# Row Addresses on this assembly  
# Column Addresses on this assembly  
# Module Banks on this assembly  
4
5
2BANK  
x64  
6
Data Width of this assembly...  
7
... Data Width continuation  
0
8
Voltage interface standard of this assembly  
SDRAM Cycletime at Max. Supported CAS Latency (CL).  
LVTTL  
9
10ns  
A0  
Cycle time for CL=3  
10  
SDRAM Access from Clock  
tAC for CL=3  
6ns  
60  
80  
00  
80  
10  
00  
01  
8F  
04  
06  
-7,7L,-8,8L  
-10,10L  
8ns  
11  
12  
13  
14  
15  
16  
17  
18  
DIMM Configuration type (Non-parity,Parity,ECC)  
Refresh Rate/Type  
Non-PARITY  
self refresh(15.625uS)  
SDRAM width,Primary DRAM  
x16  
Error Checking SDRAM data width  
Minimum Clock Delay,Back to Back Random Column Addresses  
Burst Lengths Supported  
N/A  
1
1/2/4/8/Full page  
4bank  
# Banks on Each SDRAM device  
CAS# Latency  
2/3  
19  
20  
21  
22  
23  
CS# Latency  
Write Latency  
0
01  
01  
00  
0E  
0
SDRAM Module Attributes  
SDRAM Device Attributes:General  
non-buffered,non-registered  
Precharge All,Auto precharge  
-7,7L  
10ns  
13ns  
15ns  
6ns  
SDRAM Cycle time(2nd highest CAS latency)  
Cycle time for CL=2  
A0  
D0  
-8,8L  
-10,10L  
-7,7L  
F0  
60  
SDRAM Access form Clock(2nd highest CAS latency)  
tAC for CL=2  
24  
-8,8L  
7ns  
8ns  
N/A  
70  
80  
00  
-10,10L  
25  
SDRAM Cycle time(3rd highest CAS latency)  
SDRAM Access form Clock(3rd highest CAS latency)  
N/A  
00  
14  
26  
27  
-7,7L,-8,8L  
-10,10L  
Precharge to Active Minimum  
20ns  
30ns  
20ns  
20ns  
1E  
14  
14  
28  
29  
Row Active to Row Active Min.  
RAS to CAS Delay Min  
-7,7L,-8,8L  
-10,10L  
30ns  
50ns  
1E  
32  
-7,7L,-8,8L  
30  
Active to Precharge Min  
-10,10L  
60ns  
3C  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
4
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
Serial Presence Detect Table II  
31  
32  
Density of each bank on module  
32MByte  
2ns  
08  
20  
00  
Command and Address signal input setup time -7,7L,-8,8L  
-10,10L  
Command and Address signal input hold time -7,7L,-8,8L  
-10,10L  
N/A  
33  
1ns  
N/A  
10  
00  
20  
00  
34  
35  
Data signal input setup time  
Data signal input hold time  
-7,7L,-8,8L  
-10,10L  
2ns  
N/A  
-7,7L,-8,8L  
-10,10L  
1ns  
10  
00  
00  
12  
01  
N/A  
36-61  
62  
Superset Information (may be used in future)  
option  
rev 1.2A  
rev 1  
-7,7L,-8,8L  
SPD Revision  
-10,10L  
63  
Checksum for bytes 0-62  
Check sum for -7,7L  
Check sum for -8,-8L  
Check sum for -10,-10L  
MITSUBISHI  
05  
45  
42  
64-71  
72  
Manufactures Jedec ID code per JEP-108E  
Manufacturing location  
1CFFFFFFFFFFFFFF  
Miyoshi,Japan  
Tajima,Japan  
01  
02  
03  
04  
NC,USA  
Germany  
73-90  
Manufactures Part Number  
4D483853363442424B472D374C2020202020  
4D483853363442424B472D37202020202020  
MH8S64BBKG-7  
MH8S64BBKG-7L  
4D483853363442424B472D38202020202020  
MH8S64BBKG-8  
MH8S64BBKG-8L  
MH8S64BBKG-10  
4D483853363442424B472D384C2020202020  
4D483853363442424B472D31302020202020  
4D483853363442424B472D31304C20202020  
MH8S64BBKG-10L  
PCB revision  
91-92  
93-94  
95-98  
99-125  
126  
Revision Code  
rrrr  
yyww  
ssssssss  
00  
Manufacturing date  
year/week code  
serial number  
option  
Assembly Serial Number  
Manufacture Specific Data  
Intetl specification frequency  
-7,7L-8,8L  
-10,10L  
100MHz  
66MHz  
64  
66  
CF  
-7,7L  
127  
Intel specification CAS# Latency support  
Unused storage locations  
-8,8L  
CD  
06  
-10,10L  
128+  
open  
00  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
5
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
PIN FUNCTION  
Master Clock:All other inputs are referenced to the rising  
edge of CK  
CLK  
(CLK0 ~ CLK1)  
Input  
Input  
Clock Enable:CKE controls internal clock.When CKE is  
low,internal clock for the following cycle is ceased. CKE is  
also used to select auto / self refresh. After self refresh  
mode is started, CKE E becomes asynchronous input.Self  
refresh is maintained as long as CKE is low.  
CKE0, CKE1  
Chip Select: When /S is high,any command means  
No Operation.  
/S0, /S1  
Input  
Input  
/RAS,/CAS,/WE  
Combination of /RAS,/CAS,/WE defines basic commands.  
A0-11 specify the Row/Column Address in conjunction with  
BA0,1.The Row Address is specified by A0-11.The Column  
Address is specified by A0-7.A10 is also used to indicate  
precharge option.When A10 is high at a read / write  
A0-11  
Input  
command, an auto precharge is performed. When A10 is  
high at a precharge command, both banks are precharged.  
Bank Address:BA0,1 is not simply BA.BA specifies the  
bank to which a command is applied.BA0,1 must be set  
with ACT,PRE,READ,WRITE commands  
BA0,1  
Input  
Data In and Data out are referenced to the rising edge of  
CK  
Input/Output  
DQ0-63  
Din Mask/Output Disable:When DQMB is high in burst  
write.Din for the current cycle is masked.When DQMB is high  
in burst read,Dout is disabled at the next but one cycle.  
DQMB0-7  
Vdd,Vss  
Input  
Power Supply Power Supply for the memory mounted module.  
Input  
Serial clock for serial PD  
Serial data for serial PD  
SCL  
SDA  
Output  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 6 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
BASIC FUNCTIONS  
The MH8S64BBKG provides basic functions,bank(row)activate,burst read / write,  
bank(row)precharge,and auto / self refresh.  
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In  
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and  
precharge option,respectively.  
To know the detailed definition of commands please see the command truth table.  
CK  
/S  
Chip Select : L=select, H=deselect  
Command  
/RAS  
/CAS  
Command  
Command  
define basic commands  
/WE  
CKE  
A10  
Refresh Option @refresh  
command  
Precharge Option @precharge or read/write  
command  
Activate(ACT) [/RAS =L, /CAS = /WE =H]  
ACT command activates a row in an idle bank indicated by BA.  
Read(READ) [/RAS =H,/CAS =L, /WE =H]  
READ command starts burst read from the active bank indicated by BA.First output  
data appears after /CAS latency. When A10 =H at this command,the bank is  
deactivated after the burst read(auto-precharge,READA).  
Write(WRITE) [/RAS =H, /CAS = /WE =L]  
WRITE command starts burst write to the active bank indicated by BA. Total data  
length to be written is set by burst length. When A10 =H at this command, the bank is  
deactivated after the burst write(auto-precharge,WRITEA).  
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]  
PRE command deactivates the active bank indicated by BA. This command also  
terminates burst read / write operation. When A10 =H at this command, both banks are  
deactivated(precharge all, PREA).  
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]  
PEFA command starts auto-refresh cycle. Refresh address including bank address are  
generated internally. After this command, the banks are precharged automatically.  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 7 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
COMMAND TRUTH TABLE  
CKE CKE  
/CAS  
A11  
A0-9  
COMMAND  
MNEMONIC  
/RAS  
/WE BA0,1  
A10  
/S  
n-1  
n
Deselect  
DESEL  
NOP  
H
H
X
X
H
L
X
H
X
H
X
H
X
X
X
X
X
X
X
X
No Operation  
Row Adress Entry &  
Bank Activate  
ACT  
H
X
L
L
H
H
V
V
V
V
Single Bank Precharge  
Precharge All Bank  
PRE  
H
H
X
X
L
L
L
L
H
H
L
L
V
X
X
X
L
X
X
PREA  
H
Column Address Entry  
& Write  
WRITE  
WRITEA  
READ  
H
H
H
H
X
X
X
X
L
L
L
L
H
H
H
H
L
L
L
L
L
V
V
V
V
X
X
X
X
L
V
V
V
V
Column Address Entry  
& Write with Auto-  
Precharge  
L
H
L
Column Address Entry  
& Read  
H
H
Column Address Entry  
& Read with Auto  
Precharge  
READA  
H
Auto-Refresh  
Self-Refresh Entry  
Self-Refresh Exit  
REFA  
REFS  
H
H
L
H
L
L
L
H
L
L
L
L
L
H
H
X
H
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
L
L
REFSX  
H
H
X
X
X
H
H
L
X
H
H
L
X
L
X
Burst Terminate  
TERM  
MRS  
H
H
X
V*1  
Mode Register Set  
L
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number  
NOTE:  
1.A7-9 = 0, A0-6 = Mode Address  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 8 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
FUNCTION TRUTH TABLE  
Command  
DESEL  
NOP  
Current State  
IDLE  
/S  
H
L
/RAS /CAS /WE  
Address  
Action  
X
H
H
H
L
X
H
H
L
X
H
L
X
X
NOP  
NOP  
L
BA  
TBST  
ILLEGAL*2  
L
X
H
L
BA,CA,A10  
BA,RA  
READ/WRITE ILLEGAL*2  
L
H
H
L
ACT  
Bank Active,Latch RA  
NOP*4  
L
L
BA,A10  
X
PRE/PREA  
REFA  
L
L
H
Auto-Refresh*5  
Op-Code,  
L
L
L
L
MRS  
Mode Register Set*5  
Mode-Add  
ROW ACTIVE  
H
L
L
X
H
H
X
H
H
X
H
L
X
DESEL  
NOP  
NOP  
X
NOP  
BA  
TBST  
NOP  
Begin Read,Latch CA,  
Determine Auto-Precharge  
Begin Write,Latch CA,  
Determine Auto-Precharge  
Bank Active/ILLEGAL*2  
Precharge/Precharge All  
ILLEGAL  
L
L
H
H
L
L
H
L
BA,CA,A10 READ/READA  
WRITE/  
BA,CA,A10  
WRITEA  
L
L
L
L
L
L
H
H
L
H
L
BA,RA  
ACT  
PRE/PREA  
REFA  
BA,A10  
H
X
Op-Code,  
L
L
L
L
MRS  
ILLEGAL  
Mode-Add  
READ  
H
L
L
X
H
H
X
H
H
X
H
L
X
DESEL  
NOP  
NOP(Continue Burst to END)  
NOP(Continue Burst to END)  
Terminate Burst  
X
TBST  
BA  
Terminate Burst,Latch CA,  
L
L
H
H
L
L
H
L
BA,CA,A10 READ/READA Begin New Read,Determine  
Auto-Precharge*3  
Terminate Burst,Latch CA,  
BA,CA,A10 WRITE/WRITEA Begin Write,Determine Auto-  
Precharge*3  
L
L
L
L
L
L
H
H
L
H
L
BA,RA  
BA,A10  
X
ACT  
PRE/PREA  
REFA  
Bank Active/ILLEGAL*2  
Terminate Burst,Precharge  
ILLEGAL  
H
Op-Code,  
Mode-Add  
L
L
L
L
MRS  
ILLEGAL  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 9 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
FUNCTION TRUTH TABLE(continued)  
Command  
DESEL  
NOP  
Current State  
WRITE  
/S  
H
L
/RAS /CAS /WE  
Address  
Action  
X
H
H
X
H
H
X
H
L
X
X
NOP(Continue Burst to END)  
NOP(Continue Burst to END)  
Terminate Burst  
L
BA  
TBST  
Terminate Burst,Latch CA,  
Begin Read,Determine Auto-  
Precharge*3  
READ/READA  
L
L
H
H
L
L
H
L
BA,CA,A10  
Terminate Burst,Latch CA,  
Begin Write,Determine Auto-  
Precharge*3  
WRITE/  
BA,CA,A10  
WRITEA  
L
L
L
L
L
L
H
H
L
H
L
BA,RA  
BA,A10  
X
ACT  
PRE/PREA  
REFA  
Bank Active/ILLEGAL*2  
Terminate Burst,Precharge  
ILLEGAL  
H
Op-Code,  
L
L
L
L
MRS  
ILLEGAL  
Mode-Add  
READ with  
AUTO  
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DESEL  
NOP  
NOP(Continue Burst to END)  
NOP(Continue Burst to END)  
ILLEGAL  
X
PRECHARGE  
BA  
TBST  
H
BA,CA,A10 READ/READA ILLEGAL  
WRITE/  
L
H
L
L
BA,CA,A10  
ILLEGAL  
WRITEA  
ACT  
L
L
L
L
L
L
H
H
L
H
L
BA,RA  
Bank Active/ILLEGAL*2  
ILLEGAL*2  
BA,A10  
PRE/PREA  
REFA  
H
X
ILLEGAL  
Op-Code,  
L
L
L
L
MRS  
ILLEGAL  
Mode-Add  
WRITE with  
AUTO  
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DESEL  
NOP  
NOP(Continue Burst to END)  
NOP(Continue Burst to END)  
ILLEGAL  
X
PRECHARGE  
TBST  
BA  
H
BA,CA,A10 READ/READA ILLEGAL  
WRITE/  
L
H
L
L
BA,CA,A10  
ILLEGAL  
WRITEA  
ACT  
BA,RA  
BA,A10  
X
L
L
L
L
L
L
H
H
L
H
L
Bank Active/ILLEGAL*2  
ILLEGAL*2  
PRE/PREA  
REFA  
H
ILLEGAL  
Op-Code,  
Mode-Add  
L
L
L
L
MRS  
ILLEGAL  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 10 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
FUNCTION TRUTH TABLE(continued)  
Command  
DESEL  
NOP  
Current State  
PRE -  
/S  
H
L
/RAS /CAS /WE  
Address  
Action  
NOP(Idle after tRP)  
NOP(Idle after tRP)  
ILLEGAL*2  
X
H
H
H
L
X
H
H
L
X
H
L
X
X
CHARGING  
L
BA  
TBST  
L
X
H
L
BA,CA,A10  
BA,RA  
BA,A10  
X
READ/WRITE ILLEGAL*2  
L
H
H
L
ACT  
PRE/PREA  
REFA  
ILLEGAL*2  
L
L
NOP*4(Idle after tRP)  
ILLEGAL  
L
L
H
Op-Code,  
Mode-Add  
X
L
L
L
L
MRS  
ILLEGAL  
ROW  
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
DESEL  
NOP  
NOP(Row Active after tRCD  
NOP(Row Active after tRCD  
ILLEGAL*2  
ACTIVATING  
X
BA  
TBST  
X
H
L
BA,CA,A10  
BA,RA  
BA,A10  
X
READ/WRITE ILLEGAL*2  
H
H
L
ACT  
PRE/PREA  
REFA  
ILLEGAL*2  
ILLEGAL*2  
ILLEGAL  
L
L
H
Op-Code,  
Mode-Add  
L
L
L
L
MRS  
ILLEGAL  
WRITE RE-  
COVERING  
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL  
NOP  
NOP  
X
NOP  
BA  
TBST  
ILLEGAL*2  
X
H
L
BA,CA,A10  
BA,RA  
BA,A10  
X
READ/WRITE ILLEGAL*2  
H
H
L
ACT  
PRE/PREA  
REFA  
ILLEGAL*2  
ILLEGAL*2  
ILLEGAL  
L
L
H
Op-Code,  
Mode-Add  
L
L
L
L
MRS  
ILLEGAL  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 11 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
FUNCTION TRUTH TABLE(continued)  
Current State  
RE-  
/S  
H
L
/RAS /CAS /WE  
Address  
Command  
DESEL  
NOP  
Action  
NOP(Idle after tRC)  
NOP(Idle after tRC)  
X
H
H
H
L
X
H
H
L
X
H
L
X
X
FRESHING  
L
BA  
TBST  
ILLEGAL  
L
X
H
L
BA,CA,A10  
BA,RA  
BA,A10  
X
READ/WRITE ILLEGAL  
L
H
H
L
ACT  
PRE/PREA  
REFA  
ILLEGAL  
ILLEGAL  
ILLEGAL  
L
L
L
L
H
Op-Code,  
Mode-Add  
X
L
L
L
L
MRS  
ILLEGAL  
MODE  
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
DESEL  
NOP  
NOP(Idle after tRSC)  
NOP(Idle after tRSC)  
ILLEGAL  
REGISTER  
SETTING  
X
BA  
TBST  
X
H
L
BA,CA,A10  
BA,RA  
BA,A10  
X
READ/WRITE ILLEGAL  
H
H
L
ACT  
PRE/PREA  
REFA  
ILLEGAL  
ILLEGAL  
ILLEGAL  
L
L
H
Op-Code,  
Mode-Add  
L
L
L
L
MRS  
ILLEGAL  
ABBREVIATIONS:  
H = Hige Level, L = Low Level, X = Don't Care  
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation  
NOTES:  
1. All entries assume that CKE was High during the preceding clock cycle and the current  
clock cycle.  
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,  
depending on the state of that bank.  
3. Must satisfy bus contention, bus turn around, write recovery requirements.  
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.  
5. ILLEGAL if any bank is not idle.  
ILLEGAL = Device operation and / or date-integrity are not guaranteed.  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 12 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
FUNCTION TRUTH TABLE FOR CKE  
CK  
n-1  
CK  
n
Action  
Current State  
/RAS /CAS /WE Add  
/S  
INVALID  
SELF -  
H
L
X
H
H
H
H
H
L
X
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Exit Self-Refresh(Idle after tRC)  
Exit Self-Refresh(Idle after tRC)  
ILLEGAL  
REFRESH*1  
L
L
L
ILLEGAL  
L
L
X
X
X
X
X
X
X
H
X
H
L
ILLEGAL  
L
L
X
X
X
X
X
X
L
NOP(Maintain Self-Refresh)  
INVALID  
L
X
X
X
X
X
L
X
X
X
X
X
L
POWER  
DOWN  
H
L
X
H
L
Exit Power Down to Idle  
NOP(Maintain Self-Refresh)  
Refer to Function Truth Table  
Enter Self-Refresh  
L
ALL BANKS  
IDLE*2  
H
H
H
H
H
H
H
L
H
L
Enter Power Down  
L
H
L
X
H
H
H
L
X
H
H
L
Enter Power Down  
L
ILLEGAL  
L
L
ILLEGAL  
L
L
X
X
X
X
X
X
X
ILLEGAL  
L
L
X
X
X
X
X
X
Refer to Current State = Power Down  
Refer to Function Truth Table  
Begin CK0 Suspend at Next Cycle*3  
Exit CK0 Suspend at Next Cycle*3  
Maintain CK0 Suspend  
X
H
L
X
X
X
X
X
X
X
X
X
X
ANY STATE  
other than  
H
H
L
listed above  
H
L
L
ABBREVIATIONS:  
H = High Level, L = Low Level, X = Don't Care  
NOTES:  
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.  
A minimum setup time must be satisfied before any command other than EXIT.  
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.  
3. Must be legal command.  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
13  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
SIMPLIFIED STATE DIAGRAM  
SELF  
REFRESH  
REFS  
REFSX  
MRS  
MODE  
REFA  
AUTO  
REFRESH  
IDLE  
ACT  
REGISTER  
SET  
CKEL  
CKEH  
CLK  
SUSPEND  
POWER  
DOWN  
CKEL  
CKEH  
ROW  
ACTIVE  
WRITE  
READ  
READA  
READ  
WRITEA  
WRITE  
CKEL  
CKEL  
WRITE  
SUSPEND  
READ  
SUSPEND  
WRITE  
READ  
CKEH  
CKEH  
WRITEA  
READA  
WRITEA  
READA  
PRE  
CKEL  
CKEH  
CKEL  
CKEH  
WRITEA  
SUSPEND  
READA  
SUSPEND  
PRE  
WRITEA  
READA  
PRE  
POWER  
APPLIED  
POWER  
ON  
PRE  
CHARGE  
PRE  
Automatic Sequence  
Command Sequence  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 14 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
POWER ON SEQUENCE  
Before starting normal operation, the following power on sequence is necessary to prevent a  
SDRAM from damaged or malfunctioning.  
1. Clock will be applied at power up along with power.Attempt to maintain CKE high,DQM0-7  
high and NOP condition at the inputs along with power.  
2. Maintain stable power, stable cock, and NOP input conditions for a minimum of 500us.  
3. Issue precharge commands for all banks. (PRE or PREA)  
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.  
5. Issue a mode register set command to initialize the mode register.  
After these sequence, the SDRAM is idle state and ready for normal operation.  
MODE REGISTER  
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode  
register(MRS). The mode register stores these date until the next MRS command, which may  
be issued when both banks are in idle state. After tRSC from a MRS command, the SDRAM is  
ready for new command.  
CK  
/S  
/RAS  
/CAS  
BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0  
WM  
0
0
0
0
0
0
LTMODE  
BT  
BL  
/WE  
V
BA0,1 A11-0  
BL  
BT= 0  
BT= 1  
0 0 0  
0 0 1  
0 1 0  
0 1 1  
1 0 0  
1 0 1  
1 1 0  
1 1 1  
1
2
1
2
CL  
/CAS LATENCY  
4
4
BURST  
0 0 0  
0 0 1  
0 1 0  
0 1 1  
1 0 0  
1 0 1  
1 1 0  
1 1 1  
R
R
2
8
8
LENGTH  
R
R
R
FP  
R
R
R
R
LATENCY  
MODE  
3
R
R
R
R
0
1
SEQUENTIAL  
BURST  
TYPE  
INTERLEAVED  
R:Reserved for Future Use  
FP: Full Page  
BURST  
SINGLE BIT  
0
1
WRITE  
MODE  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 15 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
[ /CAS LATENCY]  
/CAS latency,CL,is used to synchronize the first output data with the CLK frequency,i.e.,the  
speed of CLK determines which CL should be used.First output data is available after CL  
cycles from READ command.  
/CAS Latency Timing(BL=4)  
CK  
ACT  
X
READ  
Y
Command  
Address  
tRCD  
CL=2  
Q0  
Q1  
Q0  
Q2  
Q1  
Q3  
Q2  
DQ  
DQ  
CL=2  
CL=3  
CL=3  
Q3  
[ BURST LENGTH ]  
The burst length,BL,determines the number of consecutive wrutes or reads that will be  
automatically performed after the initial write or read command.For BL=1,2,4,8,full page the  
output data is tristated(Hi-Z) after the last read.For BL=FP (Full Page),the TBST (Burst  
Terminate) command should be issued to stop the output of data.  
Burst Length Timing(CL=2)  
tRCD  
CK  
READ  
ACT  
X
Command  
Y
Address  
Q0  
DQ  
DQ  
BL=1  
BL=2  
BL=4  
BL=8  
BL=FP  
Q0 Q1  
DQ  
DQ  
DQ  
Q0 Q1 Q2 Q3  
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7  
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7  
Q8  
Qm Q0 Q1  
Full Page counter rolls over  
and continues to count.  
m=255  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 16 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
CK  
Read  
Write  
Y
Command  
Y
Address  
Q0  
Q1  
Q2  
Q3  
D0  
D1  
D3  
D2  
DQ  
CL= 3  
/CAS Latency  
BL= 4  
Burst Length  
Burst Length  
Burst Type  
Initial Address  
A2 A1 A0  
BL  
Column Addressing  
Sequential  
Interleaved  
0
0
0
0
1
1
1
1
-
0
0
1
1
0
0
1
1
0
0
1
1
-
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
0
1
2
3
0
1
1
2
3
4
5
6
7
0
1
2
3
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
3
4
5
6
7
0
1
2
3
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
2
3
0
1
1
0
3
2
5
4
7
6
1
0
3
2
1
0
2
3
0
1
6
7
4
5
2
3
0
1
3
2
1
0
7
6
5
4
3
2
1
0
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
8
-
4
2
-
-
-
-
-
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 17 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
OPERATION DESCRIPTION  
BANK ACTIVATE  
The SDRAM has four independent banks. Each bank is activated by the ACT command with  
the bank address(BA0,1). A row is indicated by the row address A11-0. The minimum  
activation interval between one bank and the other bank is tRRD.  
PRECHARGE  
The PRE command deactivates indicated by BA. When both banks are active, the precharge  
all command(PREA,PRE + A10=H) is available to deactivate them at the same time. After tRP  
from the precharge, an ACT command can be issued.  
Bank Activation and Precharge All (BL=4, CL=3)  
CK  
Command  
A0-9,11  
A10  
ACT  
Xa  
ACT READ  
PRE  
ACT  
Xb  
tRRD  
tRAS  
tRP  
Xb  
Xb  
Y
0
tRCD  
Xa  
1
Xb  
BA0,1  
DQ  
00  
01  
00  
01  
Qa0 Qa1 Qa2 Qa3  
Precharge all  
READ  
After tRCD from the bank activation, a READ command can be issued. 1st output date is  
available after the /CAS Latency from the READ, followed by (BL-1) consecutive date when  
the Burst Length is BL. The start address is specified by A7-0, and the address sequence of  
burst data is defined by the Burst Type. A READ command may be applied to any active bank,  
so the row precharge time(tRP) can be hidden behind continuous output data(in case of BL=8)  
by interleaving the dual banks. When A10 is high at a READ command, the  
auto-precharge(READA) is performed. Any command (READ, WRITE, PRE, ACT) to the  
same bank is inhibited till the internal precharge is complete. The internal precharge start  
timing depends on /CAD Latency. The next ACT command can be issued after tRP from the  
internal precharge timing.  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 18 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
Dual Bank Interleaving READ (BL=4, CL=3)  
CK  
Command  
A0-9,11  
A10  
ACT  
Xa  
Xa  
0
READ ACT  
READ PRE  
Y
tRCD  
Y
0
0
Xb  
Xb  
1
0
1
0
0
BA0,1  
DQ  
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2  
Burst Length  
/CAS latency  
READ with Auto-Precharge (BL=4, CL=3)  
CK  
Command  
A0-9,11  
ACT  
Xa  
Xa  
0
READ  
ACT  
Xa  
Xa  
0
tRCD  
tRP  
Y
1
0
A10  
BA0,1  
DQ  
Qa0 Qa1 Qa2 Qa3  
Internal precharge begins  
READ Auto-Precharge Timing (BL=4)  
CK  
Command  
ACT  
READ  
CL=3 DQ  
CL=2 DQ  
Qa0 Qa1 Qa2 Qa3  
Qa0 Qa1 Qa2 Qa3  
Internal Precharge Start Timing  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 19 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
WRITE  
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set  
at the same cycle as the WRITE. Following(BL-1) data are written into the RAM, when the  
Burst Length is BL. The start address is specified by A7-0, and the address sequence of burst  
data is defined by the Burst Type. A WRITE command may be applied to any active bank, so  
the row precharge time(tRP) can be hidden behind continuous input data (in case of BL=8) by  
interleaving the dual banks. From the last input data to the PRE command, the write recovery  
time (tWR) is required. When A10 is high at a WRITE command, the auto-precharge(WRITEA)  
is performed. Any command(READ, WRITE, PRE, ACT) to the same bank is inhibited till the  
internal precharge is complete. The internal precharge begins at tWR after the last input data  
cycle. The next ACT command can be issued after tRP from the internal precharge timing.  
Dual Bank Interleaving WRITE (BL=4)  
CK  
Command  
ACT  
Xa  
Xa  
0
Write ACT  
Write PRE  
tRCD  
tRCD  
Y
0
0
Y
Xb  
Xb  
1
A0-9,11  
A10  
tWR  
0
1
0
0
BA0,1  
DQ  
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3  
Burst Length  
WRITE with Auto-Precharge (BL=4)  
CK  
Command  
A0-9,11  
ACT  
Xa  
Xa  
0
Write  
ACT  
Xa  
Xa  
0
tRCD  
Y
tRP  
1
A10  
BA0,1  
0
tWR  
DQ  
Da0 Da1 Da2 Da3  
Internal precharge begins  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 20 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
[ BURST WRITE ]  
A burst write operation is enabled by setting A9=0 at MRS.A burst write stats in  
the same cycle as a write command set.(The latency of data input is 0.) The  
burst length can be set to 1,2,4,8,and full-page,like burst read operations.  
tRCD  
CK  
READ  
ACT  
X
Command  
Y
Address  
Q0  
DQ  
DQ  
BL=1  
BL=2  
BL=4  
BL=8  
BL=FP  
Q0 Q1  
DQ  
DQ  
DQ  
Q0 Q1 Q2 Q3  
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7  
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7  
Q8  
Qm Q0 Q1  
Full Page counter rolls over  
and continues to count.  
m=255  
[ SINGLE WRITE ]  
A single write operation is enabled by setting A9=1 at MRS.In a single write  
operation,data is written only to the column address specified by the write  
command set cycle without regard to the burst length setting.(The latency of data  
input is 0.)  
CK  
READ  
ACT  
Command  
tRCD  
Y
X
Address  
DQ  
Q0  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 21 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
BURST INTERRUPTION  
[ Read Interrupted by Read ]  
Burst read option can be interrupted by new read of the same or the other bank.  
MH8S64BBKG allows random column access. READ to READ interval is minimum 1 CK  
Read Interrupted by Read (BL=4, CL=3)  
CK  
Command  
A0-9,11  
A10  
READ READ  
READ  
READ  
Yi  
0
Yj  
0
Yk  
0
Yl  
0
BA0,1  
DQ  
0
0
1
0
Qai0 Qaj0 Qaj1 Qbk0 Qbk1 Qbk2 Qal0 Qal1 Qal2 Qal3  
[ Read Interrupted by Write ]  
Burst read operation can be interrupted by write of the same or the other bank. Random  
column access is allowed. In this case, the DQ should be controlled adequately by using the  
DQMB0-7 to prevent the bus contention. The output is disabled automatically 2 cycle after  
WRITE assertion.  
Read Interrupted by Write (BL=4, CL=3)  
CK  
Command  
A0-9,11  
A10  
READ  
Write  
Yi  
0
Yj  
0
0
0
BA0,1  
DQMB0-7  
Q
D
Qai0  
Daj0 Daj1 Daj2 Daj3  
DQM control  
Write control  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 22 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
[ Read Interrupted by Precharge ]  
Burst read operation can be interrupted by precharge of the same or the other bank. Read  
to PRE interval is minimum 1 CK. A PRE command disables the data output, depending on  
the /CAS Latency. The figure below shows examples, when the dataout is terminated.  
Read Interrupted by Precharge (BL=4)  
CK  
Command  
DQ  
READ  
READ  
PRE  
Q1  
Q0  
Q0  
Q2  
Q3  
CL=3  
Command  
DQ  
PRE  
Q1  
Command  
DQ  
PRE  
Q2  
READ  
READ  
Q0  
Q1  
Q1  
Q3  
CL=2  
Command  
DQ  
PRE  
Q0  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 23 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
[ Read Interrupted by Burst Terminate ]  
Similarly to the precharge, burst terminate command,TBST, can interrupt burst read  
operation and disable the data output. READ to TBST interval is minimum of 1 CK. TBST is  
mainly used to interrupt FP bursts.The figure below show examples, of how the output data  
is terminated with TBST.  
Read Interrupted by Burst Terminate (BL=4)  
CK  
Command  
DQ  
READ  
TBST  
Q1  
Q0  
Q2  
Q2  
Q3  
Command  
DQ  
READ  
TBST  
Q0  
CL=3  
Q1  
Command  
DQ  
READ TBST  
Q0  
Command  
DQ  
READ  
READ  
TBST  
Q2  
Q0  
Q0  
Q1  
Q3  
Command  
DQ  
TBST  
Q1  
CL=2  
Q2  
Command  
DQ  
TBST  
READ  
Q0  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
24  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
[ Write Interrupted by Write ]  
Burst write operation can be interrupted by new write of the same or the other bank.  
Random column access is allowed. WRITE to WRITE interval is minimum 1 CK.  
Write Interrupted by Write (BL=4)  
CK  
Command  
A0-9,11  
A10  
Write Write  
Write  
Yk  
0
Write  
Yi  
0
Yj  
0
Yl  
0
BA0,1  
DQ  
0
0
1
0
Dai0 Daj0 Daj1 Dbk0 Dbk1 Dbk2 Dal0 Dal1 Dal2 Dal3  
[ Write Interrupted by Read ]  
Burst write operation can be interrupted by read of the same or the other bank.  
Random column access is allowed. WRITE to READ interval is minimum 1 CK. The  
input data on DQ at the interrupting READ cycle is "don't care".  
Write Interrupted by Read (BL=4, CL=3)  
CK  
Command  
A0-9,11  
A10  
Write READ  
Write  
Yk  
0
READ  
Yi  
0
Yj  
0
Yl  
0
0
0
0
1
BA0,1  
DQMB0-7  
DQ  
Dai0  
Qaj0 Qaj1  
Dak0 Dak1  
Qbl0  
MITSUBISHI  
ELECTRIC  
25  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
[ Write Interrupted by Precharge ]  
Burst write operation can be interrupted by precharge of the same bank. Random  
column access is allowed. Because the write recovery time(tWR) is required between  
the last input data and the next PRE, 3rd data should be masked with DQMB0-7  
shown as below.  
Write Interrupted by Precharge (BL=4)  
CK  
Command  
Write  
PRE  
ACT  
Xb  
Xb  
0
tWR  
tRP  
Yi  
0
A0-9,11  
A10  
0
0
0
BA0,1  
DQMB0-7  
DQ  
Dai0 Dai1  
This data should be masked to satisfy tWR requirement.  
[ Write Interrupted by Burst Terminate ]  
Burst terminate command can terminate burst write operation. In this case, the write  
recovery time is not required and the bank remains active. The figure below shows  
the case 3 words of data are written. Random column access is allowed. WRITE to  
TERM interval is minimum 1 CK.  
Write Interrupted by Burst Terminate (BL=4)  
CK  
Command  
A0-9,11  
A10  
Write  
TERM  
Yi  
0
BA0,1  
0
DQMB0-7  
DQ  
Dai0 Dai1 Dai2  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 26 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
AUTO REFRESH  
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,  
/WE=/CKE=H) command. The refresh address is generated internally. 4096 REFA  
cycle within 64ms refresh 64Mbit memory cells. The auto-refresh is performed on  
4bank alternately(ping-pong refresh). Before performing an auto-refresh, both banks  
must be in the idle state. Additional commands must not be supplied to the device  
before tRC from the REFA command.  
Auto-Refresh  
CK  
/S  
NOP or DESLECT  
/RAS  
/CAS  
/WE  
CKE  
minimum tRC  
A0-11  
BA0,1  
Auto Refresh on Bank 0  
Auto Refresh on Bank 1  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 27 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
SELF REFRESH  
Self-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,  
/WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is  
kept low.During the self-refresh mode, CKE is asynchronous and the only enabled  
input (but asynchronous), all other inputs including CK0 are disabled and ignored, and  
power consumption due to synchronous inputs is saved. To exit the self-refresh,  
supplying stable CK0 inputs, asserting DESEL or NOP command and then asserting  
CKE(REFSX). After tRC from REFSX both banks are in the idle state and a new  
command can be issued after tRC, but DESEL or NOP commands must be asserted  
till then.  
Self-Refresh  
CK  
Stable CK  
/S  
NOP  
/RAS  
/CAS  
/WE  
CKE  
new command  
A0-11  
BA0,1  
X
0
minimum tRC  
for recovery  
Self Refresh Entry  
Self Refresh Exit  
MITSUBISHI  
ELECTRIC  
28  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
CLK SUSPEND  
CKE controls the internal CLK at the following cycle. Figure below shows how CKE  
works. By negating CKE, the next internal CLK is suspended. The purpose of CLK  
suspend is power down, output suspend or input suspend. CKE is a synchronous  
input except during the self-refresh mode. CLK suspend can be performed either  
when the banks are active or idle, but a command at the following cycle is ignored.  
CK  
(ext.CLK)  
CKE  
int.CLK  
Power Down by CKE  
CK  
Standby Power Down  
CKE  
Command  
PRE  
NOP NOP NOP NOP NOP NOP NOP  
Active Power Down  
CKE  
Command  
NOP NOP NOP NOP NOP NOP NOP  
ACT  
DQ Suspend by CKE  
CK  
CKE  
Command  
Write  
D0  
READ  
DQ  
D1  
D2  
D3  
Q0  
Q1  
Q2  
Q3  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
29  
(
/ 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
DQM CONTROL  
DQMB0-7 is a dual function signal defined as the data mask for writes and the output  
disable for reads. During writes, DQMB0-7 masks input data word by word. DQMB0-7  
to write mask latency is 0.  
During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-Z  
latency is 2.  
DQM Function  
CK  
Command  
DQMB0-7  
READ  
Write  
DQ  
D0  
D2  
D3  
Q0  
Q1  
Q3  
masked by DQM=H  
disabled by DQM=H  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
30  
(
/ 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
ABSOLUTE MAXIMUM RATINGS  
Symbol  
Vdd  
Parameter  
Supply Voltage  
Input Voltage  
Condition  
Ratings  
-0.5 ~ 4.6  
Unit  
V
with respect to Vss  
VI  
with respect to Vss  
with respect to Vss  
V
-0.5 ~ Vdd+0.5  
VO  
IO  
Output Voltage  
Output Current  
V
mA  
W
-0.5 ~ Vdd+0.5  
50  
8
Pd  
Power Dissipation  
Operating Temperature  
Ta=25°C  
Topr  
0 ~ 70  
°C  
Tstg  
Storage Temperature  
-40 ~ 100  
°C  
RECOMMENDED OPERATING CONDITION  
(Ta=0 ~ 70°C, unless otherwise noted)  
Limits  
Parameter  
Symbol  
Unit  
Min.  
3.0  
0
Typ.  
3.3  
0
Max.  
3.6  
Vdd  
Vss  
VIH  
VIL  
Supply Voltage  
Supply Voltage  
V
V
V
V
0
High-Level Input Voltage all inputs  
Low-Level Input Voltage all inputs  
2.0  
-0.3  
Vdd+0.3  
0.8  
CAPACITANCE  
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)  
Parameter Test Condition Limits(max.)  
Unit  
pF  
Symbol  
CI(A) Input Capacitance, address pin  
CI(C) Input Capacitance, control pin  
42  
42  
35  
22  
VI = Vss  
f=1MHz  
pF  
pF  
CI(K)  
CI/O  
Input Capacitance, CK pin  
Input Capacitance, I/O pin  
Vi=25mVrms  
pF  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
31  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
AVERAGE SUPPLY CURRENT from Vdd  
(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)  
Limits  
(max)  
Parameter  
Symbol  
Icc1  
Test Condition  
Unit  
mA  
-7, -7L  
-8, -8L  
-10,-10L  
operating current  
one bank active (discrete)  
tRC=min.tCLK=min, BL=1, IOL=min  
548  
448  
16  
16  
precharge stanby current Icc2P  
in power-down mode  
CKE=VILmax,tCLK=15ns  
CKE=CLK=VILmax(fixed)  
mA  
mA  
8
176  
160  
16  
8
176  
160  
16  
Icc2PS  
CKE=/CS=VIHmin,tCLK=15ns(Note)  
CKE=VIHmin,CLK=VILmax(fixed)  
precharge stanby current  
Icc2N  
in non power-down mode  
mA  
mA  
Icc2NS  
mA  
mA  
mA  
mA  
active stanby current  
in power-down mode  
CKE=VILmax,tCLK=15ns  
CKE=CLK=VILmax(fixed)  
Icc3P  
8
8
Icc3PS  
active stanby current  
440  
320  
360  
320  
588  
920  
CKE=/CS=VIHmin,tCLK=15ns  
Icc3N  
Icc3NS  
Icc4  
in non power-down mode  
one bank active (discrete)  
burst current  
CKE=VIHmin,CLK=VILmax(fixed)  
588  
tCLK=min, BL=4, CL=3,IOL=0mAall banks active(discerte)  
tRC=min, tCLK=min  
mA  
mA  
mA  
auto-refresh current  
1200  
Icc5  
self-refresh current  
Icc6  
8
4
8
4
-7, -8,-10  
CKE <0.2V  
mA  
-7L,-8L,-10L  
Note:Input signals are changed one time during 30ns.  
Note:All other pins not under test are 0V.  
AC OPERATING CONDITIONS AND CHARACTERISTICS  
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)  
Limits  
Symbol  
VOH(DC) High-Level Output Voltage(DC) IOH=-2mA  
Low-Level Output Voltage(DC)  
Parameter  
Test Condition  
Unit  
Min. Max.  
2.4  
V
V
VOL(DC)  
IOZOff-stareOutputCurrentQfloatingVO=0 ~ Vdd  
IOL=2mA  
0.4  
-1010 uA
uA
Input Current  
IiVIH=0~Vdd+0.3V
-40  
40  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 32 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
AC TIMING REQUIREMENTS (SDRAM Component)  
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)  
Input Pulse Levels:  
0.8V to 2.0V  
Input Timing Measurement Level: 1.4V  
Limits  
-8,-8L  
Note  
Symbol Parameter  
Unit  
-7,-7L  
-10,-10L  
Min. Max. Min. Max. Min. Max.  
10  
10  
13  
10  
15  
10  
ns  
ns  
CL=2  
CL=3  
tCLK  
CK cycle time  
tCH  
tCL  
tT  
tIS  
tIH  
tRC  
CK High pulse width  
CK Low pilse width  
Transition time of CK  
Input Setup time(all inputs)  
Input Hold time(all inputs)  
Row cycle time  
3
3
1
2
1
70  
20  
50  
20  
10  
20  
3
3
1
2
1
70  
20  
50  
20  
10  
20  
4
4
1
3
1
90  
30  
60  
30  
10  
20  
ns 1  
ns 1  
10 ns  
10  
10  
ns 1  
ns 1  
ns  
ns  
ns  
ns  
ns  
ns  
tRCD Row to Column Delay  
tRAS Row Active time  
tRP  
tWR Write Recovery time  
tRRD Act to Act Deley time  
100K  
100K  
100K  
Row Precharge time  
10  
20  
10  
10  
20  
10  
10  
20  
10  
ns  
ns  
ns  
tCCD  
tRSC Mode Register Set Cycle time  
Self Refresh Exit time  
tREF Refresh Interval time  
Col to Col Delay time  
tSRX  
64  
64  
64 ms  
Note:1 The timing requirements are assumed tT=1ns.If tT is longer than 1ns,(tT-1)ns should  
be added to the parameter.  
1.4V  
1.4V  
Any AC timing is  
referenced to the input  
signal crossing through  
1.4V.  
CK  
Signal  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 33 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
SWITCHING CHARACTERISTICS (SDRAM Component)  
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.165V, Vss = 0V, unless otherwise noted)  
Limits  
-8,-8L  
Symbol Parameter  
-7,-7L  
-10,-10L  
Unit  
ns  
Min. Max. Min. Max. Min. Max.  
tAC  
Access time from CK  
CL=2  
CL=3  
6
6
7
6
8
8
ns  
ns  
Output Hold time  
from CK  
Delay time, output low  
impedance from CK  
Delay time, output high  
impedance from CK  
3
0
3
3
0
3
3
0
3
tOH  
tOLZ  
tOHZ  
ns  
ns  
6
6
8
Note:3 If tr(clock rising time) is longer than 1ns,(tT/2-0.5)ns should be added to parameter.  
Output Load  
Condition  
VTT=1.4V  
CK  
1.4V  
1.4V  
50W  
DQ  
VOUT  
50pF  
Output Timing  
Measurement  
Reference Point  
1.4V  
1.4V  
CK  
DQ  
tOHZ  
tAC  
tOH  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 34 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
Burst Write (single bank) @BL=4  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
CLK  
/CS  
tRC  
tRAS  
tRP  
/RAS  
/CAS  
/WE  
tRCD  
tRCD  
tWR  
CKE  
DQM  
A0-7  
X
X
X
0
Y
X
X
X
0
Y
A10  
A8,9,11  
BA0,1  
DQ  
0
0
0
D0  
D0 D0  
D0  
D0 D0  
WRITE#0  
D0  
D0  
ACT#0  
WRITE#0  
PRE#0  
ACT#0  
Italic parameter indicates minimum case  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 35 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
Burst Write (multi bank) @BL=4  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
CLK  
/CS  
tRC  
tRRD  
tRRD  
tRAS  
tRP  
/RAS  
/CAS  
/WE  
tRCD  
tRCD  
tWR  
tWR  
CKE  
DQM  
A0-7  
X
X
X
0
X
Y
Y
X
X
X
0
X
X
X
2
Y
X
X
1
A10  
A8,9,11  
0
1
0
1
0
BA0,1  
DQ  
D0  
D0 D0  
D0  
D1 D1  
D1  
D1  
D0  
D0  
D0 D0  
ACT#0  
WRITE#0  
ACT#1  
PRE#0  
WRITE#1  
ACT#0 ACT#2 WRITE#0  
PRE#1  
Italic parameter indicates minimum case  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
36  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
Burst Read (single bank) @BL=4 CL=3  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
CLK  
/CS  
tRC  
tRAS  
tRP  
/RAS  
/CAS  
/WE  
tRCD  
tRCD  
CKE  
DQM  
A0-7  
DQM read latency =2  
X
X
X
0
Y
X
X
X
0
Y
A10  
A8,9,11  
0
0
0
BA0,1  
DQ  
CL=3  
Q0  
Q0 Q0  
Q0  
Q0 Q0  
ACT#0  
READ#0  
PRE#0  
ACT#0  
READ#0  
READ to PRE ³ BL allows full data out  
Italic parameter indicates minimum case  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
37  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
Burst Read (multiple bank) @BL=4 CL=3  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
CLK  
/CS  
tRC  
tRRD  
tRRD  
tRAS  
tRP  
/RAS  
/CAS  
/WE  
tRCD  
tRCD  
CKE  
DQM  
A0-7  
DQM read latency =2  
Y
X
X
X
0
X
Y
X
X
Y
X
X
1
X
X
X
A10  
A8,9,11  
BA0,1  
DQ  
X
0
0
1
0
1
2
0
CL=3  
CL=3  
Q0  
Q0 Q0  
Q0  
Q1 Q1  
Q1  
Q1  
Q0  
ACT#0  
READ#0  
ACT#1  
PRE#0  
READ#1  
ACT#0  
READ#0  
PRE#1 ACT#2  
Italic parameter indicates minimum case  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
38  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
Burst Write (multi bank) with Auto-Precharge @BL=4  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
CLK  
/CS  
tRC  
tRRD  
tRRD  
/RAS  
/CAS  
/WE  
tRCD  
tRCD  
tRCD  
BL-1+ tWR + tRP  
BL-1+ tWR + tRP  
CKE  
DQM  
A0-7  
X
X
X
0
X
Y
Y
X
X
X
0
Y
X
X
X
1
Y
X
X
1
A10  
A8,9,11  
0
1
0
1
BA0,1  
DQ  
D0  
D0 D0  
D0  
D1 D1  
D1  
D1  
D0 D0  
D0  
D0 D1  
ACT#0  
ACT#1  
WRITE#0 with  
AutoPrecharge  
ACT#0  
WRITE#0  
ACT#1  
WRITE#1 with  
AutoPrecharge  
WRITE#1  
Italic parameter indicates minimum case  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
39  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
CLK  
/CS  
tRC  
tRRD  
tRRD  
/RAS  
/CAS  
/WE  
tRCD  
tRCD  
tRCD  
BL+tRP  
BL+tRP  
CKE  
DQM  
A0-7  
A10  
DQM read latency =2  
Y
X
X
X
0
X
Y
X
Y
X
X
X
Y
X
X
1
X
X
A8,9,11  
BA0,1  
DQ  
0
1
0
0
1
1
CL=3  
CL=3  
CL=3  
Q0  
Q0 Q0  
Q0  
Q1 Q1  
Q1  
Q1  
Q0 Q0  
ACT#0  
ACT#1  
READ#0 with  
Auto-Precharge  
ACT#0  
READ#0  
READ#1 with  
Auto-Precharge  
ACT#1  
Italic parameter indicates minimum case  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
40  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
Page Mode Burst Write (multi bank) @BL=4  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
CLK  
/CS  
tRRD  
/RAS  
/CAS  
/WE  
tRCD  
CKE  
DQM  
A0-7  
X
X
X
0
X
Y
Y
Y
Y
X
X
1
A10  
A8,9,11  
BA0,1  
DQ  
0
0
1
0
D0  
D0 D0  
D0  
D0 D0  
D0  
D0 D1  
D1  
D1 D1  
D0  
D0 D0  
ACT#0  
WRITE#0  
ACT#1  
WRITE#0  
WRITE#0  
WRITE#1  
Italic parameter indicates minimum case  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
41  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
Page Mode Burst Read (multi bank) @BL=4 CL=3  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
CLK  
/CS  
tRRD  
/RAS  
/CAS  
/WE  
tRCD  
CKE  
DQM  
A0-7  
DQM read latency=2  
Y
X
X
X
0
X
Y
Y
Y
X
X
1
A10  
A8,9,11  
BA0,1  
DQ  
0
0
1
0
CL=3  
CL=3  
CL=3  
Q0  
Q0 Q0  
Q0  
Q0 Q0  
Q0  
Q0 Q1  
Q1  
Q1 Q1  
ACT#0  
READ#0  
READ#0  
READ#0  
ACT#1  
READ#1  
Italic parameter indicates minimum case  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
42  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
Write Interrupted by Write / Read @BL=4  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
CLK  
/CS  
tRRD  
/RAS  
/CAS  
/WE  
tRCD  
tCCD  
CKE  
DQM  
A0-7  
X
X
X
0
X
Y
Y
Y
Y
Y
X
X
1
A10  
A8,9,11  
BA0,1  
0
0
0
1
0
CL=3  
D0  
D0 D0  
D0  
D0 D0  
D1  
D1  
Q0  
Q0  
Q0 Q0  
DQ  
ACT#0  
WRITE#0 WRITE#0 WRITE#0  
READ#0  
ACT#1  
WRITE#1  
Burst Write can be interrupted by Write or Read of any active bank.  
Italic parameter indicates minimum case  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
43  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
Read Interrupted by Read / Write @BL=4 CL=3  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
CLK  
/CS  
tRRD  
/RAS  
/CAS  
/WE  
tRCD  
CKE  
DQM  
A0-7  
DQM read latency=2  
X
X
X
0
X
Y
Y
Y
Y
Y
Y
X
X
1
A10  
A8,9,11  
BA0,1  
DQ  
0
0
0
1
0
0
Q0  
Q0 Q0  
Q0  
Q0 Q0  
Q1  
Q1 Q0  
D0 D0  
WRITE#0  
ACT#0  
READ#0 READ#0 READ#0  
ACT#1  
READ#0  
READ#1  
blank to prevent bus contention  
Burst Read can be interrupted by Read or Write of any active bank.  
Italic parameter indicates minimum case  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
44  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
Write Interrupted by Precharge @BL=4  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
CLK  
/CS  
tRRD  
/RAS  
/CAS  
/WE  
tRCD  
CKE  
DQM  
X
X
X
0
X
Y
Y
X
X
X
1
Y
A0-7  
A10  
X
X
1
A8,9,11  
BA0,1  
DQ  
0
1
0
1
1
D0  
D0 D0  
D0  
D1 D1  
D1  
D1 D1  
ACT#0  
WRITE#0  
PRE#0  
ACT#1  
WRITE#1  
PRE#1  
ACT#1  
WRITE#1  
Burst Write is not interrupted by  
Precharge of the other bank.  
Burst Write is interrupted by  
Precharge of the same bank.  
Italic parameter indicates minimum case  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
45  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
Read Interrupted by Precharge @BL=4 CL=3  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
CLK  
/CS  
tRRD  
tRP  
/RAS  
/CAS  
/WE  
tRCD  
tRCD  
CKE  
DQM  
A0-7  
DQM read latency=2  
Y
X
X
X
0
X
Y
X
X
X
1
Y
X
X
1
A10  
A8,9,11  
BA0,1  
DQ  
0
1
0
1
1
Q0  
Q0 Q0  
Q0  
Q1 Q1  
ACT#0  
READ#0  
ACT#1  
PRE#0  
READ#1  
PRE#1  
ACT#1  
READ#1  
Burst Read is not interrupted  
by Precharge of the other bank.  
Burst Read is interrupted  
by Precharge of the same bank.  
Italic parameter indicates minimum case  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
46  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
Mode Register Setting  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
CLK  
/CS  
tRSC  
tRC  
/RAS  
/CAS  
/WE  
tRCD  
CKE  
DQM  
A0-7  
M
X
X
X
0
Y
A10  
A8,9,11  
BA0,1  
DQ  
0
0
D0  
D0  
D0 D0  
Auto-Ref (last of 8 cycles)  
Mode  
Register  
Setting  
ACT#0  
WRITE#0  
Italic parameter indicates minimum case  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
47  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
Auto-Refresh @BL=4  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
CLK  
/CS  
tRC  
/RAS  
/CAS  
/WE  
tRCD  
CKE  
DQM  
A0-7  
X
X
X
0
Y
A10  
A8,9,11  
BA0,1  
DQ  
0
D0  
D0 D0  
D0  
Auto-Refresh  
Before Auto-Refresh,  
ACT#0  
WRITE#0  
After tRC from Auto-Refresh,  
all banks are idle state.  
all banks must be idle state.  
Italic parameter indicates minimum case  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
48  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
Self-Refresh  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
CLK  
/CS  
CLK can be stopped  
tRC  
/RAS  
/CAS  
/WE  
tSRX  
CKE  
CKE must be low to maintain Self-Refresh  
DQM  
A0-7  
X
X
X
0
A10  
A8,9,11  
BA0,1  
DQ  
Self-Refresh Entry  
Self-Refresh Exit  
ACT#0  
Before Self-Refresh Entry,  
all banks must be idle state.  
After tRC from Self-Refresh Exit,  
all banks are idle state.  
Italic parameter indicates minimum case  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
49  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
DQM Write Mask @BL=4  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
CLK  
/CS  
/RAS  
/CAS  
/WE  
tRCD  
CKE  
DQM  
A0-7  
X
X
X
0
Y
Y
Y
A10  
A8,9,11  
BA0,1  
DQ  
0
0
0
masked  
masked  
D0  
D0 D0  
D0  
D0  
D0  
D0  
ACT#0  
WRITE#0  
WRITE#0  
WRITE#0  
Italic parameter indicates minimum case  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
50  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
DQM Read Mask @BL=4 CL=3  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
CLK  
/CS  
/RAS  
/CAS  
/WE  
tRCD  
CKE  
DQM  
DQM read latency=2  
X
X
X
0
Y
Y
Y
A0-7  
A10  
A8,9,11  
BA0,1  
0
0
0
masked  
masked  
Q0  
Q0 Q0  
READ#0  
Q0  
Q0  
Q0  
Q0  
DQ  
ACT#0  
READ#0  
READ#0  
Italic parameter indicates minimum case  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
51  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
Power Down  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
CLK  
/CS  
/RAS  
/CAS  
/WE  
Standby Power Down  
Active Power Down  
CKE  
CKE latency=1  
DQM  
A0-7  
X
X
X
0
A10  
A8,9,11  
BA0,1  
DQ  
Precharge All  
ACT#0  
Italic parameter indicates minimum case  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
52  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
CLK Suspend @BL=4 CL=3  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17  
CLK  
/CS  
/RAS  
/CAS  
/WE  
tRCD  
CKE  
CKE latency=1  
CKE latency=1  
DQM  
A0-7  
X
X
X
0
Y
Y
A10  
A8,9,11  
BA0,1  
DQ  
0
0
D0  
D0  
D0  
D0  
Q0  
Q0  
Q0  
Q0  
ACT#0  
WRITE#0  
CLK suspended  
READ#0  
CLK suspended  
Italic parameter indicates minimum case  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
53  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
OUTLINE  
31.75  
20.00  
6.00  
4.00  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
( 54 / 55 )  
Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH8S64BBKG -7,-7L,-8,-8L,-10,-10L  
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM  
Keep safety first in your circuit designs!  
Mitsubishi Electric Corporation puts the maximum effort into making  
semiconductor products better and more reliable,but there is always the  
possibility that trouble may occur with them. Trouble with semiconductors  
consideration to safety when making your circuit designs,with appropriate  
measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of  
non-flammable material or (iii) prevention against any malfunction or mishap.  
Notes regarding these materials  
1.These materials are intended as a reference to assist our customers in the  
selection of the Mitsubishi semiconductor product best suited to the  
customer's application;they do not convey any license under any  
intellectual property rights,or any other rights,belonging to Mitsubishi  
Electric Corporation or a third party.  
2.Mitsubishi Electric Corporation assumes no responsibility for any damage,  
or infringement of any third-party's rights,originating in the use of any  
product data,diagrams,charts or circuit application examples contained in  
these materials.  
3.All information contained in these materials,including product data,  
diagrams and charts,represent information on products at the time of  
publication of these materials,and are subject to change by Mitsubishi  
Electric Corporation without notice due to product improvements or other  
reasons. It is therefore recommended that customers contact Mitsubishi  
Electric Corporation or an authorized Mitsubishi Semiconductor product  
distributor for the latest product information before purchasing a product  
listed herein.  
4.Mitsubishi Electric Corporation semiconductors are not designed or  
manufactured for use in a device or system that is used under  
circumstances in which human life is potentially at stake. Please contact  
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor  
product distributor when considering the use of a product contained herein  
for special applications,such as apparatus or systems for transportation,  
vehicular,medical,aerospace,nuclear,or undersea repeater use.  
5.The prior written approval of Mitsubishi Electric Corporation is necessary to  
reprint or reproduce in whole or in part these materials.  
6.If these products or technologies are subject the Japanese export  
control restrictions,they must be exported under a license from the  
Japanese government and cannot be imported into a country other than  
the approved destination.  
Any diversion or reexport contrary to the export control laws and  
regulations of Japan and/or the country of destination is prohibited.  
7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi  
Semiconductor product distributor for further details on these materials or  
the products contained therein.  
MITSUBISHI  
ELECTRIC  
MIT-DS-0291-0.0  
21.Dec.1998  
(
/ 55 )  
55  

相关型号:

MH8S64BBKG-7

536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI

MH8S64BBKG-7L

536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI

MH8S64BBKG-8

536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI

MH8S64BBKG-8L

536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI

MH8S64BMG-10

536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI

MH8S64BMG-7

536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI

MH8S64BMG-8

536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI

MH8S64DALD-6

536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
MITSUBISHI

MH8S64DALD-7

536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
MITSUBISHI

MH8S64DALD-8

536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
MITSUBISHI

MH8S64DBKG-6

536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI

MH8S64DBKG-6L

536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI