MH8S64DALD-7 [MITSUBISHI]
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM; 536870912 - BIT （ 8388608 - WORD 64位）同步DRAM
| 型号： | MH8S64DALD-7 |
| 厂家： | 
Mitsubishi Group |
| 描述： | 536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM |
| 文件： | 总55页 (文件大小：695K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
DESCRIPTION
The MH8S64DALD is 8388608 - word by 64-bit
Synchronous DRAM module. This consists of eight
industry standard 8Mx8 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual
Inline package provides any application where
high densities and large quantities of memory are
required.
85pin
1pin
This is a socket type - memory modules, suitable
for easy interchange or addition of modules.
94pin
95pin
10pin
11pin
FEATURES
CLK Access Time
Frequency
(Component SDRAM)
-6
-7
-8
5.4ns(CL=3)
133MHz
6.0ns(CL=2)
6.0ns(CL=3)
100MHz
100MHz
124pin
125pin
40pin
41pin
Utilizes industry standard 8M x 8 Sy nchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
Max. Clock frequency -6:133MHz,-7,8:100MHz
Fully synchronous operation referenced to clock
rising edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
84pin
168pin
Auto precharge / All bank precharge controlled
by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
Discrete IC and module design conform to
PC100/PC133 specification.
APPLICATION
PC main memory
MITSUBISHI
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ELECTRIC
( 1 / 55 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
PIN NO. PIN NAME
PIN NO. PIN NAME
PIN NO.
PIN NAME
PIN NO. PIN NAME
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
VSS
NC
85
86
VSS
1
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
2
CKE0
NC
87
3
/S2
88
4
DQMB2
DQMB3
NC
DQMB6
DQMB7
NC
89
5
90
6
91
7
VDD
VDD
NC
92
8
NC
NC
NC
93
9
NC
94
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
NC
NC
95
NC
96
VSS
VSS
97
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
VDD
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
DQ46
DQ47
NC
DQ48
DQ49
DQ50
DQ51
VDD
DQ52
NC
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
DQ20
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
NC
VSS
NC
DQ21
DQ22
DQ23
VSS
VSS
DQ53
DQ54
DQ55
VSS
NC
NC
NC
VDD
/WE0
VDD
/CAS
DQMB4
DQMB5
NC
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
DQMB0
DQMB1
/S0
NC
/RAS
VSS
VSS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
CK2
CK3
NC
NC
A10
BA1
VDD
VDD
CK0
BA0
SA0
SA1
SA2
VDD
WP
SDA
SCL
VDD
A11
VDD
CK1
NC
NC = No Connection
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Block Diagram
/S0
DQMB0
DQMB4
DQM /CS
I/O 0
DQM /CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
DQ32
I/O 1
I/O 2
I/O 1
DQ33
D4
D0
I/O 2
I/O 3
DQ34
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ35
I/O 4
I/O 5
I/O 6
I/O 7
DQ36
DQ37
DQ38
DQ39
DQMB1
DQMB5
DQM /CS
I/O 0
DQM /CS
I/O 0
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 1
DQ9
I/O 1
D5
D1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/S2
DQMB2
DQMB6
DQM /CS
I/O 0
DQM /CS
I/O 0
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 1
I/O 1
D2
D6
I/O 2
I/O 3
I/O 4
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 5
I/O 6
I/O 7
DQMB3
DQMB7
DQM /CS
I/O 0
DQM /CS
I/O 0
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 1
I/O 1
D3
D7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CK0
4SDRAMs+3.3pF cap.
4SDRAMs+3.3pF cap.
CK2
/RAS
/CAS
/WE
D0 - D7
D0 - D7
D0 - D7
CK1
CK3
BA0,BA1,A<11:0>
Vcc
D0 - D7
D0 - D7
SERIAL PD
A0 A1 A2
SCL
WP
47K
SDA
Vss
D0 - D7
D0 - D7
CKE0
SA0 SA1 SA2
MITSUBISHI
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MIT-DS-0339-0.0
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(
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Serial Presence Detect Table I
Byte
0
SPD enrty data
128
SPD DATA(hex)
Function described
Defines # bytes written into serial memory at module mfgr
Total # bytes of SPD memory device
Fundamental memory type
80
08
04
0C
09
01
40
00
1
256 Bytes
SDRAM
A0-A11
A0-A8
2
3
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
4
5
1BANK
x64
6
7
... Data Width continuation
0
8
Voltage interface standard of this assembly
LVTTL
7.5ns
01
75
9
SDRAM Cycletime at Max. Supported CAS Latency (CL).
Cycle time for CL=3
-6
-7,-8
10ns
5.4ns
6ns
A0
54
60
-6
10
SDRAM Access from Clock
tAC for CL=3
-7,-8
11
12
13
14
15
16
17
Non-PARITY
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
00
80
self refresh(15.625uS)
x8
SDRAM width,Primary DRAM
08
00
N/A
Error Checking SDRAM data width
Minimum Clock Delay,Back to Back Random Column Addresses
Burst Lengths Supported
1
01
8F
1/2/4/8/Full page
04
04
06
4bank
3
# Banks on Each SDRAM device
-6
18
CAS# Latency
-7,-8
2/3
19
20
21
22
CS# Latency
Write Latency
01
0
0
01
00
0E
00
non-buffered,non-registered
SDRAM Module Attributes
SDRAM Device Attributes:General
Precharge All,Auto precharge
N/A
-6
23
SDRAM Cycle time(2nd highest CAS latency)
10ns
-7
A0
Cycle time for CL=2
-8
13ns
N/A
6ns
D0
00
-6
-7
24
SDRAM Access form Clock(2nd highest CAS latency)
tAC for CL=2
60
70
7ns
-8
25
26
SDRAM Cycle time(3rd highest CAS latency)
N/A
00
SDRAM Access form Clock(3rd highest CAS latency)
N/A
00
17
-6
22.5ns
27
28
29
30
Precharge to Active Minimum
Row Active to Row Active Min.
-7,-8
20ns
14
-6
15ns
20ns
0F
14
-7,-8
RAS to CAS Delay Min
Active to Precharge Min
-6
-7,-8
-6
22.5ns
20ns
17
14
2D
45ns
-7,-8
50ns
32
MITSUBISHI
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/ 55 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Serial Presence Detect Table II
31
32
Density of each bank on module
64MByte
1.5ns
2ns
10
15
20
08
-6
Command and Address signal input setup time
-7,-8
-6
0.8ns
33
Command and Address signal input hold time
-7,-8
1ns
10
15
-6
-7,-8
-6
1.5ns
34
35
Data signal input setup time
Data signal input hold time
2ns
0.8ns
1ns
20
08
10
-7,-8
Superset Information (may be used in future)
SPD Revision
36-61
62
option
JEDEC2
00
02
-6
-7,-8
rev 1.2A
12
92
Check sum for -6
63
Checksum for bytes 0-62
Check sum for -7
Check sum for -8
MITSUBISHI
Miyoshi,Japan
Tajima,Japan
NC,USA
05
45
Manufactures Jedec ID code per JEP-108E
Manufacturing location
64-71
72
1CFFFFFFFFFFFFFF
01
02
03
Germany
04
4D483853363444414C442D36202020202020
MH8S64DALD-6
4D483853363444414C442D37202020202020
4D483853363444414C442D38202020202020
73-90
Manufactures Part Number
MH8S64DALD-7
MH8S64DALD-8
91-92
93-94
95-98
Revision Code
PCB revision
year/week code
serial number
option
rrrr
yyww
Manufacturing date
Assembly Serial Number
Manufacture Specific Data
ssssssss
00
64
99-125
126
Intetl specification frequency
100MHz
-7
CL=2/3,AP,CK0,2
CL=3,AP,CK0,2
AF
AD
127
Intel specification CAS# Latency support
Unused storage locations
-6,-8
128+
open
00
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
PIN FUNCTION
Master Clock:All other inputs are referenced to the rising
edge of CK
CK
Input
(CK0 ~ CK3)
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
CKE0
Input
Chip Select: When /S is high,any command means
No Operation.
/S
(/S0,2)
Input
Input
/RAS,/CAS,/WE
Combination of /RAS,/CAS,/WE defines basic commands.
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-8.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.
A0-11
Input
Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands
BA0,1
Input
DQ0-63
Data In and Data out are referenced to the rising edge of
CK
Input/Output
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.
DQMB0-7
Vdd,Vss
Input
Power Supply Power Supply for the memory mounted module.
Input
Serial clock for serial PD
SCL
SDA
Output
Input
Serial data for serial PD
SA0-3
Address input for serial PD
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
BASIC FUNCTIONS
The MH8S64DALD provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge.
In addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and
precharge option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S
Chip Select : L=select, H=deselect
Command
/RAS
/CAS
Command
Command
def ine basic commands
/WE
CKE
A10
Ref resh Option @ref resh command
Precharge Option @precharge or read/write command
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank is
deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
terminates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
COMMAND TRUTH TABLE
CKE CKE
/CAS
A11
MNEMONIC
COMMAND
/RAS
/WE BA0,1
A10
A0-9
/S
n-1
n
Deselect
DESEL
NOP
H
H
X
X
H
L
X
H
X
H
X
H
X
X
X
X
X
X
X
X
No Operation
Row Adress Entry &
Bank Activate
ACT
H
X
L
L
H
H
V
V
V
V
Single Bank Precharge
Precharge All Bank
PRE
H
H
X
X
L
L
L
L
H
H
L
L
V
X
X
X
L
X
X
PREA
H
Column Address Entry
& Write
WRITE
WRITEA
READ
H
H
H
H
X
X
X
X
L
L
L
L
H
H
H
H
L
L
L
L
L
V
V
V
V
V
V
V
V
L
V
V
V
V
Column Address Entry
& Write with Auto-
Precharge
L
H
L
Column Address Entry
& Read
H
H
Column Address Entry
& Read with Auto
Precharge
READA
H
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
REFA
REFS
H
H
L
H
L
L
L
H
L
L
L
L
L
H
H
X
H
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
L
L
REFSX
H
H
X
X
X
H
H
L
X
H
H
L
X
L
X
Burst Terminate
TERM
MRS
H
H
X
V*1
Mode Register Set
L
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
FUNCTION TRUTH TABLE
Command
DESEL
NOP
Current State
IDLE
/S
H
L
/RAS /CAS /WE
Address
Action
X
H
H
H
L
X
H
H
L
X
H
L
X
X
NOP
NOP
L
BA
TBST
ILLEGAL*2
L
X
H
L
BA,CA,A10
BA,RA
READ/WRITE ILLEGAL*2
ACT Bank Active,Latch RA
PRE/PREA NOP*4
L
H
H
L
L
L
BA,A10
X
L
L
H
REFA
Auto-Refresh*5
Op-Code,
L
L
L
L
MRS
Mode Register Set*5
Mode-Add
ROW ACTIVE
H
L
L
X
H
H
X
H
H
X
H
L
X
DESEL
NOP
NOP
X
NOP
BA
NOP
TBST
Begin Read,Latch CA,
Determine Auto-Precharge
Begin Write,Latch CA,
Determine Auto-Precharge
Bank Active/ILLEGAL*2
L
L
H
H
L
L
H
L
BA,CA,A10 READ/READA
WRITE/
BA,CA,A10
WRITEA
L
L
L
L
L
L
H
H
L
H
L
BA,RA
ACT
BA,A10
PRE/PREA Precharge/Precharge All
H
X
REFA
ILLEGAL
Op-Code,
L
L
L
L
MRS
ILLEGAL
Mode-Add
READ
H
L
L
X
H
H
X
H
H
X
H
L
X
DESEL
NOP
NOP(Continue Burst to END)
NOP(Continue Burst to END)
Terminate Burst
X
TBST
BA
Terminate Burst,Latch CA,
L
L
H
H
L
L
H
L
BA,CA,A10 READ/READA Begin New Read,Determine
Auto-Precharge*3
Terminate Burst,Latch CA,
BA,CA,A10 WRITE/WRITEA Begin Write,Determine Auto-
Precharge*3
L
L
L
L
L
L
H
H
L
H
L
BA,RA
BA,A10
X
ACT
Bank Active/ILLEGAL*2
PRE/PREA Terminate Burst,Precharge
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
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ELECTRIC
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
FUNCTION TRUTH TABLE(continued)
Command
DESEL
NOP
Current State
WRITE
/S
H
L
/RAS /CAS /WE
Address
Action
X
H
H
X
H
H
X
H
L
X
X
NOP(Continue Burst to END)
NOP(Continue Burst to END)
Terminate Burst
L
BA
TBST
Terminate Burst,Latch CA,
Begin Read,Determine Auto-
Precharge*3
READ/READA
L
L
H
H
L
L
H
L
BA,CA,A10
Terminate Burst,Latch CA,
Begin Write,Determine Auto-
Precharge*3
WRITE/
BA,CA,A10
WRITEA
L
L
L
L
L
L
H
H
L
H
L
BA,RA
BA,A10
X
ACT
Bank Active/ILLEGAL*2
PRE/PREA Terminate Burst,Precharge
H
REFA
ILLEGAL
Op-Code,
L
L
L
L
MRS
ILLEGAL
Mode-Add
READ with
AUTO
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DESEL
NOP
NOP(Continue Burst to END)
NOP(Continue Burst to END)
ILLEGAL
X
PRECHARGE
BA
TBST
H
BA,CA,A10 READ/READA ILLEGAL
WRITE/
L
H
L
L
BA,CA,A10
ILLEGAL
WRITEA
ACT
L
L
L
L
L
L
H
H
L
H
L
BA,RA
Bank Active/ILLEGAL*2
BA,A10
PRE/PREA ILLEGAL*2
H
X
REFA
ILLEGAL
Op-Code,
L
L
L
L
MRS
ILLEGAL
Mode-Add
WRITE with
AUTO
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DESEL
NOP
NOP(Continue Burst to END)
NOP(Continue Burst to END)
ILLEGAL
X
PRECHARGE
TBST
BA
H
BA,CA,A10 READ/READA ILLEGAL
WRITE/
L
H
L
L
BA,CA,A10
ILLEGAL
WRITEA
ACT
BA,RA
BA,A10
X
L
L
L
L
L
L
H
H
L
H
L
Bank Active/ILLEGAL*2
PRE/PREA ILLEGAL*2
H
REFA
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
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MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
FUNCTION TRUTH TABLE(continued)
Command
DESEL
NOP
Current State
PRE -
/S
H
L
/RAS /CAS /WE
Address
Action
NOP(Idle after tRP)
NOP(Idle after tRP)
ILLEGAL*2
X
H
H
H
L
X
H
H
L
X
H
L
X
X
CHARGING
L
BA
TBST
L
X
H
L
BA,CA,A10 READ/WRITE ILLEGAL*2
L
H
H
L
BA,RA
ACT
ILLEGAL*2
L
L
BA,A10
PRE/PREA NOP*4(Idle after tRP)
L
L
H
X
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
L
L
L
L
Mode-Add
ROW
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP
NOP(Row Active after tRCD
NOP(Row Active after tRCD
ILLEGAL*2
ACTIVATING
X
BA
TBST
X
H
L
BA,CA,A10 READ/WRITE ILLEGAL*2
H
H
L
BA,RA
BA,A10
X
ACT
ILLEGAL*2
L
PRE/PREA ILLEGAL*2
L
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
WRITE RE-
COVERING
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP
NOP
X
NOP
BA
TBST
ILLEGAL*2
X
H
L
BA,CA,A10 READ/WRITE ILLEGAL*2
H
H
L
BA,RA
BA,A10
X
ACT
ILLEGAL*2
L
PRE/PREA ILLEGAL*2
L
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
FUNCTION TRUTH TABLE(continued)
Current State
RE-
/S
H
L
/RAS /CAS /WE
Address
Command
DESEL
NOP
Action
NOP(Idle after tRC)
NOP(Idle after tRC)
X
H
H
H
L
X
H
H
L
X
H
L
X
X
FRESHING
L
BA
TBST
ILLEGAL
L
X
H
L
BA,CA,A10 READ/WRITE ILLEGAL
L
H
H
L
BA,RA
ACT
ILLEGAL
L
L
BA,A10
PRE/PREA ILLEGAL
L
L
H
X
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
L
L
L
L
Mode-Add
MODE
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP
NOP(Idle after tRSC)
NOP(Idle after tRSC)
ILLEGAL
REGISTER
SETTING
X
BA
TBST
X
H
L
BA,CA,A10 READ/WRITE ILLEGAL
H
H
L
BA,RA
BA,A10
X
ACT
ILLEGAL
L
PRE/PREA ILLEGAL
L
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
ABBREVIATIONS:
H = Hige Level, L = Low Level, X = Don't Care
BA = Bank Address, RA = Row Address, CA = Column Address, NOP = No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current
clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA,
depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state.May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and / or date-integrity are not guaranteed.
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MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
FUNCTION TRUTH TABLE FOR CKE
CKE CKE
Action
Current State
/RAS /CAS /WE
Add
/S
n-1
n
INVALID
SELF -
H
L
X
H
H
H
H
H
L
X
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Exit Self-Refresh(Idle after tRC)
Exit Self-Refresh(Idle after tRC)
ILLEGAL
REFRESH*1
L
L
L
ILLEGAL
L
L
X
X
X
X
X
X
X
H
X
H
L
ILLEGAL
L
L
X
X
X
X
X
X
L
NOP(Maintain Self-Refresh)
INVALID
L
X
X
X
X
X
L
X
X
X
X
X
L
POWER
DOWN
H
L
X
H
L
Exit Power Down to Idle
NOP(Maintain Self-Refresh)
Refer to Function Truth Table
Enter Self-Refresh
L
ALL BANKS
IDLE*2
H
H
H
H
H
H
H
L
H
L
Enter Power Down
L
H
L
X
H
H
H
L
X
H
H
L
Enter Power Down
L
ILLEGAL
L
L
ILLEGAL
L
L
X
X
X
X
X
X
X
ILLEGAL
L
L
X
X
X
X
X
X
Refer to Current State = Power Down
Refer to Function Truth Table
Begin CK0 Suspend at Next Cycle*3
Exit CK0 Suspend at Next Cycle*3
Maintain CK0 Suspend
X
H
L
X
X
X
X
X
X
X
X
X
X
ANY STATE
other than
H
H
L
listed above
H
L
L
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All banks idle State.
3. Must be legal command.
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Preliminary Spec.
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MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
SIMPLIFIED STATE DIAGRAM
SELF
REFRESH
REFS
REFSX
MRS
REFA
CKEL
CKEH
ACT
POWER
DOWN
CKEL
CKEH
TBST(for Full Page)
TBST(for Full Page)
READ
ROW
ACTIVE
WRITE
READA
READ
WRITEA
WRITE
CKEL
CKEH
CKEL
WRITE
SUSPEND
READ
SUSPEND
WRITE
READ
CKEH
WRITEA
READA
WRITEA
PRE
READA
PRE
CKEL
CKEH
CKEL
CKEH
PRE
POWER
APPLIED
POWER
ON
PRE
CHARGE
PRE
Automatic Sequence
Command Sequence
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MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent
a SDRAM from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQMB0-7 high and NOP
condition at the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200us.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode
register(MRS). The mode register stores these date until the next MRS command, which
may be issue when both banks are in idle state. After tRSC from a MRS command, the
SDRAM is ready for new command.
CK
/S
/RAS
BA0 BA1 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
/CAS
WM
0
0
0
0
0
0
LTMODE
BT
BL
/WE
BA0,1 A11-0
V
BL
BT= 0
BT= 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1
2
1
2
CL
/CAS LATENCY
4
4
BURST
LENGTH
8
8
0 0 0
0 0 1
0 1 0
R
R
2
R
R
R
FP
R
R
R
R
LATENCY
MODE
3
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
R
R
R
R
0
1
SEQUENTIAL
BURST
TYPE
INTERLEAVED
R:Reserved for Future Use
FP: Full Page
BURST
SINGLE BIT
0
1
WRITE
MODE
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Preliminary Spec.
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MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
CK
Read
Y
Write
Y
Command
Address
DQ
Q0
Q1
Q2
Q3
D0
D1
D2
D3
CL= 3
BL= 4
/CAS Latency
Burst Length
Burst Length
Burst Type
Initial Address
A2 A1 A0
BL
Column Addressing
Sequential
Interleaved
0
0
0
0
1
1
1
1
-
0
0
1
1
0
0
1
1
0
0
1
1
-
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
0
1
2
3
0
1
1
2
3
4
5
6
7
0
1
2
3
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
3
4
5
6
7
0
1
2
3
0
1
2
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
2
3
0
1
1
0
3
2
5
4
7
6
1
0
3
2
1
0
2
3
0
1
6
7
4
5
2
3
0
1
3
2
1
0
7
6
5
4
3
2
1
0
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
8
-
4
2
-
-
-
-
-
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Preliminary Spec.
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MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
OPERATION DESCRIPTION
BANK ACTIVATE
One of four banks is activated by an ACT command.
An bank is selected by BA0-1. A row is selected by A0-11.
Multiple banks can be active state concurrently by issuing multiple ACT commands.
Minimum activation interval between one bank and another bank is tRRD.
PRECHARGE
An open bank is deactivated by a PRE command.
A bank to be deactivated is designated by BA0-1.
When multiple banks are active, a precharge all command (PREA, PRE + A10=H)
deactivates all of open banks at the same time. BA0-1 are "Don't Care" in this case.
Minimum delay time of an ACT command after a PRE command to the same bank is tRP.
Bank Activation and Precharge All (BL=4, CL=2)
CK
Command ACT
ACT
Xb
READ
Yb
0
PRE
ACT
Xa
tRCD
tRRD
tRP
A0-9,11
A10
Xa
Xa
Xb
1
Xa
BA0,1 00
DQ
01
01
00
Qa0 Qa1 Qa2 Qa3
Precharge all
READ
A READ command can be issued to any active bank. The start address is specified by A0-8
(x8) . 1st output data is available after the /CAS Latency from the READ. The consecutive data
length is defined by the Burst Length. The address sequence of the burst data is defined by
the Burst Type. Minimum delay time of a READ command after an ACT command to the
same bank is tRCD.
When A10 is high at a READ command, auto-precharge (READA) is performed. Any
command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal
precharge is complete. The internal precharge starts at the BL after READA. The next ACT
command can be issued after (BL + tRP) from the previous READA. In any case, tRCD+BL >
tRASmin must be met.
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Preliminary Spec.
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MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Multi Bank Interleaving READ (BL=4, CL=2)
CK
Command
ACT
READ
ACT
READ PRE
Yb
ACT
tRCD
tRCD
tRP
Xa
Xa
Ya
0
Xb
Xb
Xa
Xa
A0-9, 11
0
0
A10
BA0,1
DQ
00
01
00
00
00
01
Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3
READ with Auto-Precharge (BL=4, CL=2)
CK
Command
ACT
READ
ACT
tRCD
tRP
BL
Xa
Xa
Xa
Xa
Ya
1
A0-9, 11
A10
00
BA0,1 00
00
DQ
Qa0 Qa1 Qa2 Qa3
Internal precharge starts
Auto-Precharge Timing (READ BL=4)
CK
Command
ACT
READ
ACT
tRCD
BL
CL=3 DQ
CL=2 DQ
Qa0 Qa1 Qa2 Qa3
Qa0 Qa1 Qa2 Qa3
Internal precharge starts
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
WRITE
A WRITE command can be issued to any active bank. The start address is specified by A0-8
(x8). 1st input data is set at the same cycle as the WRITE. The consecutive data length to be
written is defined by the Burst Length. The address sequence of burst data is defined by the
Burst Type. Minimum delay time of a WRITE command after an ACT command to the same
bank is tRCD. From the last input data to the PRE command, the write recovery time (tWR) is
required. When A10 is high at a WRITE command, auto-precharge (WRITEA) is performed.
Any command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal
precharge is complete. The internal precharge starts at tWR after the last input data cycle.
The next ACT command can be issued after (BL + tWR -1 + tRP) from the previous WRITEA.
In any case, tRCD + BL + tWR -1 > tRASmin must be met.
WRITE (BL=4)
CK
Command
ACT
Write
PRE
ACT
tRCD
BL
tRP
Ya
0
Xa
Xa
Xa
Xa
A0-9, 11
A10
0
BA0,1
DQ
00
00
00
tWR
Da0 Da1 Da2 Da3
WRITE with Auto-Precharge (BL=4)
CK
Command
ACT
Write
ACT
tRP
tRCD
BL
Xa
Xa
Xa
Xa
Ya
1
A0-9, 11
A10
BA0,1
DQ
00
00
00
tWR
Da0 Da1 Da2 Da3
Internal precharge begins
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Preliminary Spec.
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MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
BURST INTERRUPTION
[ Read Interrupted by Read ]
Burst read oparation can be interrupted by new read of the same or the other bank. Random
column access is allowed READ to READ interval is minimum 1 CK
Read Interrupted by Read (BL=4, CL=2)
CK
Command
A0-9,11
A10
READ
Ya
0
READ READ
Yb
0
Yc
0
BA0,1
00
00
10
DQ
Qa0 Qa1 Qa2 Qb0 Qc0 Qc1
Qc2 Qc3
[ Read Interrupted by Write ]
Burst read operation can be interrupted by write of any active bank. Random column access
is allowed. In this case, the DQ should be controlled adequately by using the DQMB0-7 to
prevent the bus contention. The output is disabled automatically 1 cycle after WRITE
assertion.
Read Interrupted by Write (BL=4, CL=2)
CK
Command
ACT
Xa
READ
Ya
0
Write
Ya
0
A0-9,11
A10
Xa
00
00
00
BA0,1
DQMB0-7
DQ
Qa0
Da0 Da1 Da2 Da3
Output disableby DQM by WRITE
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
[ Read Interrupted by Precharge ]
A burst read operation can be interrupted by precharge of the same bank. Read to PRE
interval is minimum 1 CK. A PRE command output disable latency is equivalent to the
/CAS Latency.
Read Interrupted by Precharge (BL=4)
CK
Command
READ
READ
PRE
Q0
DQ
Q1
Q1
Q2
CL=3
Command
PRE
DQ
Q0
Q0
Command
READ PRE
DQ
Command
DQ
PRE
Q1
READ
Q0
Q2
CL=2
Command
READ
PRE
Q0
DQ
Q1
Command
READ PRE
DQ
Q0
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Preliminary Spec.
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MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
[ Read Interrupted by Burst Terminate ]
Similarly to the precharge, burst terminate command can interrupt burst read operation
and disable the data output. The terminated bank remains active,READ to TBST interval is
minimum of 1 CK. A TBSTcommand to output disable latency is equivalent to the /CAS
Latency.
Read Interrupted by Terminate (BL=4)
CK
Command
DQ
READ
TBST
Q0
Q1
Q1
Q2
Command
DQ
READ
TBST
CL=3
Q0
Q0
Command
DQ
READ TBST
Command
DQ
TBST
Q1
READ
READ
Q0
Q2
Command
DQ
TBST
Q0
CL=2
Q1
Command
DQ
TBST
READ
Q0
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any active bank. Random
column access is allowed. WRITE to WRITE interval is minimum 1 CK.
Write Interrupted by Write (BL=4)
CK
Command
A0-9, 11
A10
Write
Ya
Write Write
Yb
0
Yc
0
0
BA0,1
00
00
10
DQ
Da0 Da1 Da2 Db0 Dc0 Dc1 Dc2 Dc3
[ Write Interrupted by Read ]
Burst write operation can be interrupted by read of any active bank. Random column
access is allowed. WRITE to READ interval is minimum 1 CK. The input data on DQ
at the interrupting READ cycle is "don't care".
Write Interrupted by Read (BL=4, CL=2)
CK
Command
ACT
Write
READ
A0-9,11
A10
Xa
Xa
Ya
0
Yb
0
00
BA0,1
DQ
00
00
Da0 Da1
Qb0 Qb1
Qb2 Qb3
don't care
MITSUBISHI
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17.Sep.1999
( 23/ 55 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank. Write
recovery time(tWR) is required from the last data to PRE command. During write
recovery, data inputs must be masked by DQM.
Write Interrupted by Precharge (BL=4)
CK
Command
ACT
Write
PRE
ACT
tRP
Xa
0
Ya
0
Xa
0
A0-9,11
A10
0
00
00
00
00
BA0,1
DQMB0-7
DQ
tWR
Da0 Da1
[ Write Interrupted by Burst Terminate ]
Burst terminate command can terminate burst write operation. In this case, the
write recovery time is not required and the bank remains active.The WRITE to TBST
minimum interval is 1CK.
Write Interrupted by Burst Terminate (BL=4)
CK
Command
ACT
Xa
Write
Ya
0
TBST
Write
Yb
0
A0-9,11
A10
0
BA0,1
DQ
00
00
00
Da0 Da1
Db0 Db1 Db2 Db3
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
[ Write with Auto-Precharge interrupted by Write or Read to anotehr Bank ]
Burst write with auto-precharge can be interrupted by write or read toanother bank.
Next ACT command can be issued after (BL+tWR-1+tRP) from the WRITEA. Auto-
precharge interrrupted by a command to the same bank is inhibited.
WRITEA Interrupted by WRITE to another bank (BL=4)
CK
Command
Write
Write
BL
ACT
tRP
Ya
1
Ya
0
Xa
Xa
A0-9,11
A10
tWR
00
10
00
BA0,1
DQ
Da0 Da1 Db0 Db1 Db2 Db3
activate
auto-precharge
interrupted
WRITEA interrupted by READ to another bank (CL=2,BL=4)
CK
Write
Ya
1
Command
Read
BL
ACT
Xa
tRP
Yb
A0-9,11
A10
tWR
0
Xa
BA0,1
DQ
00
10
00
Da0 Da1
Db0 Db1 Db2 Db3
activate
auto-precharge interrupted
MITSUBISHI
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17.Sep.1999
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(
/ 55 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
[ Read with Auto-Precharge interrupted by Read to anotehr Bank ]
Burst read with auto-precharge can be interrupted by read toanother bank. Next
ACT command can be issued after (BL+tRP) from the READA. Auto-precharge
interrrupted by a command to the same bank is inhibited.
READA Interrupted by READ to another bank (CL=2,BL=4)
CK
Command
Read
Read
BL
ACT
tRP
Ya
1
Ya
0
Xa
Xa
A0-9,11
A10
tWR
00
10
00
BA0,1
DQ
Qa0 Qa1 Qb0 Qb1 Qb2 Qb3
activate
auto-precharge
interrupted
Full Page Burst
Full page burst length is available for only the sequential burst type. Full page burst
read or write is repeated untill aPrecharge or a Burst Terminate command is
issued. In case of the full page burst , a read or write with auto-precharge command
is illegal.
Single Write
When single write mode is set, burst length for write is always one, independently
of Burst Length defined by (A2-0).
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,
/WE=/CKE=H) command. The refresh address is generated internally. 4096 REFA
cycle within 64ms refresh 64Mbit memory cells. The auto-refresh is performed on
4banks concurrently. Before performing an auto-refresh, all banks must be in the
idle state. Auto-refresh to auto-refresh interval is minimum tRFC. Any command
must not be issued before tRFC from the REFA command.
Auto-Refresh
CK
/S
NOP or DESLECT
/RAS
/CAS
/WE
CKE
minimum tRFC
A0-11
BA0,1
Auto Refresh on All Banks
Auto Refresh on All Banks
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,
/WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is
kept low.During the self-refresh mode, CKE is asynchronous and the only enabled
input , all other inputs including CK are disabled and ignored, so that power
consumption due to synchronous inputs is saved. To exit the self-refresh, supplying
stable CK inputs, asserting DESEL or NOP command and then asserting CKE=H.
After tRFC from the 1st CK edge follwing CKE=H, all banks are in the idle state and
a new command can be issued after, but DESEL or NOP commands must be
asserted till then.
Self-Refresh
CK
Stable CK
/S
NOP
/RAS
/CAS
/WE
CKE
new command
A0-11
BA0,1
X
00
Self Refresh Entry
Self Refresh Exit
minimum tRFC
for recovery
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
CLK SUSPEND and POWER DOWN
CKE controls the internal CLK at the following cycle. Figure below shows how CKE
works. By negating CKE, the next internal CLK is suspended. The purpose of CLK
suspend is power down, output suspend or input suspend. CKE is a synchronous
input except during the self-refresh mode. CLK suspend can be performed either
when the banks are active or idle. A command at the suspended cycle is ignored.
CK
(ext.CLK)
tIH
tIS
tIH
tIS
CKE
int.CLK
Power Down by CKE
CK
CKE
Standby Power Down
Active Power Down
Command
PRE NOP NOP NOP
CKE
Command
NOP NOP NOP
ACT
DQ Suspend by CKE
CK
CKE
Command
Write
D0
READ
DQ
D1
D2
D3
Q0
Q1
Q2
Q3
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
DQM CONTROL
DQMB0-7 is a dual function signal defined as the data mask for writes and the
output disable for reads. During writes, DQMB0-7 masks input data word by word.
DQMB0-7 to Data In latency is 0.
During reads, DQMB0-7 forces output to Hi-Z word by word. DQMB0-7 to output Hi-Z
latency is 2.
DQM Function
CK
Command
DQMB0-7
READ
Write
DQ
D0
D2
D3
Q0
Q1
Q3
masked by DQMB=H
disabled by DQMB=H
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Vdd
Parameter
Supply Voltage
Input Voltage
Condition
Ratings
Unit
V
with respect to Vss
-0.5 ~ 4.6
VI
with respect to Vss -0.5 ~ Vdd+0.5
with respect to Vss -0.5 ~ Vdd+0.5
50
V
VO
IO
Output Voltage
Output Current
V
mA
W
Ta=25°C
8
Pd
Power Dissipation
Operating Temperature
Topr
0 ~ 70
°C
°C
Tstg
Storage Temperature
-40 ~ 100
RECOMMENDED OPERATING CONDITION
(Ta=0 ~ 70°C, unless otherwise noted)
Limits
Parameter
Symbol
Unit
Min.
3.0
0
Typ.
3.3
0
Max.
3.6
Vdd
Vss
VIH
Supply Voltage
Supply Voltage
V
V
V
V
0
High-Level Input Voltage all inputs
Low-Level Input Voltage all inputs
2.0
-0.3
Vdd+0.3
0.8
VIL
Note)
1:VIH(max)=5.5V for pulse width less than 10ns.
2.VIL(min)=-1.0 for pulse width less than 10ns.
CAPACITANCE
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Limits(max.) Unit
Symbol
Parameter
Test Condition
-6
-7,-8
60
pF
(-6)
45.5
CI(A) Input Capacitance, address pin
@1MHz
1.4V bias
200mV swing
pF
pF
pF
Input Capacitance, /RAS,/CAS,/WE
45.5
32.3
16.5
60
40
22
CI(C)
(-7,-8)
CI(K) Input Capacitance, CK pin
VI = Vss
f=1MHz
Vi=25mVrms
Input Capacitance, I/O pin
CI/O
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Limits
(max)
Parameter
operating current
Symbol
Test Condition
Unit
mA
-6
600
16
-7, -8
tRC=min.tCLK=min, BL=1,CL=3
CKE=L,tCLK=15ns, /CS>Vcc-0.2V
560
16
Icc1
one bank activ e (discrete)
precharge stanby
current
mA
mA
Icc2P
in power-down mode
8
160
120
8
160
120
Icc2PS CKE=CLK=L, /CS>Vcc-0.2V
precharge stanby current
in non power-down mode
mA
mA
Icc2N CKE=H,tCLK=15ns,VIH>Vcc-0.2V,VIL<0.2V
Icc2NS
CKE=H,CLK=L,VIH>Vcc-0.2V,VIL<0.2V(f ixed)
active stanby current
in non power-down mode
one bank activ e (discrete)
mA
mA
mA
240
200
240
200
CKE=H,tCLK=15ns
Icc3N
Icc3NS
Icc4
CKE=H,CLK=L
tCLK=min, BL=4, CL=3,all banks active(discerte)
720
560
880
burst current
auto-refresh current
tRC=min, tCLK=min
CKE <0.2V
Icc5
1040
mA
mA
Icc6
8
8
self-refresh current
Note)
1:Icc(max) is specified at the output open condition.
2.Input signals are changed one time during 30ns.
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Limits
Symbol
Parameter
Test Condition
IOH=-2mA
Unit
Min. Max.
2.4
VOH(DC)
VOL(DC)
High-Level Output Voltage(DC)
Low-Level Output Voltage(DC)
V
V
0.4
IOL=2mA
Q floating VO=0 ~ Vdd
-5
5
uA
IOZ
Off-stare Output Current
-40
Input Current
uA
VIH=0 ~ Vdd+0.3V
40
Ii
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
AC TIMING REQUIREMENTS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels: 0.8V to 2.0V
Input Timing Measurement Level: 1.4V
Symbol Parameter
Limits
-7
-6
-8
Unit
Min. Max.
Min. Max. Min. Max.
CL=2
tCLK
10
10
13
ns
CK cycle time
CL=3
7.5
2.5
2.5
1
1.5
0.8
10
3
3
1
2
1
70
80
20
10
3
3
1
2
1
70
80
20
ns
ns
ns
10 ns
ns
tCH
CK High pulse width
tCL
tT
tIS
CK Low pilse width
Transition time of CK
Input Setup time(all inputs)
10
10
tIH
tRC
Input Hold time(all inputs)
Row cycle time
ns
ns
ns
ns
67.5
75
tRFC Refresh cycle time
tRCD Row to Column Delay
20
tRAS
tRP
tWR
tRRD
Row Active time
Row Precharge time
Write Recovery time
45 100K
50 100K
50 100K ns
20
15
15
20
20
20
10
20
20
20
10
ns
ns
ns
ns
Act to Act Deley time
tRSC Mode Register Set Cycle time 10
tSRX Self Refresh Exit time
tPDE Power Down Exit time
tREF Refresh Interval time
7.5
7.5
10
10
64
10
10
ns
ns
64
64 ms
Note:1 The timing requirements are assumed tT=1ns.If tT is longer than 1ns,(tT-1)ns
should be added to the parameter.
Any AC timing is
referenced to the input
signal crossing
through 1.4V.
1.4V
1.4V
CK
Signal
MITSUBISHI
MIT-DS-0339-0.0
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ELECTRIC
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
SWITCHING CHARACTERISTICS (SDRAM Component)
(Ta=0 ~ 70°C, Vdd = 3.3 ± 0.3V, Vss = 0V, unless otherwise note3)
Limits
-6
-7
-8
Symbol Parameter
Unit
ns
Max.
6
Max. Min. Max.
Min.
Min.
tAC
Access time from CK
CL=2
6
6
7
6
CL=3
CL=2
ns
ns
5.4
Output Hold time
from CK
3
3
3
3
3
tOH
CL=3
2.7
ns
Delay time, output low
impedance from CK
Delay time, output high
impedance from CK
tOLZ
tOHZ
0
0
3
0
3
ns
ns
2.7
5.4
6
6
Note)
1 If clock rising time is longer than 1ns,(tT/2-0.5)ns should be added to parameter.
Output Load Condition
VTT=1.4V
For -7,-8
CK
1.4V
50½
VREF=1.4V
VOUT
DQ
1.4V
50pF
50pF
Output Timing
Measurement
Reference Point
For -6
VOUT
1.4V
1.4V
CK
tOLZ
tAC
DQ
tOHZ
tOH
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Burst Write (single bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRAS
tRP
/RAS
/CAS
/WE
tRCD
tRCD
tWR
CKE
DQM
A0-8
A10
X
X
X
0
Y
X
X
X
0
Y
A9,11
BA0,1
DQ
0
0
0
D0
D0 D0
D0
D0 D0
WRITE#0
D0
D0
ACT#0
WRITE#0
PRE#0
ACT#0
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
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MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Burst Write (multi bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRRD
tRRD
tRP
tRAS
/RAS
/CAS
/WE
tRCD
tRCD
tWR
tWR
CKE
DQM
A0-8
X
X
X
0
X
Y
Y
X
X
X
0
X
X
X
2
Y
X
X
1
A10
A9,11
0
1
0
1
0
BA0,1
DQ
D0
D0 D0
D0
D1 D1
D1
D1
D0
D0
D0 D0
ACT#0
WRITE#0
ACT#1
PRE#0
WRITE#1
ACT#0 ACT#2 WRITE#0
PRE#1
Italic parameter indicates minimum case
MITSUBISHI
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/ 55 )
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Burst Read (single bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRAS
tRP
/RAS
/CAS
/WE
tRCD
tRCD
CKE
DQM
A0-8
DQM read latency =2
X
X
X
0
Y
X
X
X
0
Y
A10
A9,11
0
0
0
BA0,1
DQ
CL=3
Q0
Q0 Q0
Q0
Q0 Q0
ACT#0
READ#0
PRE#0
ACT#0
READ#0
READ to PRE ³BL allows full data out
Italic parameter indicates minimum case
MITSUBISHI
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Burst Read (multiple bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRRD
tRRD
tRP
tRAS
/RAS
/CAS
/WE
CKE
tRCD
tRCD
DQM
A0-8
DQM read latency =2
Y
X
X
X
0
X
Y
X
X
X
X
X
X
Y
X
X
1
A10
A9,11
BA0,1
DQ
0
1
0
0
1
2
0
CL=3
CL=3
Q0
Q0 Q0
Q0
Q1 Q1
Q1
Q1
Q0
ACT#0
READ#0
ACT#1
PRE#0
READ#1
ACT#0
READ#0
PRE#1 ACT#2
Italic parameter indicates minimum case
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38
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Burst Write (multi bank) with Auto-Precharge @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRRD
tRRD
/RAS
/CAS
/WE
tRCD
tRCD
tRCD
BL-1+ tWR + tRP
BL-1+ tWR + tRP
CKE
DQM
A0-8
X
X
X
0
X
Y
Y
X
X
X
0
Y
X
X
X
1
Y
X
X
1
A10
A9,11
0
1
0
1
BA0,1
DQ
D0
D0
D0
D0
D1 D1
D1
D1
D0 D0
D0
D0 D1
ACT#0
ACT#1
WRITE#0 with
AutoPrecharge
ACT#0
WRITE#0
ACT#1
WRITE#1 with
AutoPrecharge
WRITE#1
Italic parameter indicates minimum case
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MIT-DS-0339-0.0
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(
39
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
tRRD
tRRD
/RAS
/CAS
/WE
tRCD
tRCD
tRCD
BL+tRP
BL+tRP
CKE
DQM
A0-8
A10
DQM read latency =2
Y
X
X
X
0
X
Y
X
X
X
Y
X
X
X
Y
X
X
1
A9,11
BA0,1
DQ
0
1
0
0
1
1
CL=3
CL=3
CL=3
Q0
Q0 Q0
Q0
Q1 Q1
Q1
Q1
Q0 Q0
ACT#0
ACT#1
READ#0 with
Auto-Precharge
ACT#0
READ#1 with
Auto-Precharge
READ#0
ACT#1
Italic parameter indicates minimum case
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(
40
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Page Mode Burst Write (multi bank) @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-8
X
X
X
0
X
Y
Y
Y
Y
X
X
1
A10
A9,11
BA0,1
DQ
0
0
1
0
D0
D0 D0
D0
D0
D0
D0
D0 D1
D1
D1 D1
D0
D0 D0
ACT#0
WRITE#0
ACT#1
WRITE#0
WRITE#0
WRITE#1
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Page Mode Burst Read (multi bank) @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-8
A10
DQM read latency=2
Y
X
X
X
0
X
Y
Y
Y
X
X
1
A9,11
BA0,1
DQ
0
0
1
0
CL=3
CL=3
CL=3
Q0
Q0 Q0
Q0
Q0
Q0
Q0
Q0 Q1
Q1
Q1 Q1
ACT#0
READ#0
ACT#1
READ#0
READ#0
READ#1
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Write Interrupted by Write / Read @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
CKE
tRCD
tCCD
DQM
A0-8
X
X
X
0
X
Y
Y
Y
Y
Y
X
X
1
A10
A9,11
BA0,1
0
0
0
1
0
CL=3
D0
D0
D0 D0
D0 D0
D1
D1
Q0
Q0
Q0 Q0
DQ
ACT#0
WRITE#0 WRITE#0 WRITE#0
READ#0
ACT#1
WRITE#1
Burst Write can be interrupted by Write or Read of any active bank.
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Read Interrupted by Read / Write @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-8
A10
DQM read latency=2
X
X
X
0
X
Y
Y
Y
Y
Y
Y
X
X
1
A9,11
BA0,1
DQ
0
0
0
1
0
0
Q0
Q0 Q0 Q0
Q0
Q0
Q1
Q1 Q0
D0 D0
ACT#0
READ#0 READ#0 READ#0
ACT#1
READ#0
WRITE#0
READ#1
blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank.
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Write Interrupted by Precharge @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-8
A10
X
X
X
0
X
Y
Y
X
X
X
1
Y
X
X
1
A9,11
BA0,1
DQ
0
1
0
1
1
D0 D0
D0
D1 D1
D1
D1 D1
D0
ACT#0
WRITE#0
PRE#0
ACT#1
WRITE#1
PRE#1
ACT#1
WRITE#1
Burst Write is interrupted by
Precharge of the same bank.
Burst Write is not interrupted
by Precharge of the other bank.
Italic parameter indicates minimum case
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ELECTRIC
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Read Interrupted by Precharge @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRRD
tRP
/RAS
/CAS
/WE
tRCD
tRCD
CKE
DQM
A0-8
A10
DQM read latency=2
Y
X
X
X
0
X
Y
X
X
X
1
Y
X
X
1
A9,11
BA0,1
DQ
0
1
0
1
1
Q0
Q0 Q0
Q0
Q1 Q1
ACT#0
READ#0
ACT#1
PRE#0
READ#1
PRE#1
ACT#1
READ#1
Burst Read is interrupted
by Precharge of the same bank.
Burst Read is not interrupted
by Precharge of the other bank.
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Mode Register Setting
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRSC
tRC
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-8
A10
M
X
X
X
0
Y
A9,11
BA0,1
DQ
0
0
D0
D0 D0 D0
Auto-Ref (last of 8 cycles)
Mode
ACT#0
WRITE#0
Register
Setting
Italic parameter indicates minimum case
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ELECTRIC
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Auto-Refresh @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-8
X
X
X
0
Y
A10
A9,11
BA0,1
DQ
0
D0
D0 D0
D0
Auto-Refresh
Before Auto-Refresh,
ACT#0
WRITE#0
After tRC from Auto-Refresh,
all banks are idle state.
all banks must be idle state.
Italic parameter indicates minimum case
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ELECTRIC
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Self-Refresh
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
tRC
CLK can be stopped
/RAS
/CAS
/WE
tSRX
CKE
DQM
A0-8
A10
CKE must be low to maintain Self-Refresh
X
X
X
0
A9,11
BA0,1
DQ
Self-Refresh Entry
Self-Refresh Exit
ACT#0
Before Self-Refresh Entry,
all banks must be idle state.
After tRC from Self-Refresh Exit,
all banks are idle state.
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
DQM Write Mask @BL=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-8
A10
X
X
X
0
Y
Y
Y
A9,11
BA0,1
DQ
0
0
0
masked
masked
D0
D0 D0
D0
D0
D0
D0
ACT#0
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case
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ELECTRIC
MIT-DS-0339-0.0
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50
Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
DQM Read Mask @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
/WE
CKE
tRCD
DQM read latency=2
DQM
A0-8
X
X
X
0
Y
Y
Y
A10
A9,11
BA0,1
0
0
0
masked
masked
Q0
Q0 Q0
Q0
Q0
Q0
Q0
DQ
ACT#0
READ#0
READ#0
READ#0
Italic parameter indicates minimum case
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Power Down
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
/WE
Standby Power Down
Active Power Down
CKE
DQM
A0-8
CKE latency=1
X
X
X
0
A10
A9,11
BA0,1
DQ
Precharge All
ACT#0
Italic parameter indicates minimum case
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ELECTRIC
MIT-DS-0339-0.0
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
CLK Suspend @BL=4 CL=3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
CLK
/CS
/RAS
/CAS
/WE
tRCD
CKE
DQM
A0-8
A10
CKE latency=1
CKE latency=1
X
X
X
0
Y
Y
A9,11
BA0,1
DQ
0
0
D0
D0
D0
Q0
Q0
Q0
Q0
D0
ACT#0
WRITE#0
CLK suspended
READ#0
CLK suspended
Italic parameter indicates minimum case
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ELECTRIC
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
OUTLINE
MITSUBISHI
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Preliminary Spec.
MITSUBISHI LSIs
Some contents are subject to change without notice.
MH8S64DALD -6,-7,-8
536870912-BIT (8388608 - WORD BY 64-BIT)Synchronous DRAM
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making
semiconductor products better and more reliable,but there is always the
possibility that trouble may occur with them. Trouble with semiconductors
consideration to safety when making your circuit designs,with appropriate
measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of
non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the
customer's application;they do not convey any license under any
intellectual property rights,or any other rights,belonging to Mitsubishi
Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage,
or infringement of any third-party's rights,originating in the use of any
product data,diagrams,charts or circuit application examples contained in
these materials.
3.All information contained in these materials,including product data,
diagrams and charts,represent information on products at the time of
publication of these materials,and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other
reasons. It is therefore recommended that customers contact Mitsubishi
Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product
listed herein.
4.Mitsubishi Electric Corporation semiconductors are not designed or
manufactured for use in a device or system that is used under
circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor when considering the use of a product contained herein
for special applications,such as apparatus or systems for transportation,
vehicular,medical,aerospace,nuclear,or undersea repeater use.
5.The prior written approval of Mitsubishi Electric Corporation is necessary to
reprint or reproduce in whole or in part these materials.
6.If these products or technologies are subject the Japanese export
control restrictions,they must be exported under a license from the
Japanese government and cannot be imported into a country other than
the approved destination.
Any diversion or reexport contrary to the export control laws and
regulations of Japan and/or the country of destination is prohibited.
7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or
the products contained therein.
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ELECTRIC
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17.Sep.1999
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