MH64D64AKQH-75 [MITSUBISHI]
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module; 4,294,967,296位（ 67108864 - WORD 64位），双数据速率同步DRAM模组
| 型号： | MH64D64AKQH-75 |
| 厂家： | 
Mitsubishi Group |
| 描述： | 4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module |
| 文件： | 总40页 (文件大小：361K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
DESCRIPTION
- Utilizes industry standard 32M X 8 DDR Synchronous DRAMs
in Smal TSOP package , industry standard EEPROM(SPD) in
TSSOP package
The MH64D64AKQH is 67108864 - word x 64-bit Double
Data Rate(DDR) Sy nchronous DRAM mounted module.
This consists of 16 industry standard 32M x 8 DDR
Sy nchronous DRAMs in Small TSOP with SSTL_2 interf ace
which achiev es v ery high speed data rate up to 133MHz.
This socket-ty pe memory module is suitable f or main
memory in computer systems and easy to interchange or
add modules.
- 200pin SO-DIMM
- Vdd=Vddq=2.5v ±0.2V
- Double data rate architecture; two data transf ers per
clock cycle
- Bidirectional, data strobe (DQS) is transmitted/receiv ed
with data
- Dif f erential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions with CLK transition edges of DQS
- Commands entered on each positiv e CLK edge
- Data and data mask ref erenced to both edges of DQS
- 4bank operation concontrolled by BA0,BA1(Bank Address
,discrete)
- /CAS latency - 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst Ty pe - sequential/interleav e(programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 ref resh cycles /64ms
FEATURES
CLK
Max.
Access Time
Type name
Frequency
[component level]
+ 0.75ns
MH64D64AKQH-75
MH64D64AKQH-10
133MHz
100MHz
+ 0.8ns
- Auto ref resh and Self ref resh
- Row address A0-12 / Column address A0-9
- SSTL_2 Interf ace
- Module 2bank Conf igration
APPLICATION
Main memory unit for Note PC, Mobile etc.
PCB Outline
(Front)
(Back)
1
2
199
200
MIT-DS-0418-0.1
MITSUBISHI
ELECTRIC
17.May.2001
1
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
PIN CONFIGURATION
PIN
NO.
PIN
NO.
86
PIN
NO.
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
PIN
NO.
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
PIN
PIN
NO.
2
PIN
PIN
NO.
85
PIN
NAME
NC
PIN
NAME
NC
PIN
NAME
DQS6
DQ50
Vss
PIN
NAME
DM6
DQ54
Vss
NAME
Vref
NAME
Vref
1
3
5
Vss
4
Vss
87
Vss
CK2
/CK2
Vdd
CKE1
NC
88
Vss
Vss
Vdd
Vdd
CKE0
NC
DQ0
DQ1
Vdd
6
DQ4
DQ5
Vdd
89
90
7
8
91
92
DQ51
DQ56
Vdd
DQ55
DQ60
Vdd
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
93
94
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
DQS0
DQ2
Vss
DM0
DQ6
Vss
95
96
97
98
DQ57
DQS7
Vss
DQ61
DM7
Vss
99
A12
A9
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
A11
A8
DQ3
DQ8
Vdd
DQ7
DQ12
Vdd
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
Vss
A7
Vss
A6
DQ58
DQ59
Vdd
DQ62
DQ63
Vdd
DQ9
DQS1
Vss
DQ13
DM1
Vss
A5
A4
A3
A2
SDA
SA0
A1
A0
SCL
SA1
Vdd
BA1
/RAS
/CAS
/S1
DQ10
DQ11
Vdd
DQ14
DQ15
Vdd
Vdd
A10/AP
BA0
/WE
/S0
VddSPD
VddID
SA2
NC
CK0
/CK0
Vss
Vdd
Vss
Vss
NC
NC
NC: No Connect
DQ16
DQ17
Vdd
DQ20
DQ21
Vdd
Vss
DQ32
DQ33
Vss
DQ36
DQ37
DQS2
DQ18
Vss
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
DM2
DQ22
Vss
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
Vdd
DQS4
DQ34
Vss
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
Vdd
DM4
DQ38
Vss
DQ19
DQ24
Vdd
DQ23
DQ28
Vdd
DQ35
DQ40
Vdd
DQ39
DQ44
Vdd
DQ25
DQS3
Vss
DQ29
DM3
Vss
DQ41
DQS5
Vss
DQ45
DM5
Vss
DQ26
DQ27
Vdd
DQ30
DQ31
Vdd
DQ42
DQ43
Vdd
DQ46
DQ47
Vdd
NC
NC
NC
NC
Vdd
/CK1
CK1
Vss
Vss
Vss
NC
NC
Vss
Vss
NC
NC
DQ48
DQ49
Vdd
DQ52
DQ53
Vdd
Vdd
Vdd
NC
NC
MIT-DS-0418-0.1
MITSUBISHI
ELECTRIC
17.May.2001
2
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
Block Diagram
/S0
/S1
DQS4
DM4
DQS0
DM0
DQ32
/S DQS
/S DQS
DQ0
/S DQS
/S DQS
DM
DM
DM
DM
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ1
DQ2
DQ3
D4
D12
DQ4
DQ5
D0
D8
DQ6
DQ7
DQS5
DM5
DQ40
DQS1
DM1
DQ8
DQS
DQS
/S
/S
DQS
DQS
/S
/S
DM
DM
DM
DM
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D5
D13
D1
D9
DQS6
DM6
DQS2
DM2
DQ16
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
/S DQS
/S DQS
/S DQS
/S DQS
DM
DM
DM
DM
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D6
D14
D2
D10
DQS7
DM7
DQS3
DM3
DQ24
DQ56
DQS
DQS
/S
/S
/S DQS
/S DQS
DM
DM
DM
DM
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D7
D15
D3
D11
22W
SERIAL PD
SCL
SA0
SA1
SA2
SDA
A0
A1
A2
CKE0
CK0
D0 - D7
8loads
8loads
CKE1
/RAS
/CAS
/CK0
D8-D15
WP
NOTE: DQ wiring may differ from that
described in this drawing; however
DQ/DM/DQS relationships are
maintained as shown.
CK1
/CK1
CK2
D0 - D15
D0 - D15
D0 - D15
SPD
VddSPD
Vdd
/WE
D0 - D15
0loads
BA0,BA1,
A<12:0>
/CK2
Vdd ID strap connections:
Vref
D0 - D15
D0 - D15
(for memory device Vdd, VddQ)
Strap out (open): Vdd=VddQ
Strap in (closed): Vdd=VddQ
D0 - D15
Vss
VddID
MIT-DS-0418-0.1
MITSUBISHI
ELECTRIC
17.May.2001
3
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
PIN FUNCTION
SYMBOL
TYPE
DESCRIPTION
Clock: CK0-2 and /CK0-2 are dif f erential clock inputs. All address and control
input signals are sampled on the crossing of the positiv e edge of CK0-2 and
negativ e edge of /CK0-2. Output (read) data is ref erenced to the crossings of
CK0-2 and /CK0-2 (both directions of crossing).
CK0-2,/CK0-2
Input
Clock Enable: CKE0-1 controls internal clock. When CKE0-1 is low, internal
clock f or the f ollowing cycle is ceased. CKE0-1 is also used to select auto /
self ref resh. After self ref resh mode is started, CKE0-1 becomes
asy nchronous input. Self ref resh is maintained as long as CKE is low.
Input
CKE0-1
Chip Select: When /S0-1 is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
/S0-1
Input
Input
/RAS, /CAS, /WE
A0-12 specif y the Row / Column Address in conjunction with BA0,1. The Row
Address is specif ied by A0-12. The Column Address is specif ied by A0-9.
A10 is also used to indicate precharge option. When A10 is high at a read / write
command, an auto precharge is perf ormed. When A10 is high at a precharge
command, all banks are precharged.
A0-12
BA0-1
Input
Input
Bank Address: BA0-1 specif ies one of f our banks in SDRAM to which a command
is applied. BA0-1 must be set with ACT, PRE, READ, WRITE commands.
DQ 0-63
DQS0-7
Input / Output
Input / Output
Data Input/Output: Data bus
Data Strobe: Output with read data, input with write data. Edge-aligned with read
data, centered in write data. Used to capture write data.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM0-7 is
sampled HIGH along with that input data during a WRITE access. DM0-7 is sampled on both
edges of DQS0-7. Although DM pins are input only, the DM0-7 loading matches the DQ0-63 and
DQS0-7 loading.
Input
DM0-7
Power Supply for the memory array and peripheral circuitry.
Vdd, Vss
Power Supply
Power Supply Power Supply for SPD
Vddspd
Vref
Input
SSTL_2 reference voltage.
This is a bidirectional pin used to transf er data into or out of the SPD EEPROM.
A resistor must be connected to Vdd to act as a pullup.
Input / Output
SDA
This signal is used to clock data into and out of the SPD EEPROM. A resistor
may be connected f rom the SCL to Vdd to act as a pullup.
SCL
Input / Output
Input
Address pins used to select the Serial Presence Detect.
Vdd identif ication f lag
SA0-2
VddID
Output
MIT-DS-0418-0.1
MITSUBISHI
ELECTRIC
17.May.2001
4
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
BASIC FUNCTIONS
The MH64D64AKQH provides basic functions, bank (row) activate, burst read / write, bank
(row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS,
/CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip
select, refresh option, and precharge option, respectively. To know the detailed definition of
commands, please see the command truth table.
/CK0
CK0
/S0
Chip Select : L=select, H=deselect
Command
/RAS
/CAS
/WE
Command
Command
def ine basic commands
Ref resh Option @ref resh command
CKE0
A10
Precharge Option @precharge or read/write command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data
appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the
burst read (auto-precharge,READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be
written is set by burst length. When A10 =H at this command, the bank is deactivated after
the burst write (auto-precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates
burst read /write operation. When A10 =H at this command, all banks are deactivated
(precharge all, PREA).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE0 =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are
generated internally. After this command, the banks are precharged automatically.
MIT-DS-0418-0.1
MITSUBISHI
ELECTRIC
17.May.2001
5
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
COMMAND TRUTH TABLE
CKE
n-1
CKE
n
A0-9,
11-12
A10
/AP
note
COMMAND
MNEMONIC
/S
/RAS /CAS /WE BA0,1
Deselect
DESEL
NOP
H
H
X
X
H
X
H
X
H
X
H
X
X
X
X
X
X
No Operation
L
L
Row Address Entry &
Bank Activate
ACT
H
H
L
H
H
V
V
V
Single Bank Precharge
Precharge All Banks
PRE
H
H
H
H
L
L
L
L
H
H
L
L
V
X
L
X
X
PREA
H
Column Address Entry
& Write
WRITE
H
H
L
H
L
L
V
L
V
Column Address Entry
& Write with
WRITEA
READ
H
H
H
H
L
L
H
H
L
L
L
V
V
H
L
V
V
Auto-Precharge
Column Address Entry
& Read
H
Column Address Entry
& Read with
READA
H
H
L
H
L
H
V
H
V
Auto-Precharge
Auto-Refresh
REFA
REFS
H
H
L
H
L
L
L
H
L
L
L
L
L
H
H
X
H
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
V
Self-Refresh Entry
Self-Refresh Exit
L
L
H
H
H
H
X
H
H
L
X
H
H
L
REFSX
L
1
2
Burst Terminate
TERM
MRS
H
H
Mode Register Set
L
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. Applies only to read bursts with autoprecharge disabled; this command is undefined (and should
not be used) for read bursts with autoprecharge enabled, and for write bursts.
2. BA0-BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode
Register; BA0 = 1, BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are
reserved; A0-A12 provide the op-code to be written to the selected Mode Register.
MIT-DS-0418-0.1
MITSUBISHI
ELECTRIC
17.May.2001
6
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE
Current State /S /RAS /CAS /WE
Address
Command
DESEL
NOP
Action
Notes
IDLE
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
NOP
X
NOP
BA
TERM
ILLEGAL
2
2
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL
ACT Bank Active, Latch RA
PRE / PREA NOP
H
H
L
4
5
L
L
H
REFA
MRS
Auto-Refresh
Op-Code,
Mode-Add
5
L
L
L
L
Mode Register Set
ROW ACTIVE
H
L
L
X
H
H
X
H
H
X
H
L
X
DESEL
NOP
NOP
NOP
NOP
X
BA
TERM
Begin Read, Latch CA,
L
L
H
H
L
L
H
L
BA, CA, A10
BA, CA, A10
READ / READA
Determine Auto-Precharge
WRITE /
WRITEA
Begin Write, Latch CA,
Determine Auto-Precharge
2
L
L
L
L
L
L
H
H
L
H
L
BA, RA
BA, A10
X
ACT
Bank Active / ILLEGAL
PRE / PREA Precharge / Precharge All
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
H
L
L
X
H
H
X
H
H
X
H
L
X
DESEL
NOP
NOP (Continue Burst to END)
NOP (Continue Burst to END)
Terminate Burst
READ
(Auto-
X
Precharge
Disabled)
BA
TERM
Terminate Burst, Latch CA,
3
2
L
L
H
H
L
L
H
L
BA, CA, A10
BA, CA, A10
READ / READA Begin New Read, Determine
Auto-Precharge
WRITE
ILLEGAL
WRITEA
L
L
L
L
L
L
H
H
L
H
L
BA, RA
BA, A10
X
ACT
Bank Active / ILLEGAL
PRE / PREA Terminate Burst, Precharge
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MIT-DS-0418-0.1
MITSUBISHI
ELECTRIC
17.May.2001
7
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE (continued)
/S
H
Current State
/RAS /CAS /WE
Address
Command
DESEL
Action
Notes
X
X
X
X
NOP (Continue Burst to END)
WRITE
(Auto-
L
L
H
H
H
H
H
L
X
NOP
NOP (Continue Burst to END)
ILLEGAL
Precharge
Disabled)
BA
TERM
Terminate Burst, Latch CA,
3
L
H
L
H
BA, CA, A10
READ / READA Begin Read, Determine Auto-
Precharge
Terminate Burst, Latch CA,
WRITE /
3
2
L
L
H
L
L
L
BA, CA, A10
BA, RA
Begin Write, Determine Auto-
WRITEA
Precharge
H
H
ACT
Bank Active / ILLEGAL
L
L
L
L
H
L
L
BA, A10
X
PRE / PREA Terminate Burst, Precharge
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DESEL
NOP
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
READ with
AUTO
X
PRECHARGE
BA
TERM
H
BA, CA, A10
READ / READA ILLEGAL
WRITE /
L
H
L
L
BA, CA, A10
ILLEGAL
WRITEA
2
2
L
L
L
L
L
L
H
H
L
H
L
BA, RA
BA, A10
X
ACT
Bank Active / ILLEGAL
PRE / PREA PRECHARGE/ILLEGAL
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DESEL
NOP
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
WRITE with
AUTO
X
PRECHARGE
BA
TERM
H
BA, CA, A10
READ / READA ILLEGAL
WRITE /
ILLEGAL
WRITEA
L
H
L
L
BA, CA, A10
2
2
L
L
L
L
L
L
H
H
L
H
L
BA, RA
ACT
Bank Active / ILLEGAL
BA, A10
PRE / PREA PRECHARGE/ILLEGAL
H
X
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MIT-DS-0418-0.1
MITSUBISHI
ELECTRIC
17.May.2001
8
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE (continued)
Current State /S
/RAS /CAS /WE
Address
Command
DESEL
NOP
Action
NOP (Idle after tRP)
NOP (Idle after tRP)
ILLEGAL
Notes
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
PRE -
CHARGING
X
2
BA
TERM
2
2
4
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL
ACT ILLEGAL
PRE / PREA NOP (Idle after tRP)
H
H
L
L
L
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP
NOP (Row Active after tRCD)
NOP (Row Active after tRCD)
ILLEGAL
ROW
ACTIVATING
X
2
2
BA
TERM
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL
ACT ILLEGAL
PRE / PREA ILLEGAL
2
2
H
H
L
L
L
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP
NOP
WRITE RE-
COVERING
X
NOP
2
2
BA
TERM
ILLEGAL
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL
ACT ILLEGAL
PRE / PREA ILLEGAL
2
2
H
H
L
L
L
H
REFA
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
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MITSUBISHI LSIs
Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE (continued)
Current State /S
/RAS /CAS /WE
Address
Command
DESEL
NOP
Action
NOP (Idle after tRC)
NOP (Idle after tRC)
ILLEGAL
Notes
H
X
H
H
H
L
X
H
H
L
X
H
L
X
RE-
FRESHING
L
L
L
L
L
L
X
BA
TERM
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL
ACT ILLEGAL
PRE / PREA ILLEGAL
H
H
L
L
L
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP
NOP (Idle after tRSC)
NOP (Idle after tRSC)
ILLEGAL
MODE
REGISTER
SETTING
X
BA
TERM
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL
ACT ILLEGAL
PRE / PREA ILLEGAL
H
H
L
L
L
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation
NOTES:
1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of
that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
MIT-DS-0418-0.1
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MITSUBISHI LSIs
Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE for CKE
CKE0 CKE0
/S0 /RAS /CAS
Current State
/WE Add
Action
Notes
n
n-1
1
1
1
1
1
H
L
X
X
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
SELF-
REFRESH
H
H
H
H
H
L
Exit Self-Refresh (Idle after tRC)
Exit Self-Refresh (Idle after tRC)
ILLEGAL
L
L
L
L
L
X
X
X
X
X
X
X
H
X
H
L
ILLEGAL
1
1
L
L
X
X
X
X
X
X
L
ILLEGAL
L
X
X
X
X
X
L
X
X
X
X
X
L
NOP (Maintain Self-Refresh)
INVALID
H
L
X
H
L
POWER
DOWN
Exit Power Down to Idle
NOP (Maintain Self-Refresh)
Refer to Function Truth Table
Enter Self-Refresh
L
2
H
H
H
H
H
H
H
L
H
L
ALL BANKS
IDLE
2
2
2
L
H
L
X
H
H
H
L
X
H
H
L
Enter Power Down
L
Enter Power Down
2
2
2
L
L
ILLEGAL
L
L
X
X
X
X
X
X
X
ILLEGAL
L
L
X
X
X
X
X
X
ILLEGAL
2
X
H
L
X
X
X
X
X
X
X
X
X
X
Refer to Current State =Power Down
Refer to Function Truth Table
Begin CLK Suspend at Next Cycle
Exit CLK Suspend at Next Cycle
Maintain CLK Suspend
H
H
L
ANY STATE
other than
3
3
listed above
H
L
L
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
asynchronously
1. CKE Low to High transition will re-enable CK0 and other inputs
. A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
MIT-DS-0418-0.1
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
SIMPLIFIED STATE DIAGRAM
POWER
PRE
CHARGE
ALL
APPLIED
SELF
POWER
ON
PREA
REFRESH
REFS
MRS
MRS
REFSX
MODE
REGISTER
SET
REFA
AUTO
IDLE
ACT
REFRESH
CKEL
CKEH
Active
Power
Down
POWER
DOWN
CKEL
CKEH
ROW
BURST
STOP
ACTIVE
WRITE
READ
WRITE
READ
WRITEA
READA
READ
WRITE
READ
TERM
WRITEA
READA
READA
PRE
PRE
WRITEA
READA
PRE
PRE
CHARGE
Automatic Sequence
Command Sequence
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM
from damaged or multifunctioning.
1. Apply VDD before or the same time as VDDQ
2. Apply VDDQ before or at the same time as VTT & Vref
3. Maintain stable condition for 200us after stable power and CLK, apply NOP or DSEL
4. Issue precharge command for all banks of the device
5. Issue EMRS
6. Issue MRS for the Mode Register and to reset the DLL
7. Issue 2 or more Auto Refresh commands
8. Maintain stable condition for 200 cycle
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
CK0
Burst Length, Burst Type and /CAS Latency can be programmed by
setting the mode register (MRS). The mode register stores these data until
the next MRS command, which may be issued when all banks in discrete
are in idle state. After tMRD from a MRS command, the DDR DIMM is
ready for new command.
/CK0
/S0
/RAS
/CAS
/WE
BA1
0
BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
BA0
0
0
0
0
DR
0
LTMODE
BT
BL
0
BA1
V
A12-A0
BL
BT= 0
BT= 1
R
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
R
2
CL
/CAS Latency
2
4
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
R
R
2
4
Burst
8
8
Length
R
R
R
R
R
R
R
R
Latency
Mode
R
R
R
2.5
R
0
1
Burst
Type
Sequential
Interleaved
NO
0
1
DLL
YES
Reset
R: Reserved for Future Use
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
EXTENDED MODE REGISTER
DLL disable / enable mode can be programmed by setting the extended
mode register (EMRS). The extended mode register stores these data
until the next EMRS command, which may be issued when all banks in
discrete are in idle state. After tRSC from a EMRS command, the DDR DIMM
is ready for new command.
CK0
/CK0
/S0
/RAS
/CAS
/WE
BA1
0
BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
QFC DS DD
BA0
BA1
1
0
0
0
0
0
0
0
0
0
0
V
A12-A0
DLL
0
1
DLL enable
Disable
DLL disable
Drive
0
1
Normal
Weak
Strength
0
1
Disable
Enable
QFC
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
/CLK
CLK
Command
Read
Y
Write
Y
Address
DQS
DQ
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Burst
Burst
/CAS
CL= 2
Length
Length
Latency
BL= 4
Initial Address
A2 A1 A0
BL
Column Addressing
Sequential
Interleaved
0
0
0
0
1
1
1
1
-
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
0
1
1
2
3
4
5
6
7
0
1
2
2
3
4
5
6
7
0
1
2
3
3
4
5
6
7
0
1
2
3
0
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
1
0
3
2
5
4
7
6
1
0
2
3
0
1
6
7
4
5
2
3
3
2
1
0
7
6
5
4
3
2
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
8
-
4
2
-
-
1
1
0
1
2
3
3
0
0
1
1
2
2
3
3
2
0
1
1
0
-
-
-
-
0
1
0
1
1
0
0
1
1
0
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
ABSOLUTE MAXIMUM RATINGS
Symbol
Vdd
VI
Parameter
Supply Voltage
Conditions
Ratings
-0.5 ~ 3.7
-0.5 ~ Vdd+0.5
-0.5 ~ Vdd+0.5
50
Unit
V
with respect to Vss
with respect to Vss
with respect to Vss
Input Voltage
V
VO
Output Voltage
V
IO
Output Current
mA
W
16
Pd
Power Dissipation
Operating Temperature
Storage Temperature
Ta = 25°C
Topr
Tstg
0 ~ 70
°C
°C
-45 ~ 100
DC OPERATING CONDITIONS
(Ta=0 ~ 70°C , unless otherwise noted)
Limits
Symbol
Parameter
Unit Notes
Min.
2.3
Typ.
Max.
Vdd
Vref
Supply Voltage
2.5
2.7
V
V
Input Reference Voltage
High-Level Input Voltage
0.49*Vdd
Vref + 0.18
-0.3
0.5*Vdd
0.51*Vdd
5
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VTT
Vdd+0.3
V
V
V
V
V
Low-Level Input Voltage
Vref - 0.18
Vdd + 0.3
Vdd + 0.6
Vref + 0.04
Input Voltage Level, CK0 and /CK0
Input Differential Voltage, CK0 and /CK0
I/O Termination Voltage
-0.3
0.36
7
6
Vref - 0.04
CAPACITANCE
(Ta=0 ~ 70°C , Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)
Parameter
Limits(max.)
Notes
11
Symbol
CI(A)
Test Condition
Unit
pF
Input Capacitance, address pin
Input Capacitance, control pin
Input Capacitance, CK0 pin
Input Capacitance, I/O pin
80
80
45
20
VI - 1.25V
f=100MHz
VI = 25mVrm
pF
11
CI(C)
CI(K)
pF
pF
11
11
CI/O
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70°C , Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
Limits(max)
Symbol
Parameter/Test Conditions
Unit Notes
mA
-75
-10
OPERATING CURRENT: One Bank(Discrete); Activ e-Precharge;
t RC = t RC MIN; t CK = t CK MIN; DQ, DM and DQS inputs changing
twice per clock cycle; address and control inputs changing once per
clock cycle
IDD0
1480
1400
OPERATING CURRENT: One Bank(Discrete); Activ e-Read-Precharge;
Burst = 2; t RC = t RC MIN; CL = 2.5; t CK = t CK MIN; IOUT= 0
mA;Address and control inputs changing once per clock cycle
IDD1
1520
320
640
480
1440
320
640
480
mA
mA
mA
mA
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
power-down mode; CKE VIL (MAX); t CK = t CK MIN
IDD2P
IDLE STANDBY CURRENT: /CS > VIH (MIN); All banks idle;
IDD2N CKE > VIH (MIN); t CK = t CK MIN; Address and other control inputs
changing once per clock cycle
ACTIVE POWER-DOWN STANDBY CURRENT: One bank activ e;
IDD3P
power-down mode; CKE VIL (MAX); t CK = t CK MIN
ACTIVE STANDBY CURRENT: /CS > VIH (MIN); CKE > VIH (MIN);
One bank; Activ e-Precharge; t RC = t RAS MAX; t CK = t CK MIN;
IDD3N
1040
1960
1920
960
1840
1800
mA
mA
DQ,DM and DQS inputs changing twice per clock cycle; address and
other control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;One
IDD4R bank activ e(Discrete); Address and control inputs changing once per
clock cycle; CL = 2.5; t CK = t CK MIN; IOUT = 0 mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
bank activ e(Discrete); Address and control inputs changing once per
IDD4W
mA
mA
clock cycle; CL = 2.5; t CK = t CK MIN; DQ, DM and DQS inputs
changing twice per clock cycle
IDD5
IDD6
AUTO REFRESH CURRENT: t RC = t RFC (MIN)
SELF REFRESH CURRENT: CKE 0.2V
2960
48
2800
48
9
mA
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70°C
, Vdd = VddQ = 2.5 ± 0.2V, Vss =VssQ= 0V, unless otherwise noted)
Limits
Symbol
Parameter/Test Conditions
Unit Notes
Min.
Max.
VIH(AC) High-Level Input Voltage (AC)
VIL(AC) Low-Level Input Voltage (AC)
Vref + 0.35
V
V
Vref - 0.35
Vdd + 0.6
0.5*Vdd+0.2
10
VID(AC) Input Differential Voltage, CLK and /CLK
VIX(AC) Input Crossing Point Voltage, CLK and /CLK
0.7
0.5*Vdd-0.2
-10
V
7
8
V
µA
IOZ
Ii
Off-state Output Current /Q floating Vo=0~VDDQ
Input Current / VIN=0 ~ VddQ
µA
32
-32
MIT-DS-0418-0.1
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MITSUBISHI LSIs
Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
AC TIMING REQUIREMENTS (Component Level)
(Ta=0 ~ 70°C
, Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)
AC Characteristics
Parameter
-75
-10
Symbol
Min.
-0.75
-0.75
0.45
0.45
7.5
Max.
+0.75
+0.75
0.55
0.55
15
Min.
-0.8
-0.8
0.45
0.45
8
Max.
+0.8
+0.8
0.55
0.55
15
Unit Notes
tAC
DQ Output Valid data delay time f rom CLK//CLK
ns
ns
tDQSCK DQ Output Valid data delay time f rom CLK//CLK
tCH
tCL
CLK High lev el width
CLK Low lev el width
tCK
tCK
ns
CL=2.5
CL=2
tCK
CLK cycle time
10
15
10
15
ns
tDS
tDH
Input Setup time (DQ,DM)
Input Hold time(DQ,DM)
0.5
0.6
0.6
2
ns
0.5
ns
tDIPW
tHZ
DQ and DM input pulse width (f or each input)
Data-out-high impedance time f rom CLK//CLK
Data-out-low impedance time f rom CLK//CLK
1.75
-0.75
-0.75
ns
+0.75
+0.75
+0.5
-0.8
-0.8
+0.8
+0.8
+0.6
ns
ns
ns
14
14
tLZ
tDQSQ DQ Valid data delay time f rom DQS
tCLmin
or
tCLmin
or
tHP
tQH
Clock half period
ns
ns
tCHmin
tCHmin
tHP-
0.75
Output DQS v alid window
tHP-1.0
tDQSS Write command to f irst DQS latching transition
tDQSH DQS input High lev el width
0.75
0.35
0.35
0.2
0.2
15
1.25
0.75
0.35
0.35
0.2
0.2
15
1.25
tCK
tCK
tCK
tCK
tCK
ns
tDQSL DQS input Low lev el width
tDSS
tDSH
tMRD
DQS f alling edge to CLK setup time
DQS f alling edge hold time f rom CLK
Mode Register Set command cycle time
tWPRES Write preamble setup time
tWPST Write postamble
0
0
ns
16
15
0.4
0.25
0.9
0.9
0.4
0.9
0.6
0.4
0.25
1.1
1.1
0.4
0.9
0.6
tCK
tCK
ns
tWPRE Write preamble
tIS
tIH
Input Setup time (address and control)
Input Hold time (address and control)
19
19
ns
tRPST Read postamble
tRPRE Read preamble
0.6
1.1
0.6
1.1
tCK
tCK
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MITSUBISHI LSIs
Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
AC TIMING REQUIREMENTS(Continues)
(Ta=0 ~ 70°C
, Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)
AC Characteristics
Parameter
-75
-10
Symbol
tRAS
tRC
Min.
45
65
75
20
20
15
15
35
1
Max.
120,000
Min.
50
70
80
20
20
15
15
35
1
Max.
Unit Notes
Row Active time
120,000 ns
Row Cycle time(operation)
ns
ns
tRFC
Auto Ref. to Active/Auto Ref. command period
Row to Column Delay
tRCD
tRP
ns
Row Precharge time
ns
tRRD
tWR
Act to Act Delay time
ns
Write Recovery time
ns
tDAL
Auto Precharge write recovery + precharge time
Internal Write to Read Command Delay
Exit Self Ref. to non-Read command
Exit Self Ref. to -Read command
Exit Power down to command
Exit Power down to -Read command
Average Periodic Refresh interval
ns
tWTR
tXSNR
tXSRD
tXPNR
tXPRD
tREFI
tCK
ns
75
200
1
80
200
1
tCK
tCK
tCK
us
1
1
18
17
7.8
7.8
Output Load Condition
(f or component measurement)
VREF
DQS
VTT=VREF
50ohm
Zo=50 ohm
30pF
DQ
VREF
VO U
VREF
Output Timing
Measurement
Reference
Point
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MITSUBISHI
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Preliminary Spec.
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
Notes
1. All voltages referenced to Vss.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still
referenced to VREF (or to the crossing point for CK//CK), and parameter specifications are guaranteed for the specified
AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range
between VIL(AC) and VIH(AC).
4. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver will effectively switch
as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back
above (below) the DC input LOW (HIGH) level.
5. VREF is expected to be equal to 0.5*VddQ of the transmitting device, and to track variations in the DC level of the
same. Peak-to-peak noise on VREF may not exceed +/-2% of the DC value.
6. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set
equal to VREF, and must track variations in the DC level of VREF.
7. VID is the magnitude of the difference between the input level on CLK and the input level on /CLK.
8. The value of VIX is expected to equal 0.5*VddQ of the transmitting device and must track variations in the DC level of
the same.
9. Enables on-chip refresh and address counters.
10. IDD specification are tested after the device is properly initialized.
11. This parameter is sampled. VddQ = +2.5V+/-0.2V, Vdd = +2.5V+/-0.2V, f =100MHz, Ta = 25 OC , VOUT(DC)=
VddQ/2, VOUT(PEAK TO PEAK) = 25mV, DM inputs are grouped with I/O pins - reflecting the fact that they are
matched in laoding (to faciliate trace matching at the board level).
12. The CLK//CLK input reference level (for timing referenced to CLK//CLK) is the point at which CLK and /CLK cross;
the input reference level for signals other than CLK//CLK, is VREF.
13. Inputs are not recognized as valid until VREF stabilized. Exception: during the period before VREF stabilizes, CKE=<
0.3VddQ is recognized as LOW.
14. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not
referenced to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving
(LZ).
15. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
16. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this
CLK edge. A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. When
no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous
write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
tDQSS.
17. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
18. tXPRD should be 200 tCLK in the condition of the unstable CLK operation during the power down mode.
19. For command/address and CLK & /CLK slew rate >1.0V/ns.
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
(Component Level)
Read Operation
tCK
tCH
tCL
/CLK
CLK
tIS
tIH
Cmd &
Add.
Valid Data
VREF
tDQSCK
tQH
tRPST
tRPRE
DQS
tDQSQ
tAC
DQ
Write Operation / tDQSS=max.
/CLK
CLK
tDQSS
tWPST
tDSS
tWPRES
DQS
tDQSH
tDH
tDQSL
tDS
tWPRE
DQ
Write Operation / tDQSS=min.
/CLK
CLK
tDSH
tDQSS
tWPST
tWPRES
DQS
tDQSH
tDH
tDQSL
tDS
tWPRE
DQ
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
OPERATIONAL DESCRIPTION (Component Level)
BANK ACTIVATE
The DDR SDRAM has four independent banks. Each bank is activated by the ACT command
with the bank addresses (BA0,1). A row is indicated by the row address A12-0. The minimum
activation interval between one bank and the other bank is tRRD.
PRECHARGE
The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active,
the precharge all command (PREA,PRE+A10=H) is available to deactivate them at the same
time. After tRP from the precharge, an ACT command to the same bank can be issued.
Bank Activation and Precharge All (BL=8, CL=2)
/CLK
CLK
2 ACT command / tRCmin
tRCmin
Command
A0-9,11-12
ACT
READ
PRE
ACT
Xb
ACT
tRRD
tRAS
BL/2
tRP
Xa
Xb
Y
0
tRCD
Xb
Xb
A10
Xa
1
BA0,1
01
00
01
00
DQS
DQ
Q a Q a
Q a Q a Q a Q a Q a Q a
Precharge all
A precharge command can be issued at BL/2 from a read command without data loss.
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
READ
After tRCD from the bank activation, a READ command can be issued. 1st Output data is
available after the /CAS Latency from the READ, followed by (BL-1) consecutive data when the
Burst Length is BL. The start address is specified by A9-A0, and the address sequence of burst data is
defined by the Burst Type. A READ command may be applied to any active bank, so the row precharge
time (tRP) can be hidden behind continuous output data by interleaving the
multiple banks. When A10 is high at a READ command, the auto-precharge(READA) is
performed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal
precharge is complete. The internal precharge starts at BL/2 after READA. The next ACT
command can be issued after (BL/2+tRP) from the previous READA.
Multi Bank Interleaving READ (BL=8, CL=2)
/CLK
CLK
ACT
READ ACT
Command
READ
PRE
tRCD
Y
0
Xb
Xb
A0-9,11-12
A10
Xa
Xa
Y
0
0
BA0,1
00
10
00
00
10
DQS
DQ
Q a Q a Q a Q a
Q a Q a Q a Q a Q b Q b
Q b Q b Q b Q b Q b Q b
Burst Length
/CAS latency
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
READ with Auto-Precharge (BL=8, CL=2)
/CLK
CLK
BL/2 + tRP
Command
A0-9,11-12
A10
ACT
READ
ACT
Xb
BL/2
tRCD
tRP
Y
1
Xa
Xa
Xb
00
BA0,1
00
00
DQS
DQ
Q a Q a Q a Q a
Q a Q a Q a Q a
Internal precharge
start
READ Auto-Precharge Timing (BL=8)
/CLK
CLK
Command
ACT
READ
BL/2
Q a Q a Q a
Q a Q a Q a Q a Q a
CL=2.5
DQ
Q a Q a Q a Q a Q a
Q a Q a Q a
CL=2 DQ
Internal Precharge Start
Timing
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set from the
WRITE command with data strobe input, following (BL-1) data are written into RAM, when the Burst
Length is BL. The start address is specified by A9-A0, and the address sequence of burst data is defined
by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time
(tRP) can be hidden behind continuous input data by interleaving the multiple banks. From the last data to
the PRE command, the write recovery time (tWRP) is required. When A10 is high at a WRITE command,
the auto-precharge(WRITEA) is performed. Any command(READ,WRITE,PRE,ACT) to the same bank
is inhibited till the internal precharge is complete. The next ACT command can be issued after tDAL from
the last input data cycle.
Multi Bank Interleaving WRITE (BL=8)
/CLK
CLK
Command
A0-9,11-12
ACT
Xa
WRITE
WRITE
PRE
ACT
Xb
PRE
tRCD
tRCD
Yb
0
Ya
0
Xb
0
Xa
0
A10
BA0,1
10
00
00
00
10
10
DQS
DQ
Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 Db0 Db1 Db2 Db3 Db4 Db5 Db6 Db7
WRITE with Auto-Precharge (BL=8)
/CLK
CLK
Command
WRITE
ACT
Xb
ACT
Xa
tDAL
tRCD
A0-9,11-12
Y
1
Xa
Xb
00
A10
BA0,1
00
00
DQS
DQ
Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7
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MITSUBISHI LSIs
Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
BURST INTERRUPTION
[Read Interrupted by Read]
Burst read operation can be interrupted by new read of any bank. Random column access is allowed.
READ to READ interval is minimum 1CLK.
Read Interrupted by Read (BL=8, CL=2)
/CLK
CLK
Command
A0-9,11-12
READ
Yl
READ
Yk
READ READ
Yi
0
Yj
0
0
A10
0
BA0,1
01
00
00
10
DQS
DQ
Qai0 Qai1 Qaj0 Qaj1 Qaj2 Qaj3 Qak Qak Qak Qak Qak Qak Qal0 Qal1 Qal2 Qal3 Qal4 Qal5 Qal6 Qal7
[Read Interrupted by precharge]
Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is
minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. As
a result, READ to PRE interval determines valid data length to be output. The figure below shows
examples of BL=8.
Read Interrupted by Precharge (BL=8)
/CLK
CLK
Command
READ
PRE
DQS
Q0 Q1 Q2 Q3 Q4 Q5
DQ
Command
READ
PRE
CL=2.5
DQS
DQ
Q0 Q1 Q2 Q3
READ PRE
Command
DQS
DQ
Q0 Q1
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
Read Interrupted by Precharge (BL=8)
/CLK
CLK
READ
PRE
Command
DQS
Q0 Q1 Q2 Q3 Q4 Q5
DQ
Command
READ
PRE
CL=2.0
DQS
DQ
Q0 Q1 Q2 Q3
Command
READ PRE
DQS
DQ
Q0 Q1
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
[Read Interrupted by Burst Stop]
Burst read operation can be interrupted by a burst stop command(TERM). READ to TERM
interval is minimum 1 CLK. A TERM command to output disable latency is equivalent to the /CAS
Latency. As a result, READ to TERM interval determines valid data length to be output. The figure
below shows examples of BL=8.
Read Interrupted by TERM (BL=8)
/CLK
CLK
Command
TERM
READ
READ
READ
DQS
Q0 Q1 Q2 Q3 Q4 Q5
DQ
Command
TERM
CL=2.5
DQS
DQ
Q0 Q1 Q2 Q3
TERM
Command
DQS
DQ
Q0 Q1
Command
DQS
READ
READ
READ
TERM
Q0 Q1 Q2 Q3 Q4 Q5
DQ
Command
TERM
CL=2.0
DQS
DQ
Q0 Q1 Q2 Q3
Command
TERM
DQS
DQ
Q0 Q1
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
[Read Interrupted by Write with TERM]
Read Interrupted by TERM (BL=8)
/CLK
CLK
TERM
Command
READ
WRITE
DQS
DQ
CL=2.5
CL=2.0
Q0 Q1 Q2 Q3
D0 D1 D2 D3 D4 D5
TERM
Command
READ
WRITE
DQS
DQ
Q0 Q1 Q2 Q3
D0 D1 D2 D3 D4 D5 D6 D7
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
[Write interrupted by Write]
Burst write operation can be interrupted by write of any bank. Random column access is
allowed. WRITE to WRITE interval is minimum 1 CLK.
Write Interrupted by Write (BL=8)
/CLK
CLK
Command
WRITE
WRITE
WRITE
WRITE
Yi
Yj
0
Yk
0
A0-9,11-12
Yl
0
0
A10
BA0,1
00
00
10
00
DQS
DQ
Dai0 Dai1 Daj0 Daj1 Daj2 Daj3 Dak0 Dak1 Dak2 Dak3 Dak4 Dak5 Dal0 Dal1 Dal2 Dal3 Dal4 Dal5 Dal6 Dal7
[Write interrupted by Read]
Burst write operation can be interrupted by read of the same or the other bank. Random column access is
allowed. Internal WRITE to READ command interval(tWTR) is minimum 1 CLK. The input data on DQ
at the interrupting READ cycle is "don't care". tWTR is referenced from the first positive edge after the
last data input.
Write Interrupted by Read (BL=8, CL=2.5)
/CLK
CLK
Command
READ
WRITE
A0-9,11-12
Yi
0
Yj
0
A10
BA0,1
00
00
DM
tWTR
QS
DQ
Dai0 Dai1
Qaj0 Qaj1 Qaj2 Qaj3 Qaj4 Qaj5 Qaj6 Qaj7
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
[Write interrupted by Precharge]
Burst write operation can be interrupted by precharge of the same or all bank. Random column access is
allowed. tWR is referenced from the first positive CLK edge after the last data input.
Write Interrupted by Precharge (BL=8, CL=2.5)
/CLK
CLK
Command
WRITE
PRE
A0-9,11-12
A10
Yi
0
BA0,1
DM
00
00
tWR
QS
DQ
Dai0 Dai1
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
[Initialize and Mode Register sets]
/CLK
CLK
Command
A0-9,11-12
A10
NOP
PRE
EMRS
Code
Code
1 0
MRS
Code
Code
0 0
PRE
AR
AR
MRS
ACT
Xa
Code
0 0
Xa
1
1
BA0,1
DQS
Xa
DQ
tMRD
tMRD
tRP
tRFC
tRFC
tMRD
Extended Mode
Mode Register Set,
Register Set
Reset DLL
[AUTO REFRESH]
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,/WE=CKE=H) command. The
refresh address is generated internally. 8192 REFA cycles within 64ms refresh 256Mbits memory cells.
The auto-refresh is performed on 4 banks concurrently. Before performing an auto refresh, all banks must
be in the idle state. Auto-refresh to auto-refresh interval is minimum tRFC . Any command must not be
supplied to the device before tRFC from the REFA command.
Auto-Refresh
/CLK
CLK
/CS
NOP or DESELECT
/RAS
/CAS
/WE
CKE
tRFC
A0-12
BA0,1
Auto Refresh on All Banks
Auto Refresh on All Banks
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
[SELF REFRESH]
Self -refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,/WE=H,CKE=L). Once
the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE
is asynchronous and the only enable input, all other inputs including CLK are disabled and ignored, so that
power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK
inputs, asserting DESEL or NOP command and then asserting CKE for longer than tXSNR/tXSRD.
Self-Refresh
/CLK
CLK
/CS
/RAS
/CAS
/WE
CKE
A0-12
BA0,1
X
X
Y
Y
tXSRD
tXSNR
Read
Act
Self Refresh Exit
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
[Asynchronous SELF REFRESH]
Asynchronous Self -refresh mode is entered by CKE=L within 2 tCLK after issuing a REFA command
(/CS=/RAS=/CAS=L,/WE=H). Once the self-refresh is initiated, it is maintained as long as CKE is kept
low. During the self-refresh mode, CKE is asynchronous and the only enable input, all other inputs
including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved.
To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then
asserting CKE for longer than tXSNR/tXSRD.
Asynchronous Self-Refresh
/CLK
CLK
/CS
/RAS
/CAS
/WE
CKE
max 2 tCLK
A0-12
BA0,1
tXSNR
Act
Self Refresh Exit
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Preliminary Spec.
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
[Power DOWN]
The purpose of CLK suspend is power down. CKE is synchronous input except during the self-refresh
mode. A command at cycle is ignored. From CKE=H to normal function, DLL recovery time is NOT
required in the condition of the stable CLK operation during the power down mode.
Power Down by CKE
/CLK
CLK
Standby Power
CKE
Down
Command
NOP
NOP
PRE
ACT
Valid
Valid
NOP
NOP
tXPNR/
tXPRD
Active Power
Down
CKE
Command
[DM CONTROL]
DM is defined as the data mask for writes. During writes,DM masks input data word by word. DM to
write mask latency is 0.
DM Function(BL=8,CL=2)
/CLK
CLK
Command
Write
READ
DM
Don't Care
DQS
DQ
Q2 Q3 Q4 Q5
Q0 Q1
Q6
D0 D1
D3 D4 D5 D6
D7
masked by DM=H
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
Serial Presence Detect Table I
Function described
SPD DATA(hex)
Byte
SPD enrty data
Number of Serial PD Bytes Written during Production
Total # bytes of SPD memory device
Fundamental memory type
0
1
2
3
4
5
6
7
8
9
128
256 Bytes
SDRAM DDR
13
80
08
07
0D
0A
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
10
2BANK
x64
02
40
00
04
75
80
75
80
0
... Data Width continuation
SSTL2.5V
7.5ns
Voltage interface standard of this assembly
-75
-10
-75
-10
SDRAM Cycletime at Max. Supported CAS Latency (CL).
8.0ns
Cycle time for CL=2.5
+0.75ns
+0.8 ns
10
SDRAM Access from Clock
tAC for CL=2.5
None-parity,Non-ECC
00
82
11
12
13
14
15
16
17
18
19
20
21
22
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
7.8uS/SR
x8
08
00
01
0E
SDRAM width,Primary DRAM
N/A
Error Checking SDRAM data width
1 clock
MIimum Clock Delay, Random Column Access
2, 4, 8
Burst Lengths Supported
Number of Device Banks
4bank
2.0, 2.5
0
04
0C
CAS# Latency
CS# Latency
01
02
1
WE Latency
Differential Clock
VDD + 0.2V
SDRAM Module Attributes
SDRAM Device Attributes:General
20
00
-75
10ns
A0
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
23
10ns
-10
-75
A0
75
+0.75ns
SDRAM Access form Clock(2nd highest CAS latency)
tAC for CL=2
24
25
-10
+0.8ns
Undefined
Undefined
Undefined
Undefined
80
00
00
00
00
-75
-10
SDRAM Cycle time(3rd highest CAS latency)
-75
-10
26
27
SDRAM Access form Clock(3rd highest CAS latency)
Minimum Row Precharge Time (tRP)
20ns
15ns
20ns
45ns
50
3C
50
28
29
Minimum Row Active to Row Active Delay (tRRD)
RAS to CAS Delay Minv (tRCD)
-75
-10
2D
32
30
Active to Precharge Min (tRAS)
50ns
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MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
Serial Presence Detect Table II
31
32
Density of each bank on module
256MByte
0.9nS
1.1nS
0.9nS
1.1nS
0.5nS
0.6nS
0.5nS
0.6nS
40
90
B0
90
B0
-75
-10
Command and Address signal input setup time
-75
-10
33
34
Command and Address signal input hold time
Data signal input setup time
-75
-10
-75
-10
50
60
50
60
35
Data signal input hold time
Superset Information (may be used in future)
SPD Revision
option
0
36-61
00
00
62
Check sum for -75
C0
63
Checksum for bytes 0-62
46
Check sum for -10
MITSUBISHI
64-71
Manufactures Jedec ID code per JEP-108E
1CFFFFFFFFFFFFFF
Manufacturing location
72
Manufacturing Location
XX
73-90
Manufactures Part Number
MH64D64AKQH-75
MH64D64AKQH-10
4D483634443634414B51482D373520202020
4D483634443634414B51482D313020202020
91-92
93-94
Revision Code
Manufacturing date
Assembly Serial Number
Reserved
PCB revision
year/week code
serial number
Undefined
rrrr
yyww
ssssssss
00
95-98
99-127
128-255
Open for Customer Use
Undefined
00
MIT-DS-0418-0.1
MITSUBISHI
ELECTRIC
17.May.2001
37
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
EEPROM Components A.C. and D.C. Characteristics
Limits
Typ.
Symbol
Parameter
Units
Min.
2.2
Max.
5.5
VCC
Supply Voltage
Supply Voltage
V
V
V
V
VSS
VIH
0
Vccx0.7
-1
0
0
Vcc+0.5
Input High Voltage
Input Low Voltage
Vccx0.3
0.4
VIL
VOL
Output Low Voltage
V
EEPROM A.C.Timing Parameters(Ta=0 to 70°C)
Limits
Symbol
fSCL
Parameter
SCL Clock Frequency
Units
Min.
Max.
100
200
3.5
KHz
Noise Supression Time Constant at SCL, SDA inputs
SCL Low to SDA Data Out Valid
TI
TAA
ns
us
Time the Bus Must Be Free before a New
Transmission Can Start
TBUF
4.7
us
THD:STA
TLOW
4.0
4.7
4.0
4.7
0
Start Condition Hold Time
Clock Low Time
us
us
THIGH
Clock High Time
us
us
TSU:STA
Start Condition Setup Time
THD:DAT
TSU:DAT
TR
Data In Hold Time
us
ns
us
ns
250
Data In Setup Time
1
SDA and SCL Rise Time
SDA and SCL Fall Time
TF
300
TSU:STO
TDH
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
4.0
us
ns
ms
100
TWR
10
tWR is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle.
TR
TF
THIGH
TLOW
SCL
TSU:STO
TSU:STA
THD:DAT
THD:STA
TSU:DAT
SDA
IN
TAA
TDH
TBUF
SDA
OUT
MIT-DS-0418-0.1
MITSUBISHI
ELECTRIC
17.May.2001
38
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
OUTLINE
31.75
20.00
6.00
4.00
4.00
0.25Max
2.55
Unit.mm
MIT-DS-0418-0.1
MITSUBISHI
ELECTRIC
17.May.2001
39
MITSUBISHI LSIs
Preliminary Spec.
Some contents are subject to change without notice.
MH64D64AKQH-75,-10
4,294,967,296-BIT (67,108,864-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products
better and more reliable, but there is always the possibility that trouble may occur with them.
Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with
appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-
flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the selection of the
Mitsubishi semiconductor product best suited to the customer's application; they do not
convey any license under any intellectual property rights, or any other rights, belonging to
Mitsubishi Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement
of any third-party's rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
3.All information contained in these materials, including product data, diagrams, charts,
programs and algorithms represents information on products at the time of publication of
these materials, and are subject to change by Mitsubishi Electric Corporation without notice
due to product improvements or other reasons. It is therefore recommended that customers
contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other
loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by
various means, including the Mitsubishi Semiconductor home page
(http://www.mitsubishichips.com).
4.When using any or all of the information contained in these materials, including product
data, diagrams, charts, programs and algorithms, please be sure to evaluate all information
as a total system before making a final decision on the applicability of the information and
products.
Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other
loss resulting from the information contained herein.
5.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in
a device or system that is used under circumstances in which human life is potentially at stake.
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor when considering the use of a product contained herein for any specific
purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace,
nuclear, or undersea repeater use.
6.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or
reproduce in whole or in part these materials.
7.If these products or technologies are subject to the Japanese export control restrictions, they
must be exported under a license from the Japanese government and cannot be imported
into a country other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or
the country of destination is prohibited.
8.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for further details on these materials or the products contained therein.
MIT-DS-0418-0.1
MITSUBISHI
ELECTRIC
17.May.2001
40
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