MH64D72KLH-10 [MITSUBISHI]
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module; 4831838208位（ 67108864 - WORD 72 - BIT）双数据速率同步DRAM模组
| 型号： | MH64D72KLH-10 |
| 厂家： | 
Mitsubishi Group |
| 描述： | 4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module |
| 文件： | 总39页 (文件大小：349K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
DESCRIPTION
The MH64D72KLH is 67108864 - word x 72-bit Double
Data Rate(DDR) Sy nchronous DRAM mounted module.
This consists of 18 industry standard 32M x 8 DDR
Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which
achiev es v ery high speed data rate up to 133MHz.
This socket-ty pe memory module is suitable f or main
memory in computer systems and easy to interchange or
add modules.
93pin
1pin
FEATURES
CLK
Max.
Access Time
[component level]
Type name
Frequency
+ 0.75ns
MH64D72KLH-75
MH64D72KLH-10
133MHz
100MHz
+ 0.8ns
144pin
145pin
- Utilizes industry standard 32M X 8 DDR Synchronous DRAMs
in TSOP package , industry standard Registered Buffer in
TSSOP package , and industry standard PLL in TSSOP package.
- Vdd=Vddq=2.5v ±0.2V
52pin
53pin
- Double data rate architecture; two data transf ers per
clock cycle
- Bidirectional, data strobe (DQS) is transmitted/receiv ed
with data
- Dif f erential clock inputs (CK0 and /CK0)
- data and data mask ref erenced to both edges of DQS
- /CAS latency - 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Auto precharge / All bank precharge controlled by A10
- 8192 ref resh cycles /64ms
- Auto ref resh and Self ref resh
- Row address A0-12 / Column address A0-9
- SSTL_2 Interf ace
184pin
92pin
- Module 2bank Conf igration
- Burst Ty pe - sequential/interleav e(programmable)
- Commands entered on each positiv e CLK edge
APPLICATION
Main memory unit for PC, PC server, Server, W S.
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
1
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
,
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
PIN CONFIGURATION
PIN
NO.
1
PIN
NO.
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
PIN
NO.
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
PIN
PIN
NO.
43
PIN
PIN
NO.
84
PIN
PIN
PIN
NAME
NAME
NAME
NAME
NAME
NC
VREF
DQ0
VSS
A1
CB0
DQ57
VDD
DQ28
85
86
2
44
45
46
47
48
49
50
51
52
VDD
DM6
DQ29
VDDQ
3
CB1
VDD
DQS8
A0
DQS7
DQ58
DQ59
87
4
DM3
DQ1
DQS0
DQ2
VDD
DQ3
NC
DQ54
DQ55
VDDQ
NC
88
5
A3
DQ30
VSS
89
6
VSS
NC
90
7
CB2
VSS
91
8
SDA
SCL
VSS
DQ4
DQ5
DQ31
CB4
DQ60
DQ61
92
9
CB3
BA1
KEY
93
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
RESET
VSS
CB5
VSS
DM7
94
VDDQ
CK0
95
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
DQ8
DQ9
DQS1
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
DQ62
DQ63
VDDQ
SA0
96
VDDQ
DM0
/CK0
97
VSS
DM8
98
VDDQ
NC
DQ6
DQ7
99
A10
CB6
SA1
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
NC
VSS
NC
SA2
VSS
BA0
VDDQ
CB7
VDDSPD
NC
DQ10
DQ35
DQ40
A13
KEY
DQ11
CKE0
NC: No Connect
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
VDDQ
/WE
VDDQ
DQ12
DQ13
VSS
VDDQ
DQ16
DQ17
DQS2
VSS
DQ36
DQ37
DQ41
/CAS
VSS
VDD
DM4
DM1
VDD
DQ14
DQS5
DQ42
DQ43
VDD
NC
DQ38
DQ39
VSS
A9
DQ15
CKE1
DQ28
A7
VDDQ
NC
DQ44
/RAS
DQ45
VDDQ
DQ19
DQ48
DQ49
DQ20
A12
A5
VDDQ
/S0
DQ24
VSS
VSS
NC
VSS
/S1
DQ21
NC
DM5
DQ25
A11
DM2
DQS3
A4
VDDQ
DQS6
DQ50
VSS
VDD
DQ46
VDD
DQ22
DQ47
NC
A8
DQ26
DQ27
A2
DQ51
VSS
DQ23
VSS
A6
VDDQ
DQ52
VDDID
DQ56
VSS
DQ53
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
2
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
Block Diagram
/RS1
/RS0
DQS0
DM0
DQS4
DM4
DQ32
DQ0
/S DQS
DQS
/S DQS
DQS
DM
DM /S
DM
DM
/S
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D0
D4
D9
D13
DQS1
DM1
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ8
DQ9
/S DQS
DQS
DQS
DQS
/S
/S
/S
DM
DM
DM
DM
DM
DM
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
D1
D5
D10
D14
DQS2
DM2
DQS6
DM6
DQ48
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
/S DQS
DQS
/S DQS
DQS
/S
DM
DM
DM
/S
DQ49
DQ50
DQ51
DQ52
DQ53
D2
D6
D11
D15
DQ22
DQ23
DQ54
DQ55
DQS3
DM3
DQS7
DM7
DQ56
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS
DQS
DQS
DQS
/S
/S
DM
DM /S
DM
/S
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
SERIAL PD
WP
SCL
SDA
D3
D7
D12
D16
A1 A2
A0
SA0 SA1 SA2
VDDQ
VDD
D0 to D17
D0 to D17
DQS8
DM8
/S0
/S1
/RS0 -> SDRAMs D0-D8
/RS1 -> SDRAMs D9-D17
VREF
D0 to D17
D0 to D17
CB0
CB1
DQS
DQS
DM /S
/S
DM
RBA0-RBA1 -> SDRAMs D0-D17
RA0-RA12 -> SDRAMs D0-D17
/RRAS -> SDRAMs D0-D17
/RCAS -> SDRAMs D0-D17
/RCKE0 -> SDRAMs D0-D8
BA0-BA1
A0-A12
/RAS
VSS
CB2
CB3
VDDID
/CAS
VDDID: OPEN -> VDD = VDDQ
VSS -> VDD = VDDQ
CKE0
CB4
CB5
CB6
CB7
D8
/RCKE1 -> SDRAMs D9-D17
/RWE -> SDRAMs D0-D17
D17
CKE1
/WE
CK0
PCK0 -> SDRAMs D0-D17,
Registered Buffer
PLL
PCK
/PCK
/CK0
/PCK0 -> SDRAMs D0-D17,
Registered Buffer
/RESET
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
3
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
PIN FUNCTION
SYMBOL
TYPE
DESCRIPTION
Clock: CK0 and /CK0 are dif f erential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK0 and negativ e
edge of /CK0. Output (read) data is ref erenced to the crossings of CK0 and
/CK0 (both directions of crossing).
CK0,/CK0
Input
Clock Enable: CKE0 controls SDRAM internal clock. When CKE0 is low, the
internal clock f or the f ollowing cycle is ceased. CKE0 is also used to select
auto / self ref resh. After self ref resh mode is started, CKE0 becomes
asy nchronous input. Self ref resh is maintained as long as CKE0 is low.
Input
CKE0, CKE1
Physical Bank Select: When /S0,/S1 is high, any command means No Operation.
Combination of /RAS, /CAS, /WE defines basic commands.
/S0, /S1
Input
Input
/RAS, /CAS, /WE
A0-12 specif y the Row / Column Address in conjunction with BA0,1. The Row
Address is specif ied by A0-12. The Column Address is specif ied by A0-9.
A10 is also used to indicate precharge option. When A10 is high at a read / write
command, an auto precharge is perf ormed. When A10 is high at a precharge
command, all banks are precharged.
A0-12
BA0,1
Input
Input
Bank Address: BA0,1 specifies one of four banks in SDRAM to which a command is applied. BA0,1
must be set with ACT, PRE, READ, WRITE commands.
DQ 0-64
CB 0-7
Input / Output
Input / Output
Input
Data Input/Output: Data bus
Data Strobe: Output with read data, input with write data. Edge-aligned with read
data, centered in write data. Used to capture write data.
DQS0-8
Masks write data when high, issued concurrently with input data. Both DM and DQ have a write
latency of one clock once the write command is registered into the SDRAM.
DM0-8
Vdd, Vss
Power Supply Power Supply for the memory array and peripheral circuitry.
VddQ, VssQ
Vddspd
Vref
Power Supply VddQ and VssQ are supplied to the Output Buffers only.
Power Supply Power Supply for SPD
Input
Input
SSTL_2 reference voltage.
This signal is asy nchronous and is driv en low to the register in order to
guarantee the register outputs are low.
RESET
This bidirectional pin is used to transf er data into or out of the SPD EEPROM.
A resistor must be connected f rom the SDA bus line to VDD to act as a pullup.
Input / Output
SDA
SCL
This signal is used to clock data into and out of the SPD EEPROM. A resistor
may be connected f rom the SCL bus time to VDD to act as a pullup.
These signals are tied at the system planar to either VSS or VDD to conf igure
the serial SPD EEPROM address range.
Input
Input
SA0-2
VDD identif ication f lag
VDDID
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
4
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
BASIC FUNCTIONS
The MH64D72KLH provides basic functions, bank (row) activate, burst read / write, bank (row)
precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS
and /WE at CLK rising edge. In addition to 3 signals, /S0(/S1) ,CKE0(CKE1) and A10 are used
as chip select, refresh option, and precharge option, respectively. To know the detailed
definition of commands, please see the command truth table.
/CK0
CK0
/S0, /S1
Chip Select : L=select, H=deselect
Command
/RAS
/CAS
Command
Command
def ine basic commands
/WE
Ref resh Option @ref resh command
CKE0, CKE1
A10
Precharge Option @precharge or read/write command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data
appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the
burst read (auto-precharge,READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be
written is set by burst length. When A10 =H at this command, the bank is deactivated after
the burst write (auto-precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates
burst read /write operation. When A10 =H at this command, all banks are deactivated
(precharge all, PREA).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE0(CKE1) =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are
generated internally. After this command, the banks are precharged automatically.
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
5
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
COMMAND TRUTH TABLE
CKE0
n-1
A0-9,
11-12
CKE0
n
A10
/AP
note
COMMAND
MNEMONIC
/RAS /CAS /WE BA0,1
/S
Deselect
DESEL
NOP
H
H
X
X
H
L
X
H
X
H
X
H
X
X
X
X
X
X
No Operation
Row Address Entry &
Bank Activate
ACT
H
X
L
L
H
H
V
V
V
Single Bank Precharge
Precharge All Banks
PRE
H
H
X
X
L
L
L
L
H
H
L
L
V
X
L
X
X
PREA
H
Column Address Entry
& Write
WRITE
H
X
L
H
L
L
V
L
V
Column Address Entry
& Write with
WRITEA
READ
H
H
X
X
L
L
H
H
L
L
L
V
V
H
L
V
V
Auto-Precharge
Column Address Entry
& Read
H
Column Address Entry
& Read with
READA
H
X
L
H
L
H
V
H
V
Auto-Precharge
Auto-Refresh
REFA
REFS
H
H
L
H
L
L
L
H
L
L
L
L
L
H
H
X
H
L
X
X
X
X
X
L
X
X
X
X
X
L
X
X
X
X
X
V
Self-Refresh Entry
Self-Refresh Exit
L
L
H
H
X
X
X
H
H
L
X
H
H
L
REFSX
L
1
2
Burst Terminate
TERM
MRS
H
H
Mode Register Set
L
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. Applies only to read bursts with autoprecharge disabled; this command is undefined (and should
not be used) for read bursts with autoprecharge enabled, and for write bursts.
2. BA0-BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode
Register; BA0 = 1, BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are
reserved; A0-A11 provide the op-code to be written to the selected Mode Register.
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
6
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE
/S
Current State
/RAS /CAS /WE
Address
Command
DESEL
NOP
Action
Notes
IDLE
H
X
H
H
H
L
X
H
H
L
X
H
L
X
NOP
L
L
L
L
L
L
X
NOP
BA
TERM
ILLEGAL
2
2
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL
ACT Bank Active, Latch RA
PRE / PREA NOP
H
H
L
4
5
L
L
H
REFA
MRS
Auto-Refresh
Op-Code,
Mode-Add
5
L
L
L
L
Mode Register Set
ROW ACTIVE
H
L
L
X
H
H
X
H
H
X
H
L
X
DESEL
NOP
NOP
NOP
NOP
X
BA
TERM
Begin Read, Latch CA,
L
L
H
H
L
L
H
L
BA, CA, A10
BA, CA, A10
READ / READA
Determine Auto-Precharge
WRITE /
WRITEA
Begin Write, Latch CA,
Determine Auto-Precharge
2
L
L
L
L
L
L
H
H
L
H
L
BA, RA
BA, A10
X
ACT
Bank Active / ILLEGAL
PRE / PREA Precharge / Precharge All
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
H
L
L
X
H
H
X
H
H
X
H
L
X
DESEL
NOP
NOP (Continue Burst to END)
NOP (Continue Burst to END)
Terminate Burst
READ
(Auto-
X
Precharge
Disabled)
BA
TERM
Terminate Burst, Latch CA,
3
2
L
L
H
H
L
L
H
L
BA, CA, A10
BA, CA, A10
READ / READA Begin New Read, Determine
Auto-Precharge
WRITE
ILLEGAL
WRITEA
L
L
L
L
L
L
H
H
L
H
L
BA, RA
BA, A10
X
ACT
Bank Active / ILLEGAL
PRE / PREA Terminate Burst, Precharge
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
7
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE (continued)
/S
Current State
/RAS /CAS /WE
Address
Command
DESEL
Action
Notes
H
X
X
X
X
NOP (Continue Burst to END)
WRITE
(Auto-
L
L
H
H
H
H
H
L
X
NOP
NOP (Continue Burst to END)
ILLEGAL
Precharge
Disabled)
BA
TERM
Terminate Burst, Latch CA,
3
L
H
L
H
BA, CA, A10 READ / READA Begin Read, Determine Auto-
Precharge
Terminate Burst, Latch CA,
WRITE /
3
2
L
L
H
L
L
L
BA, CA, A10
BA, RA
Begin Write, Determine Auto-
Precharge
WRITEA
H
H
ACT
Bank Active / ILLEGAL
L
L
L
L
H
L
L
BA, A10
X
PRE / PREA Terminate Burst, Precharge
H
REFA
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DESEL
NOP
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
READ with
AUTO
X
PRECHARGE
BA
TERM
H
BA, CA, A10 READ / READA ILLEGAL
WRITE /
L
H
L
L
BA, CA, A10
ILLEGAL
WRITEA
2
2
L
L
L
L
L
L
H
H
L
H
L
BA, RA
BA, A10
X
ACT
Bank Active / ILLEGAL
PRE / PREA PRECHARGE/ILLEGAL
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
H
L
L
L
X
H
H
H
X
H
H
L
X
H
L
X
DESEL
NOP
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
WRITE with
AUTO
X
PRECHARGE
BA
TERM
H
BA, CA, A10 READ / READA ILLEGAL
WRITE /
L
H
L
L
BA, CA, A10
ILLEGAL
WRITEA
ACT
2
2
L
L
L
L
L
L
H
H
L
H
L
BA, RA
Bank Active / ILLEGAL
BA, A10
PRE / PREA PRECHARGE/ILLEGAL
H
X
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
8
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE (continued)
/S
Current State
/RAS /CAS /WE
Address
Command
DESEL
NOP
Action
NOP (Idle after tRP)
NOP (Idle after tRP)
ILLEGAL
Notes
H
X
H
H
H
L
X
H
H
L
X
H
L
X
PRE -
CHARGING
L
L
L
L
L
L
X
2
BA
TERM
2
2
4
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL
ACT ILLEGAL
PRE / PREA NOP (Idle after tRP)
H
H
L
L
L
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP
NOP (Row Active after tRCD)
NOP (Row Active after tRCD)
ILLEGAL
ROW
ACTIVATING
X
2
2
BA
TERM
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL
ACT ILLEGAL
PRE / PREA ILLEGAL
2
2
H
H
L
L
L
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP
NOP
WRITE RE-
COVERING
X
NOP
2
2
BA
TERM
ILLEGAL
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL
ACT ILLEGAL
PRE / PREA ILLEGAL
2
2
H
H
L
L
L
H
REFA
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
MRS
ILLEGAL
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
9
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE (continued)
/S
Current State
/RAS /CAS /WE
Address
Command
DESEL
NOP
Action
NOP (Idle after tRC)
NOP (Idle after tRC)
ILLEGAL
Notes
H
X
H
H
H
L
X
H
H
L
X
H
L
X
RE-
FRESHING
L
L
L
L
L
L
X
BA
TERM
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL
ACT ILLEGAL
PRE / PREA ILLEGAL
H
H
L
L
L
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
H
L
L
L
L
L
L
X
H
H
H
L
X
H
H
L
X
H
L
X
DESEL
NOP
NOP (Idle after tRSC)
NOP (Idle after tRSC)
ILLEGAL
MODE
REGISTER
SETTING
X
BA
TERM
X
H
L
BA, CA, A10
BA, RA
BA, A10
X
READ / WRITE ILLEGAL
ACT ILLEGAL
PRE / PREA ILLEGAL
H
H
L
L
L
H
REFA
MRS
ILLEGAL
ILLEGAL
Op-Code,
Mode-Add
L
L
L
L
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation
NOTES:
1. All entries assume that CKE0 was High during the preceding clock cycle and the current clock cycle.
2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of
that bank.
3. Must satisfy bus contention, bus turn around, write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA.
5. ILLEGAL if any bank is not idle.
ILLEGAL = Device operation and/or data-integrity are not guaranteed.
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
10
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE for CKE
CKE0 CKE0
/S /RAS /CAS
Current State
/WE Add
Action
Notes
n
n-1
1
1
1
1
1
H
L
X
X
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
INVALID
SELF-
REFRESH
H
H
H
H
H
L
Exit Self-Refresh (Idle after tRC)
Exit Self-Refresh (Idle after tRC)
ILLEGAL
L
L
L
L
L
X
X
X
X
X
X
X
H
X
H
L
ILLEGAL
1
1
L
L
X
X
X
X
X
X
L
ILLEGAL
L
X
X
X
X
X
L
X
X
X
X
X
L
NOP (Maintain Self-Refresh)
INVALID
H
L
X
H
L
POWER
DOWN
Exit Power Down to Idle
NOP (Maintain Self-Refresh)
Refer to Function Truth Table
Enter Self-Refresh
L
2
H
H
H
H
H
H
H
L
H
L
ALL BANKS
IDLE
2
2
2
L
H
L
X
H
H
H
L
X
H
H
L
Enter Power Down
L
Enter Power Down
2
2
2
L
L
ILLEGAL
L
L
X
X
X
X
X
X
X
ILLEGAL
L
L
X
X
X
X
X
X
ILLEGAL
2
X
H
L
X
X
X
X
X
X
X
X
X
X
Refer to Current State =Power Down
Refer to Function Truth Table
Begin CLK Suspend at Next Cycle
Exit CLK Suspend at Next Cycle
Maintain CLK Suspend
H
H
L
ANY STATE
other than
3
3
listed above
H
L
L
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
asynchronously
1. CKE0 Low to High transition will re-enable CK0 and other inputs
. A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
11
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
SIMPLIFIED STATE DIAGRAM
POWER
PRE
CHARGE
ALL
APPLIED
SELF
POWER
ON
PREA
REFRESH
REFS
MRS
MRS
REFSX
MODE
REGISTER
SET
REFA
AUTO
IDLE
ACT
REFRESH
CKEL
CKEH
Active
Power
Down
POWER
DOWN
CKEL
CKEH
ROW
BURST
STOP
ACTIVE
WRITE
READ
WRITE
READ
WRITEA
READA
READ
WRITE
READ
TERM
WRITEA
READA
READA
PRE
PRE
WRITEA
READA
PRE
PRE
CHARGE
Automatic Sequence
Command Sequence
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
12
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM
from damaged or multifunctioning.
1. Apply VDD and VDDQ before or at the same time as VTT & Vref
2. Maintain stable condition for 200us after stable power and CLK, apply NOP or DSEL
3. Issue precharge command for all banks of the device
4. Issue EMRS
5. Issue MRS
6. Issue 2 or more Auto Refresh commands
7. Maintain stable condition for 200 cycle
After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
CK0
/CK0
/S
Burst Length, Burst Type and /CAS Latency can be programmed by
setting the mode register (MRS). The mode register stores these data until
the next MRS command, which may be issued in idle state.
After tMRD from a MRS command, the DDR DIMM is ready for new
command.
/RAS
/CAS
/WE
BA1
0
BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
BA0
0
0
0
DR
0
LTMODE
BT
BL
0
BA1
V
A11-A0
BL
BT= 0
BT= 1
R
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
R
2
CL
/CAS Latency
2
4
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
R
R
4
Burst
8
8
2
Length
R
R
R
R
R
R
R
R
Latency
Mode
R
R
1.5
2.5
R
0
1
Burst
Type
Sequential
Interleaved
NO
YES
0
1
DLL
Reset
R: Reserved for Future Use
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
13
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
EXTENDED MODE REGISTER
DLL disable / enable mode can be programmed by setting the extended
mode register (EMRS). The extended mode register stores these data
until the next EMRS command, which may be issued in idle state.
After tMRD from a EMRS command, the DDR DIMM is ready for new
command.
CK0
/CK0
/S
/RAS
/CAS
/WE
BA1
0
BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
QFC DS DD
BA0
BA1
1
0
0
0
0
0
0
0
0
0
V
A11-A0
DLL
Disable
0
1
DLL enable
DLL disable
Drive
0
1
Normal
Weak
Strength
0
1
Disable
Enable
QFC
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
14
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
( Componennt Level )
/CLK
CLK
Command
Read
Y
Write
Y
Address
DQS
DQ
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Burst
Burst
/CAS
CL= 2
BL= 4
Length
Length
Latency
Initial Address BL
A2 A1 A0
Column Addressing
Sequential
Interleaved
0
0
0
0
1
1
1
1
-
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
0
1
1
2
3
4
5
6
7
0
1
2
2
3
4
5
6
7
0
1
2
3
3
4
5
6
7
0
1
2
3
0
4
5
6
7
0
1
2
3
5
6
7
0
1
2
3
4
6
7
0
1
2
3
4
5
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
0
1
1
0
3
2
5
4
7
6
1
0
2
3
0
1
6
7
4
5
2
3
3
2
1
0
7
6
5
4
3
2
4
5
6
7
0
1
2
3
5
4
7
6
1
0
3
2
6
7
4
5
2
3
0
1
7
6
5
4
3
2
1
0
8
-
4
2
-
-
1
1
0
1
2
3
3
0
0
1
1
2
2
3
3
2
0
1
1
0
-
-
-
-
0
1
0
1
1
0
0
1
1
0
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
15
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
ABSOLUTE MAXIMUM RATINGS
Symbol
Vdd
Parameter
Conditions
Ratings
-0.5 ~ 3.7
Unit
V
Supply Voltage
with respect to Vss
VddQ Supply Voltage for Output with respect to VssQ
-0.5 ~ 3.7
V
VI
VO
IO
Input Voltage
Output Voltage
with respect to Vss
-0.5 ~ Vdd+0.5
V
with respect to VssQ -0.5 ~ VddQ+0.5
50
V
Output Current
mA
W
C
20
Pd
Power Dissipation
Operating Temperature
Storage Temperature
Ta = 25 C
Topr
Tstg
0 ~ 70
-40 ~ 100
C
DC OPERATING CONDITIONS
OC
(Ta=0 ~ 70 , unless otherwise noted)
Limits
Symbol
Parameter
Unit Notes
Min.
Typ.
2.5
Max.
Vdd/VddQ
Vref
Supply Voltage
Input Reference Voltage
2.3
1.15
2.7
V
V
V
V
V
V
V
1.25
1.35
5
Vref + 0.18
-0.3
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VTT
High-Level Input Voltage
VddQ+0.3
Vref - 0.18
VddQ + 0.3
VddQ + 0.6
Vref + 0.04
Low-Level Input Voltage
Input Voltage Level, CK0 and /CK0
Input Differential Voltage, CK0 and /CK0
I/O Termination Voltage
-0.3
0.36
7
6
Vref - 0.04
CAPACITANCE
O
(Ta=0 ~ 70 , Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)
C
Parameter
Limits(max.)
11.0
Notes
11
Symbol
CI(A)
Test Condition
Unit
pF
Input Capacitance, address pin
Input Capacitance, control pin
Input Capacitance, CK0 pin
Input Capacitance, I/O pin
VI - 1.25V
f=100MHz
VI = 25mVrm
pF
11.0
11
CI(C)
CI(K)
pF
pF
38.0
22.0
11
11
CI/O
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
16
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
AVERAGE SUPPLY CURRENT from Vdd
O
(Ta=0 ~ 70 C, Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
Limits(max)
Symbol
Parameter/Test Conditions
Unit Notes
-75
-10
OPERATING CURRENT: One Bank; Activ e-Precharge;
t RC = t RC MIN; t CK = t CK MIN; DQ, DM and DQS inputs changing
twice per clock cycle; address and control inputs changing once per
clock cycle
IDD0
1660
1543
mA
OPERATING CURRENT: One Bank; Activ e-Read-Precharge;
Burst = 2; t RC = t RC MIN; CL = 2.5; t CK = t CK MIN; IOUT= 0
mA;Address and control inputs changing once per clock cycle
IDD1
1705
760
940
940
1588
688
868
868
mA
mA
mA
mA
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
power-down mode; CKE VIL (MAX); t CK = t CK MIN
IDD2P
IDLE STANDBY CURRENT: /CS > VIH (MIN); All banks idle;
IDD2N CKE > VIH (MIN); t CK = t CK MIN; Address and other control inputs
changing once per clock cycle
ACTIVE POWER-DOWN STANDBY CURRENT: One bank activ e;
IDD3P
power-down mode; CKE VIL (MAX); t CK = t CK MIN
ACTIVE STANDBY CURRENT: /CS > VIH (MIN); CKE > VIH (MIN);
One bank; Activ e-Precharge; t RC = t RAS MAX; t CK = t CK MIN;
IDD3N
1210
2155
1930
1093
1993
1813
mA
mA
DQ,DM and DQS inputs changing twice per clock cycle; address and
other control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;One
IDD4R bank activ e; Address and control inputs changing once per clock
cycle; CL = 2.5; t CK = t CK MIN; IOUT = 0 mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
bank activ e; Address and control inputs changing once per clock
IDD4W
mA
mA
cycle; CL = 2.5; t CK = t CK MIN; DQ, DM and DQS inputs changing
twice per clock cycle
IDD5
IDD6
AUTO REFRESH CURRENT: t RC = t RFC (MIN)
SELF REFRESH CURRENT: CKE 0.2V
3730
454
3478
382
9
mA
AC OPERATING CONDITIONS AND CHARACTERISTICS
O
(Ta=0 ~ 70
, Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)
C
Limits
Symbol
Parameter/Test Conditions
Min.
Unit Notes
Max.
VIH(AC) High-Level Input Voltage (AC)
VIL(AC) Low-Level Input Voltage (AC)
Vref + 0.35
V
V
Vref - 0.35
VDDQ + 0.6
VID(AC) Input Differential Voltage, CLK and /CLK
VIX(AC) Input Crossing Point Voltage, CLK and /CLK
0.7
V
7
8
V
0.5*VDDQ-0.2 0.5*VDDQ+0.2
µA
IOZ
Ii
Off-state Output Current /Q floating Vo=0~VDDQ
Input Current / VIN=0 ~ VddQ
-5
5
µA
-10
10
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
17
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
AC TIMING REQUIREMENTS (Component Level)
O
(Ta=0 ~ 70 C , Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)
AC Characteristics
Parameter
-75
-10
Symbol
tAC
Min.
Max.
Min.
-0.8
Max.
+0.8
Unit Notes
ns
DQ Output Valid data delay time f rom CLK//CLK
-0.75
+0.75
tDQSCK DQ Output Valid data delay time f rom CLK//CLK
-0.75
+0.75
-0.8
+0.8
ns
tCH
tCL
CLK High lev el width
CLK Low lev el width
0.45
0.45
0.55
0.55
0.45
0.45
0.55
0.55
tCK
tCK
min(tCL,
tCH
min(tCL,t
CH
tHP
CLK half period
ns
20
CL=2.5
CL=2
7.5
10
15
15
8
15
15
ns
ns
tCK
CLK cycle time
10
tDH
tDS
Input Setup time (DQ,DM)
Input Hold time(DQ,DM)
0.5
0.5
0.6
0.6
2
ns
ns
tDIPW
tHZ
DQ and DM input pulse width (f or each input)
Data-out-high impedance time f rom CLK//CLK
Data-out-low impedance time f rom CLK//CLK
1.75
-0.75
-0.75
ns
+0.75
+0.75
+0.5
-0.8
-0.8
+0.8
+0.8
+0.6
+0.6
ns
14
14
tLZ
ns
tDQSQ DQS-DQ Skew(f or DQS and associated DQ signals)
tDQSA DQS-DQ Skew(f or DQS and all DQ signals)
ns
+0.5
ns
tQH
DQ/DQS output hold time f rom DQS
tHP-0.75
0.75
0.35
0.35
0.2
tHP-1.0
0.75
0.35
0.35
0.2
ns
tDQSS Write command to f irst DQS latching transition
tDQSH DQS input High lev el width
1.25
1.25
tCK
tCK
tCK
tCK
tCK
ns
tDQSL DQS input Low lev el width
tDSS
tDSH
tMRD
DQS f alling edge to CLK setup time
DQS f alling edge hold time f rom CLK
Mode Register Set command cycle time
0.2
0.2
15
15
tWPRES Write preamble setup time
tWPST Write postamble
0
0
ns
16
15
0.4
0.6
0.4
0.6
tCK
tCK
ns
tWPRE Write preamble
0.25
0.9
0.25
1.2
tIS
tIH
Input Setup time (address and control)
Input Hold time (address and control)
19
19
0.9
1.2
ns
tRPST Read postamble
tRPRE Read preamble
0.4
0.6
1.1
0.4
0.6
1.1
tCK
tCK
0.9
0.9
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
18
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
AC TIMING REQUIREMENTS(Continues)
O
(Ta=0 ~ 70
, Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)
C
AC Characteristics
Parameter
-75
-10
Symbol
tRAS
Min.
45
Max.
120,000
Min.
50
Max.
Unit Notes
Row Active time
120,000 ns
tRC
Row Cycle time(operation)
65
75
20
20
15
15
35
1
70
80
20
20
15
15
35
1
ns
ns
tRFC
tRCD
tRP
Auto Ref. to Active/Auto Ref. command period
Row to Column Delay
ns
Row Precharge time
ns
tRRD
tWR
Act to Act Delay time
ns
Write Recovery time
ns
tDAL
tWTR
tXSNR
tXSRD
tXPNR
tXPRD
Auto Precharge write recovery + precharge time
Internal Write to Read Command Delay
Exit Self Ref. to non-Read command
Exit Self Ref. to -Read command
Exit Power down to command
Exit Power down to -Read command
ns
tCK
ns
75
200
1
80
200
1
tCK
tCK
tCK
1
1
18
17
tREFI
Average Periodic Refresh interval
7.8
7.8
us
Output Load Condition
(f or component measurement)
VREF
DQS
VTT=VREF
50ohm
Zo=50 ohm
30pF
DQ
VREF
10cm
VOUT
VREF
Output Timing
Measurement
Reference
Point
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
19
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
Notes
1. All voltages referenced to Vss.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply
voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still
referenced to VREF (or to the crossing point for CK//CK), and parameter specifications are guaranteed for the specified
AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range
between VIL(AC) and VIH(AC).
4. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver will effectively switch
as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back
above (below) the DC input LOW (HIGH) level.
5. VREF is expected to be equal to 0.5*VddQ of the transmitting device, and to track variations in the DC level of the
same. Peak-to-peak noise on VREF may not exceed +/-2% of the DC value.
6. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set
equal to VREF, and must track variations in the DC level of VREF.
7. VID is the magnitude of the difference between the input level on CLK and the input level on /CLK.
8. The value of VIX is expected to equal 0.5*VddQ of the transmitting device and must track variations in the DC level of
the same.
9. Enables on-chip refresh and address counters.
10. IDD specification are tested after the device is properly initialized.
O
11. This parameter is sampled. VddQ = +2.5V+/-0.2V, Vdd = +2.5V+/-0.2V, f =100MHz, Ta = 25
, VOUT(DC)=
C
VddQ/2, VOUT(PEAK TO PEAK) = 25mV, DM inputs are grouped with I/O pins - reflecting the fact that they are
matched in laoding (to faciliate trace matching at the board level).
12. The CLK//CLK input reference level (for signals other than CLK//CLK) is the point at which CLK and /CLK cross;
the input reference level for signals other than CLK//CLK, is VREF.
13. Inputs are not recognized as valid until VREF stabilized. Exception: during the period before VREF stabilizes, CKE=<
0.3VddQ is recognized as LOW.
14. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not
referenced to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving
(LZ).
15. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this
parameter, but system performance (bus turnaround) will degrade accordingly.
16. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this
CLK edge. A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. When
no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous
write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
tDQSS.
17. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
18. tXPRD should be 200 tCLK in the condition of the unstable CLK operation during the power down mode.
19. For command/address and CLK & /CLK slew rate >1.0V/ns.
20. Min(tCL, tCH)refers to the smaller of the actual clock low time and the actualclock high time as provided to the
device.
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
20
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
(Component Level)
Read Operation
tCK
tCH
tCL
/CLK
CLK
tIS
tIH
Cmd &
Add.
Valid
VREF
Data
tDQSCK
tRPST
tRPRE
DQS
tDQSQ
tDV
tAC
DQ
Write Operation / tDQSS=max.
/CLK
CLK
tDQSS
tWPST
tDSS
tWPRES
DQS
tDQSH
tDH
tDQSL
tDS
tWPRE
DQ
Write Operation / tDQSS=min.
/CLK
CLK
tDSH
tDQSS
tWPST
tWPRES
DQS
tDQSH
tDH
tDQSL
tDS
tWPRE
DQ
MIT-DS-0390-1.0
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MITSUBISHI ELECTRIC
21
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
OPERATIONAL DESCRIPTION
BANK ACTIVATE
The DDR SDRAM has four independent banks. Each bank is activated by the ACT command
with the bank addresses (BA0,1). A row is indicated by the row address A12-0. The minimum
activation interval between one bank and the other bank is tRRD. Maximum 2 ACT commands
are allowed within tRC,although the number of banks which are active concurrently is not limited.
PRECHARGE
The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active,
the precharge all command (PREA,PRE+A10=H) is available to deactivate them at the same
time. After tRP from the precharge, an ACT command to the same bank can be issued.
Bank Activation and Precharge All (BL=8, CL=2 (Discrete level))
Module input and output timing.
/CLK
CLK
2 ACT command / tRCmin
tRCmin
Command
A0-9,11-12
ACT
READ
PRE
ACT
Xb
ACT
tRRD
tRAS
BL/2
tRP
Xa
Xb
Y
0
tRCD
Xb
Xb
A10
Xa
00
1
BA0,1
01
00
01
DQS
DQ
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7
Precharge all
A precharge command can be issued at BL/2(Discrete) from a read command without data loss.
MIT-DS-0390-1.0
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MITSUBISHI ELECTRIC
22
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
15
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
READ
After tRCD from the bank activation, a READ command can be issued. 1st Output data is
available after the /CAS Latency from the READ, followed by (BL-1) consecutive data when the
Burst Length is BL. The start address is specified by A11,A9-A0, and the address sequence of burst data
is defined by the Burst Type. A READ command may be applied to any active bank, so the row
precharge time (tRP) can be hidden behind continuous output data by interleaving the
multiple banks. When A10 is high at a READ command, the auto-precharge(READA) is
performed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal
precharge is complete. The internal precharge starts at BL/2(Discrete, In case of module, BL/2+1) after
READA. The next ACT command can be issued after (BL/2+tRP) from the previous READA.
Multi Bank Interleaving READ (BL=8, CL=2(Discrete level))
Module input and output timing.
/CLK
CLK
ACT
READ ACT
Command
A0-9,11-12
A10
READ
PRE
tRCD
Y
0
Xb
Xb
Xa
Xa
Y
0
0
BA0,1
00
10
00
00
10
DQS
DQ
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb7
Burst Length
Module /CAS latency (Discrete CL + 1)
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
23
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
READ with Auto-Precharge (BL=8, CL=2(Discrete))
Module input and output timing.
/CLK
CLK
BL/2 + tRP
Command
A0-9,11-12
A10
ACT
READ
ACT
Xb
tRCD
BL/2
tRP
Y
1
Xa
Xa
Xb
00
BA0,1
00
00
DQS
DQ
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7
Internal precharge start
(BL/2+1 in case of Module)
READ Auto-Precharge Timing (BL=8)
Module input and output timing.
/CLK
CLK
Command
ACT
READ
BL/2
Module Discrete
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7
CL=3.5 CL=2.5
DQ
Qa0 Qa1 Qa2 Qa3 Qa4 Qa5 Qa6 Qa7
CL=3
CL=2 DQ
Internal Precharge Start Timing
(In case of module, Precharge start at BL/2+1)
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
24
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set from the
WRITE command with data strobe input, following (BL-1) data are written into RAM, when the Burst
Length is BL. The start address is specified by A11,A9-A0, and the address sequence of burst data is
defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge
time (tRP) can be hidden behind continuous input data by interleaving the multiple banks. From the last
data to the PRE command, the write recovery time (tWRP) is required. When A10 is high at a WRITE
command, the auto-precharge(WRITEA) is performed. Any command(READ,WRITE,PRE,ACT) to the
same bank is inhibited till the internal precharge is complete. The next ACT command can be issued after
tDAL from the last input data cycle.
Multi Bank Interleaving WRITE (BL=8)
Module input and output timing.
/CLK
CLK
Command
A0-9,11-12
ACT
Xa
WRITE
WRITE
PRE
ACT
Xb
PRE
tRCD
tRCD
Yb
0
Ya
0
Xb
0
Xa
0
A10
BA0,1
10
00
00
00
10
10
DQS
DQ
Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 Db0 Db1 Db2 Db3 Db4 Db5 Db6 Db7
WRITE with Auto-Precharge (BL=8)
Module input and output timing.
/CLK
CLK
Command
WRITE
ACT
Xb
ACT
Xa
tRCD
tDAL
Y
1
A0-9,11-12
Xa
Xb
00
A10
BA0,1
00
00
DQS
DQ
Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
25
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
BURST INTERRUPTION
[Read Interrupted by Read]
Burst read operation can be interrupted by new read of any bank. Random column access is allowed.
READ to READ interval is minimum 1CLK.
Read Interrupted by Read (BL=8, CL=2(Discrete))
Module input and output timing.
/CLK
CLK
Command
READ
Yl
READ
Yk
READ READ
A0-9,11
Yi
0
Yj
0
0
A10
0
BA0,1
01
00
00
10
DQS
DQ
Qai0 Qai1 Qaj0 Qaj1 Qaj2 Qaj3 Qak0 Qak1 Qak2 Qak3 Qak4 Qak5 Qal0 Qal1 Qal2 Qal3 Qal4 Qal5 Qal6 Qal7
[Read Interrupted by precharge]
Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is
minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. As
a result, READ to PRE interval determines valid data length to be output. The figure below shows
examples of BL=8.
Read Interrupted by Precharge (BL=8)
/CLK
CLK
Command
READ
PRE
DQS
Q0 Q1 Q2 Q3 Q4 Q5
DQ
Module
CL=3.5
Command
READ
PRE
Discrete
CL=2.5
DQS
DQ
Q0 Q1 Q2 Q3
Command
READ PRE
DQS
DQ
Q0 Q1
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
26
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
Module input and output timing.
Read Interrupted by Precharge (BL=8)
/CLK
CLK
READ
PRE
Command
DQS
Q0 Q1 Q2 Q3 Q4 Q5
DQ
Module
CL=3.0
Command
READ
PRE
Discrete
CL=2.0
DQS
DQ
Q0 Q1 Q2 Q3
Command
READ PRE
DQS
DQ
Q0 Q1
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
27
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
[Read Interrupted by Burst Stop]
Burst read operation can be interrupted by a burst stop command(TERM). READ to TERM
interval is minimum 1 CLK. A TERM command to output disable latency is equivalent to the /CAS
Latency. As a result, READ to TERM interval determines valid data length to be output. The figure
below shows examples of BL=8.
Read Interrupted by TERM (BL=8)
Module input and output timing.
/CLK
CLK
Command
TERM
READ
READ
READ
DQS
Q0 Q1 Q2 Q3 Q4 Q5
DQ
Module
CL=3.5
Discrete
CL=2.5
Command
TERM
DQS
DQ
Q0 Q1 Q2 Q3
TERM
Command
DQS
DQ
Q0 Q1
Command
DQS
READ
READ
READ
TERM
Q0 Q1 Q2 Q3 Q4 Q5
DQ
Module
CL=3.0
Discrete
CL=2.0
Command
TERM
DQS
DQ
Q0 Q1 Q2 Q3
Command
TERM
DQS
DQ
Q0 Q1
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
28
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
[Read Interrupted by Write with TERM]
Module input and output timing.
/CLK
Read Interrupted by TERM (BL=8)
CLK
Module
TERM
Command
CL=3.5
Discrete
CL=2.5
READ
WRITE
DQS
DQ
Q0 Q1 Q2 Q3
D0 D1 D2 D3
Module
CL=3.0
Discrete
CL=2.0
TERM
Command
READ
WRITE
DQS
DQ
Q0 Q1 Q2 Q3
D0 D1 D2 D3 D4 D5
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
29
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
[Write interrupted by Write]
Burst write operation can be interrupted by write of any bank. Random column access is
allowed. WRITE to WRITE interval is minimum 1 CLK.
Write Interrupted by Write (BL=8)
Module input and output timing.
/CLK
CLK
Command
WRITE
WRITE
WRITE
WRITE
Yk
0
Yi
0
Yj
0
A0-9,11
Yl
0
A10
BA0,1
00
00
10
00
DQS
DQ
Dai Dai1 Daj Daj1 Daj Daj3 Dak Dak1 Dak Dak3 Dak Dak5 Dal Dal1 Dal Dal Dal Dal Dal Dal
0
0
2
0
2
4
0
2
3
4
5
6
7
[Write interrupted by Read]
Burst write operation can be interrupted by read of the same or the other bank. Random column access is
allowed. Internal WRITE to READ command interval(tWTR) is minimum 1 CLK. The input data on DQ
at the interrupting READ cycle is "don't care". tWTR is referenced from the first positive edge after the
last data input.
Module input and output timing.
Write Interrupted by Read (BL=8, CL=2.5(Discrete))
/CLK
CLK
Command
WRITE
READ
A0-9,11-12
Yi
0
Yj
0
A10
BA0,1
00
00
DM
tWTR
QS
DQ
Dai0 Dai1
Qaj0 Qaj1 Qaj2 Qaj3 Qaj4 Qaj5 Qaj6 Qaj7
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
30
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
[Write interrupted by Precharge]
Burst write operation can be interrupted by precharge of the same or all bank. Random column access is
allowed. tWR is referenced from the first positive CLK edge after the last data input.
Write Interrupted by Precharge (BL=8, CL=2.5(Discrete))
Module input and output timing.
/CLK
CLK
Command
WRITE
PRE
A0-9,11-12
Yi
0
A10
BA0,1
DM
00
00
tWR
QS
DQ
Dai0 Dai1
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
31
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
[Initialize and Mode Register sets]
/CLK
CLK
Command
NOP
PRE
EMRS
Code
Code
1 0
MRS
Code
Code
0 0
PRE
AR
AR
MRS
Code
Code
0 0
ACT
Xa
A0-9,11,12
A10
Xa
1
1
BA0,1
DQS
Xa
DQ
tMRD
tMRD
tRP
tRFC
tRFC
tMRD
[AUTO REFRESH]
Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,/WE=CKE=H) command. The
refresh address is generated internally. 8192 REFA cycles within 64ms refresh 256Mbits memory cells.
The auto-refresh is performed on 4 banks concurrently. Before performing an auto refresh, all banks must
be in the idle state. Auto-refresh to auto-refresh interval is minimum tRFC . Any command must not be
supplied to the device before tRFC from the REFA command.
Auto-Refresh
/CLK
CLK
/CS
NOP or DESELECT
/RAS
/CAS
/WE
tRFC
CKE
A0-12
BA0,1
Auto Refresh on All Banks
Auto Refresh on All Banks
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
32
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
[SELF REFRESH]
Self -refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,/WE=H,CKE=L). Once
the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE
is asynchronous and the only enable input, all other inputs including CLK are disabled and ignored, so that
power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK
inputs, asserting DESEL or NOP command and then asserting CKE for longer than tXSNR/tXSRD.
Self-Refresh
/CLK
CLK
/CS
/RAS
/CAS
/WE
CKE
A0-12
BA0,1
X
X
Y
Y
tXSRD
tXSNR
Read
Act
Self Refresh Exit
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
33
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
[Asynchronous SELF REFRESH]
Asynchronous Self -refresh mode is entered by CKE=L within 2 tCLK after issuing a REFA command
(/CS=/RAS=/CAS=L,/WE=H). Once the self-refresh is initiated, it is maintained as long as CKE is kept
low. During the self-refresh mode, CKE is asynchronous and the only enable input, all other inputs
including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved.
To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then
asserting CKE for longer than tXSNR/tXSRD.
Asynchronous Self-Refresh
/CLK
CLK
/CS
/RAS
/CAS
/WE
CKE
max 2 tCLK
A0-12
BA0,1
tXSNR
Act
Self Refresh Exit
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
34
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
[Power DOWN]
The purpose of CLK suspend is power down. CKE is synchronous input except during the self-refresh
mode. A command at cycle is ignored. From CKE=H to normal function, DLL recovery time is NOT
required in the condition of the stable CLK operation during the power down mode.
Power Down by CKE
/CLK
CLK
Standby Power
CKE
Down
Command
NOP
NOP
PRE
ACT
Valid
Valid
NOP
NOP
tXPNR/
tXPRD
Active Power
Down
CKE
Command
[DM CONTROL]
DM is defined as the data mask for writes. During writes,DM masks input data word by word. DM to
write mask latency is 0.
DM Function(BL=8,CL=2(Discrete))
Module input and output timing.
/CLK
CLK
Command
Write
READ
DM
Don't Care
DQS
DQ
Q2 Q3 Q4
Q0 Q1
D0 D1
D3 D4 D5 D6
D7
masked by DM=H
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
35
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
133.35
3.00
3.00
4-R2
2 - 2.50
1.8
6.35
1.27
64.77
6.35
49.53
73.295
128.95
3.9Max
1.27
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
36
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
Serial Presence Detect Table I
Function described
SPD DATA(hex)
Byte
SPD enrty data
Number of Serial PD Bytes Written during Production
Total # bytes of SPD memory device
Fundamental memory type
0
1
2
3
4
5
6
7
8
9
128
256 Bytes
SDRAM DDR
13
80
08
07
0D
0A
# Row Addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly...
10
2BANK
x72
02
48
00
04
75
80
75
80
0
... Data Width continuation
SSTL2.5V
7.5ns
Voltage interface standard of this assembly
SDRAM Cycletime at Max. Supported CAS Latency (CL).
-75
-10
-75
-10
8.0ns
Cycle time for CL=2.5
+0.75ns
+0.8 ns
10
SDRAM Access from Clock
tAC for CL=2.5
ECC
7.8uS/SR
x8
02
82
11
12
13
14
15
16
17
18
19
20
21
22
DIMM Configuration type (Non-parity,Parity,ECC)
Refresh Rate/Type
08
08
01
SDRAM width,Primary DRAM
x8
Error Checking SDRAM data width
1 clock
MIimum Clock Delay, Random Column Access
2, 4, 8
Burst Lengths Supported
Number of Device Banks
0E
04
0C
01
4bank
2.0, 2.5
0
CAS# Latency
CS# Latency
02
1
WE Latency
Registered with PLL
Differential Clock
SDRAM Module Attributes
SDRAM Device Attributes:General
26
00
VDD + 0.2V
-75
10ns
A0
SDRAM Cycle time(2nd highest CAS latency)
Cycle time for CL=2
23
10ns
-10
-75
A0
75
+0.75ns
SDRAM Access form Clock(2nd highest CAS latency)
tAC for CL=2
24
25
-10
+0.8ns
N/A
80
00
00
75
80
-75
-10
SDRAM Cycle time(3rd highest CAS latency)
N/A
+0.75ns
+0.8ns
-75
-10
26
27
SDRAM Access form Clock(3rd highest CAS latency)
Minimum Row Precharge Time (tRP)
20ns
15ns
20ns
45ns
50
3C
50
28
29
Minimum Row Active to Row Active Delay (tRRD)
RAS to CAS Delay Minv (tRCD)
-75
-10
2D
32
30
Active to Precharge Min (tRAS)
50ns
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
37
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
Serial Presence Detect Table II
31
32
Density of each bank on module
256MByte
0.9nS
40
90
-75
-10
Command and Address signal input setup time
1.2nS
C0
90
0.9nS
1.2nS
0.5nS
0.6nS
0.5nS
0.6nS
-75
-10
33
34
Command and Address signal input hold time
Data signal input setup time
C0
-75
-10
-75
-10
50
60
50
60
35
Data signal input hold time
Superset Information (may be used in future)
SPD Revision
option
0
36-61
00
00
62
10
Check sum for -75
63
Checksum for bytes 0-62
B6
Check sum for -10
MITSUBISHI
64-71
Manufactures Jedec ID code per JEP-108E
1CFFFFFFFFFFFFFF
Manufacturing location
xx
72
Manufacturing location
73-90
Manufactures Part Number
4D4836344437324B4C482D37352020202020
4D4836344437324B4C482D31302020202020
MH64D72KLH-75
MH64D72KLH-10
91-92
93-94
Revision Code
Manufacturing date
Assembly Serial Number
Reserved
PCB revision
year/week code
serial number
Undefined
rrrr
yyww
ssssssss
00
95-98
99-127
128-255
Open for Customer Use
Undefined
00
MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
38
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH64D72KLH-75,-10
4,831,838,208-BIT (67,108,864-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products
better and more reliable, but there is always the possibility that trouble may occur with them.
Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with
appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-
flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the selection of the
Mitsubishi semiconductor product best suited to the customer's application; they do not
convey any license under any intellectual property rights, or any other rights, belonging to
Mitsubishi Electric Corporation or a third party.
2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement
of any third-party's rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
3.All information contained in these materials, including product data, diagrams, charts,
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these materials, and are subject to change by Mitsubishi Electric Corporation without notice
due to product improvements or other reasons. It is therefore recommended that customers
contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
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MIT-DS-0390-1.0
24.Nov.2000
MITSUBISHI ELECTRIC
39
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