M64282FP [MITSUBISHI]
Mitsubishi Integrated Circuit Image Sensor (Artificial Retina LSI); 三菱集成电路图像传感器（人造视网膜LSI ）
| 型号： | M64282FP |
| 厂家： | 
Mitsubishi Group |
| 描述： | Mitsubishi Integrated Circuit Image Sensor (Artificial Retina LSI) |
| 文件： | 总18页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Mitsubishi Integrated Circuit
M64282FP
Image Sensor (Artificial Retina LSI)
PRELIMINARY
MITSUBISHI
1. Description
M64282FP is a 128 x 128 pixel
CMOS image sensor with built-in
image processing and analog
image output tuning functions. This
device can detect an image and
process the image simultaneously
as human retinas can. M64282FP
can achieve smaller system size,
lower power consumption, and
more intelligent image processing
functions.
PIN CONFIGURATION (TOP VIEW)
RESET
READ
TSW
Xck
Xrst
LOAD
DGND
DVDD
SIN
PGND
PVDD
VOUT
AVDD
AGND
NC
START
Outline : 16C 9-B
2. Features
l
l
l
l
l
Single 5.0V supply
Low power dissipation ( Typ. 15 mW )
Positive and negative image output
Edge enhancement / extraction
Output level & gain tuning
3. Application
Image input device, Gaming, Human interface for PC, etc.
4. Block Diagram
AGND
AVDD
VOUT
14
PVDD
13
PGND
12
TSW
11
READ
10
RESET
9
16
15
Level
Control
Gain
Control
Edge
Control
Pixel Array
128 x 128
LOGIC
2
6
1
3
4
5
7
8
START
NC
SIN
DVDD
DGND
LOAD
Xrst
Xck
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Mitsubishi Integrated Circuit
M64282FP
Image Sensor (Artificial Retina LSI)
PRELIMINARY
MITSUBISHI
5. Pin Configuration
9
8
1
16
Pin No. Symbol
Function
1
START
Start Input
Image sensing start.
Pulled down internally by 10k ohm.
Non Connect
2
3
NC1
SIN
Data Input
Parameter input.
Pulled down internally by 10k ohm.
4
DVDD Digital Power Supply Power for logic circuits.
Must be connected to 5.0 V digital supply.
Ground for logic parts.
5
6
DGND
LOAD
Digital GND
Data Set Input
Parameter set enable.
Pulled down internally by 10k ohm.
System reset terminal.
7
8
9
Xrst
Xck
System Reset
Pulled up internally by 10k ohm. Low active.
Clock input for MUX.
System Clock Input
Pulled down internally by 10k ohm.
RESET Memory Reset Input Parameter register reset.
Pulled up internally by 10k ohm. Low active
Read image signal.
10
11
READ
TSW
Read Image
Reserved
NOTE: Don’t connect to this pin.
Ground for analog circuits.
12 AGND1
Analog GND
13
AVDD1 Analog Power Supply Power for analog circuits.
Must be connected to 5.0 V analog supply.
Analog image signal output in voltage.
AVDD2 Analog Power Supply Power for analog circuits.
Must be connected to 5.0 V analog supply.
14
15
Vout
Signal Output
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Mitsubishi Integrated Circuit
M64282FP
Image Sensor (Artificial Retina LSI)
PRELIMINARY
MITSUBISHI
16
AGND2
Analog GND
Ground for analog circuits.
6. Image Sensing Specifications 1
Item
Specification
128 x 123
1/4 inch
1
2
Resolution
Optical System
7. Image Sensing Specifications 2
Item
Specification
1lx ~ 10000lx*
16 µsec ~ 1sec
500KHz
1
2
3
4
5
Detectable Illumination Range (Faceplate)
Exposure Time Range
System Clock (Xck)
Frame Rate
10 fps ~ 30 fps
2.0Vp-p
Output Voltage Range (Vout)
* Under Halogen Light Valve Illumination
8. Electrical Specifications - Absolute Maximum Ratings
Limits
Symbol
Parameter
Unit
Min.
4.5
Typ.
5.0
Max.
5.5
DVDD
AVDD
Digital Power Supply Voltage
Analog Power Supply Voltage
V
V
4.5
5.0
5.5
9. Electrical specifications - DC Specifications
Limits
Typ.
Symbol
Parameter
Unit
Min.
4.5
0.0
2.2
0.0
Max.
DVDD
0.5
VOH
VOL
VIH
"H" Output Voltage (READ)
"L" Output Voltage (READ)
"H" Input Voltage
V
V
V
V
DVDD
0.8
VIL
"L" Input Voltage
10. AC Timing Requirements
See the waveforms on page 5 and 6.
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Mitsubishi Integrated Circuit
M64282FP
Image Sensor (Artificial Retina LSI)
PRELIMINARY
MITSUBISHI
Limits
Units
Symbol
Parameter
Min
2
Typ.
Max
tcr
tWHX
tWLX
tr
Xck cycle time
Xck high pulse width
Xck low pulse width
Xck rise time
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
0.8
0.8
-
-
-
0.2
tf
Xck fall time
-
0.2
tSS
SIN setup time
0.4
0.4
0.4
0.4
0.8
0.4
0.4
0.4
0.4
-
tHS
tSL
SIN hold time
-
LOAD setup time
LOAD hold time
LOAD high pulse width
Xrst setup time
-
tHL
tWLX-0.4
tWHL
tSXR
tHXR
tSR
tHR
-
-
-
-
-
Xrst hold time
RESET setup time
RESET hold time
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Mitsubishi Integrated Circuit
M64282FP
Image Sensor (Artificial Retina LSI)
PRELIMINARY
MITSUBISHI
(A) Xck, SIN Timing
tcr
75%
Xck
25%
tr
tf
tWHX
tWLX
SIN
SS
HS
t
t
(B) Xck, LOAD Timing
Xck
tWHL
LOAD
tSL
tHL
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Mitsubishi Integrated Circuit
M64282FP
Image Sensor (Artificial Retina LSI)
PRELIMINARY
MITSUBISHI
(C) Xck, Xrst, RESET Timing
Xck
Xrst
SXR
HXR
t
t
RESET
SR
HR
t
t
(D) Xck, START Timing
Xck
START
SST
HST
t
t
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Mitsubishi Integrated Circuit
M64282FP
Image Sensor (Artificial Retina LSI)
PRELIMINARY
MITSUBISHI
11. Operation
Reset
Exposure
Time Setup
Image Sensing
Mode Setup
Parameter
Setup
Start Sensing
Data
Output
END
Fig. 11-1 Operation Flow Chart
Figure 11-1 shows the image sensing sequence. First of all, all the registers must be
reset and must be initialized to the appropriate values. The reset sequence completes
when both Xrst and RESET signals are set low. There are 8 sets of registers, each of
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Mitsubishi Integrated Circuit
M64282FP
Image Sensor (Artificial Retina LSI)
PRELIMINARY
MITSUBISHI
which consists of 8 bits of data. Each input data consists of 11 bits; of these 11 bits, the
first 3 bits are the address and the last 8 bits are the data. The input data is latched at the
rising edge of Xck when LOAD signal is high, and the data of a register become valid at
the falling edge of Xck.
After all register are set, START signal must be asserted. Then, image sensing
sequence starts at the rising edge of Xck. Image sensing sequence consists of two
different processes: the exposing process to adjust the light intensity and the image read
process to put out the image data after converting optical signal into electrical signal. After
the exposure time defined by the registers 2 and 3 has passed, analog image data (total
16k pixels) is read out. To read image signal, READ signal must be asserted. At this
moment, it becomes possible to change the registers, because the registers are irrelevant
to the image read sequence.
Once image sensing sequence starts, the chip will continue to put out image data until
it is reset.
11.1. Parameter Register Assignments
Symbol
Bit Assignment
1 bit
Operation
Exclusively set edge enhancement mode
Select vertical - horizontal edge operation mode
Edge enhancement ratio
N
VH
E
2 bits
4 bits
Z
2 bits
Zero point calibration
( Set the dark level output signal to Vref )
I
C0, C1
O
1 bit
8 bits x 2
6 bits
Select inverted/non-inverted output
Exposure time
Output reference voltage
( In both plus and minus direction )
Output node bias voltage (Vref)
V
3 bits
G
5 bits
Analog output gain
1-D filtering kernel.
P, M, X
8 bits x 3
11.2. Image Acquisition Modes
(a) Positive Image
(b) Negative Image 1
(c) Negative Image 2
Set “P” register
Set “I” register
Set “M” register (optional)
(d) Edge Extraction (V, H, 2-D)
(e) Edge Extraction (1-D)
(f) Edge Enhancement
(g) Offset Level Output
Set “N” and “VH” register
Set “P” and “M” register (optional)
Set “N”, “VH” and “E” register
Set “0” to both “C0” and “C1”
11.3
Register Assignment
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Mitsubishi Integrated Circuit
M64282FP
Image Sensor (Artificial Retina LSI)
PRELIMINARY
MITSUBISHI
Reg. No.
Address
7
6
5
4
3
G3
C13
C03
P3
M3
X3
I
2
1
0
1
2
3
4
5
6
7
0
001
010
011
100
101
110
111
000
N
VH1
C16
C06
P6
VH0
C15
C05
P5
G4
C14
C04
P4
G2
C12
C02
P2
G1
C11
C01
P1
G0
C10
C00
P0
C17
C07
P7
M7
X7
E3
Z1
M6
X6
M5
X5
M4
X4
M2
X2
M1
X1
M0
X0
E2
E1
E0
V2
V1
V0
Z0
O5
O4
O3
O2
O1
O0
11.4. Data LOAD sequence
Xck
SIN
A
A
A
D
D
D
D
D
D
D
D
0
2
1
0
7
6
5
4
3
2
1
3 bit address
8 bit data
LOAD
11.5. About the image processing functions
Artificial retina chip can put out positive, negative, edge extracted, and edge enhanced
image in accordance with the parameter register settings.
On-chip image processing is done with the 3 x 3 neighboring pixels. This chip executes
subtraction between the central pixel P and the four neighboring pixels MN, MS, MW, and
ME(see the right figure) to realize edge extraction as shown
below: vertical edge (V edge), horizontal edge (H edge), and 2
N
dimensional edge (2-D edge). Moreover, this chip can program
the weight value of the central pixel P and the other four pixels to
W
E
produce edge enhanced images.
S
Four connected
neighboring pixels
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Mitsubishi Integrated Circuit
M64282FP
Image Sensor (Artificial Retina LSI)
PRELIMINARY
MITSUBISHI
Positive
V edge
H edge
2-D edge
Edge Modes
Output Signal
Effective Pixels
V-Edge Extraction
{2P - (MN+MS)} x a
128(H) x 121(V)
128(H) x 123(V)
128(H) x 123(V)
128(H) x 121(V)
128(H) x 121(V)
128(H) x 123(V)
128(H) x 121(V)
P-MS
H-Edge Extraction
{2P - (MW+ME)} x a
2D-Edge Extraction
V-Edge Enhancement
H-Edge Enhancement
2D-Edge Enhancement
{4P - (MN+MS+ME+MW)} x a
P + {2P - (MN+MS)} x a
P + {2P - (MW+ME)} x a
P + {4P - (MN+MS+ ME+ MW)} x a
a is the edge enhancement ratio set by “E” register.
P and M indicate the signal value from each pixel.
11.6. Register Descriptions
11.6.1. “N” register (1 bit)
If the “N” register is set, P and M registers (see 11.6.11.) are exclusively set to a
specific vertical edge extraction / enhancement mode. In the case of “H”, for example, P
register is set to 02 (HEX), and M register is set to 05 (HEX). If “N” register is set, access
to P and M registers is always ignored.
11.6.2. “VH” register (2 bits)
The “VH” register selects vertical, horizontal, and 2-dimensional edge
extraction/enhancement operation.
Register Setting
Edge Mode
V H 1
V H 0
0
0
0
1
No edge operation
Horizontal edge mode
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Mitsubishi Integrated Circuit
M64282FP
Image Sensor (Artificial Retina LSI)
PRELIMINARY
MITSUBISHI
1
1
0
1
Vertical edge mode
2-D edge mode
11.6.3. “E” register (4 bits)
The “E” register sets the edge enhancement ratio a . The most significant bit E3
specifies edge enhancement mode or edge extraction mode: “H” for edge extraction mode
and “L” for edge enhancement mode. (In the case of normal image sensing operation, E3
should be set low) The ratio a is set as follows. 100 % means the same level as the P
signal, which is the signal of the central pixel in the 3x3 processing kernel.
Register Setting
Edge Enhancement Ratio
E2
E1
0
E0
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
50 %
75 %
0
1
100 %
125 %
200 %
300 %
400 %
500 %
1
0
0
1
1
11.6.4. “Z” Register (2 bits)
It calibrates the zero value by setting the dark level output signal to Vref.
Register Setting
Calibration
Z1
0
Z0
0
No calibration
1
0
Calibration for positive signal
Calibration for negative signal
0
1
11.6.5. “I” register (1 bit)
If the “I” register is set to “H”, the output signal is inverted. if it is set to “L”, the signal is
not inverted.
11.6.6. “C0 & C1” register (8 bits x 2)
Both C0 and C1 registers determine Exposure time; the sum of the value of C0 register
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Mitsubishi Integrated Circuit
M64282FP
Image Sensor (Artificial Retina LSI)
PRELIMINARY
MITSUBISHI
and that of C1 register determines the actual exposure time.
The offset level of image output can be obtained by setting both of C0 and C1 registers
to 00 (the minimum exposure time). In this case, all pixels are read out as black level
(optical black). The signal output format is the same as that of the normal output image.
(Synchronized with the READ signal.)
“C0” register (8 bits)
Register Setting
00 (HEX)
Exposure time (msec)
0
FF (HEX)
4.080
Step width
16 µsec
256
Step number
“C1” register (8 bits)
Register Setting
00 (HEX)
Exposure time (msec)
0
FF (HEX)
1044.5
Step width
4.096 msec
256
Step number
Notice: In the case of vertical edge extraction / enhancement mode, the exposure time
should be greater than 0.768 msec.
11.6.7. “O” register (6 bits)
The “O” register adjusts the offset level of the signal voltage. The most significant bit
O5 is the sign bit: “H” for plus direction, “L” for minus direction modulation. The offset is
adjusted by 5 bit accuracy. The maximum absolute value of the offset level is 1V.
( In the case O5 is “H”. )
Register Setting
20 (HEX)
Offset voltage (V)
0
1
3F (HEX)
Step width
32mV
32
Step number
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Mitsubishi Integrated Circuit
M64282FP
Image Sensor (Artificial Retina LSI)
PRELIMINARY
MITSUBISHI
(In the case O5 is “L”)
Register Setting
00 (HEX)
Offset voltage (V)
0
1F (HEX)
-1
Step width
-32mV
32
Step number
11.6.8. “V” register ( 3 bits )
It sets the output node voltage Vref.
Register Setting
Vref (V)
V2
0
V1
0
V0
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
11.6.9. “G” register (5 bits)
The “G” register sets the output gain of the image output signal. If the most significant
bit G4 is “H”, The total gain increases by 6dB.
Register Setting
Total Gain (dB)
G4
G3
G2
G1
G0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
14.0
15.5
17.0
18.5
20.0
21.5
23.0
20.0
21.5
23.0
24.5
26.0
27.5
29.0
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Mitsubishi Integrated Circuit
M64282FP
Image Sensor (Artificial Retina LSI)
PRELIMINARY
MITSUBISHI
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
24.5
26.0
29.0
32.0
35.0
38.0
41.0
45.5
51.5
30.5
32.0
35.0
38.0
41.0
44.0
47.0
51.5
57.5
11.6.10. Typical register settings
The following table shows the typical image acquisition modes and the register settings
to each mode.
Mode
Z1
Z0
N
VH1 VH0
P
M
X
E3
I
Posi.
Inv.
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
01
01
01
01
01
01
01
01
01
01
01
01
01
01
00
00
00
00
00
00
00
00
00
00
00
00
00
00
01
01
01
01
01
01
01
01
01
01
01
01
01
01
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
H Enh.
H Enh. Inv.
H Ext.
H Ext. Inv.
V Enh.
V Enh. Inv.
V Ext.
V Ext. Inv.
2D Enh.
2D Enh. Inv.
2D Ext.
2D Ext. Inv.
11.6.11. P and M register settings for programmable 1-D filtering
Both P and M registers specify 1-D filtering kernel consisting of +1, 0 and -1 weight
values. The kernel is processed with the image pixels along vertical direction.
The following table shows the typical image acquisition modes and the register
settings. Some modes are the same as those of the table in 11.6.10. Moreover,
“Negative” output in the table is the same as the “Inverted” output in the table in 11.6.10.
V(PM) mode works similar to the filtering pattern of (+1, -1).
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Mitsubishi Integrated Circuit
M64282FP
Image Sensor (Artificial Retina LSI)
PRELIMINARY
MITSUBISHI
Mode
Z1
Z0
N
VH1 VH0
P
M
X
E3
I
Posi.
Neg.
1
0
0
1
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
01
00
01
02
02
02
02
00
01
02
05
05
05
05
01
01
01
01
01
01
01
0
0
0
0
1
0
1
0
1
0
0
0
0
0
V (PM)
V Enh.
V Ext.
2D Enh.
2D Ext.
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Mitsubishi Integrated Circuit
M64282FP
Image Sensor (Artificial Retina LSI)
PRELIMINARY
MITSUBISHI
12. Operation Timing
(1) Chip Reset
Reset timing of the chip. Reset timing is synchronized with the rising edge of Xck
clock.
(2) Data Input
Settings of the exposure time, initial value of each scanner, Vref value, and gain value.
Data (8 bits x 8) input timing is synchronized with the rising edge of Xck clock.
(3) Image Data Output
Image pixel data is serially read out synchronized with Xck clock.
(1) Chip Reset
1 clock cycle
Xck
XRST
RESET
(2) Data Input
Xck
SIN
A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
LOAD
Data 0
Data 7
becomes
valid
becomes
valid
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Mitsubishi Integrated Circuit
M64282FP
Image Sensor (Artificial Retina LSI)
PRELIMINARY
MITSUBISHI
(3) Image Data Output
Xck
START
Exposure Time
READ
Vout
(0,0)
(1,0)(2,0)(3,0)
(127,0()0,1)(1,1)
Start sensing 1st frame.
Start 1st frame
(start exposre)
image data output.
Xck
START
READ
Exposure Time
Vout
(124,127)
(126,127)
(127,127)
(125,127)
End sensing 1st frame.
Start sensing 2nd frame.
(START signal is automatically
generated inside the chip 5 clocks
after the fall edge of READ. )
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Mitsubishi Integrated Circuit
M64282FP
Image Sensor (Artificial Retina LSI)
PRELIMINARY
MITSUBISHI
13. Outline dimension
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