M5M29GB161BWG
更新时间：2024-09-18 01:52:08
品牌：MITSUBISHI
描述：16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
概述
规格参数
数据手册M5M29GB161BWG 概述
16,777,216-BIT (1048,576-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY 16777216位（ 1048,576 - WORD BY16 - BIT ） CMOS 3.3V -ONLY ，块擦除闪存 闪存
M5M29GB161BWG 规格参数
| 生命周期： | Obsolete | 零件包装代码： | BGA |
| 包装说明： | TFBGA, | 针数： | 48 |
| Reach Compliance Code： | unknown | ECCN代码： | EAR99 |
| HTS代码： | 8542.32.00.51 | 风险等级： | 5.84 |
| Is Samacsys： | N | 最长访问时间： | 90 ns |
| 其他特性： | 100K ERASE/PROGRAM CYCLES | JESD-30 代码： | R-PBGA-B48 |
| 长度： | 8.5 mm | 内存密度： | 16777216 bit |
| 内存集成电路类型： | FLASH | 内存宽度： | 16 |
| 功能数量： | 1 | 端子数量： | 48 |
| 字数： | 1048576 words | 字数代码： | 1000000 |
| 工作模式： | ASYNCHRONOUS | 最高工作温度： | 85 °C |
| 最低工作温度： | -40 °C | 组织： | 1MX16 |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | TFBGA |
| 封装形状： | RECTANGULAR | 封装形式： | GRID ARRAY, THIN PROFILE, FINE PITCH |
| 并行/串行： | PARALLEL | 编程电压： | 3.3 V |
| 认证状态： | Not Qualified | 座面最大高度： | 1.06 mm |
| 最大供电电压 (Vsup)： | 3.6 V | 最小供电电压 (Vsup)： | 2.7 V |
| 标称供电电压 (Vsup)： | 3.3 V | 表面贴装： | YES |
| 技术： | CMOS | 温度等级： | INDUSTRIAL |
| 端子形式： | BALL | 端子节距： | 0.75 mm |
| 端子位置： | BOTTOM | 宽度： | 7 mm |
| Base Number Matches： | 1 |
M5M29GB161BWG 数据手册
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PDF下载MITSUBISHI LSIs
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
DESCRIPTION
The MITSUBISHI Mobile FLASH M5M29GB/T161BWG are 3.3V-only high speed 16,777,216-bit CMOS boot block Flash Memories with
alternating BGO (Back Ground Operation) feature. The BGO feature of the device allows Program or Erase operations to be performed in
one bank while the device simultaneously allows Read operations to be performed on the other bank. This BGO feature is suitable for
mobile and personal computing, and communication products. The M5M29GB/T161BWG are fabricated by CMOS technology for the
peripheral circuits and DINOR(Divided bit line NOR) architecture for the memory cells, and are available in 6x8-balls CSP (0.75mm ball
pitch) .
FEATURES
Boot Block
.................................
Organization
1048,576 word x 16bit
(M5M29GB/T161BWG)
........................
........................
M5M29GB161BWG
M5M29GT161BWG
Bottom Boot
Top Boot
.............................
Supply voltage ................................
VCC = 2.7~3.6V
90ns (Max.)
Other Functions
Soft Ware Command Control
Selective Block Lock
..............................
Access time
Erase Suspend/Resume
Program Suspend/Resume
Status Register Read
Alternating Back Ground Program/Erase Operation
Between Bank(I) and Bank(II)
Power Dissipation
Read
.................................
..........
54 mW (Max. at 5MHz)
0.33µW (typ.)
(After Automatic Power saving)
Program/Erase
Standby
.......................
.................................
.......................
126 mW (Max.)
0.33µW (typ.)
0.33µW (typ.)
Deep power down mode
Auto program for Bank(I)
Program Time
Program Unit
Package
7mm x 8.5mm CSP (Chip Scale Package)
6 x 8 balls, 0.75mm ball pitch
.................................
4ms (typ.)
-
.........................
.........................
(Byte Program)
(Page Program)
1word
128word
Auto program for Bank(II)
.................................
.................................
APPLICATION
Digital Cellular Phone
Telecommunication
Mobile Computing Machine
PDA (Personal Digital Assistance)
Car Navigation System
Video Game Machine
Program Time
Program Unit
Auto Erase
Erase time
4ms (typ.)
128word
.................................
.....................
40 ms (typ.)
Erase Unit
Bank(I) Boot Block
16Kword x 1
16Kword x 7
32Kword x 28
..............
......................
Parameter Block
Bank(II) Main Block
.........................................
Program/Erase cycles
100Kcycles
PIN CONFIGURATION (TOP VIEW)
8.5mm
A19
A17
A6
A13
A14
A15
A11
A10
A8
WP2# WP1#
A7
A5
A4
A2
6
5
4
A18
NC
WE# RP#
A3
A12
D14
A9
NC
A1
A0
D11
CE#
A16
NC
D5
D6
D2
D3
D8
D9
3
GND
OE#
D0
D1
D12
D4
D15
D7
2
1
D10
GND
D13
VCC
A
B
C
D
E
F
G
H
INDEX
M5M29GB/T161BWG
CSP(0.75mm ball pitch):48FJA
NC : NO CONNECTION
16-bit version
Sep.1999. Rev4.0
1
MITSUBISHI LSIs
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
BLOCK DIAGRAM
A19
A18
A17
128 WORD PAGE BUFFER
Main Block
32KW
VCC (3.3V)
GND (0V)
A16
A15
A14
A13
A12
A11
A10
A9
28
X-DECODER
Main Block
32KW
16KW
Parameter Block7
Parameter Block6
Parameter Block5
Parameter Block4
Parameter Block3
Parameter Block2
ADDRESS
INPUTS
16KW
16KW
16KW
16KW
16KW
16KW
16KW
A8
A7
Parameter Block1
Boot Block
A6
A5
A4
Y-GATE / SENSE AMP.
MULTIPLEXER
Y-DECODER
A3
A2
A1
A0
STATUS / ID REGISTER
CHIP ENABLE INPUT
CE#
OUTPUT ENABLE INPUT OE#
WRITE ENABLE INPUT WE#
WRITE PROTECT INPUT WP1#
CUI
WSM
WRITE PROTECT INPUT
WP2#
INPUT/OUTPUT
BUFFERS
RESET/POWER DOWN INPUT RP#
DQ15 DQ14DQ13DQ12
DQ3DQ2DQ1DQ0
DATA INPUTS/OUTPUTS
M5M29GB/T161BWG (16 bit version)
Sep.1999. Rev4.0
2
MITSUBISHI LSIs
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
FUNCTION
Deep Power-Down
The M5M29GB/T161BWG includes on-chip program/erase control
circuitry. The Write State Machine (WSM) controls block erase
and byte/page program operations. Operational modes are
selected by the commands written to the Command User Interface
(CUI). The Status Register indicates the status of the WSM and
when the WSM successfully completes the desired program or
block erase operation.
When RP# is at VIL, the device is in the deep powerdown
mode and its power consumption is substantially low. During
read modes, the memory is deselected and the data
input/output are in a high-impedance(High-Z) state. After
return from powerdown, the CUI is reset to Read Array , and
the Status Register is cleared to value 80H.
During block erase or program modes, RP# low will abort
either operation. Memory array data of the block being altered
become invalid.
A Deep Powerdown mode is enabled when the RP# pin is at GND,
minimizing power consumption.
Automatic Power-Saving (APS)
Read
The Automatic Power-Saving minimizes the power
consumption during read mode. The device automatically
turns to this mode when any addresses or CE# isn't changed
more than 200ns after the last alternation. The power
consumption becomes the same as the stand-by mode. While
in this mode, the output data is latched and can be read out.
New data is read out correctly when addresses are changed.
The M5M29GB/T161BWG has three read modes, which accesses
to the memory array, the Device Identifier and the Status Register.
The appropriate read command are required to be written to the
CUI. Upon initial device powerup or after exit from deep
powerdown, the M5M29GB/T161BWG automatically resets to read
array mode. In the read array mode, low level input to CE# and
OE#, high level input to WE# and RP#, and address signals to the
address inputs (A19-A0:M5M29GB/T161BWG) output the data of
the addressed location to the data input/output
(D15-D0:M5M29GB/T161BWG).
Write
Writes to the CUI enables reading of memory array data, device
identifiers and reading and clearing of the Status Register. They
also enable block erase and program. The CUI is written by
bringing WE# to low level, while CE# is at low level and OE# is at
high level. Address and data are latched on the earlier rising edge
of WE# and CE#. Standard micro-processor write timings are
used.
Alternating Background Operation (BGO)
The M5M29GB/T161BWG allows to read array from one bank
while the other bank operates in software command write cycling
or the erasing / programming operation in the background. Read
array operation with the other bank in BGO is performed by
changing the bank address without any additional command.
When the bank address points the bank in software command
write cycling or the erasing / programming operation, the data is
read out from the status register. The access time with BGO is the
same as the normal read operation.
Output Disable
When OE# is at VIH, output from the devices is disabled. Data
input/output are in a high-impedance(High-Z) state.
Standby
When CE# is at VIH, the device is in the standby mode and its
power consumption is reduced. Data input/output are in a
high-impedance(High-Z) state. If the memory is deselected
during block erase or program, the internal control circuits
remain active and the device consume normal active power
until the operation completes.
Sep.1999. Rev4.0
3
MITSUBISHI LSIs
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
C)Single Data Load to Page Buffer (74H)
/ Page Buffer to Flash (0EH/D0H)
SOFTWARE COMMAND DEFINITIONS
The device operations are selected by writing specific software
command into the Command User Interface.
Single data load to the page buffer is performed by writing 74H
followed by a second write specifying the column address and
data. Distinct data up to 128word can be loaded to the page
buffer by this two-command sequence. On the other hand, all of
the loaded data to the page buffer is programed simultaneously
by writing Page Buffer to Flash command of 0EH followed by the
confirm command of D0H. After completion of programing the
data on the page buffer is cleared automatically.
Read Array Command (FFH)
The device is in Read Array mode on initial device power up and
after exit from deep powerdown, or by writing FFH to the
Command User Interface. After starting the internal operation the
device is set to the read status register mode automatically.
This command is valid for only Bank(I) alike Word Program.
Read Device Identifier Command (90H)
Clear Page Buffer Command (55H)
It can normally read device identifier codes when Read Device
Identifier Code Command(90H) is written to the command latch.
Following the command write, the manufacturer code and the
device code can be read from address 0000H and 0001H,
respectively.
Loaded data to the page buffer is cleared by writing the Clear
Page Buffer command of 55H followed by the Confirm command
of D0H. This command is valid for clearing data loaded by Single
Data Load to Page Buffer command.
Suspend/Resume Command (B0H/D0H)
Read Status Register Command (70H)
Writing the Suspend command of B0H during block erase
operation interrupts the block erase operation and allows read out
from another block of memory. Writing the Suspend command of
B0H during program operation interrupts the program operation
and allows read out from another block of memory. The Bank
address is required when writing the Suspend/Resume Command.
The device continues to output Status Register data when read,
after the Suspend command is written to it. Polling the WSM
Status and Suspend Status bits will determine when the erase
operation or program operation has been suspended. At this
point, writing of the Read Array command to the CUI enables
reading data from blocks other than that which is suspended.
When the Resume command of D0H is written to the CUI,
the WSM will continue with the erase or program processes.
The Status Register is read after writing the Read Status Register
command of 70H to the Command User Interface. Also, after
starting the internal operation the device is set to the Read Status
Register mode automatically.
The contents of Status Register are latched on the later falling
edge of OE# or CE#. So CE# or OE# must be toggled every status
read.
Clear Status Register Command (50H)
The Erase Status, Program Status and Block Status bits are set to
"1"s by the Write State Machine and can only be reset by the Clear
Status Register command of 50H. These bits indicates various
failure conditions.
DATA PROTECTION
Block Erase / Confirm Command (20H/D0H)
The M5M29GB/T161BWG provides selectable block locking of
memory blocks. Each block has an associated nonvolatile lock-bit
which determines the lock status of the block. In addition, the
M5M29GB/T161BWG have a master Write Protect pin (WP1# &
WP2#) which prevents any modifications to memory blocks whose
lock-bits are set to "0", when WP1# or WP2# is low. When WP1#
& WP2# are high , all blocks can be programmed or erased
regardless of the state of the lock-bits, and the lock-bits are
cleared to "1" by erase. See the BLOCK LOCKING table on P.9 for
details.
Automated block erase is initiated by writing the Block Erase
command of 20H followed by the Confirm command of D0H. An
address within the block to be erased is required. The WSM
executes iterative erase pulse application and erase verify
operation.
Program Commands
A)Word Program (40H)
Word program is executed by a two-command sequence. The
Word Program Setup command of 40H is written to the
Command Interface, followed by a second write specifying the
address and data to be written. The WSM controls the program
pulse application and verify operation. The Word Program
Command is Valid for only Bank(I).
Power Supply Voltage
When the power supply voltage (Vcc) is less than VLKO, Low VCC
Lock-Out voltage, the device is set to the Read-only mode.
Regarding DC electrical characteristics of VLKO, see P.9
A delay time of 2 us is required before any device operation is
initiated. The delay time is measured from the time Vcc reaches
Vccmin (2.7V).
B)Page Program for Data Blocks (41H)
During power up, RP#=GND is recommended. Falling in Busy
status is not recommended for possibility of damaging the device.
Page Program for Bank(I) and Bank(II) allows fast programming of
128words of data. Writing of 41H initiates the page program
operation for the Data area. From 2nd cycle to 129th cycle , write
data must be serially inputted. Address A6-A0 have to be
incremented from 00H to 7FH. After completion of data loading, the
WSM controls the program pulse application and verify operation.
MEMORY ORGANIZATION
The M5M29GB/T161BWG has one 16Kword boot block, seven
16Kword parameter blocks, for Bank(I) and twenty-eight 32Kword
main blocks for Bank(II). A block is erased independently of other
blocks in the array.
4
Sep.1999. Rev4.0
MITSUBISHI LSIs
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Mitsubishi 16M Flash Memory Type name
M 5 M 29G T 160B WG
Operating Voltage :
29G : 2.7 - 3.6V
Standard / BGO Type
Boot Block :
T : Top Boot
B : Bottom Boot
29W : 1.65 - 2.2V
Standard / BGO Type
Package :
VP : 48pin TSOP(I) 12mm x 20mm (Nomal Pinout)
WG: CSP Ball Pitch 0.75mm,6x8 array, 7mm x 8.5mm
Density/Write Protect/
Word Organizetion:
160B : 16M WP1#, x8/x16
161B : 16M WP1# & WP2#, x16
Sep.1999. Rev4.0
5
MITSUBISHI LSIs
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
MEMORY ORGANIZATION
x16 ( Wordmode)
F8000H-FFFFFH
F0000H-F7FFFH
E8000H-EFFFFH
E0000H-E7FFFH
D8000H-DFFFFH
D0000H-D7FFFH
C8000H-CFFFFH
C0000H-C7FFFH
B8000H-BFFFFH
B0000H-B7FFFH
A8000H-AFFFFH
A0000H-A7FFFH
98000H-9FFFFH
90000H-97FFFH
x16 ( Wordmode)
FC000H-FFFFFH
16Kword BOOT BLOCK 35
32Kword MAIN BLOCK 35
32Kword MAIN BLOCK 34
32Kword MAIN BLOCK 33
32Kword MAIN BLOCK 32
32Kword MAIN BLOCK 31
32Kword MAIN BLOCK 30
32Kword MAIN BLOCK 29
32Kword MAIN BLOCK 28
32Kword MAIN BLOCK 27
32Kword MAIN BLOCK 26
32Kword MAIN BLOCK 25
32Kword MAIN BLOCK 24
32Kword MAIN BLOCK 23
32Kword MAIN BLOCK 22
32Kword MAIN BLOCK 21
F8000H-FBFFFH
F4000H-F7FFFH
F0000H-F3FFFH
EC000H-EFFFFH
E8000H-EBFFFH
E4000H-E7FFFH
E0000H-E3FFFH
D8000H-DFFFFH
D0000H-D7FFFH
C8000H-CFFFFH
C0000H-C7FFFH
B8000H-BFFFFH
B0000H-B7FFFH
16Kword PARAMETER BLOCK 34
16Kword PARAMETER BLOCK 33
16Kword PARAMETER BLOCK 32
16Kword PARAMETER BLOCK 31
16Kword PARAMETER BLOCK 30
16Kword PARAMETER BLOCK 29
16Kword PARAMETER BLOCK 28
32Kword MAIN BLOCK 27
32Kword MAIN BLOCK 26
32Kword MAIN BLOCK 25
32Kword MAIN BLOCK 24
32Kword MAIN BLOCK 23
32Kword MAIN BLOCK 22
88000H-8FFFFH
80000H-87FFFH
78000H-7FFFFH
70000H-77FFFH
68000H-6FFFFH
60000H-67FFFH
58000H-5FFFFH
50000H-57FFFH
48000H-4FFFFH
A8000H-AFFFFH
A0000H-A7FFFH
98000H-9FFFFH
90000H-97FFFH
88000H-8FFFFH
80000H-87FFFH
78000H-7FFFFH
70000H-77FFFH
68000H-6FFFFH
32Kword MAIN BLOCK 21
32Kword MAIN BLOCK 20
32Kword MAIN BLOCK 19
32Kword MAIN BLOCK 18
32Kword MAIN BLOCK 17
32Kword MAIN BLOCK 16
32Kword MAIN BLOCK 15
32Kword MAIN BLOCK 14
32Kword MAIN BLOCK 13
32Kword MAIN BLOCK 12
32Kword MAIN BLOCK 11
32Kword MAIN BLOCK 10
32Kword MAIN BLOCK 20
32Kword MAIN BLOCK 19
32Kword MAIN BLOCK 18
32Kword MAIN BLOCK 17
32Kword MAIN BLOCK 16
32Kword MAIN BLOCK 15
32Kword MAIN BLOCK 14
32Kword MAIN BLOCK 13
40000H-47FFFH
38000H-3FFFFH
60000H-67FFFH
58000H-5FFFFH
32Kword MAIN BLOCK 12
32Kword MAIN BLOCK 11
32Kword MAIN BLOCK 10
30000H-37FFFH
28000H-2FFFFH
20000H-27FFFH
1C000H-1FFFFH
50000H-57FFFH
48000H-4FFFFH
40000H-47FFFH
38000H-3FFFFH
32Kword MAIN BLOCK
32Kword MAIN BLOCK
9
8
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
9
8
7
6
5
16Kword PARAMETER BLOCK
16Kword PARAMETER BLOCK
7
6
18000H-1BFFFH
14000H-17FFFH
10000H-13FFFH
0C000H-0FFFFH
08000H-0BFFFH
04000H-07FFFH
30000H-37FFFH
28000H-2FFFFH
20000H-27FFFH
18000H-1FFFFH
10000H-17FFFH
08000H-0FFFFH
16Kword PARAMETER BLOCK
16Kword PARAMETER BLOCK
16Kword PARAMETER BLOCK
16Kword PARAMETER BLOCK
16Kword PARAMETER BLOCK
5
4
3
2
1
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
32Kword MAIN BLOCK
4
3
2
1
00000H-03FFFH
00000H-07FFFH
32Kword MAIN BLOCK
0
16Kword BOOT BLOCK 0
A19-A0
(M5M29GT161BWG)
A19-A0
(M5M29GB161BWG)
M5M29GB161BWG Memory Map
M5M29GT161BWG Memory Map
Sep.1999. Rev4.0
6
MITSUBISHI LSIs
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
BUS OPERATIONS
Bus Operations for Word-Wide Mode (M5M29GB/T161BWG)
Pins
CE#
OE#
WE#
RP#
DQ0-15
Mode
Array
VIL
VIL
VIL
VIL
VIL
VIH
VIL
VIL
VIL
X
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
VIH
VIH
X
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIH
VIL
Data out
Status Register Data
Lock Bit Data (DQ6)
Identifier Code
Hi-Z
Read
Status Register
Lock Bit Status
Identifier Code
Output disable
Stand by
1)
X
VIH
VIH
VIH
X
Hi-Z
Program
VIL
VIL
VIL
X
Command/Data in
Command
Write
Erase
Others
Command
Deep Power Down
Hi-Z
1) X can be VIH or VIL for control pins.
Sep.1999. Rev4.0
7
MITSUBISHI LSIs
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
SOFTWARE COMMAND DEFINITION
Command List
3rd ~129th bus cycles (M5M29GB/T161BWG)
2nd bus cycle
Address
1st bus cycle
Address
Command
Data
Data
(DQ15-0)
Data
(DQ15-0)
Mode
Address
1)
(DQ15-0)
Mode
Mode
Read Array
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
X
X
FFH
90H
70H
50H
55H
40H
41H
74H
0EH
20H
B0H
D0H
71H
77H
2)
2)
Device Identifier
Read Status Register
Clear Status Register
Clear Page Buffer
Read
Read
IA
ID
3)
4)
Bank
X
X
Bank
SRD
1)
Write
Write
Write
Write
Write
Write
X
D0H
WD
WD0
WD
5)
5)
6)
6)
7)
Bank(I)
Word Program
Page Program
Single Data Load to Page Buffer
Page Buffer to Flash
WA
WA0
7)
7)
7)
7)
Write
WAn
WDn
Bank
Bank(I)
5)
5)
WA
5)
8)
1)
1)
5)
D0H
Bank(I)
Bank
Bank
WA
9)
Block Erase / Confirm
Suspend
Resume
BA
D0H
Bank
X
10)
1)
Read Lock Bit Status
Lock Bit Program / Confirm
Erase All Unlocked Blocks
BA
Read
Write
Write
DQ6
D0H
D0H
Write
Write
Bank
X
BA
X
1)
A7H
1) Upper byte data (DQ8-DQ15) is ignored.
2) IA=ID Code Address : A0=VIL (Manufacturer's Code) : A0=VIH (Device Code), ID=ID Code
3) Bank = Bank Address (Bank(I) or Bank(II)). A19-A17.
4) SRD = Status Register Data
5) Word Program, Single Data Load and Page Buffer to Flash Command is valid for only Bank(I).
6) WA = Write Address,WD = Write Data
7) WA0,WAn=Write Address, WD0,WDn=Write Data.
: Write Address and Write Data must be provided sequentially from 00H to 7FH for A6-A0. Page size is 128word (128word x 16bit).
and also A19-A7(Block Address, Page Address) must be valid.
8) WA = Write Address : Upper page address, A19-A7(Block Address, Page Address) must be valid.
9) BA = Block Address : Bank1: A19-A14
Bank2: A19-A15
10) DQ6 provides Block Lock Status, DQ6 = 1 : Block Unlock, DQ6 = 0 : Block Locked.
Sep.1999. Rev4.0
8
MITSUBISHI LSIs
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
BLOCK LOCKING
Write Protection Provided
Lock
Bit
(Internally)
161BWG
BANK(I)
BANK(II)
Data
Note
Lock Bit
RP#
VIL
WP1# WP2#
Boot
Parameter
Locked
X
X
X
0
1
X
X
0
1
Locked
Locked
Locked
Locked
Locked
Locked Deep Power Down Mode
Locked
Locked
Locked
VIL
VIH
Unlocked Unlocked
VIH
VIH
VIL
VIH
VIL
All Blocks Unlocked
All Blocks Locked
Unlocked Unlocked Unlocked Unlocked
Locked
Locked
Locked
Locked
Locked
Locked
Locked
Locked
Locked
Locked
Locked
VIH
VIL
Only Parameter Block is Unlocked
Unlocked
1) DQ6 provides Lock Status of each block after writing the Read Lock Status command (71H).
WP1# & WP2# pins must not be switched during performing Erase / Write operations or WSM Busy (WSMS = 0).
2) Erase/Write command for locked blocks is aborted. At this time read mode is not array read mode but status read mode and
00B0H is read. Please issue Clear Status Register command plus Read Array command to change the mode from status read mode
to array read mode.
STATUS REGISTER
Definition
Symbol
Status
"1"
Ready
Suspended
Error
"0"
Busy
Write State Machine Status
SR.7 (DQ7)
SR.6 (DQ6) Suspend Status
SR.5 (DQ5) Erase Status
Operation in Progress / Completed
Successful
Program Status
SR.4 (DQ4)
SR.3 (DQ3)
SR.2 (DQ2)
SR.1 (DQ1)
SR.0 (DQ0)
Error
Error
Successful
Successful
Block Status after Program
Reserved
-
-
-
-
-
-
Reserved
Reserved
*DQ3 indicates the block status after the page programming, byte/word programming and page buffer to flash. When DQ3 is "1", the page has the
over-programed cell . If over-program occurs, the device is block fail. However if DQ3 is "1", please try the block erase to the block. The block may revive.
9
Sep.1999. Rev4.0
MITSUBISHI LSIs
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
DEVICE IDENTIFIER CODE
Pins
Hex. Data
1CH
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
A0
Code
VIL
0
1
1
0
0
0
0
1
1
1
0
0
1
0
0
1
0
0
0
0
0
0
0
1
Manufacturer Code
Device Code (-T161BWG)
VIH
VIH
A0H
A1H
Device Code (-B161BWG)
The upper data(D15-8) is "0".
ABSOLUTE MAXIMUM RATINGS
Symbol
Conditions
Parameter
Min
Max
Unit
V
Vcc
Vcc voltage
-0.2
-0.6
4.6
4.6
With respect to Ground
1)
All input or output voltage except Vcc,A9,RP#
Ambient temperature
VI1
Ta
V
-40
-50
-65
85
95
°C
°C
°C
mA
Tbs
Temperature under bias
Tstg
Storage temperature
125
100
I OUT
Output short circuit current
1) Minimum DC voltage is -0.5V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage
on input/output pins is VCC+0.5V which, during transitions, may overshoot to VCC+1.5V for periods <20ns.
CAPACITANCE
Limits
Parameter
Symbol
Test conditions
Unit
Typ
Min
Max
8
pF
pF
CIN
COUT
Input capacitance (Address, Control Pins)
Output capacitance
Ta = 25°C, f = 1MHz, Vin = Vout = 0V
12
DC ELECTRICAL CHARACTERISTICS (Ta = -40~ 85°C, Vcc = 2.7V ~ 3.6V, unless otherwise noted)
Limits
Typ1)
Symbol
Parameter
Test conditions
Unit
Min
Max
±1.0
±10
0V≤VIN≤VCC
ILI
Input leakage current
Output leakage current
µA
µA
µA
0V≤VOUT≤VCC
ILO
ISB1
VCC = 3.6V, VIN=VIL/VIH, CE# = RP# =WP# = VIH
50
200
VCC standby current
VCC = 3.6V, VIN=GND or VCC,
CE# = RP# = WP# = VCC±0.3V
ISB2
0.1
5
µA
ISB3
ISB4
VCC = 3.6V, VIN=VIL/VIH, RP# = VIL
5
0.1
8
15
µA
µA
VCC deep powerdown current
VCC = 3.6V, VIN=GND or VCC, RP# =GND±0.3V
VCC = 3.6V, VIN=VIL/VIH, CE# = VIL,
RP#=OE#=VIH, IOUT = 0mA
5
15
4
5MHz
1MHz
ICC1
ICC2
VCC read current for Word or Byte
VCC Write current for Word or Byte
mA
mA
2
VCC = 3.6V,VIN=VIL/VIH, CE# =WE#= VIL,
RP#=OE#=VIH
15
ICC3
ICC4
ICC5
VIL
VCC program current
VCC erase current
VCC suspend current
Input low voltage
VCC = 3.6V, VIN=VIL/VIH, CE# = RP# =WP# = VIH
VCC = 3.6V, VIN=VIL/VIH, CE# = RP# =WP# = VIH
VCC = 3.6V, VIN=VIL/VIH, CE# = RP# =WP# = VIH
mA
mA
µA
V
35
35
200
0.8
– 0.5
2.0
Vcc+0.5
VIH
Input high voltage
Output low voltage
V
VOL
VOH1
VOH2
VLKO
IOL = 4.0mA
IOH = –2.0mA
IOH = –100µA
0.45
V
V
0.85Vcc
Vcc–0.4
1.5
Output high voltage
V
Low VCC Lock-Out voltage 2)
V
2.2
All currents are in RMS unless otherwise noted.
1) Typical values at Vcc=3.3V, Ta=25°C
2) To protect against initiation of write cycle during Vcc power-up/ down, a write cycle is locked out for Vcc less than VLKO.
If Vcc is less than VLKO, Write State Machine is reset to read mode. When the Write State Machine is in Busy state, if Vcc is less than VLKO, the alteration of memory contents
may occur.
10
Sep.1999. Rev4.0
MITSUBISHI LSIs
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC ELECTRICAL CHARACTERISTICS (Ta = -40 ~85°C, Vcc = 2.7V ~3.6V)
Read-Only Mode
Limits
Vcc=2.7-3.6V
90ns
Unit
Symbol
Parameter
Min
90
Typ
Max
tRC
tAVAV
Read cycle time
ns
ns
ns
ns
ns
ns
ns
ns
ta (AD)
90
90
30
tAVQV Address access time
ta (CE)
ta (OE)
tCLZ
tELQV Chip enable access time
tGLQV Output enable access time
tELQX Chip enable to output in low-Z
tEHQZ Chip enable high to output in high Z
tGLQX Output enable to output in low-Z
0
0
tDF(CE)
25
tOLZ
tDF(OE) tGHQZ Output enable high to output in high Z
25
tPHZ
tOH
tPS
tPLQZ
tOH
RP# low to output high-Z
ns
ns
ns
150
0
Output hold from CE#, OE#, addresses
RP# recovery to CE# low
tPHEL
150
Timing measurements are made under AC waveforms for read operations.
AC ELECTRICAL CHARACTERISTICS (Ta = -40 ~85°C, Vcc = 2.7V ~3.6V)
Write Mode (WE# control)
Limits
Symbol
Parameter
Vcc=2.7-3.6V
Unit
90ns
Typ
Min
90
50
0
Max
tWC
tAS
tAVAV
ns
ns
ns
ns
ns
ns
ns
Write cycle time
tAVWH
tWHAX
tDVWH
tWHDX
tWHGL
-
Address set-up time
tAH
tDS
tDH
tOEH
tRE
tCS
tCH
tWP
Address hold time
50
0
Data set-up time
Data hold time
OE# hold from WE# high
Latency between Read and Write FFH or 71H
Chip enable set-up time
Chip enable hold time
10
30
0
tELWL
tWHEH
ns
ns
ns
0
tWLWH
60
30
0
Write pulse width
tWPH tWHWL
tGHWL tGHWL
ns
ns
ns
ns
Write pulse width high
OE# hold to WE# Low
tBLS
tBLH
tPHHWH
tQVPH
Block Lock set-up to write enable high
Block Lockhold from valid SRD
90
0
tDAP tWHRH1 Duration of auto-program operation
4
80
600
90
ms
ms
ns
tDAE
tWHRL tWHRL
tPS tPHWL
tWHRH2
Duration of auto-block erase operation
Write enable high to F-RY/BY# low
RP# high recovery to write enable low
40
ns
150
Read timing parameters during command write operations mode are the same as during read-only operations mode.
Typical values at Vcc=3.3V, Ta=25°C
11
Sep.1999. Rev4.0
MITSUBISHI LSIs
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC ELECTRICAL CHARACTERISTICS (Ta = -40 ~ 85°C, Vcc = 2.7V ~ 3.6V)
Write Mode (F-CE# control)
Limits
Vcc=2.7-3.6V
90ns
Symbol
Parameter
Unit
Min
90
50
0
Typ
Max
tWC
tAS
tAH
tDS
tDH
tAVAV
tAVWH
tEHAX
tDVWH
tEHDX
ns
ns
ns
ns
ns
ns
ns
Write cycle time
Address set-up time
Address hold time
50
0
Data set-up time
Data hold time
tOEH tEHGL
OE# hold from CE# high
Latency between Read and Write FFH or 71H
Write enable set-up time
10
30
0
-
tRE
tWS
tWH
tCEP
tWLEL
ns
ns
ns
ns
tEHWH Write enable hold time
0
CE# pulse width
tELEH
60
30
90
90
0
tCEPH tEHEL
tGHEL tGHEL
CE# pulse width high
OE# hold to CE# Low
ns
ns
tBLS
tBLH
tPHHEH
tQVPH
Block Lock set-up to chip enable high
Block Lockhold from valid SRD
ns
Duration of auto-program operation
80
600
90
ms
ms
ns
tDAP
tDAE
tEHRH1
tEHRH2
4
Duration of auto-block erase operation
CE# high to F-RY/BY# low
RP# high recovery to write enable low
40
tEHRL tEHRL
tPS tPHWL
ns
150
Read timing parameters during command write operation mode are the same as during read-only operation mode.
Typical values at Vcc=3.3V, Ta=25°C
Erase and Program Performance
Typ
Unit
Parameter
Min
Max
ms
sec
ms
Block Erase Time
40
1.0
4
600
1.8
80
Main Block Write Time (Page Mode)
Page Write Time
Program Suspend Latency / Erase Suspend Time
Typ
Parameter
Min
Max
Unit
Program Suspend Latency
Erase Suspend Time
Please see page 19.
µs
µs
15
15
Vcc Power Up / Down Timing
Symbol
tVCS
Parameter
Min
2
Typ
Max
Unit
RP# =VIH set-up time from Vccmin
µs
Please see page 12.
During power up/down, by the noise pulses on control pins, the device has possibility of accidental erasure or programming.
The device must be protected against initiation of write cycle for memory contents during power up/down.
The delay time of min.2µsec is always required before read operation or write operation is initiated from the time Vcc reaches Vccmin during power up/down.
By holding RP# VIL, the contents of memory is protected during Vcc power up/down.
During power up, RP# must be held VIL for min.2µs from the time Vcc reaches Vccmin.
During power down, RP# must be held VIL until Vcc reaches GND.
RP# doesn't have latch mode ,therefore RP# must be held VIH during read operation or erase/program operation.
12
Sep.1999. Rev4.0
MITSUBISHI LSIs
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
Vcc POWER UP / DOWN TIMING
Read /Write Inhibit
Read /Write Inhibit
Read /Write Inhibit
3.3V
VCC
GND
tVCS
VIH
RP#
VIL
VIH
CE#
VIL
tPS
tPS
VIH
VIL
WE#
AC WAVEFORMS FOR READ OPERATION AND TEST CONDITIONS
TEST CONDITIONS
VIH
FOR AC CHARACTERISTICS
ADDRESSES
ADDRESS VALID
tRC
VIL
Input voltage : VIL = 0V, VIH = 3.0V
Input rise and fall times : ≤5ns
Reference voltage
VIH
VIL
ta (AD)
CE#
OE#
tDF(CE)
at timing measurement : 1.5V
ta (CE)
VIH
VIL
Output load : 1TTL gate +CL(30pF)
or
tOEH
tDF(OE)
tOH
VIH
VIL
WE#
ta (OE)
tOLZ
1.3V
VOH
VOL
tCLZ
HIGH-Z
HIGH-Z
DATA
RP#
OUTPUT VALID
tPHZ
1N914
3.3kΩ
tPS
VIH
VIL
DUT
CL
AC WAVEFORMS FOR WRITE FFH or 71H AND READ OPERATION
VIH
ADDRESSES
ADDRESS VALID
tRC
VIL
VIH
VIL
ta (AD)
CE#
OE#
tDF(CE)
ta (CE)
VIH
VIL
tRE
tDF(OE)
tOH
VIH
VIL
WE#
DATA
RP#
ta (OE)
tOLZ
FFH or 71H
Valid
VOH
VOL
tCLZ
HIGH-Z
HIGH-Z
OUTPUT VALID
tPHZ
tPS
VIH
VIL
In the case of use CE# is Low fixed, it is allowed to define a timming specification of tRE
from rising edge of WE# to falling edge of OE#, and valid data is read after spec of tRE+ta(CE).
(This is only for FFH,71H program and read)
13
Sep.1999. Rev4.0
MITSUBISHI LSIs
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC WAVEFORMS FOR PAGE PROGRAM OPERATION (WE# control)
READ STATUS
REGISTER
WRITE READ
The other bank
PROGRAM
ARRAY COMMAND
address
VIH
VIL
VALID
VALID
ADDRESS VALID
BANK ADDRESS VALID
A19~A7
A6~A0
VIH
VIL
01H~7EH
7FH
00H
tAS
VALID
tAH ta(CE)
tWC
VIH
VIL
ta(CE)
ta(OE)
CE#
OE#
tCS
tCH
VIH
VIL
tOEH
tDAP
tGHWL
tWPH
tOEH
ta(OE)
VIH
VIL
WE#
tDH
tWP
41H
tDS
VIH
VIL
DATA
RP#
DOUT
SRD
FFH
DIN
DIN
DIN
tPS
VIH
VIL
VIH
tBLH
tBLS
WP1#,
WP2#
VIL
AC WAVEFORMS FOR PAGE PROGRAM OPERATION (CE# control)
READ STATUS
REGISTER
WRITE READ
The other bank
PROGRAM
ARRAY COMMAND
address
VIH
VALID
VALID
ADDRESS VALID
BANK ADDRESS VALID
A19~A7
A6~A0
VIL
VIH
VIL
00H
tAS
01H~7EH
7FH
VALID
tAH ta(CE)
tWC
VIH
VIL
ta(CE)
ta(OE)
CE#
OE#
tCEPH
ta(OE)
VIH
VIL
tCEP
tOEH
tDAP
tOEH
tGHEL
tWS
tWH
VIH
VIL
WE#
tDH
tDS
VIH
VIL
DATA
FFH
41H
DIN
DOUT
DIN
DIN
SRD
tPS
VIH
RP#
VIL
VIH
tBLH
tBLS
WP1#,
WP2#
VIL
14
Sep.1999. Rev4.0
MITSUBISHI LSIs
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION (WE# control) (to only BANK(I))
READ STATUS
REGISTER
WRITE READ
ARRAY COMMAND
PROGRAM
VIH
VIL
ADDRESS
VALID
BANK(I) ADDRESS VALID
ta(CE)
ADDR
CE#
tWC
tAS
tAH
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
tCS
tCH
ta(OE)
tWP
tWPH
OE#
tOEH
WE#
DATA
tDS
40H
DIN
SRD
FFH
tDH
tPS
VIH
VIL
VIH
VIL
RST#
tDAP
tBLS
tBLH
WP1#,
WP2#
AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION (CE# control) (to only BANK(I))
READ STATUS
REGISTER
WRITE READ
PROGRAM
ARRAY COMMAND
VIH
VIL
ADDRESS
VALID
ADDR
CE#
BANK(I) ADDRESS VALID
ta(CE)
tWC
tAS
tAH
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
ta(OE)
OE#
tCEP
tWH
tOEH
tWS
WE#
DATA
tDS
40H
DIN
SRD
FFH
tDH
tPS
VIH
VIL
VIH
VIL
RP#
tDAP
tBLS
tBLH
WP1#,
WP2#
15
Sep.1999. Rev4.0
MITSUBISHI LSIs
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC WAVEFORMS FOR ERASE OPERATIONS (WE# control)
READ STATUS
REGISTER
WRITE READ
ERASE
ARRAY COMMAND
VIH
ADDRESSES
BANK ADDRESS VALID
ADDRESS VALID
VIL
tWC
tAH
tAS
ta(CE)
VIH
VIL
CE#
OE#
tCS
tCH
ta(OE)
VIH
VIL
tOEH
tDAE
tWPH
VIH
VIL
WE#
tDH
tWP
tDS
VIH
VIL
SRD
tBLH
FFH
20H
D0H
DATA
RP#
tPS
VIH
tBLS
VIL
VIH
VIL
WP1#,
WP2#
AC WAVEFORMS FOR ERASE OPERATIONS (CE# control)
READ STATUS
REGISTER
WRITE READ
ERASE
ARRAY COMMAND
VIH
ADDRESSES
ADDRESS VALID
tAS
BANK ADDRESS VALID
VIL
tWC
tAH
ta(CE)
VIH
VIL
CE#
OE#
tCEPH
tCEP
ta(OE)
VIH
VIL
tOEH
tDAE
tWS
tWH
VIH
VIL
WE#
DATA
RP#
tDH
tDS
VIH
VIL
SRD
tBLH
FFH
20H
D0H
tPS
VIH
tBLS
VIL
VIH
VIL
WP1#,
WP2#
16
Sep.1999. Rev4.0
MITSUBISHI LSIs
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC WAVEFORMS FOR PAGE PROGRAM OPERATION WITH BGO (WE# control)
Change Bank Address
ARRAY READ FROM THE OTHER BANK
PROGRAM DATA TO ONE BANK
ADDRESS VALID
WITH BGO
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VALID
VALID
VALID
A19~A7
A6~A0
CE#
01H~7EH
tAH
00H
7FH
VALID
tWC
tAS
ta(CE)
tCS
tCH
ta(OE)
OE#
tOEH
tWP
tWPH
WE#
DATA
tDS
41H
DIN
DIN
DIN
SRD
DOUT
DOUT
tDH
AC WAVEFORMS FOR PAGE PROGRAM OPERATION WITH BGO (CE# control)
Change Bank Address
PROGRAM DATA TO ONE BANK
ADDRESS VALID
ARRAY READ FROM THE OTHER BANK
WITH BGO
VIH
VALID
VALID
A19~A7
A6~A0
VIL
VIH
VIL
01H~7EH
00H
7FH
VALID
VALID
tWC
tAS
tCEPH
ta(CE)
ta(OE)
tAH
VIH
CE#
OE#
VIL
VIH
tCEP
tWS
tOEH
VIL
VIH
VIL
VIH
VIL
tCH
WE#
tDS
41H
DIN
DIN
DIN
SRD
DOUT
DOUT
DATA
tDH
17
Sep.1999. Rev4.0
MITSUBISHI LSIs
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION WITH BGO (WE# control)
Change Bank Address
ARRAY READ FROM BANK(II) WITH BGO
READ STATUS
REGISTER
PROGRAM DATA TO
BANK(I)
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
ADDRESS VALID
VALID
VALID
VALID
A19~A7
VALID
VALID
A6~A0
CE#
tAH
tWC
tAS
ta(CE)
ta(OE)
tCS
tCH
OE#
tOEH
tWP
tWPH
WE#
DATA
tDS
40H
DIN
SRD
DOUT
DOUT
tDH
AC WAVEFORMS FOR BYTE / WORD PROGRAM OPERATION WITH BGO (CE# control)
Change Bank Address
READ STATUS
REGISTER
PROGRAM DATA TO
BANK(I)
ARRAY READ FROM BANK(II) WITH BGO
VIH
VIL
VIH
VIL
ADDRESS VALID
VALID
VALID
VALID
A19~A7
A6~A0
VALID
tAS
VALID
tWC
ta(CE)
ta(OE)
VIH
CE#
OE#
tCEPH
VIL
VIH
tCEP
tWS
tOEH
VIL
VIH
VIL
VIH
VIL
tCH
WE#
tDS
40H
DIN
SRD
DOUT
DOUT
DATA
tDH
18
Sep.1999. Rev4.0
MITSUBISHI LSIs
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC WAVEFORMS FOR BLOCK ERASE OPERATION WITH BGO (WE# control)
Change Bank Address
READ STATUS
REGISTER
ARRAY READ FROM THE OTHER
BLOCK ERASE IN
ONE BANK
BANK WITH BGO
VALID
VIH
VIL
ADDRESS VALID
tAH
VALID
ADDRESSES
CE#
tWC
tAS
tCH
ta(CE)
ta(OE)
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
tCS
OE#
tOEH
tWP
tWPH
WE#
tDS
20H
D0H
SRD
DATA
DOUT
DOUT
tDH
AC WAVEFORMS FOR BLOCK ERASE OPERATION WITH BGO (CE# control)
Change Bank Address
READ DATA FROM THE OTHER BANK
WITH BGO
BLOCK ERASE IN
ONE BANK
READ STATUS
REGISTER
VIH
VIL
ADDRESSES
ADDRESS VALID
VALID
VALID
tWC
tAS
tAH
ta(CE)
ta(OE)
VIH
CE#
OE#
tCEPH
VIL
VIH
tCEP
tWS
tOEH
VIL
VIH
VIL
VIH
VIL
tCH
WE#
tDS
SRD
20H
D0H
DOUT
DOUT
DATA
tDH
19
Sep.1999. Rev4.0
MITSUBISHI LSIs
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
AC WAVEFORMS FOR SUSPEND OPERATION (WE# control)
READ STATUS
REGISTER
VIH
VIL
ADDRESSES
BANK ADDRESS VALID
tAS
BANK ADDRESS VALID
tAH
ta(CE)
VIH
VIL
CE#
OE#
tCS
tCH
ta(OE)
VIH
VIL
tOEH
Program Suspend Latency
VIH
VIL
WE#
tWP
S.R.6,7=1
VALID SRD
VIH
VIL
B0H
DATA
RP#
VIH
tBLS
VIL
VIH
VIL
tBLH
WP1#,
WP2#
AC WAVEFORMS FOR SUSPEND OPERATION (CE# control)
READ STATUS
REGISTER
VIH
ADDRESSES
BANK ADDRESS VALID
tAS
BANK ADDRESS VALID
VIL
tAH
ta(CE)
VIH
VIL
tCEP
CE#
OE#
ta(OE)
VIH
VIL
tOEH
Program Suspend Latency
VIH
VIL
tWS
tWH
WE#
S.R.6,7=1
VALID SRD
VIH
VIL
B0H
DATA
RP#
VIH
tBLS
tBLH
VIL
VIH
VIL
WP1#,
WP2#
20
Sep.1999. Rev4.0
MITSUBISHI LSIs
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
FULL STATUS CHECK PROCEDURE
LOCK BIT PROGRAM FLOW CHART
STATUS REGISTER
READ
START
WRITE 77H
SR.4 =1
and
SR.5 =1
?
COMMAND SEQUENCE ERROR
BLOCK ERASE ERROR
YES
NO
NO
NO
WRITE D0H
NO
BLOCK ADDRESS
SR.5 = 0 ?
YES
SR.7 = 1 ?
NO
YES
PROGRAM ERROR
(PAGE, LOCK BIT)
SR.4 = 0 ?
YES
LOCK BIT PROGRAM
SR.4 = 0 ?
FAILED
NO
YES
PROGRAM ERROR
(BLOCK)
LOCK BIT PROGRAM
SUCCESSFUL
SR.3 = 0 ?
YES
SUCCESSFUL
(BLOCK ERASE, PROGRAM)
BYTE PROGRAM FLOW CHART
PAGE PROGRAM FLOW CHART
START
START
WRITE 40H
WRITE 41H
n = 0
WRITE
ADDRESS , DATA
n = n+1
WRITE
ADDRESS n, DATA n
STATUS REGISTER
READ
n = FFH ?
or
n = 7FH ?
NO
NO
NO
SR.7 = 1 ?
WRITE B0H ?
YES
YES
YES
STATUS REGISTER
READ
SUSPEND LOOP
WRITE D0H
FULL STATUS CHECK
IF DESIRED
NO
NO
SR.7 = 1 ?
YES
WRITE B0H ?
YES
PAGE PROGRAM
COMPLETED
YES
* Word program is admitted to only BANK(I).
SUSPEND LOOP
WRITE D0H
FULL STATUS CHECK
IF DESIRED
PAGE PROGRAM
COMPLETED
YES
Sep.1999. Rev4.0
21
MITSUBISHI LSIs
M5M29GB/T161BWG
16,777,216-BIT (1048,576-WORD BY16-BIT)
CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY
SUSPEND / RESUME FLOW CHART
CLEAR PAGE BUFFER
START
START
WRITE B0H
SUSPEND
WRITE 55H
STATUS REGISTER
READ
WRITE D0H
SR.7 = 1?
YES
NO
NO
PAGE BUFFER CLEAR
COMPLETED
PROGRAM / ERASE
COMPLETED
SR.6 =1?
SINGLE DATA LOAD TO PAGE BUFFER
YES
WRITE FFH
START
WRITE 74H
READ ARRAY DATA
WRITE
ADDRESS , DATA
DONE
READING ?
NO
YES
NO
DONE
LOADING?
RESUME
WRITE D0H
OPERATION
RESUMED
YES
SINGLE DATA LOAD
TO PAGE BUFFER
COMPLETED
* The bank address is required when writing this command. Also, there is
no need to suspend the erase or program operation when reading data
from the other bank. Please use BGO function.
BLOCK ERASE FLOW CHART
PAGE BUFFER TO FLASH
START
START
WRITE 20H
WRITE 0EH
WRITE D0H
BLOCK ADDRESS
WRITE D0H
PAGE ADDRESS
STATUS REGISTER
READ
STATUS REGISTER
READ
NO
NO
WRITE B0H ?
NO
NO
SR.7 = 1 ?
WRITE B0H ?
SR.7 = 1 ?
YES
YES
YES
FULL STATUS CHECK
IF DESIRED
SUSPEND LOOP
WRITE D0H
FULL STATUS CHECK
IF DESIRED
SUSPEND LOOP
WRITE D0H
BLOCK ERASE
COMPLETED
PAGE BUFFER TO FLASH
COMPLETED
YES
YES
22
Sep.1999. Rev4.0
Read/Standby State
70H
71H
Read
Status Register
50H
Clear
Status Register
70H
90H
70H
90H
Read
Read
Lock Status
Device Identifier
71H
71H
90H
FFH
FFH
FFH
Read Array
D0H
WD
20H
A7H
Setup State
0EH
41H
40H
77H
55H
74H
Clear
Page Buffer
Setup
Single Data Load Page Buffer to Flash
Page Program
Setup
Lock Bit Program
Setup
Erase All Unlocked
Blocks Setup
Block Erase
Setup
Byte Program
Setup
to Page Buffer
Setup
Setup
OTHER
OTHER
D0H
D0H
WDi
i=0-127
WD
D0H
D0H
OTHER
OTHER
Internal State
Erase &
Verify
Program &
Verify
Ready
Read
Read
Status Register
Status Register
B0H
B0H
D0H
D0H
Suspend State
Change Bank
Address
70H
Read
Status Register
Read State with BGO
Change Bank
Address
70H
Read Array
FFH
(From The Other Bank)
Read Array
M5M29GB161BWG 相关器件
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| M5M29GB320VP | RENESAS | 33,554,432-BIT (4,194,304-WORD BY 8-BIT / 2,097,152-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY | 获取价格 |
|
| M5M29GB320VP-80 | RENESAS | 33,554,432-BIT (4,194,304-WORD BY 8-BIT / 2,097,152-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY | 获取价格 |
|
| M5M29GB320WG | RENESAS | 33,554,432-BIT (4,194,304-WORD BY 8-BIT / 2,097,152-WORD BY16-BIT) CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY | 获取价格 |
|
| M5M29GB640C3BTC-12 | ETC | 3.3V ONLY FLASHMEMORY | 获取价格 |
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| M5M29GB640C3BTC-90 | ETC | 3.3V ONLY FLASHMEMORY | 获取价格 |
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| M5M29GB640C3BTI-12 | ETC | 3.3V ONLY FLASHMEMORY | 获取价格 |
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| M5M29GB640C3BTI-90 | ETC | 3.3V ONLY FLASHMEMORY | 获取价格 |
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| M5M29GB640C3BXAC-12 | ETC | 3.3V ONLY FLASHMEMORY | 获取价格 |
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| M5M29GB640C3BXAC-90 | ETC | 3.3V ONLY FLASHMEMORY | 获取价格 |
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| M5M29GB640C3BXAI-12 | ETC | 3.3V ONLY FLASHMEMORY | 获取价格 |
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