VP2611CGGH1R_技术文档

VP^V2^P6²1⁶¹1¹

H.261 Encoder

Supersedes June 1996 edition, DS3487 - 4.0

DS3487 - 4.1 December 1998

FEATURES

DESCRIPTION

TheVP2611VideoCompressionSourceCoderformspart

of a chip set used in video conferencing, video telephony and

multimedia applications. It produces data which conforms to

the H261 standard for video compression with rates between

64K and 2M bits per second. With a 27 MHz clock the device

will accept data produced to full CIF resolution at 30 Hz frame

rates. The pipeline latency through the device is only 3 macro

block periods.

The VP2611 contains all the elements necessary for the

compression algorithm. It incorporates a Motion Vector Esti-

mator which performs a +/- 7 pixel search. The decision to use

interorintraframecompressionismadebythedevice,andthe

selected data blocks are read from the frame store. New or

difference data is then passed through a Discrete Cosine

Transformer and quantized. Data from the quantizer is also

inverse quantized and passed through an Inverse Discrete

Cosine Transformer. This re-constructed data is then written

to the frame store for use in the next frame period.This frame

store is managed by an internal DRAM controller, and no

external logic is needed.

The input data must be in YUV space, and must also

conform to the six sub blocks per macro block format defined

by H261. Any conversion from RGB format is performed by

the VP510 Colour Space Converter. Any reduction in spatial

resolution, down to CIF or QCIF requirements, is done by the

VP520 Three Channel Video Filter.

The quantized data is zig-zag scanned and run length

coded before being output, together with block information

and motion vectors.

■

Fully integrated H261 video encoder

Up to full CIF resolution and 30 Hz frame rates

Inputs YUV data in 8 x 8 sub block format

Outputs run length coded coefficients

On chip motion vector estimator with +/-7 pixel search

window

■

Addresses and control generated internally for DRAM

frame store

QFP package

ASSOCIATED PRODUCTS

■

VP510 Colour Space Converter

VP520S CIF/QCIF Converter

VP2612 Video Multiplexer

VP2614 Video Demultiplexer

VP2615 H.261 Decoder

SYSTEM

CONTROLLER

USER

INTERFACE

VIDEO

SYNC

R

VP510

COLOUR SPACE

CONVERTER

G

B

Y

RLC DATA

VP2612

VIDEO

MULTIPLEXER

H261

BIT

STREAM

64kb to 2Mb/s

VP520

3 CHANNEL

VIDEO FILTER

VP2611

INTEGRATED

VIDEO ENCODER

REQYUV

FRMIN

FLAGS

Cr/Cb

MBLK'S

NTSC

PAL

COMP VIDEO

DECODER

ADDR

DATA

CIF FRAME

STORE

16 X128K

CIF FRAME

STORE

16X128K

TX BUFFER

32K X 8

CCIR601 RESOLUTION

CIF RESOLUTION

Y

720 X 288

720 X 240

Cr/Cb 360 x 288

Cr/Cb 360 x 240

PAL

Y 352 X 288

Cr/Cb 176 x 144

NTSC

Fig 1 : Typical Video Conferencing Transmission System

1

VP2611

PIN DESCRIPTIONS

R/W1

R/W2

Read/Write control for external DRAM 1.

YUV7:0

PCLK

This input bus accepts YUV data one pixel at a

time from the preprocessor, clocked in on the

rising edge of PCLK.

Read/Write control for external DRAM 2.

N/C if 256k DRAMs.

OE1

OE2

Output Enable control for external DRAM 1

or ADR8.

This signal is used to strobe in data at the YUV

port and must be derived by dividing SYSCLK

with an integer greater than one.

Output Enable control for external DRAM 2.

N/C if 256k DRAMs.

FRMIN

This input should be pulled high to prepare the

VP2611 to code a new frame. It must be held

high for at least one SYSCLK cycle and then

must be pulled low again before the next frame

begins. The VP2611 will respond to the rising

edge of FRMIN by asserting REQYUV

ADR7:0

Address output for the external DRAMs.

CBUS7:0

Bi-directional data bus for use by a Microproce-

ssor. Data and insructions are clocked on and

off the chip on the rising edge of CSTR.

appproximately 184 SYSCLK cycles later.

CSTR

Data strobe for the CBUS port.

REQYUV

DBUS7:0

This output is pulled high to request that YUV

data be input for a new MacroBlock. It is pulled

low again 1871 SYSCLK cycles later. It re-

mains low during Dummy MacroBlocks and

during the lay period between frames.

CEN

An enabling signal for the CBUS port.

CADR

When high, this signal defines CBUS as a data

bus, and when low as an instruction input.

This output bus serves several functions as

defined by DMODE3:0. In addition to providing

the quantized coefficients and motion vectors,

it is used to output control information.

SYSCLK

System clock, run at 27MHz maximum. The

clock must be high for between 35% and 65%

of each clock cycle. This clock is used for all

internal operations.

DMODE3:0

DCLK

Output flag port for DBUS7:0 bus. The value at

this port identifies the data type appearing on

DBUS7:0 during the same period.

RESET

Active low power on reset which must be held

low for at least 2064 cycles.

TCK

TMS

TDI

Test clock for JTAG.

This output pulses high for a minimum of 37ns

each time new data is output on DBUS or

DMODE. It can be used as an edge sensitive

strobe signal or a level sensitive "valid" signal.

Test Mode Select for JTAG.

Input JTAG test data.

Output JTAG test data.

SW15:0

This bidirectional port is connected to the

frame store.

TDO

TRST

Reset JTAG controller (active low).

RAS

CAS

Row Address Strobe output for the external

DRAMs.

NOTE:

"Barred" active low signals do not appear with a bar in the

main body of the text.

Column Address Strobe output for the external

DRAMs.

FORWARD PATH

YUV

BLOCK

FORMAT

DCT

RLC

Motion Vectors

Q

Zig Zag

SUB

Q Step

IQ

INTER/INTRA

DECISION

PROCESSOR

Force

Intra

DATA

BUS

IDCT

LOW

PASS

FILTER

MOTION

VECTOR

ESTIMATOR

BUS

FLAGS

ADD

Force

Intra

CONTROL

LOGIC

Block Info

Force

Filter

Search

Window

Predicted

block

Force

Filter

FRAME STORE INTERFACE

DATA

HOST DATA & CONTROL

ADDRESS

CONTROL

Fig 2 : Simplified Block Diagram

2

VP2611

OPERATION OF MAJOR BLOCKS

Motion Vector Estimator

180

140

100

x = 1.125y

MC Off

The motion estimator calculates the mean absolute error

( MAE ) for each possible position of the combined luminance

block in a search window from the previous frame. The

combined luminance block consists of 16 x 16 pixels, and in

thesearchwindowthisisdisplacedbetween-7to+7vertically,

and -8 to +7 horizontally. The two lsb's of each pixel are

discarded and the MAE value is contained within 14 bits.

The minimum MAE value, representing the best match

between the previous and current block, is passed to the

motion compensation decision block, together with the posi-

tion of this best fit in the search window. The zero displace-

ment MAE value is also passed to this block, which then

decides whether the best fit is sufficiently better than the zero

displacement fit. It uses the characteristic shown in Figure 3,

where the 14 bit MAE is a Hex value. In the area to the right

of the line all points defined by the two MAE values will cause

motion compensation to be applied. In this case the best fit

MAE value is used by the inter/intra decision processor,

otherwise the zero displacement value is used.

CO

80

AB

5F

MC On

40

20

40

80 CO 100 140 180

Zero Movement Absolute Error in Hex

Fig 3 : MC Decision Slope

counter will be disabled.

The user may overide the internal Inter/Intra decision at

any time using the CBUS control port. A user generated

forced inter mode will overide an internally generated `Force

Intra'.

Inter/Intra Decision Processor

The MAE value passed by the motion compensation

decision block is compared to the simplified variance of the

current block. This simplified variance is calculated by sum-

ming the moduli of the differences between each luminance

pixel and the mean luminance value over the whole macrob-

lock. Eight bit pixels are used, and the variance value is

expressedin14bitsbydiscardingthetwolsb'sfromtheactual

16 bit result. It can then be directly compared to the 14 bit MAE

value.

If the MAE value is below a user defined threshold inter

modecodingisalwaysselected. Thedefaultthresholdis3, on

a scale from 0 to 255 using the 8 msb's from the 14 bit value.

Abovethisthresholdintermodeisonlyselectedifthevariance

of the current block is greater than or equal to the MAE value

in use.

Low Pass Filter

The macroblock selected from the previous frame in

motion compensated inter mode coding, will be filtered before

it is subtracted from the current block. This decision can be

overidden externally by the system controller. The Filter uses

a simple [ 1 2 1 ] characteristic in both vertical and horizontal

dimensionsasspecifiedinH.261onthemacroblockboundaries

[010] is used.

In order to avoid gradual picture degredation, every 61st

Macroblock input to the VP2611 is coded in intra mode

regardlessoftheabovedecision.As61isaprimenumber,this

will ensure that each macroblock will be transmitted in intra

mode at least once in every 61 transmissions. If FIX MAC-

ROBLOCK or SKIP PICTURE is invoked this `Force Intra'

SYMBOL

t RAC

PARAMETER

MINIMUM

-

MAXIMUM

Access time from RAS

105ns or under

t CAC

t RP

t CP

Access time from CAS

RAS precharge time

CAS precharge time

-

25ns or under

50ns or under

15ns or under

-

t RAS

t CAS

t REF

RAS pulse width

CAS pulse width

Time to refresh 256 rows

90ns or under

50ns or under

-

0.25ms or over

N.B. All times are quoted assuming 27MHz operation. For lower clock

frequencies increase the above values proportionately.

Table 1 : External DRAM timing requirements

3

VP2611

Frame Store Manager

Zig Zag Scan

The previous picture is stored in an external CIF DRAM

frame store, which is connected by a glueless interface. The

internal Frame Store Manager controls all read, write, and

refresh operations to these DRAMs. No provision is made to

allow the use of smaller DRAM's, if only QCIF operation is

required.

This is essentially an address generator which reorders

the DCT coefficients according to the standard zig-zag scan

pattern. This has the effect of concentrating the significant

coefficients at the beginning of the sub-block, improving the

efficiency of the Run Length Coder.

During the coding of each macroblock columns of the

search window are read from these DRAMs, and finally the

"best fit" macroBlock is obtained. At the completion of coding

the fully processed new macroblock is written to the DRAM's,

after it has been decoded again. In this way the frame store

maintains a bit-accurate duplicate of the image seen by the

Decoder (excepting transmission errors).

Several configurations are possible to make the required

128Kx16 store. Two 64K x 16 DRAMs could be employed; in

this case use the default 1M DRAM mode when setting up the

chip. Otherwise, a single 256K x 16 DRAM or four 256K x 4

DRAMs could be used. In these last two cases use OE1 as

ADR8, RW1 as R/W, and do not connect RW2 and OE2. Also,

use the Setup instruction at the CPORT to put the device into

4M DRAM mode.

Run Length Coder

Each coefficient output from the zig zag scan is examined.

If it is non-zero, then the Run Length Coding circuit will pass

the coefficient magnitude to the output port along with its zero

count i.e. the number of zero magnitude coefficients preced-

ing it within the same 8x8 sub-block.

Inverse Quantize

This circuit replicates the operation of the inverse quan-

tizer in the decoder. It reconstructs the 12 bit DCT coefficients

from the 8 bit quantized inputs, using the 5 bit quantization

value. This is achieved using the following formulae.

Table 1 details the critical timing parameters which the

external DRAM must meet with SYSCLK running at 27MHz.

Note that, if used at slower speeds, the requirements on the

DRAM timing are relaxed with the exception of refresh. The

number of refresh cycles the VP2611 produces is directly

proportional to the SYSCLK frequency.

If QUANT is odd :

REC = QUANT*(2*LEVEL+1) : LEVEL > 0

REC = QUANT*(2*LEVEL-1) : LEVEL < 0

If QUANT is even :

REC = QUANT*(2*LEVEL+1)-1 : LEVEL > 0

REC = QUANT*(2*LEVEL-1)+1 : LEVEL < 0

Discrete Cosine Transform

For Intra Coded DC Coefficients :

REC = 8*LEVEL

except if LEVEL=255 when REC=1024

ThiscircuitperformsaDiscreteCosineTransformoneach

8x8 sub block, whether in inter or intra mode. In intra mode,

eightbitpixeldata isused,withaninthimpliedsignbit(allpixel

data is positive ). In inter mode the difference between the

current and best fit previous block is used. This will be a two's

complement number. Twelve bit coefficients are produced by

the DCT, and passed on to the quantizer.

If LEVEL=0 then REC=0 in all cases.

The reconstructed values (REC) are passed through a

Clipping Circuit in case of arithmetic overflow.

Thus, the Inverse Quantizer restores the DCT coefficients

to their original value but with quantisation error.

Quantize

This section quantizes the results of the DCT by dividing

the 12 bit output from the DCT with a host supplied value. The

5bitquantizationvaluesuppliedcorrespondstodivisionofthe

12 bit coefficients ( range ± 2048 ) by values from 2 to 62, but

in steps of 2. This variable quantization strategy allows the

volume of data generated by the encoder to be adjusted

dynamically, depending on the fullness of the transmission

buffer. For H.261 applications it uses the quantisation value

provided at the control port during the previous Macroblock

period (or at some earlier time). An option is provided which

allows two quantisation values to be used, one for use with

inter coded macroblocks, and the other for use with intra

coded macroblocks.

As specified in H.261, the DC coefficient of an Intra coded

Block is treated differently and the 12 bit value is always

divided by 8.

When the quantization value is small, and the DCT coef-

ficient is large, there is a danger of overflow in the eight bit

output. To avoid this a clipping circuit is included at the output

of the quantizer, which saturates at the maximum values.

Inverse DCT

This circuit replicates the operation of the Inverse Cosine

Transform in the Decoder, and outputs 9 bit signed pixel data

(intra mode) or pixel difference data (inter mode). The IDCT

fully meets the CCITT specification.

Reconstruction Adder

In Inter Mode, the IDCT data is added to the best fit block

from the previous frame store. In Intra mode, the IDCT data is

simply added to zero. After the adder, the sign bit is removed

from the result to give 8 bit pixels. Clipping circuits ensure that

any pixels with values exceeding 255 are clipped to 255, and

any with negative values are clipped to zero (such values are

possible due to quantization noise).

4

VP2611

2064 cycles

MB2

SUBBLOCK ORDER WITHIN MACROBLOCK

MB1

MB3

MB2

MB4

MB3

MB1

YUV Input

Frame Store Read

DUMMY

MB1

1

3

2

4

5

6

Control Decisions

Frame Store Write

DBUS Output

MB1

MB2

DUMMY

U

V

Y

Fig 4: MacroBlock Pipelining

OPERATION OF INTERFACES

Macroblock Delays

PIXEL ORDER WITHIN SUBBLOCK

00 01 02 03 04 05 06 07

08 09 10 11 12 13 14 15

The VP2611 has a three macroblock pipeline delay be-

tween pixel inputs and run length coded outputs. This is

illustrated in Figure 4. Whilst the second macroblock is being

input, the best fit macroblock from the previous frame is being

identified and then read from the frame store. At this time any

ControlDecisionswhicharetoeffectthefirstmacroblockmust

be supplied by the host controller. The run length coded

outputs for the first macroblock are not available until the

fourth macroblock is supplied at the input pins.

16 17 18 03 20 21 22 23

19

24 25 26 27 28 29 30 31

32 33 34 35 36 37 38 39

40 41 42 43 44 45 46 47

48 49 50 51 52 53 54 55

56 57 58 59 60 61 62 63

Fig 5 : Ordering of Pixels

then theoretically the average rate need only be 384/1871

times the SYSCLK rate. Note that PCLK must always be

obtained by dividing SYSCLK by an integer greater than one.

WhentheVP520CIF/QCIFConverterissupplyingtheVP2611

with data, it provides a peak PCLK rate equivalent to SYSCLK

divided by two, and an average rate of SYSCLK divided by

four.

The mimimum gap between REQYUV going active is

2064 SYSCLK periods. In full CIF mode "dummy" macrob-

locks are internally inserted between rows, in order to give the

chip sufficient time to load a new search window. No new YUV

data must be loaded during these dummy macroblocks, and

REQYUV will remain inactive. No dummy macroblocks are

required in QCIF mode. With a 27MHz SYSCLK all macrob-

locks will be coded in less than a 30Hz frame rate period, and

there will be a period of inactivity before FRMIN goes active

again. During this period the output bus will remain static at all

ones, and no output strobe ( DCLK ) will be produced.

YUV Input Port

The YUV port accepts pixel data from the preprocessor in

block format as illustrated in Figure 5. Within a complete

system the VP2611 is always the master device, and must be

supplied with macroblock data when it makes a demand. The

orderinwhichpixelsaresuppliedispre-determined, andmust

be strictly maintained. There are 64 pixels per sub-block and

4 luminance and 2 chrominance sub-blocks per macroblock.

Themacroblocksthemselvesaredividedintogroupsofblocks

( GOB's ), and the sequence specified in H.261 must also be

maintained.Notethat,sincethechrominanceresolutionishalf

the luminance resolution both vertically and horizontally, then

the two chrominance blocks cover the same picture area as

the four luminance blocks.

The pre-processor producing macroblock data must pro-

duce a frame start signal ( FRMIN ) when it has a complete

frame of data available. This resets the input controller within

the VP2611, which will then generate sequential GOB and

macroblock numbers for the coded outputs referenced to this

input.

FRMIN must go high for at least one system clock period,

and must go low before the next frame is available. The

VP2611 responds to FRMIN with a request for macroblock

data ( REQYUV ), which occurs approximately 184 SYSCLK

periods after FRMIN. It must then receive a complete macrob-

lock within 1871 SYSCLK periods, and at the end of this time

REQYUV will go inactive. The VP2611 must be provided with

a PCLK signal to strobe in the data. This must be derived from

SYSCLK, and must only be present when there is valid data

at the input. Data must meet the set up and hold times with

respect to PCLK as specified in Figure 6.

SCLK/2

20ns

PCLK

20ns

0ns

10ns

YUV7:0

N.B. All timings given are MINIMUM values.

Fig 6 : Timing at YUV Port

The maximum peak rate for PCLK is the SYSCLK rate

divided by two, but since there are 384 bytes per macroblock

5

VP2611

DBUS Output Port

START MB

WAIT

The DBUS port is used to pass data and control informa-

tion directly to the VP2612 Video Multiplexer. The type of data

on the output pins is identified by the DMODE 3:0 outputs,

using the codes shown in Table 2. An output strobe is also

produced ( DCLK ) which always goes high one system clock

period after the data defined by DMODE 3:0 becomes valid.

This edge is used to strobe the data into the Video Multiplexer,

and thus the data set up time is always one SYSCLK period

minus differential output delays.

(2 cycles)

IS IT

A DUMMY

BLOCK?

yes

no

CONTROL

(2 cycles)

The number of SYSCLK periods during which data re-

mains valid is dependent on the type of data, and DCLK

remains high for this same period. It goes low as the result of

the same SYSCLK rising edge which produces a change in

DMODE 3:0. The output delays with respect to SYSCLK are

illustrated in Figure 8, and Figure 9 shows a typical output

sequence during which DCLK remains high for several cycles

as the sub-block number ( code 7 ) is produced. During a Wait

State

GOB

MB

CBP

QUANT

(2 cycles)

( code 15 ) no DCLK transitions are produced. The actual

sequence of output events which occur for each macroblock,

and the duration of each event, are illustrated in Figure 7.

HORZ MV

VERT MV

The output events are defined in more detail below;

Control Decisions : This byte shows which control decisions

have been taken for the forthcoming macroblock. DBUS0

will be high if a Fixed Macroblock (FIX MB) was enforced

i.e. no new data will be transmitted this macroblock.

DBUS1 indicates whether Inter (high) or Intra (low) coding

was used for the macroblock. DBUS2 will be high if the

macroblock was filtered, and DBUS3 will be high if motion

compensation was used. DBUS5 will be high if the current

frame is being coded in FAST UPDATE mode. In this

mode the complete frame will be intra coded. DBUS6 will

be high if the current frame is a SKIP FRAME i.e. not being

coded - so no coefficients will be transmitted. DBUS4 and

DBUS7 are not used.

ARE

no

ANY BLOCKS

CODED?

yes

WAIT

(32 cycles)

SUB BLK NO (15 cycles)

RUN LENGTH

(2 cycles)

MAGNITUDE

WAIT

(1 cycle)

DMODE3:0

FUNCTION

ARE

ALL COEFFS

O/P?

GOB Number

MB Number

Control Decisions

Quant Value

Horizontal MV

Vertical MV

Coded Blk Pattern

Sub-Block No

Zero Run Count

RLC Coefficient

Not used

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

no

yes

(wait variable time to make total

time since start of sub-block up

to 335 cycles)

WAIT

ARE

ALL BLOCKS

O/P?

no

yes

Not used

WAIT

(variable cycles)

END MB

Wait State

Fig 7 : DBUS Port Flow Chart

Table 2 : DBUS Functions

6

VP2611

CBUS3:0

INSTRUCTION

SCLK

DCLK

Input VAR Threshold

Reserved

Input Inter Quantiser

Input Intra Quantiser

Input Setup Data

Input Control Functions

Reserved

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

20ns max

25ns max

20ns max

DATA FROM

VP2611

DATA VALID

DMODE

3:0

DATA VALID

Reserved

Output GOB Number

Output MB Number

Reserved

Output Control Decisions

Output Setup Data

Reserved

Fig 8: Timing diagram

GOB Number : At the start of each new macroblock, the

current GOB Number is output on DBUS3:0. (DBUS3 is

MSB).

Reserved

Overide internal clock doubler

MB Number : After the GOB Number, the macroblock

Number is output on DBUS5:0 (DBUS5 is MSB).

Table 3 : CBUS Instruction Codes

Coded Block Pattern : This byte contains a 6 bit linear code

that indicates which of the sub-blocks actually contain

coded data. DBUS6 will be high if sub-block 1 contains

coded data, through to DBUS 1 being high if sub-block 6

contains coded data. DBUS7 and DBUS0 are not used.

Note that if the macro block is not motion compensated

and the coded block pattern is all zero's, the fixed macro

block bit will be set in the control decisions byte.

Sub-block Number : An identifier for the run length coded

coefficients which are about to be made available. DBUS

2:0 contain the coded sub-block number from 1 to 6. All

zero sub-blocks will not be produced at the outputs, and

their corresponding numbers will not appear.

Zero Run Count : The number of zero valued coefficents

preceding the next non zero coefficient is available on

DBUS5:0 (DBUS5 is MSB). Normally, DBUS7:6 are low,

except to signify the end of a Sub-block, when they will

both be high. Zero Run Count is always followed by a

coefficient, even at the end of a sub-block.

Quant Value :The quantisation value used in processing the

current macroblock is output on DBUS4:0 (DBUS4 is

MSB). This represents an actual quantisation level be-

tween 2 and 62, in steps of 2 and as defined in H.261.

RLC Coefficient : This byte contains the 8 bit coefficient value.

It will always be a non-zero value, except when the

previous Zero Run Count signalled the end of sub-Block.

A zero value is then possible since, as stated above, the

run count is always followed by a coefficient byte, which

may be zero if the last coefficient is zero.

Horizontal MV : If motion compensation is used, the horizontal

componentofthemotionvectorwillbeoutputon DBUS4:0

(DBUS4 is MSB). This 5 bit value represents a two's

complement number in the range +/-15

(although only vectors in the range -8 to +7 are currently

possible with the VP2611).

Wait State : This indicates that no valid data is being output

from the DBUS port during this cycle. No DCLK is pro-

duced for this state.

Vertical MV : If motion compensation is used, the vertical

componentofthemotionvectorwillbeoutputon DBUS4:0

(DBUS4 is MSB). This 5 bit value represents a two's

complement number in the range ±15 ( although only

vectors in the range ±7 are currently possible with the

VP2611).

Pins which are "not used" for certain functions will be

forced low.

This diagram shows a typical Sub-block being output from the VP2611.

DCLK

DMODE

DBUS

15

X

7

2

8

0

9

15

X

8

9

15

8

9

0

15

X

4

1

-2

X

252

Both msb's are high showing end of block.

Fig 9: DBUS Timing

7

VP2611

tion is given in Figure 10, and when writing data or instructions

to the VP2615 the set up and hold times which are referenced

to the rising edge of CSTR must be maintained.

CBUS Control Port

The CBUS control port is used to input control and setup

information and also to output status information. In order to

save on pin count, a microprocessor driving this port is

required to execute two I/O instructions in order to transfer a

single byte of information to or from the device. The first

transfer is always a write operation, with a low level on the

single address line which is used by the interface. Data on the

bus then defines the instructions listed in Table 3. The second

transfer can be a read or write operation as necessary, but the

address line must then be high with the set up time given in

Figure 10.

When a write instruction has been defined CADR should

be pulled high, valid data presented to CBUS7:0 and then

strobed in using CSTR. Other system I/O transfers can occur

between defining a write operation and supplying the data to

be written, assuming CEN is not active during those other

transfers. If CSTR does not go active because of I/O transfers

to other devices, then CEN can remain active low between the

instruction and data.

When a read instruction has been specified the requested

data will then be output on CBUS7:0 after the access time

specified from CEN going low, assuming that CADR was

already high. Otherwise the data will become valid after the

access time specified from CADR going high after CEN was

In addition to the single addresss line (CADR), data

transfers use a control strobe (CSTR) which is only effective

when a chip enable is present (CEN). Detailed timing informa-

WRITING DATA FROM THE CBUS:

This diagram shows a typical instruction and associated data field being written to the device.

10ns

CEN

20ns

10ns

20ns

CADR

CSTR

20ns

10ns

20ns

10ns

20ns

CBUS

I/P

INSTRUCTION

DATA IN

READING INFORMATION ON CBUS :

This diagram shows a typical instruction and associated data field being read from the device.

10ns

CEN

Th

10ns

20ns

CADR

CSTR

20ns

10ns

20ns

10ns

20ns

*

20ns

*

20ns

50ns

10ns

*

20ns

CBUS

INSTRUCTION

DATA OUT

If Th is less than 5 ns then CBUS may be driven by the VP2615until CEN going high eventually turns off

the drivers. It will not prevent correct data being read when CEN again goes active

N.B. All timings shown are minimum values except those marked * which are maximums.

Fig 10 : Use of the Control Port

8

VP2611

Decision circuitry will be overidden according to CBUS1;

if CBUS1 is HIGH then all subsequent macroblocks will be

intra coded, if it is LOW they will be inter coded. When

CBUS2 is HIGH the on-board Filter Decision circuitry is

overiddenaccordingtoCBUS3;ifCBUS3isHIGHthenthe

filter will be forced on, if it is LOW the filter will be forced off.

If CBUS4 is HIGH then FIX MB will be implemented, and

no new data from the current macroblock will be coded. A

two macroblock delay exists between defining the Force

Inter/Intra, Force Filter or FIX MB decisions through the

control bus and data being affected at the outputs. These

decisions will stand for all subsequent macroblocks until

they are again changed. If CBUS5 is HIGH a FAST

UPDATE will be performed on the next frame and all

blocks will be coded in intra mode. If CBUS6 is HIGH then

the next frame will not be transmitted ( SKIP FRAME ).

Notethatthesetwoglobalframebitsdonottakeeffectuntil

the start of the next frame, and stay in effect for all frames

until they are removed. If CBUS7 is HIGH, then the on-

board Force Update Controller will be overidden, and the

user will have to enforce their own Force Update policy

using the Force Intra command. RESET will cause the

options to default to those defined by the LOW state. Note

that SKIP FRAME has priority over any other bits and that

FIXMB has priority over all bits bar SKIP FRAME. See

note below.

low. Note that in the data read phase CADR must always go

high before CSTR goes high, with the set up time specified.

When CEN goes high, or CADR goes low, the CBUS will go

high impedance after the delay specified.

Note that the access times under the conditions given

above are only true when the gap between CSTR going high

in the instruction phase, and CEN going low in the data phase,

is greater than the minimum specified in figure 10.

Only the four LSBs, CBUS3:0, are used when writing

instructions to the VP2611. The remaining bits, CBUS7:4,

should be pulled low while the instruction is strobed into the

VP2611.

The instructions listed in Table 3 are described below in

greater detail;

Input VAR Threshold: VAR is the difference between the best

fit MAE value and the variance of the current macroblock.

The VAR Threshold is the best fit MAE value below which

Inter Frame Prediction is always used, no matter what the

variance of the current block. Above this threshold inter

mode coding is only used if the best fit value is less than

the current block variance. The default value is 3, within a

range of 0 - 255 using the eight most significant bits of the

14 bit value. In normal operation values below 15 should

be used.

Output GOB Number: This instruction will output the GOB

Number on CBUS3:0, for the data currently being output

on DBUS. CBUS7:4 are not used (always low).

Input Inter Quantiser:Coefficents of inter coded macroblocks

will be quantized using the value on CBUS4:0 following

this instruction. Internally this represents a 6 bit number

with the lsb always zero, giving a value between 0 and 62

in steps of two. Where only one quantization value is to be

used for both inter and intra cases, this instruction should

be used. On reset the value will default to the maximum

allowed. See note below.

Output MB Number: This instruction will output the macrob-

lock number on CBUS5:0, for the data currently being

output on DBUS. If CBUS6 is low it indicates that the

macroblock number has just changed, or is about to

change. New Quantization Value or Control Function

words should not be written at this time since it is uncertain

which macroblock they will effect. CBUS7 is not used

(always low).

Input Intra Quantiser: This instruction is similar to the above,

except that it defines the quantization level for intra mode

codingwhenitistobedifferenttothatofintermodecoding.

See note below.

Output Control Decisions: This instruction will output the

details of several control decisions on the CBUS. CBUS0

shows whether the MacroBlock currently being output on

DBUS was inter or intra coded (0=Intra). CBUS1 shows

whether motion compensation was used (1=MC used).

CBUS3 shows whether the macroblock was passed

through the loop filter or not (1=Filtered). CBUS4 will be

high if the FIX MB instruction was enforced. CBUS5 will be

high if FAST UPDATE is currently being undertaken.

CBUS6 will be high if SKIP FRAME is in force. CBUS2 and

CBUS7 are not used.

Input Setup Data: This instruction allows several user defined

optionstobespecified,usingindividualbitsinthefollowing

data word. If CBUS0 is LOW the device will work in full CIF

mode , if HIGH it uses the QCIF mode. If CBUS3 is HIGH

both inter and intra quantization values will be used,

otherwise a common value will be used. If CBUS5 is high

then the motion compensation circuits will be disabled. If

CBUS6 is high, then the device will be configured to use

256Kx16or256Kx4DRAM's,otherwiseitwillassumethe

use of two 64K x 16 DRAM's. The default conditions after

RESET are those selected by the Low level. CBUS1,

CBUS2, CBUS4 and CBUS7 are not used but must be low

during the definition phase. This instruction may be used

any time after RESET has gone high, but the video input

bus must not be active. If a subsequent mode change

between CIF and QCIF is made then a further RESET is

needed.

Output Setup Data: This instruction allows the user to verify

the internal setup previously selected. The bits have the

same significance as in the Input Setup Data Instruction.

Note

For definitive operation the output MB number should be

read first, and these bytes only changed if CBUS b is high.

Input Control Functions: This instruction specifies several

control options using individual bits in the following data

word. If CBUS0 is HIGH then the on board Inter/Intra

9

VP2611

Initialising the VP2611

On power-up, RESET should be low and must remain low

for at least 2064 cycles of SYSCLK. After RESET is pulled

high, FRMIN may be activated to start the first frame. Before

activating FRMIN for the first time, it is advisable to use the

CBUS to implement a FAST UPDATE for the first frame (i.e.

all blocks Intra coded).

Instructions are clocked into the 8 bit instruction register

(no parity bit) and the following are available.

Instruction Register Name

( MSB first )

11111111

00000000

01000000

XX001011

BYPASS

EXTEST (No inversion)

INTEST

JTAG Test Interface

SAMPLE/PRELOAD

The VP2611 includes a test interface consisting of a

boundary scan loop of test registers placed between the pads

and the core of the chip. The control of this loop is fully JTAG/

IEEE 1149-1 1990 compatible. Please refer to this document

for a full description of the standard.

The interface has five dedicated pins: TMS, TDI, TDO,

TCK and TRST. The TRST pin is an independent reset for the

interface controller and should be pulsed low, soon after

power up; if the JTAG interface is not to be used it can be tied

low permanently. The TDI pin is the input for shifting in serial

instruction and test data; TDO the output for test data. The

TCK pin is the independent clock for the test interface and

registers, and TMS the mode select signal.

TimingdetailsfortheJTAGcontrolsignalsareshowninfig

11.The maximum TCK frequency is 5 MHz.

The test registers, their positions in the boundary loop and

thecorrespondingi/opadaredetailedinTable4. Notethatthe

three state control signals also have test registers associated

with them which are labelled as TRI in Table 4. DHz is an

output enable for all signals to the DRAM. The order given in

Table 4 determines the serial data stream needed for JTAG

testing.

TDI and TMS are clocked in on the rising edge of TCK, and

all output transitions on TDO happen on its falling edge.

Pad

Type Reg No Pad

Type Reg No

TCK

RESET

CADR

DBUS5

DBUS6

DBUS7

SW15

OP

62

IN

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

OP

TRI

IN

SW1

SW0

OP

IN

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

CSTR

CEN

IN

Signal

IN

OP

IN

CBUS0

OP

TRI

Tsu

Thd

DHZ

RAS

TRI

OP

IN

SW14

SW13

SW12

OP

IN

TCK

Signal

CBUS1

CBUS2

CBUS3

OP

IN

CAS

RW1

OP

IN

OP

IN

RW2

OE1

OE2

OP

IN

OP

IN

SW11

SW10

OP

ADR0

OP

Tprop

CBUS4

CBUS5

CBUS6

CBUS7

DCLK

OP

IN

OP

ADR1

ADR2

OP

IN

ADR3

ADR4

OP

Tsu

15

Thd

5

Tprop

SW9

SW8

OP

TMS toTCK timing

OP

IN

OP

ADR5

ADR6

OP

15

TDI to TCK timing

5

ADR7

PCLK

OP

IN

OP

IN

SW7

OP

IN

Chip i/p to TCK timing

15

5

OP

IN

YUV7

YUV6

DMODE0 OP

DMODE1 OP

SW6

SW5

OP

IN

20

TCK to TDO timing

8

YUV5

YUV4

YUV3

IN

DMODE2

DMODE3

OP

IN

7

Fig 11 : JTAG Interface timing

6

DBUS0

DBUS1

OP

SW4

SW3

SW2

OP

IN

5

YUV2

YUV1

YUV0

IN

4

IN

DBUS2

DBUS3

DBUS4

OP

3

SYSCLK IN

2

IN

OP

IN

1

FRMIN

OP

REQYUV

OP

0

Table 4 Pin and JTAG test registers

10

VP2611

ABSOLUTE MAXIMUM RATINGS [See Notes]

Supply voltage VDD

Input voltage V

-0.5V to 7.0V

-0.5V to VDD+ 0.5V

-0.5V to VDD + 0.5V

Output voltage^INV_OUT

Clamp diode current per pin I (see note 2)

Static discharge voltage (HBM)

18mA

500V

K

Storage temperature T

-55°C to 150°C

S

Ambient temperature with power applied T

AMB

0°C to 70°C

125°C

Junction temperature

Package power dissipation

3000mW

NOTES ON MAXIMUM RATINGS

1. Exceeding these ratings may cause permanent damage.

Functional operation under these conditions is not implied.

2. Maximumdissipationfor1secondshouldnotbeexceeded,

only one output to be tested at any one time.

3. Exposure to absolute maximum ratings for extended

periods may affect device reliablity.

4. Current is defined as negative into the device.

STATIC ELECTRICAL CHARACTERISTICS

Operating Conditions (unless otherwise stated)

Tamb = 0 C to +70°C VDD = 5.0v ± 5%

Characteristic

Symbol

Conditions

Units

Value

Min.

Max.

Typ.

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input leakage current

Input capacitance

Output leakage current

Output S/C current

I

V

_OH= 4mA

_OL= -4mA

_DD-1V for SYSCLK and PCLK

V_OH

V_OL

V_IH

V_IL

I_IN

C_IN

I_OZ

I_SC

V

2.4

-

2.0

-

0.4

-

0.8

+10

V

GND < V < V_DD

µA

pF

µA

mA

-10

IN

10

GND < V_OUT< V_DD

V_DD= Max

-50

10

+50

300

ORDERING INFORMATION

VP2611 CG GH1R (Commercial - Plastic QFP power package)

11

VP2611

Function

YUV3

NC

DCLK

NC

87

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

SW3

1

88

NC

2

YUV4

YUV5

VDD

GND

YUV6

YUV7

NC

CBUS7

VDD

89

SW4

3

90

SW5

4

CBUS6

GND

91

GND

5

92

VDD

6

VDD

93

SW6

7

CBUS5

GND

94

SW7

8

95

NC

9

PCLK

NC

CBUS4

CBUS3

CBUS2

CBUS1

NC

96

SW8

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

97

SW9

NC

98

SW10

SW11

NC

ADR7

ADR6

ADR5

VDD

GND

NC

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

GND

VDD

SW12

NC

CBUS0

TRST

CEN

VDD

ADR4

ADR3

ADR2

ADR1

GND

ADR0

VDD

GND

NC

SW13

SW14

NC

CSTR

NC

SW15

DBUS7

DBUS6

NC

CADR

RESET

VDD

DBUS5

GND

OE2

OE1

VDD

RW2

RW1

CAS

RAS

VDD

GND

NC

TCK

VDD

TMS

DBUS4

DBUS3

NC

TDI

NC

TDO

DBUS2

NC

(CLK54)

REQYUV

FRMIN

VDD

NC

DBUS1

DBUS0

DMODE3

NC

SW0

SW1

SW2

NC

SYSCLK

GND

NC

VDD

YUV0

YUV1

YUV2

DMODE2

DMODE1

DMODE0

NC

Pin out table for GH128 PQFP package

12

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Tel: +1 (613) 592 2122

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Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. However, Mitel assumes no

liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of

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service conveys any license, either express or implied, under patents or other intellectual property rights owned by Mitel or licensed from third parties by Mitel, whatsoever.

Purchasers of products are also hereby notiﬁed that the use of product in certain ways or in combination with Mitel, or non-Mitel furnished goods or services may infringe patents or

other intellectual property rights owned by Mitel.

This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or

contract nor to be regarded as a representation relating to the products or services concerned. The products, their speciﬁcations, services and other information appearing in this

publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or

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data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in

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Printed in CANADA

TECHNICAL DOCUMENTATION - NOT FOR RESALE


型号：	VP2611CGGH1R
厂家：	MITEL NETWORKS CORPORATION
描述：	H.261 Encoder H.261编码器编码器
文件：	总14页 (文件大小：153K)
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