VP2612CGGPFR [MITEL]

Video Multiplexer; 视频多路复用器


型号：	VP2612CGGPFR
厂家：	MITEL NETWORKS CORPORATION
描述：	Video Multiplexer 视频多路复用器复用器
文件：	总11页 (文件大小：157K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

VP2612

Video Multiplexer

Supersedes version in June 1995 Digital Video & DSP IC Handbook, HB3923-2

DS3511 - 3.0 June 1996

The VP2612 Video Multiplexer forms part of the Mitel

FEATURES

Semiconductor chip-set for video conferencing, video

telephony, and multimedia applications. This chip set

implements the H261 standard for video compression for line

rates of between 64K and 2M bits per second. With a 27MHz

clock rate full CIF resolution images can be coded at a frame

rate of up to 30Hz.

The device contains all the elements necessary to

convert the run length coded data from the VP2611 source

coder into an H261 compatible bit stream. It also calculates

the differential motion vectors and macroblock addresses

from the absolute values received from the VP2611. These

values are variable length coded, and bit packed for temporary

storage in the transmission buffer. The size of this buffer can

be either 256Kbits or 512Kbits. Data from the transmission

buffer is output through an X21 compatible serial interface,

and consists of frames containing framing bits, data, and the

BCH (511,493) forward error correction code.

The system processor interface is used to write data for

PTYPE, PSPARE, GSPARE, and to select the source of

temporal reference. The interface can also be used to monitor

the pointers into the transmission buffer, so that the buffer

fullness can be controlled using proprietary software

algorithms. In addition to the bus interface, flags are supplied

which indicate the start of each macroblock, each FEC stuffed

frame, the number of bits per picture is reaching the allowable

maximum, and impending buffer overflow.

■

Fully integrated H261 video multiplexer

■

Inputs data direct from VP2611 source coder

Output to X21 line buffers

Line rates from 64kbits/s up to 2Mbits/s

100 Pin Quad Flatpack

ASSOCIATED PRODUCTS

■

VP2611 H.261 Encoder

VP2615 H.261 Decoder

VP2614 Video Demultiplexer

VP520S CIF/QCIF Converter

VP510 Colour Space Converter

Fig. 1. VP2612 Video Multiplexer

VP2612

If a 256kBit buffer is being used this Chip Enable

should be used.

PIN DESCRIPTIONS

DBUS7:0 The input data bus from VP2611. The data type is

defined by the value present on DMODE3:0

TXE2

Active low chip enable for the Transmission buffer.

This is used for the optional second memory chip,

DMODE3:0These inputs define the data type present on the

if a 512kBit buffer is being used.

Active low write enable for the Transmission buffer.

Active low O/P enable for the Transmission buffer.

Test clock for JTAG.

data bus D7:0. Polarities are given in Table 1.

TXWE

TXOE

TCK

DCLK

HD7:0

HA3:0

A strobe for DM3:0 and DBUS7:0.The high

going edge latches data into the VMUX.

A bidirectional tri-state data bus connecting the

VMUX to the system processor.

TMS

TDI

Test mode select.

Four system processor address bits used to

address internal registers.

Test data I/P.

TDO

TRST

TOE

Test data O/P.

An active low write strobe from the system

processor.

JTAG reset.

An active low read strobe from the system

processor.

When low ALL O/P pins are high impedance.

NOTE: "Barred" active low signals do not appear with a

CEN

An active low chip select input from the system

processor.

bar in the main body of the text.

OPERATIONS OF MAJOR BLOCKS

Variable Length Coding

OVR

An active high output which signals impending

buffer overflow.

STUFF

MTICK

TOOM

An active high output that signals that FEC stuffing

is occuring.

This block is responsible for ordering the data from the

VP2611 Encoder into the correct sequence for the H261 bit

stream, and for performing the variable length coding. It also

uses data supplied by the system controller and the Temporal

Reference Counter.

Data for PTYPE, PSPARE, GSPARE is only obtained

from the system controller, and only 8 bits of PSPARE and

GSPARE information can be transmitted per picture or GOB

respectively. The temporal reference can either be obtained

from an internal counter, from the VP2611 outputs, or can be

written by the system controller. The actual source is

determined by bits in a control register as described later. The

internal counter is clocked from either a frame clock with a

maximum frequency of 29.97Hz, or a 29.97Hz clock derived

from the 27MHz system clock, or it simply counts H.261

frames from the encoder.

An output which pulses high for every macroblock

received.

This active high output indicates that the picture is

likely to exceed the allowable number of bits per

picture.

VAL

This line is taken low to indicate that the VMUX is

ready to transmit valid data. The C line in an

X21 system.

This is the serial data output from the VMUX.

CTS

Indicates that the receiver can accept data. The I

line in an X21 system.

There is no support provided for macroblock stuffing,

however FEC stuffing is implemented, and can be used to

provide bit stuffing.

RDY

Indicates that the receiver can accept data. The

R line in an X21 system.

This block is also responsible for converting the absolute

values that are output from the V2611 into the relative values

that are required in parts of the H261 bitstream. The VMUX

has been designed so that it can accept ±15 motion vectors,

rather than the +7/-8 motion vectors produced by the VP2611.

Thus it will be compatible with any future upgrades to the

VP2611 that increase the size of the motion estimator search

window.

XCLK

SCLK

X21 line clock input. 0 to 2.048MHz.

System clock input. Only the high going edge is

used internally, apart from TXWE generation.

A 29.97 Hz frame strobe for the temporal reference

counter. Must be high for at least 4 SCLK periods.

VMUX Block

RES

Active low reset signal. Must be low for at least 16

SCLK periods.

The VMUX section performs the bit packing on the data

coming from the variable length coder. This data is in the form

of a delimiter and a variable number of valid bits. The VMUX

section packs these variable length fields into bytes for

storage in the transmission buffer.

The transmission buffer is controlled by this block. It thus

generates read and write pointers, and performs the

arbitration between read and write operations. Buffer level

TXA14:0 Address output to Transmission buffer.

TXD7:0 Bidirectional data interface to Transmission buffer.

TXE1

Active low chip enable for the Transmission buffer.

VP2612

monitoring is, however, done by the FEC block as described

later.

SCLK

DCLK

The two address pointers can be read by the system

processor, thus allowing the level of the buffer to be monitored.

These are provided as 16 bit words with no truncation, and thus

require two bytes. The 16 bit value is internally frozen when the

most significant byte is requested by the system processor, and

for accuracy the write pointer should be read first. There is also

a control register bit which selects a buffer size of either 256kbits

or 512kbits.

25ns max

20ns max

DATA FROM

VP2611

DATA VALID

DMODE

3:0

DATA VALID

FEC Block

Figure 2. DBUS Timing

The FEC section performs the framing, and adds the error

correction parity bits. If sufficient data for a frame is not available

in the transmission buffer, then the frame will be stuffed

automatically. There is no absolute threshold at which the FEC

will start to stuff, as the buffer level monitor in the FEC only works

to a resolution of ±128bits. FEC stuffing can also be forced by

setting the "Force FEC stuffing" bit in the VMUX/FEC control

least two cycles, and DCLK is high for minimum of one

cycle. The rising DCLK edge occurs one cycle after

DBUS7:0 and DMODE3:0 are valid, as shown in Figure 2.

The sequence of events, and the duration of each

event, is shown in Figure 3. These duration times have

been chosen to satisfy the internal requirements of the

VP2612, and Wait States are inserted such that the time

to transfer a macroblock is always 2064 SCLK periods.

If the buffer level reaches a threshold, internally set to 512

short of the buffer being full, the OVERFLOW output is asserted.

The parameters used by the VP2612 are described

in more detail below;

DMODE3:0

FUNCTION

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

GOB Number

MB Number

Control Decisions

Quant Value

Horizontal MV

Vertical MV

GOB Number : The current GOB Number is provided on

DBUS3:0 after the Control Decisions byte. (DBUS3 is

MSB).

MB Number : After the GOB Number, the macroblock

Number is provided on DBUS5:0 (DBUS5 is MSB).

Control Decisions : This byte shows which control decisions

have been taken for the forthcoming macroblock, and is

the first in the sequence. DBUS0 will be high if a Fixed

Macroblock (FIX MB) was enforced i.e. no new data will

be transmitted this macroblock. DBUS1 indicates

whether Inter (high) or Intra (low) coding was used for the

macroblock. DBUS2 will be high if the macroblock was

filtered, and DBUS3 will be high if motion compensation

was used. DBUS5 will be high if the current frame is being

coded in FAST UPDATE mode. In this mode the com-

plete frame will be intra coded. DBUS6 will be high if the

current frame is a SKIP FRAME i.e. not being coded - so

no coefficients will be transmitted. DBUS4 and DBUS7

are not used.

Coded Blk Pattern

Sub-Block No.

Zero Run Count

RLC Coefficient

Not Used

Wait State

Table 1

Quant Value :The quantisation value used in processing the

current macroblock is provided on DBUS4:0 (DBUS4 is

MSB). This represents an actual quantisation level be-

tween 2 and 62, in steps of 2 and as defined in H.261.

This is to warn the system processor that drastic action is

needed to avert a buffer overflow, which will result in corruption

and loss of data. Since the buffer level monitor only works to

resolution of ±128bits, then the overflow detection can only be

accurate to ±128bits.

Horizontal MV : If motion compensation was used the hori-

zontal component of the motion vector will be provided on

DBUS4:0 (DBUS4 is MSB). (This 5 bit value represents

a two's complement number in the range (-15 to +15)

(although only vectors in the range +7/-8 are currently

possible with the VP2611). If motion compensation was

not used this is a don't care value.

VP2611 Interface

The VMUX has been designed to interface directly to

the VP2611 encoder, with no buffering. The interface consists

of two buses DBUS7:0 and DMODE3:0, and a strobe signal

DCLK. The value on DMODE3:0 identifies the data type on

DBUS7:0 during the same period (see Table 1).

The output of the VP2611 is structured such that the

data on DBUS7:0 and DMODE3:0 is always valid for at

VP2612

Vertical MV : If motion compensation was used the vertical

component of the motion vector will be provided on

DBUS4:0 (DBUS4 is MSB). (This 5 bit value represents a

two's complement number in the range ±15 ( although only

vectors in the range (±7) are currently possible with the

VP2611). If motion compensation was not used this is a

don't care value.

START MB

WAIT

(2 cycles)

IS IT

A DUMMY

BLOCK?

yes

Coded Block Pattern : This byte contains a 6 bit linear code

that indicates which of the sub-blocks actually contain

coded data. DBUS6 will be high if sub-block 1 contains

coded data, through to DBUS1 being high if sub-block 6

contains coded data. DBUS7 and DBUS0 are not used.

CONTROL

(2 cycles)

GOB

Sub-block Number : An identifier for the run length coded

coefficients which are about to be made available.

DBUS2:0 contain the coded sub-block number from 1 to 6.

All zero sub-blocks will not be produced, and their corre-

sponding numbers will not appear.

CBP

QUANT

(2 cycles)

Zero Run Count : The number of zero valued coefficents

preceding the next non zero coefficient is provided on

DBUS5:0 (DBUS5 is MSB). Normally, DBUS7:6 are low,

except to signify the end of a Sub-block, when they will

both be high. Zero Run Count is always followed by a

coefficient, even at the end of a sub-block.

HORZ MV

VERT MV

ARE

ANY BLOCKS

CODED?

RLC Coefficient : This byte contains the 8 bit coefficient value.

It will always be a non-zero value, except when the

previous Zero Run Count signalled the end of sub-Block.

A zero value is then possible since, as stated above, the

run count is always followed by a coefficient byte, which

may be zero if the last coefficient is zero.

yes

WAIT

(32 cycles)

SUB BLK NO (15 cycles)

Wait State : This indicates that no valid data is being output

from the DBUS port during this cycle. No DCLK is pro-

RUN LENGTH

(2 cycles)

(1 cycle)

duced for this state.

MAGNITUDE

WAIT

SYSTEM PROCESSOR INTERFACE

The system processor interface is a memory

mapped microprocessor compatible interface. It has been

designed for use with any system processor, and consists

of the following buses and signals:

ARE

ALL COEFFS

O/P?

HD7:0

HA3:0

CEN

Processor Data Bus

LSBs of address bus

Active Low Write strobe

Active Low Read strobe

Decoded Active Low chip select

yes

(wait variable time to make total

time since start of sub-block up

to 335 cycles)

WAIT

Detailed interface timing is shown in Figure 4. Since there

are several internal pipeline registers which are clocked by

SCLK, then access times and strobe widths are dependent

on the period of SCLK.

ARE

ALL BLOCKS

O/P?

Table 2 shows the addresses used for each of the user

accessible registers, and the function of each register is

described in detail below.

yes

WAIT

(variable cycles)

END MB

Figure 3. DBUS Port Flow Chart

VP2612

Temporal Reference If the temporal reference is being

written from the system processor, then the 5 LSB's in this

to be transmitted.

Read / Write

Address

Function

PTYPE

Temporal Reference

PSPARE

PSPARE This register holds 8 bits of PSPARE information

which may be transmitted for each picture. The data in the

PSPARE register will be transmitted at the start of the next

picture after it has been written. Once an item of data has been

transmitted, it will not be re-transmitted until data is written

from the system processor. It is the responsibility of the

system processor to ensure that it does not rewrite to this

can be done by utilizing a frame interrupt from the video source

in conjunction with the MBTICK output from the VMUX.

TR Source

GSPARE

Not Used

TX-buffer Write Address MSB

TX-buffer Write Address LSB*

TX-buffer Read Address MSB

TX-buffer Read Address LSB*

FEC / VMUX status word

Bits per Picture Threshold

Not Used

TR Source The 3 LSB's in this register define the source for

the strobe used by the 5 bit temporal reference counter. When

the sytem processor is selected, the counter value is replaced

by the contents of the Temporal Reference Register.

VALUE

SOURCE

0XX

100

System Processor

Actual coded frames from the VP2611

are counted

Not Used

101

110

111

SCLK is divided down to provide a

29.97 Hz frame strobe

The strobe is provided by the frame

strobe input pin (FS)

* N.B. The LSB must be read after the appropriate MSB.

Illegal

Table 2. Address Locations

PTYPE This is the picture type as defined in H261.

GSPARE This register holds 8 bits of GSPARE information

which may be transmitted every GOB. Once written the data

is transmitted at the start of the next GOB, but will not be re-

transmitted until the system processor again writes to this

address. The system processor must ensure that data is not

overwritten before it is used.

The bits are assigned as follows:

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4:5

Split screen indicator, "0" off, "1" on.

Document camera indicator, "0" off, "1" on.

Freeze picture release, "0" off, "1" on.

Source Format, "0" QCIF, "1" CIF.

Both are set to one as presently defined in the

H261 specification

TX Buffer Addresses

These allow the system

[Bit 0 is LSB].

processor to monitor the level of the buffer. The write pointer

should be read first to minimize the error between the the two

These values can be changed at will by the system processor,

and will be transmitted at the start of each picture.

WRITE CYCLE

READ CYCLE

ADDRESS

Tsh

Tas

Tws

CHIP

SELECT

Tah

CHIP

SELECT

Tah

Tas

Trs

Tri

Twi

WRITE

STROBE

READ

STROBE

Twa

Thz

Data Valid

Tdh

Tds

Tac

Tlz

DATA

OUT

DATA

Data Valid

CHARACTERISTIC

SYMBOL

MAX

SYMBOL

MIN

MAX

NOTE

Addresss Set Up Time

Address Hold Time

Cip Select Set Up Time

Chip Select Hold Time

Strobe In active Time

Data Access Time

Addresss Set Up Time

Address Hold Time

Chip Select Set Up Time

Chip Select Hold Time

Strobe In active Time

Strobe Active Time

Tas

Tah

Trs

Tsh

Tri

Tac

Tlz

Thz

Tas

Tah

Tws

Tsh

Twi

Twa

Tds

Tdh

10ns

2ns

2Øns

10ns

2ns

Øns

4Øns

Ø is the period of the

input clock

10 +5Øns

25ns

Delay to O/P's low Z

Delay to O/P's high Z

Data Set Up Time

Data Hold Time

Figure 4. Host Controller Timing

VP2612

values. With a 2Mbits/sec line the error will increase at a rate

of 0.25 bytes per microsecond. Reading the most significant

bytes will trigger the internal latching of the least significant

bytes.

They perform the following functions:

OVR This line signals an impending buffer overflow. When

the buffer reaches 512±128 bits from being full this line will be

taken high, and will remain high until the buffer level falls below

the threshold. It is intended that this line be used as a

processor interrupt, to signal that drastic action must be taken.

FEC / VMUX Control

This register controls the

operation of the transmission buffer and the FEC block.

Actions taken when bits are set are given below;

BIT

FUNCTION

STUFF This line signals that FEC stuffing is occuring, and can

be used to monitor the amount of stuffing being performed. It

will pulse high once at the start of each FEC stuffed frame, the

length of the pulse being one line clock period. It is intended

that this should be used to clock a system processor counter,

to keep a running total of the number of FEC stuffed frames.

Select 512K buffer. The buffer size must

not be changed during normal operation and must

be defined within 2.4 ms of reset.

Enable FEC framing.The option to disable FEC

framing is only provided as a test mode.

MTICK This output pulses high once for every Macroblock

received from the VP2611. The pulse is 3 clock cycles in

duration, and the leading edge will occur 6 SCLK cycles after

the Macroblock address was received from the VP2611. It is

anticipated that this should be used to clock a counter in the

system processor, so that the system processor can keep

track of which MB is being processed. In conjunction with the

frame pulse this will enable the system processor to write

information to the VP2611 at appropriate times.

Force FEC stuffing. If force FEC stuffing is selected

it will start at the beginning of the next frame and

only stop at the start of subsequent frames. The

system processor must ensure that the

transmission buffer does not overflow with forced

stuffing. In normal operation FEC stuffing only

occurs when there is insufficient data in the

transmission buffer.

TOOM This signal indicates that the present picture has

reached a threshold relative to the maximum number of bits

per picture allowed by H.261 (256k if CIF, 64k if QCIF). It is set

when the number of bits remaining before the maximum will be

exceeded reaches the value in the Bits Per Picture Register,

and stays high until the end of the current picture.

Bits Per Picture Register When the number of bits which

have been coded has been subtracted from the maximum

possible ( as defined by H.261 ), and the result reaches the

value in this register, then the TOO MANY interrupt will be

generated. The programmed value thus defines in Kbits the

number of bits which may still be generated before reaching

the maximum allowed. The default value is 8 Kbits, and the

maximum number used internally changes between CIF and

TRANSMISSION BUFFER INTERFACE

The transmission buffer can consist of either one or

two 32K x 8 bit static RAMs. Fifteen address outputs are

provided for direct connection to the memory devices, and two

RAM select pins are provided to define the device in use. If

only a single device is being used then CE2 is redundant.

An internal FIFO is provided to average out high speed bursts

of transmission buffer cycles. This allows the external SRAM

read cycles to occupy at least three SCLK periods. Detailed

timing for the buffer is given in Figure 5, and shows that with

a 27 MHz clock the RAM must have an access time of less than

39 nanoseconds. Figure 5 illustrates the worst case read

access time, which occurs when a second read cycle follows

the first without an intermediate write cycle. Chip enable and

output enable remain low from the first read cycle.

QCIF.

INTERRUPT OUTPUTS

The special signals listed below are provided to drive

timers and interrupt inputs on the system processor.

OVERFLOW

FEC STUFF

MACROBLOCK TICK

TOO MANY

( OVR )

( STUFF )

( MTICK )

( TOOM )

The write cycle uses two SCLK periods and requires the use

of both the falling and rising edges of SCLK. The Write Enable

output thus remains active for one SCLK period minus

differential rising and falling edge delays. These are limited to

two nanoseconds. Note that when consecutive read or write

operations take place then Chip Enable will remain active, and

not go inactive between cycles.

SCLK

ADDRESS

O/P

ADDRESS VALID

20ns

max

20ns

max

0ns

min

15ns

min

CHIP ENABLE/

O/P ENEBALE

Tac

VALID

DATA I/P

WORST CASE READ CYCLE

LINE INTERFACE

WRITE CYCLE

A serial interface is provided which facilitates the

operation of the encoder and decoder in a back to back

configuration. It is similar in operation to an X21 interface but

does not support balanced lines. Alternatively the interface

can be used in a simple serial manner by tying the control lines

to fixed logic levels. It uses the following signals:

ADDRESS

O/P

20ns max

20ns

max

CHIP

ENABLE

DATA

O/P

DATA VALID

20ns

max

20ns

max

WRITE

ENABLE

Figure 5. Transmission Buffer Timing

VP2612

XCLK

VAL

CTS

RDY

Line rate clock

Ready to send

Transmitted Data

Clear To Send

Receiver ready

XCLK

I/P

20 min

READY FROM

RECEIVER

RECEIVER READY

R =1, I =1

DATA VALID

O/P (VAL)

Of these signals XCLK, CTS and RDY are supplied by

the receiving device, the latter two indicating that the receiver

is ready to accept data. The VAL line is used to signal that the

VMUX is ready to start transmitting valid data, and the TD line

provides the data. The signaling convention is as follows:

25ns max

DATA

O/P

DATA VALID

CTS = 1

RDY = 0

Receiving device not ready

Figure 6. Serial Interface Timing

CTS = 0

RDY = X

Receiving device ready to accept data

The TAP controller used in this device does not support

a separate INTEST instruction but allows EXTEST to drive the

internals of the device as well as to drive the output pins.

Output enables are thus present in the chain which are not

connected to pins but which allow EXTEST to be used to

control the impedance of all the outputs. The JTAG signal

TXD controls the TXD bus, HD controls the HD bus, and TOPS

controls all remaining outputs. The TOE pin, which can

separately be used to control the impedance of all the outputs,

can be monitored as an input through the scan chain but

cannot be used to control the outputs through the TAP

controller.

CTS =1

RDY =1

Receiving device ready to accept data

The VAL line is taken high by the reset input, and when

the receiving device signals that it is ready to accept data then

the VP2612 takes the VAL line low on a falling edge of an

XCLK. The data is then clocked out on subsequent falling

edges of the XCLK signal, so that it can be sampled by the

receiver on the rising edge of the clock.

If a simple serial interface is required, the CTS input

should be tied low and the RDY input tied high. It is possible

to use a variable rate clock provided the maximum

instantaneous bit rate does not exceed 8Mbits/s, and the

average clock rate over 32 bits does not exceed 2Mbits/s.

Timing delays with respect to the incoming XCLK are shown

in Figure 6.

JTAG Test Interface

The VP2612 includes a test interface consisting of a

boundary scan loop of test registers placed between the pads

and the core of the chip. The control of this loop is fully JTAG/

IEEE 1149-1 1990 compatible. Please refer to this document

for a full description of the standard.

The interface has five dedicated pins: TMS, TDI, TDO,

TCK and TRST. The TRST pin is an independent reset for the

interface controller and should be pulsed low, soon after

power up; if the JTAG interface is not to be used it can be tied

low permanently. The TDI pin is the input for shifting in serial

instruction and test data; TDO the output for test data. The

TCK pin is the independent clock for the test interface and

registers, and TMS the mode select signal.

TDI and TMS are clocked in on the rising edge of TCK,

and all output transitions on TDO happen on its falling edge.

Instructions are clocked into the 3 bit instruction register

(no parity bit) and the following instructions are available.

Instruction Register

( MSB first )

Name

111

000

010

BYPASS

EXTEST

SAMPLE/PRELOAD

VP2612

NOTES ON MAXIMUM RATINGS

ABSOLUTE MAXIMUM RATINGS [See Notes]

1. Exceeding these ratings may cause permanent damage.

Functional operation under these conditions is not implied.

2. Maximum dissipation or 1 second should not be exceeded,

only one output to be tested at any one time.

3. Exposure to absolute maximum ratings for extended

periods may affect device reliablity.

Supply voltage VDD

Input voltage V_IN

Output voltage V_OUT

Clamp diode current per pin I_K(see note 2)

Static discharge voltage (HMB)

Storage temperature T_S

-0.5V to 7.0V

-0.5V to VDD + 0.5V

-0.5V to VDD+ 0.5V

18mA

500V

-65°C to 150°C

4. Current is defined as negative into the device.

Ambient temperature with power applied T_AMB

0°C to 70°C

100°C

Junction temperature

Package power dissipation

1000mW

STATIC ELECTRICAL CHARACTERISTICS

Operating Conditions (unless otherwise stated)

Tamb = 0 C to +70°C VDD = 5.0v ± 5%

Characteristic

Symbol

Units

Conditions

Value

Typ.

Min.

Max.

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input leakage current

Input capacitance

Output leakage current

Output S/C current

V_OH

V_OL

V_IH

V_IL

I_IN

C_IN

I_OZ

I_SC

I_OH= 4mA

I_OL= -4mA

3.0V for SYSCLK and DCLK

2.4

2.0

0.4

0.8

+10

µA

GND < V_IN< V_DD

GND < V_OUT< V_DD

-10

-50

+50

300

FUNC

N/C

TOE

FUNC

TXD1

TXD0

TXA14

TXA13

TXA12

TXA11

TXA10

TXA9

TXA8

TXA7

VDD

FUNC

TXA1

TXA0

TXWE

TXOE

GND

VDD

TXE2

TXE1

TDI

TMS

TRST

TCK

TDO

VDD

FUNC

GND

DCLK

XCLK

RDY

CTS

VAL

N/C

100

HD3

HD4

HD5

HD6

HD7

VDD

GND

OVR

DMODE0

DMODE1

DMODE2

DMODE3

GND

CEN

N/C

VDD

HA0

HA1

HA2

HA3

SCLK

GND

VDD

HD0

HD1

HD2

DBUS0

DBUS1

DBUS2

DBUS3

DBUS4

DBUS5

DBUS6

DBUS7

VDD

N/C

GND

TXD7

TXD6

TXD5

TXD4

TXD3

TXD2

GND

VDD

TXA6

TXA5

TXA4

TXA3

TXA2

N/C

GND

RES

MTICK

STUFF

TOOM

N/C

Pin Out Diagram

VP2612

PAD

TYPE

PAD

TYPE

REG No.

TXE1

TXE2

TX0E

TXWE

TXA0

TXA1

TXA2

TXA3

TXA4

TXA5

TXA6

TXA7

TXA8

TXA9

TXA10

TXA11

TXA12

TXA13

TXA14

TXD

TXD0

TXD1

TXD2

TXD3

TXD4

TXD5

TXD6

TXD7

CEN

O/P

HD5

HD4

HD3

HD2

HD1

HD0

SCLK

HA3

HA2

HA1

HA0

VAL

(input)

(output)

(input)

(output)

(input)

(output)

(input)

(output)

(input)

(output)

(input)

I/P

O/P

I/P

O/P

I/P

O/P

I/P

O/P

I/P

CTS

RDY

(input)

(output)

(input)

(output)

(input)

(output)

(input)

(output)

(input)

(output)

(input)

(output)

(input)

(output)

(input)

(output)

I/P

XCLK

DCLK

DBUS7

DBUS6

DBUS5

DBUS4

DBUS3

DBUS2

DBUS1

DBUS0

DMODE3

DMODE2

DMODE1

DMODE0

OVR

TOE

TOPS

TSE

DEN

TOOM

STUFF

MTICK

RES

HD7

HD6

HD5

I/P

(output)

(input)

(output)

(input)

(output)

JTAG Register Allocation

ORDERING INFORMATION

VP2612 CG GPFR (Commercial - Plastic QFP package)

http://www.mitelsemi.com

World Headquarters - Canada

Tel: +1 (613) 592 2122

Fax: +1 (613) 592 6909

North America

Tel: +1 (770) 486 0194

Fax: +1 (770) 631 8213

Asia/Paciﬁc

Tel: +65 333 6193

Fax: +65 333 6192

Europe, Middle East,

and Africa (EMEA)

Tel: +44 (0) 1793 518528

Fax: +44 (0) 1793 518581

Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. However, Mitel assumes no

liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of

patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or

service conveys any license, either express or implied, under patents or other intellectual property rights owned by Mitel or licensed from third parties by Mitel, whatsoever.

Purchasers of products are also hereby notiﬁed that the use of product in certain ways or in combination with Mitel, or non-Mitel furnished goods or services may infringe patents or

other intellectual property rights owned by Mitel.

This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or

contract nor to be regarded as a representation relating to the products or services concerned. The products, their speciﬁcations, services and other information appearing in this

publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or

service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a speciﬁc

piece of equipment. It is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or

data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in

any medical products whose failure to perform may result in signiﬁcant injury or death to the user. All products and materials are sold and services provided subject to Mitel’s

conditions of sale which are available on request.

M Mitel (design) and ST-BUS are registered trademarks of MITEL Corporation

Mitel Semiconductor is an ISO 9001 Registered Company

Printed in CANADA

TECHNICAL DOCUMENTATION - NOT FOR RESALE

VP2612CGGPFR [MITEL]

相关型号：

VP2614

VP2614CGGPFR

VP2615

VP2615CGGGCR

VP2615CGGH1R

VP2615CGGPFR

VP2BKX

VP2BLX

VP2GNX

VP2GYX

VP2OX

VP2PX